2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
69 /* board IDs for specific chipsets in alphabetical order */
76 board_ahci_sb700, /* for SB700 and SB800 */
80 board_ahci_mcp_linux = board_ahci_mcp65,
81 board_ahci_mcp67 = board_ahci_mcp65,
82 board_ahci_mcp73 = board_ahci_mcp65,
83 board_ahci_mcp79 = board_ahci_mcp77,
86 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
87 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
88 unsigned long deadline);
89 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
90 unsigned long deadline);
91 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
92 unsigned long deadline);
94 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
95 static int ahci_pci_device_resume(struct pci_dev *pdev);
98 static struct scsi_host_template ahci_sht = {
102 static struct ata_port_operations ahci_vt8251_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_vt8251_hardreset,
107 static struct ata_port_operations ahci_p5wdh_ops = {
108 .inherits = &ahci_ops,
109 .hardreset = ahci_p5wdh_hardreset,
112 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114 static struct ata_port_operations ahci_avn_ops = {
115 .inherits = &ahci_ops,
116 .hardreset = ahci_avn_hardreset,
119 static const struct ata_port_info ahci_port_info[] = {
123 .flags = AHCI_FLAG_COMMON,
124 .pio_mask = ATA_PIO4,
125 .udma_mask = ATA_UDMA6,
126 .port_ops = &ahci_ops,
128 [board_ahci_ign_iferr] =
130 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
136 [board_ahci_nomsi] = {
137 AHCI_HFLAGS (AHCI_HFLAG_NO_MSI),
138 .flags = AHCI_FLAG_COMMON,
139 .pio_mask = ATA_PIO4,
140 .udma_mask = ATA_UDMA6,
141 .port_ops = &ahci_ops,
143 [board_ahci_noncq] = {
144 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ),
145 .flags = AHCI_FLAG_COMMON,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
150 [board_ahci_nosntf] =
152 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
158 [board_ahci_yes_fbs] =
160 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
168 .flags = AHCI_FLAG_COMMON,
169 .pio_mask = ATA_PIO4,
170 .udma_mask = ATA_UDMA6,
171 .port_ops = &ahci_avn_ops,
175 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
177 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
178 .pio_mask = ATA_PIO4,
179 .udma_mask = ATA_UDMA6,
180 .port_ops = &ahci_ops,
184 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
188 .port_ops = &ahci_ops,
192 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
193 .flags = AHCI_FLAG_COMMON,
194 .pio_mask = ATA_PIO4,
195 .udma_mask = ATA_UDMA6,
196 .port_ops = &ahci_ops,
200 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
201 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
202 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
203 .pio_mask = ATA_PIO4,
204 .udma_mask = ATA_UDMA6,
205 .port_ops = &ahci_ops,
209 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
210 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
211 AHCI_HFLAG_32BIT_ONLY),
212 .flags = AHCI_FLAG_COMMON,
213 .pio_mask = ATA_PIO4,
214 .udma_mask = ATA_UDMA6,
215 .port_ops = &ahci_pmp_retry_srst_ops,
217 [board_ahci_sb700] = /* for SB700 and SB800 */
219 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
220 .flags = AHCI_FLAG_COMMON,
221 .pio_mask = ATA_PIO4,
222 .udma_mask = ATA_UDMA6,
223 .port_ops = &ahci_pmp_retry_srst_ops,
225 [board_ahci_vt8251] =
227 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
228 .flags = AHCI_FLAG_COMMON,
229 .pio_mask = ATA_PIO4,
230 .udma_mask = ATA_UDMA6,
231 .port_ops = &ahci_vt8251_ops,
235 static const struct pci_device_id ahci_pci_tbl[] = {
237 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
238 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
239 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
240 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
241 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
242 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
243 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
244 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
245 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
246 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
247 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
248 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
249 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
250 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
251 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
252 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
253 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
254 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
255 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
256 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
257 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
258 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
259 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
260 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
261 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
262 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
263 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
264 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
265 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
266 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
267 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
268 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
269 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
270 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
271 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
272 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
273 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
274 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
275 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
276 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
277 { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
278 { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
279 { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
280 { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
281 { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
282 { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
283 { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
284 { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
285 { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
286 { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
287 { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
288 { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
289 { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
290 { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
291 { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
292 { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
293 { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
294 { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
295 { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
296 { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
297 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
298 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
299 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
300 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
301 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
302 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
303 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
304 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
305 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
306 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
307 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
308 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
309 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
310 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
311 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
312 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
313 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
314 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
315 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
316 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
317 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
318 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
319 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
320 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
321 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
322 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
323 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
324 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
325 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
326 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
327 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
328 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
329 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
330 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
331 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
332 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
333 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
334 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
335 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
336 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
337 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
338 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
339 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
340 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
341 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
342 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
343 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
344 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
345 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
346 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
347 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
348 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
349 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
350 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
351 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
352 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
353 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
354 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
355 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
356 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
357 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
358 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
359 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
360 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
361 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
362 { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
363 { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
364 { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
365 { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
366 { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
367 { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
368 { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
369 { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
370 { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
371 { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
372 { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
373 { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
374 { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
375 { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
376 { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
377 { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
378 { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
379 { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
380 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
381 { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
382 { PCI_VDEVICE(INTEL, 0xa184), board_ahci }, /* Lewisburg RAID*/
383 { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
384 { PCI_VDEVICE(INTEL, 0xa18e), board_ahci }, /* Lewisburg RAID*/
385 { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
386 { PCI_VDEVICE(INTEL, 0xa204), board_ahci }, /* Lewisburg RAID*/
387 { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
388 { PCI_VDEVICE(INTEL, 0xa20e), board_ahci }, /* Lewisburg RAID*/
390 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
391 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
392 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
393 /* JMicron 362B and 362C have an AHCI function with IDE class code */
394 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
395 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
398 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
399 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
400 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
401 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
402 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
403 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
404 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
407 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
408 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
409 /* AMD is using RAID class only for ahci controllers */
410 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
411 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
414 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
415 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
418 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
419 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
420 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
421 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
422 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
423 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
424 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
425 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
426 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
427 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
428 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
429 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
430 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
431 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
432 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
433 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
434 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
435 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
436 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
437 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
438 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
439 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
440 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
441 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
442 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
443 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
444 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
445 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
446 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
447 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
448 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
449 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
450 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
451 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
452 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
453 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
454 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
455 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
456 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
457 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
458 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
459 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
460 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
461 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
462 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
463 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
464 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
465 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
466 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
467 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
468 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
469 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
470 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
471 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
472 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
473 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
474 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
475 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
476 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
477 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
478 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
479 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
480 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
481 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
482 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
483 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
484 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
485 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
486 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
487 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
488 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
489 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
490 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
491 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
492 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
493 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
494 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
495 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
496 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
497 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
498 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
499 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
500 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
501 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
504 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
505 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
506 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
508 /* ST Microelectronics */
509 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
512 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
513 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
514 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
515 .class = PCI_CLASS_STORAGE_SATA_AHCI,
516 .class_mask = 0xffffff,
517 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
518 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
519 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
520 { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
521 PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
522 .driver_data = board_ahci_yes_fbs }, /* 88se9170 */
523 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
524 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
525 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
526 .driver_data = board_ahci_yes_fbs }, /* 88se9182 */
527 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
528 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
529 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
530 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
531 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
532 .driver_data = board_ahci_yes_fbs },
533 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2), /* 88se91a2 */
534 .driver_data = board_ahci_yes_fbs },
535 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
536 .driver_data = board_ahci_yes_fbs },
537 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
538 .driver_data = board_ahci_yes_fbs },
539 { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
540 .driver_data = board_ahci_yes_fbs },
543 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
544 { PCI_VDEVICE(PROMISE, 0x3781), board_ahci }, /* FastTrak TX8660 ahci-mode */
547 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
548 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
549 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
550 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
553 * Samsung SSDs found on some macbooks. NCQ times out if MSI is
554 * enabled. https://bugzilla.kernel.org/show_bug.cgi?id=60731
556 { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
557 { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
560 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
562 /* Generic, PCI class code for AHCI */
563 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
564 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
566 { } /* terminate list */
570 static struct pci_driver ahci_pci_driver = {
572 .id_table = ahci_pci_tbl,
573 .probe = ahci_init_one,
574 .remove = ata_pci_remove_one,
576 .suspend = ahci_pci_device_suspend,
577 .resume = ahci_pci_device_resume,
581 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
582 static int marvell_enable;
584 static int marvell_enable = 1;
586 module_param(marvell_enable, int, 0644);
587 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
590 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
591 struct ahci_host_priv *hpriv)
593 unsigned int force_port_map = 0;
594 unsigned int mask_port_map = 0;
596 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
597 dev_info(&pdev->dev, "JMB361 has only one port\n");
602 * Temporary Marvell 6145 hack: PATA port presence
603 * is asserted through the standard AHCI port
604 * presence register, as bit 4 (counting from 0)
606 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
607 if (pdev->device == 0x6121)
612 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
615 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
619 static int ahci_pci_reset_controller(struct ata_host *host)
621 struct pci_dev *pdev = to_pci_dev(host->dev);
623 ahci_reset_controller(host);
625 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
626 struct ahci_host_priv *hpriv = host->private_data;
630 pci_read_config_word(pdev, 0x92, &tmp16);
631 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
632 tmp16 |= hpriv->port_map;
633 pci_write_config_word(pdev, 0x92, tmp16);
640 static void ahci_pci_init_controller(struct ata_host *host)
642 struct ahci_host_priv *hpriv = host->private_data;
643 struct pci_dev *pdev = to_pci_dev(host->dev);
644 void __iomem *port_mmio;
648 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
649 if (pdev->device == 0x6121)
653 port_mmio = __ahci_port_base(host, mv);
655 writel(0, port_mmio + PORT_IRQ_MASK);
658 tmp = readl(port_mmio + PORT_IRQ_STAT);
659 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
661 writel(tmp, port_mmio + PORT_IRQ_STAT);
664 ahci_init_controller(host);
667 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
668 unsigned long deadline)
670 struct ata_port *ap = link->ap;
676 ahci_stop_engine(ap);
678 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
679 deadline, &online, NULL);
681 ahci_start_engine(ap);
683 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
685 /* vt8251 doesn't clear BSY on signature FIS reception,
686 * request follow-up softreset.
688 return online ? -EAGAIN : rc;
691 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
692 unsigned long deadline)
694 struct ata_port *ap = link->ap;
695 struct ahci_port_priv *pp = ap->private_data;
696 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
697 struct ata_taskfile tf;
701 ahci_stop_engine(ap);
703 /* clear D2H reception area to properly wait for D2H FIS */
704 ata_tf_init(link->device, &tf);
706 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
708 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
709 deadline, &online, NULL);
711 ahci_start_engine(ap);
713 /* The pseudo configuration device on SIMG4726 attached to
714 * ASUS P5W-DH Deluxe doesn't send signature FIS after
715 * hardreset if no device is attached to the first downstream
716 * port && the pseudo device locks up on SRST w/ PMP==0. To
717 * work around this, wait for !BSY only briefly. If BSY isn't
718 * cleared, perform CLO and proceed to IDENTIFY (achieved by
719 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
721 * Wait for two seconds. Devices attached to downstream port
722 * which can't process the following IDENTIFY after this will
723 * have to be reset again. For most cases, this should
724 * suffice while making probing snappish enough.
727 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
730 ahci_kick_engine(ap);
736 * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
738 * It has been observed with some SSDs that the timing of events in the
739 * link synchronization phase can leave the port in a state that can not
740 * be recovered by a SATA-hard-reset alone. The failing signature is
741 * SStatus.DET stuck at 1 ("Device presence detected but Phy
742 * communication not established"). It was found that unloading and
743 * reloading the driver when this problem occurs allows the drive
744 * connection to be recovered (DET advanced to 0x3). The critical
745 * component of reloading the driver is that the port state machines are
746 * reset by bouncing "port enable" in the AHCI PCS configuration
747 * register. So, reproduce that effect by bouncing a port whenever we
748 * see DET==1 after a reset.
750 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
751 unsigned long deadline)
753 const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
754 struct ata_port *ap = link->ap;
755 struct ahci_port_priv *pp = ap->private_data;
756 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
757 unsigned long tmo = deadline - jiffies;
758 struct ata_taskfile tf;
764 ahci_stop_engine(ap);
766 for (i = 0; i < 2; i++) {
769 int port = ap->port_no;
770 struct ata_host *host = ap->host;
771 struct pci_dev *pdev = to_pci_dev(host->dev);
773 /* clear D2H reception area to properly wait for D2H FIS */
774 ata_tf_init(link->device, &tf);
775 tf.command = ATA_BUSY;
776 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
778 rc = sata_link_hardreset(link, timing, deadline, &online,
781 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
782 (sstatus & 0xf) != 1)
785 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
788 pci_read_config_word(pdev, 0x92, &val);
790 pci_write_config_word(pdev, 0x92, val);
791 ata_msleep(ap, 1000);
793 pci_write_config_word(pdev, 0x92, val);
797 ahci_start_engine(ap);
800 *class = ahci_dev_classify(ap);
802 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
808 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
810 struct ata_host *host = dev_get_drvdata(&pdev->dev);
811 struct ahci_host_priv *hpriv = host->private_data;
812 void __iomem *mmio = hpriv->mmio;
815 if (mesg.event & PM_EVENT_SUSPEND &&
816 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
818 "BIOS update required for suspend/resume\n");
822 if (mesg.event & PM_EVENT_SLEEP) {
823 /* AHCI spec rev1.1 section 8.3.3:
824 * Software must disable interrupts prior to requesting a
825 * transition of the HBA to D3 state.
827 ctl = readl(mmio + HOST_CTL);
829 writel(ctl, mmio + HOST_CTL);
830 readl(mmio + HOST_CTL); /* flush */
833 return ata_pci_device_suspend(pdev, mesg);
836 static int ahci_pci_device_resume(struct pci_dev *pdev)
838 struct ata_host *host = dev_get_drvdata(&pdev->dev);
841 rc = ata_pci_device_do_resume(pdev);
845 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
846 rc = ahci_pci_reset_controller(host);
850 ahci_pci_init_controller(host);
853 ata_host_resume(host);
859 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
864 * If the device fixup already set the dma_mask to some non-standard
865 * value, don't extend it here. This happens on STA2X11, for example.
867 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
871 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
872 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
874 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
877 "64-bit DMA enable failed\n");
882 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
884 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
887 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
890 "32-bit consistent DMA enable failed\n");
897 static void ahci_pci_print_info(struct ata_host *host)
899 struct pci_dev *pdev = to_pci_dev(host->dev);
903 pci_read_config_word(pdev, 0x0a, &cc);
904 if (cc == PCI_CLASS_STORAGE_IDE)
906 else if (cc == PCI_CLASS_STORAGE_SATA)
908 else if (cc == PCI_CLASS_STORAGE_RAID)
913 ahci_print_info(host, scc_s);
916 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
917 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
918 * support PMP and the 4726 either directly exports the device
919 * attached to the first downstream port or acts as a hardware storage
920 * controller and emulate a single ATA device (can be RAID 0/1 or some
921 * other configuration).
923 * When there's no device attached to the first downstream port of the
924 * 4726, "Config Disk" appears, which is a pseudo ATA device to
925 * configure the 4726. However, ATA emulation of the device is very
926 * lame. It doesn't send signature D2H Reg FIS after the initial
927 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
929 * The following function works around the problem by always using
930 * hardreset on the port and not depending on receiving signature FIS
931 * afterward. If signature FIS isn't received soon, ATA class is
932 * assumed without follow-up softreset.
934 static void ahci_p5wdh_workaround(struct ata_host *host)
936 static struct dmi_system_id sysids[] = {
938 .ident = "P5W DH Deluxe",
940 DMI_MATCH(DMI_SYS_VENDOR,
941 "ASUSTEK COMPUTER INC"),
942 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
947 struct pci_dev *pdev = to_pci_dev(host->dev);
949 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
950 dmi_check_system(sysids)) {
951 struct ata_port *ap = host->ports[1];
954 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
956 ap->ops = &ahci_p5wdh_ops;
957 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
961 /* only some SB600 ahci controllers can do 64bit DMA */
962 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
964 static const struct dmi_system_id sysids[] = {
966 * The oldest version known to be broken is 0901 and
967 * working is 1501 which was released on 2007-10-26.
968 * Enable 64bit DMA on 1501 and anything newer.
970 * Please read bko#9412 for more info.
973 .ident = "ASUS M2A-VM",
975 DMI_MATCH(DMI_BOARD_VENDOR,
976 "ASUSTeK Computer INC."),
977 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
979 .driver_data = "20071026", /* yyyymmdd */
982 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
985 * BIOS versions earlier than 1.5 had the Manufacturer DMI
986 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
987 * This spelling mistake was fixed in BIOS version 1.5, so
988 * 1.5 and later have the Manufacturer as
989 * "MICRO-STAR INTERNATIONAL CO.,LTD".
990 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
992 * BIOS versions earlier than 1.9 had a Board Product Name
993 * DMI field of "MS-7376". This was changed to be
994 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
995 * match on DMI_BOARD_NAME of "MS-7376".
998 .ident = "MSI K9A2 Platinum",
1000 DMI_MATCH(DMI_BOARD_VENDOR,
1001 "MICRO-STAR INTER"),
1002 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1006 * All BIOS versions for the Asus M3A support 64bit DMA.
1007 * (all release versions from 0301 to 1206 were tested)
1010 .ident = "ASUS M3A",
1012 DMI_MATCH(DMI_BOARD_VENDOR,
1013 "ASUSTeK Computer INC."),
1014 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1019 const struct dmi_system_id *match;
1020 int year, month, date;
1023 match = dmi_first_match(sysids);
1024 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1028 if (!match->driver_data)
1031 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1032 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1034 if (strcmp(buf, match->driver_data) >= 0)
1037 dev_warn(&pdev->dev,
1038 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1044 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1048 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1050 static const struct dmi_system_id broken_systems[] = {
1052 .ident = "HP Compaq nx6310",
1054 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1055 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1057 /* PCI slot number of the controller */
1058 .driver_data = (void *)0x1FUL,
1061 .ident = "HP Compaq 6720s",
1063 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1064 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1066 /* PCI slot number of the controller */
1067 .driver_data = (void *)0x1FUL,
1070 { } /* terminate list */
1072 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1075 unsigned long slot = (unsigned long)dmi->driver_data;
1076 /* apply the quirk only to on-board controllers */
1077 return slot == PCI_SLOT(pdev->devfn);
1083 static bool ahci_broken_suspend(struct pci_dev *pdev)
1085 static const struct dmi_system_id sysids[] = {
1087 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1088 * to the harddisk doesn't become online after
1089 * resuming from STR. Warn and fail suspend.
1091 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1093 * Use dates instead of versions to match as HP is
1094 * apparently recycling both product and version
1097 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1102 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1103 DMI_MATCH(DMI_PRODUCT_NAME,
1104 "HP Pavilion dv4 Notebook PC"),
1106 .driver_data = "20090105", /* F.30 */
1111 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1112 DMI_MATCH(DMI_PRODUCT_NAME,
1113 "HP Pavilion dv5 Notebook PC"),
1115 .driver_data = "20090506", /* F.16 */
1120 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1121 DMI_MATCH(DMI_PRODUCT_NAME,
1122 "HP Pavilion dv6 Notebook PC"),
1124 .driver_data = "20090423", /* F.21 */
1129 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1130 DMI_MATCH(DMI_PRODUCT_NAME,
1131 "HP HDX18 Notebook PC"),
1133 .driver_data = "20090430", /* F.23 */
1136 * Acer eMachines G725 has the same problem. BIOS
1137 * V1.03 is known to be broken. V3.04 is known to
1138 * work. Between, there are V1.06, V2.06 and V3.03
1139 * that we don't have much idea about. For now,
1140 * blacklist anything older than V3.04.
1142 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1147 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1148 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1150 .driver_data = "20091216", /* V3.04 */
1152 { } /* terminate list */
1154 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1155 int year, month, date;
1158 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1161 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1162 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1164 return strcmp(buf, dmi->driver_data) < 0;
1167 static bool ahci_broken_online(struct pci_dev *pdev)
1169 #define ENCODE_BUSDEVFN(bus, slot, func) \
1170 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1171 static const struct dmi_system_id sysids[] = {
1173 * There are several gigabyte boards which use
1174 * SIMG5723s configured as hardware RAID. Certain
1175 * 5723 firmware revisions shipped there keep the link
1176 * online but fail to answer properly to SRST or
1177 * IDENTIFY when no device is attached downstream
1178 * causing libata to retry quite a few times leading
1179 * to excessive detection delay.
1181 * As these firmwares respond to the second reset try
1182 * with invalid device signature, considering unknown
1183 * sig as offline works around the problem acceptably.
1186 .ident = "EP45-DQ6",
1188 DMI_MATCH(DMI_BOARD_VENDOR,
1189 "Gigabyte Technology Co., Ltd."),
1190 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1192 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1195 .ident = "EP45-DS5",
1197 DMI_MATCH(DMI_BOARD_VENDOR,
1198 "Gigabyte Technology Co., Ltd."),
1199 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1201 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1203 { } /* terminate list */
1205 #undef ENCODE_BUSDEVFN
1206 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1212 val = (unsigned long)dmi->driver_data;
1214 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1217 #ifdef CONFIG_ATA_ACPI
1218 static void ahci_gtf_filter_workaround(struct ata_host *host)
1220 static const struct dmi_system_id sysids[] = {
1222 * Aspire 3810T issues a bunch of SATA enable commands
1223 * via _GTF including an invalid one and one which is
1224 * rejected by the device. Among the successful ones
1225 * is FPDMA non-zero offset enable which when enabled
1226 * only on the drive side leads to NCQ command
1227 * failures. Filter it out.
1230 .ident = "Aspire 3810T",
1232 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1233 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1235 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1239 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1240 unsigned int filter;
1246 filter = (unsigned long)dmi->driver_data;
1247 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1248 filter, dmi->ident);
1250 for (i = 0; i < host->n_ports; i++) {
1251 struct ata_port *ap = host->ports[i];
1252 struct ata_link *link;
1253 struct ata_device *dev;
1255 ata_for_each_link(link, ap, EDGE)
1256 ata_for_each_dev(dev, link, ALL)
1257 dev->gtf_filter |= filter;
1261 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1265 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1267 unsigned int board_id = ent->driver_data;
1268 struct ata_port_info pi = ahci_port_info[board_id];
1269 const struct ata_port_info *ppi[] = { &pi, NULL };
1270 struct device *dev = &pdev->dev;
1271 struct ahci_host_priv *hpriv;
1272 struct ata_host *host;
1274 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1278 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1280 ata_print_version_once(&pdev->dev, DRV_VERSION);
1282 /* The AHCI driver can only drive the SATA ports, the PATA driver
1283 can drive them all so if both drivers are selected make sure
1284 AHCI stays out of the way */
1285 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1289 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1290 * ahci, use ata_generic instead.
1292 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1293 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1294 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1295 pdev->subsystem_device == 0xcb89)
1298 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1299 * At the moment, we can only use the AHCI mode. Let the users know
1300 * that for SAS drives they're out of luck.
1302 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1303 dev_info(&pdev->dev,
1304 "PDC42819 can only drive SATA devices with this driver\n");
1306 /* Both Connext and Enmotus devices use non-standard BARs */
1307 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1308 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1309 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1310 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1312 /* acquire resources */
1313 rc = pcim_enable_device(pdev);
1317 /* AHCI controllers often implement SFF compatible interface.
1318 * Grab all PCI BARs just in case.
1320 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1322 pcim_pin_device(pdev);
1326 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1327 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1330 /* ICH6s share the same PCI ID for both piix and ahci
1331 * modes. Enabling ahci mode while MAP indicates
1332 * combined mode is a bad idea. Yield to ata_piix.
1334 pci_read_config_byte(pdev, ICH_MAP, &map);
1336 dev_info(&pdev->dev,
1337 "controller is in combined mode, can't enable AHCI mode\n");
1342 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1345 hpriv->flags |= (unsigned long)pi.private_data;
1347 /* MCP65 revision A1 and A2 can't do MSI */
1348 if (board_id == board_ahci_mcp65 &&
1349 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1350 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1352 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1353 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1354 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1356 /* only some SB600s can do 64bit DMA */
1357 if (ahci_sb600_enable_64bit(pdev))
1358 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1360 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1363 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1365 /* save initial config */
1366 ahci_pci_save_initial_config(pdev, hpriv);
1369 if (hpriv->cap & HOST_CAP_NCQ) {
1370 pi.flags |= ATA_FLAG_NCQ;
1372 * Auto-activate optimization is supposed to be
1373 * supported on all AHCI controllers indicating NCQ
1374 * capability, but it seems to be broken on some
1375 * chipsets including NVIDIAs.
1377 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1378 pi.flags |= ATA_FLAG_FPDMA_AA;
1381 if (hpriv->cap & HOST_CAP_PMP)
1382 pi.flags |= ATA_FLAG_PMP;
1384 ahci_set_em_messages(hpriv, &pi);
1386 if (ahci_broken_system_poweroff(pdev)) {
1387 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1388 dev_info(&pdev->dev,
1389 "quirky BIOS, skipping spindown on poweroff\n");
1392 if (ahci_broken_suspend(pdev)) {
1393 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1394 dev_warn(&pdev->dev,
1395 "BIOS update required for suspend/resume\n");
1398 if (ahci_broken_online(pdev)) {
1399 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1400 dev_info(&pdev->dev,
1401 "online status unreliable, applying workaround\n");
1404 /* CAP.NP sometimes indicate the index of the last enabled
1405 * port, at other times, that of the last possible port, so
1406 * determining the maximum port number requires looking at
1407 * both CAP.NP and port_map.
1409 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1411 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1414 host->private_data = hpriv;
1416 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1417 host->flags |= ATA_HOST_PARALLEL_SCAN;
1419 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1421 if (pi.flags & ATA_FLAG_EM)
1422 ahci_reset_em(host);
1424 for (i = 0; i < host->n_ports; i++) {
1425 struct ata_port *ap = host->ports[i];
1427 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1428 ata_port_pbar_desc(ap, ahci_pci_bar,
1429 0x100 + ap->port_no * 0x80, "port");
1431 /* set enclosure management message type */
1432 if (ap->flags & ATA_FLAG_EM)
1433 ap->em_message_type = hpriv->em_msg_type;
1436 /* disabled/not-implemented port */
1437 if (!(hpriv->port_map & (1 << i)))
1438 ap->ops = &ata_dummy_port_ops;
1441 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1442 ahci_p5wdh_workaround(host);
1444 /* apply gtf filter quirk */
1445 ahci_gtf_filter_workaround(host);
1447 /* initialize adapter */
1448 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1452 rc = ahci_pci_reset_controller(host);
1456 ahci_pci_init_controller(host);
1457 ahci_pci_print_info(host);
1459 pci_set_master(pdev);
1460 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1464 static int __init ahci_init(void)
1466 return pci_register_driver(&ahci_pci_driver);
1469 static void __exit ahci_exit(void)
1471 pci_unregister_driver(&ahci_pci_driver);
1475 MODULE_AUTHOR("Jeff Garzik");
1476 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1477 MODULE_LICENSE("GPL");
1478 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1479 MODULE_VERSION(DRV_VERSION);
1481 module_init(ahci_init);
1482 module_exit(ahci_exit);