2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
59 /* board IDs by feature in alphabetical order */
65 /* board IDs for specific chipsets in alphabetical order */
71 board_ahci_sb700, /* for SB700 and SB800 */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
87 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
88 static int ahci_pci_device_resume(struct pci_dev *pdev);
91 static struct scsi_host_template ahci_sht = {
95 static struct ata_port_operations ahci_vt8251_ops = {
96 .inherits = &ahci_ops,
97 .hardreset = ahci_vt8251_hardreset,
100 static struct ata_port_operations ahci_p5wdh_ops = {
101 .inherits = &ahci_ops,
102 .hardreset = ahci_p5wdh_hardreset,
105 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
107 static const struct ata_port_info ahci_port_info[] = {
111 .flags = AHCI_FLAG_COMMON,
112 .pio_mask = ATA_PIO4,
113 .udma_mask = ATA_UDMA6,
114 .port_ops = &ahci_ops,
116 [board_ahci_ign_iferr] =
118 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
124 [board_ahci_nosntf] =
126 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
132 [board_ahci_yes_fbs] =
134 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
143 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
145 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
146 .pio_mask = ATA_PIO4,
147 .udma_mask = ATA_UDMA6,
148 .port_ops = &ahci_ops,
152 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
153 .flags = AHCI_FLAG_COMMON,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
168 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
169 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
170 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
171 .pio_mask = ATA_PIO4,
172 .udma_mask = ATA_UDMA6,
173 .port_ops = &ahci_ops,
177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
178 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
179 AHCI_HFLAG_32BIT_ONLY),
180 .flags = AHCI_FLAG_COMMON,
181 .pio_mask = ATA_PIO4,
182 .udma_mask = ATA_UDMA6,
183 .port_ops = &ahci_pmp_retry_srst_ops,
185 [board_ahci_sb700] = /* for SB700 and SB800 */
187 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
188 .flags = AHCI_FLAG_COMMON,
189 .pio_mask = ATA_PIO4,
190 .udma_mask = ATA_UDMA6,
191 .port_ops = &ahci_pmp_retry_srst_ops,
193 [board_ahci_vt8251] =
195 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
196 .flags = AHCI_FLAG_COMMON,
197 .pio_mask = ATA_PIO4,
198 .udma_mask = ATA_UDMA6,
199 .port_ops = &ahci_vt8251_ops,
203 static const struct pci_device_id ahci_pci_tbl[] = {
205 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
206 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
207 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
208 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
209 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
210 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
211 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
212 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
213 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
215 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
216 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
217 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
218 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
219 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
220 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
221 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
222 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
226 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
227 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
233 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
234 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
235 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
236 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
237 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
238 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
239 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
240 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
241 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
242 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
244 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
245 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
246 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
248 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
249 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
251 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
252 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
253 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
254 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
255 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
256 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
257 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
258 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
259 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
260 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
264 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
265 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
266 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
269 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
270 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
271 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
272 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
278 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
279 /* AMD is using RAID class only for ahci controllers */
280 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
281 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
284 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
285 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
288 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
289 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
290 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
297 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
298 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
309 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
310 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
325 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
326 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
337 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
349 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
361 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
362 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
375 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
376 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
379 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
380 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
381 { PCI_DEVICE(0x1b4b, 0x9123),
382 .class = PCI_CLASS_STORAGE_SATA_AHCI,
383 .class_mask = 0xffffff,
384 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
385 { PCI_DEVICE(0x1b4b, 0x9125),
386 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
387 { PCI_DEVICE(0x1b4b, 0x917a),
388 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
389 { PCI_DEVICE(0x1b4b, 0x9192),
390 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
391 { PCI_DEVICE(0x1b4b, 0x91a3),
392 .driver_data = board_ahci_yes_fbs },
395 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
398 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1061 */
400 /* Generic, PCI class code for AHCI */
401 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
402 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
404 { } /* terminate list */
408 static struct pci_driver ahci_pci_driver = {
410 .id_table = ahci_pci_tbl,
411 .probe = ahci_init_one,
412 .remove = ata_pci_remove_one,
414 .suspend = ahci_pci_device_suspend,
415 .resume = ahci_pci_device_resume,
419 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
420 static int marvell_enable;
422 static int marvell_enable = 1;
424 module_param(marvell_enable, int, 0644);
425 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
428 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
429 struct ahci_host_priv *hpriv)
431 unsigned int force_port_map = 0;
432 unsigned int mask_port_map = 0;
434 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
435 dev_info(&pdev->dev, "JMB361 has only one port\n");
440 * Temporary Marvell 6145 hack: PATA port presence
441 * is asserted through the standard AHCI port
442 * presence register, as bit 4 (counting from 0)
444 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
445 if (pdev->device == 0x6121)
450 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
453 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
457 static int ahci_pci_reset_controller(struct ata_host *host)
459 struct pci_dev *pdev = to_pci_dev(host->dev);
461 ahci_reset_controller(host);
463 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
464 struct ahci_host_priv *hpriv = host->private_data;
468 pci_read_config_word(pdev, 0x92, &tmp16);
469 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
470 tmp16 |= hpriv->port_map;
471 pci_write_config_word(pdev, 0x92, tmp16);
478 static void ahci_pci_init_controller(struct ata_host *host)
480 struct ahci_host_priv *hpriv = host->private_data;
481 struct pci_dev *pdev = to_pci_dev(host->dev);
482 void __iomem *port_mmio;
486 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
487 if (pdev->device == 0x6121)
491 port_mmio = __ahci_port_base(host, mv);
493 writel(0, port_mmio + PORT_IRQ_MASK);
496 tmp = readl(port_mmio + PORT_IRQ_STAT);
497 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
499 writel(tmp, port_mmio + PORT_IRQ_STAT);
502 ahci_init_controller(host);
505 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
506 unsigned long deadline)
508 struct ata_port *ap = link->ap;
514 ahci_stop_engine(ap);
516 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
517 deadline, &online, NULL);
519 ahci_start_engine(ap);
521 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
523 /* vt8251 doesn't clear BSY on signature FIS reception,
524 * request follow-up softreset.
526 return online ? -EAGAIN : rc;
529 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
530 unsigned long deadline)
532 struct ata_port *ap = link->ap;
533 struct ahci_port_priv *pp = ap->private_data;
534 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
535 struct ata_taskfile tf;
539 ahci_stop_engine(ap);
541 /* clear D2H reception area to properly wait for D2H FIS */
542 ata_tf_init(link->device, &tf);
544 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
546 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
547 deadline, &online, NULL);
549 ahci_start_engine(ap);
551 /* The pseudo configuration device on SIMG4726 attached to
552 * ASUS P5W-DH Deluxe doesn't send signature FIS after
553 * hardreset if no device is attached to the first downstream
554 * port && the pseudo device locks up on SRST w/ PMP==0. To
555 * work around this, wait for !BSY only briefly. If BSY isn't
556 * cleared, perform CLO and proceed to IDENTIFY (achieved by
557 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
559 * Wait for two seconds. Devices attached to downstream port
560 * which can't process the following IDENTIFY after this will
561 * have to be reset again. For most cases, this should
562 * suffice while making probing snappish enough.
565 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
568 ahci_kick_engine(ap);
574 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
576 struct ata_host *host = dev_get_drvdata(&pdev->dev);
577 struct ahci_host_priv *hpriv = host->private_data;
578 void __iomem *mmio = hpriv->mmio;
581 if (mesg.event & PM_EVENT_SUSPEND &&
582 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
584 "BIOS update required for suspend/resume\n");
588 if (mesg.event & PM_EVENT_SLEEP) {
589 /* AHCI spec rev1.1 section 8.3.3:
590 * Software must disable interrupts prior to requesting a
591 * transition of the HBA to D3 state.
593 ctl = readl(mmio + HOST_CTL);
595 writel(ctl, mmio + HOST_CTL);
596 readl(mmio + HOST_CTL); /* flush */
599 return ata_pci_device_suspend(pdev, mesg);
602 static int ahci_pci_device_resume(struct pci_dev *pdev)
604 struct ata_host *host = dev_get_drvdata(&pdev->dev);
607 rc = ata_pci_device_do_resume(pdev);
611 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
612 rc = ahci_pci_reset_controller(host);
616 ahci_pci_init_controller(host);
619 ata_host_resume(host);
625 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
630 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
631 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
633 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
636 "64-bit DMA enable failed\n");
641 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
643 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
646 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
649 "32-bit consistent DMA enable failed\n");
656 static void ahci_pci_print_info(struct ata_host *host)
658 struct pci_dev *pdev = to_pci_dev(host->dev);
662 pci_read_config_word(pdev, 0x0a, &cc);
663 if (cc == PCI_CLASS_STORAGE_IDE)
665 else if (cc == PCI_CLASS_STORAGE_SATA)
667 else if (cc == PCI_CLASS_STORAGE_RAID)
672 ahci_print_info(host, scc_s);
675 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
676 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
677 * support PMP and the 4726 either directly exports the device
678 * attached to the first downstream port or acts as a hardware storage
679 * controller and emulate a single ATA device (can be RAID 0/1 or some
680 * other configuration).
682 * When there's no device attached to the first downstream port of the
683 * 4726, "Config Disk" appears, which is a pseudo ATA device to
684 * configure the 4726. However, ATA emulation of the device is very
685 * lame. It doesn't send signature D2H Reg FIS after the initial
686 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
688 * The following function works around the problem by always using
689 * hardreset on the port and not depending on receiving signature FIS
690 * afterward. If signature FIS isn't received soon, ATA class is
691 * assumed without follow-up softreset.
693 static void ahci_p5wdh_workaround(struct ata_host *host)
695 static struct dmi_system_id sysids[] = {
697 .ident = "P5W DH Deluxe",
699 DMI_MATCH(DMI_SYS_VENDOR,
700 "ASUSTEK COMPUTER INC"),
701 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
706 struct pci_dev *pdev = to_pci_dev(host->dev);
708 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
709 dmi_check_system(sysids)) {
710 struct ata_port *ap = host->ports[1];
713 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
715 ap->ops = &ahci_p5wdh_ops;
716 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
720 /* only some SB600 ahci controllers can do 64bit DMA */
721 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
723 static const struct dmi_system_id sysids[] = {
725 * The oldest version known to be broken is 0901 and
726 * working is 1501 which was released on 2007-10-26.
727 * Enable 64bit DMA on 1501 and anything newer.
729 * Please read bko#9412 for more info.
732 .ident = "ASUS M2A-VM",
734 DMI_MATCH(DMI_BOARD_VENDOR,
735 "ASUSTeK Computer INC."),
736 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
738 .driver_data = "20071026", /* yyyymmdd */
741 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
744 * BIOS versions earlier than 1.5 had the Manufacturer DMI
745 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
746 * This spelling mistake was fixed in BIOS version 1.5, so
747 * 1.5 and later have the Manufacturer as
748 * "MICRO-STAR INTERNATIONAL CO.,LTD".
749 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
751 * BIOS versions earlier than 1.9 had a Board Product Name
752 * DMI field of "MS-7376". This was changed to be
753 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
754 * match on DMI_BOARD_NAME of "MS-7376".
757 .ident = "MSI K9A2 Platinum",
759 DMI_MATCH(DMI_BOARD_VENDOR,
761 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
765 * All BIOS versions for the Asus M3A support 64bit DMA.
766 * (all release versions from 0301 to 1206 were tested)
771 DMI_MATCH(DMI_BOARD_VENDOR,
772 "ASUSTeK Computer INC."),
773 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
778 const struct dmi_system_id *match;
779 int year, month, date;
782 match = dmi_first_match(sysids);
783 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
787 if (!match->driver_data)
790 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
791 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
793 if (strcmp(buf, match->driver_data) >= 0)
797 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
803 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
807 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
809 static const struct dmi_system_id broken_systems[] = {
811 .ident = "HP Compaq nx6310",
813 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
814 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
816 /* PCI slot number of the controller */
817 .driver_data = (void *)0x1FUL,
820 .ident = "HP Compaq 6720s",
822 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
823 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
825 /* PCI slot number of the controller */
826 .driver_data = (void *)0x1FUL,
829 { } /* terminate list */
831 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
834 unsigned long slot = (unsigned long)dmi->driver_data;
835 /* apply the quirk only to on-board controllers */
836 return slot == PCI_SLOT(pdev->devfn);
842 static bool ahci_broken_suspend(struct pci_dev *pdev)
844 static const struct dmi_system_id sysids[] = {
846 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
847 * to the harddisk doesn't become online after
848 * resuming from STR. Warn and fail suspend.
850 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
852 * Use dates instead of versions to match as HP is
853 * apparently recycling both product and version
856 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
861 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
862 DMI_MATCH(DMI_PRODUCT_NAME,
863 "HP Pavilion dv4 Notebook PC"),
865 .driver_data = "20090105", /* F.30 */
870 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
871 DMI_MATCH(DMI_PRODUCT_NAME,
872 "HP Pavilion dv5 Notebook PC"),
874 .driver_data = "20090506", /* F.16 */
879 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
880 DMI_MATCH(DMI_PRODUCT_NAME,
881 "HP Pavilion dv6 Notebook PC"),
883 .driver_data = "20090423", /* F.21 */
888 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
889 DMI_MATCH(DMI_PRODUCT_NAME,
890 "HP HDX18 Notebook PC"),
892 .driver_data = "20090430", /* F.23 */
895 * Acer eMachines G725 has the same problem. BIOS
896 * V1.03 is known to be broken. V3.04 is known to
897 * work. Between, there are V1.06, V2.06 and V3.03
898 * that we don't have much idea about. For now,
899 * blacklist anything older than V3.04.
901 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
906 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
907 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
909 .driver_data = "20091216", /* V3.04 */
911 { } /* terminate list */
913 const struct dmi_system_id *dmi = dmi_first_match(sysids);
914 int year, month, date;
917 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
920 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
921 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
923 return strcmp(buf, dmi->driver_data) < 0;
926 static bool ahci_broken_online(struct pci_dev *pdev)
928 #define ENCODE_BUSDEVFN(bus, slot, func) \
929 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
930 static const struct dmi_system_id sysids[] = {
932 * There are several gigabyte boards which use
933 * SIMG5723s configured as hardware RAID. Certain
934 * 5723 firmware revisions shipped there keep the link
935 * online but fail to answer properly to SRST or
936 * IDENTIFY when no device is attached downstream
937 * causing libata to retry quite a few times leading
938 * to excessive detection delay.
940 * As these firmwares respond to the second reset try
941 * with invalid device signature, considering unknown
942 * sig as offline works around the problem acceptably.
947 DMI_MATCH(DMI_BOARD_VENDOR,
948 "Gigabyte Technology Co., Ltd."),
949 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
951 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
956 DMI_MATCH(DMI_BOARD_VENDOR,
957 "Gigabyte Technology Co., Ltd."),
958 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
960 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
962 { } /* terminate list */
964 #undef ENCODE_BUSDEVFN
965 const struct dmi_system_id *dmi = dmi_first_match(sysids);
971 val = (unsigned long)dmi->driver_data;
973 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
976 #ifdef CONFIG_ATA_ACPI
977 static void ahci_gtf_filter_workaround(struct ata_host *host)
979 static const struct dmi_system_id sysids[] = {
981 * Aspire 3810T issues a bunch of SATA enable commands
982 * via _GTF including an invalid one and one which is
983 * rejected by the device. Among the successful ones
984 * is FPDMA non-zero offset enable which when enabled
985 * only on the drive side leads to NCQ command
986 * failures. Filter it out.
989 .ident = "Aspire 3810T",
991 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
992 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
994 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
998 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1005 filter = (unsigned long)dmi->driver_data;
1006 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1007 filter, dmi->ident);
1009 for (i = 0; i < host->n_ports; i++) {
1010 struct ata_port *ap = host->ports[i];
1011 struct ata_link *link;
1012 struct ata_device *dev;
1014 ata_for_each_link(link, ap, EDGE)
1015 ata_for_each_dev(dev, link, ALL)
1016 dev->gtf_filter |= filter;
1020 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1024 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1026 unsigned int board_id = ent->driver_data;
1027 struct ata_port_info pi = ahci_port_info[board_id];
1028 const struct ata_port_info *ppi[] = { &pi, NULL };
1029 struct device *dev = &pdev->dev;
1030 struct ahci_host_priv *hpriv;
1031 struct ata_host *host;
1036 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1038 ata_print_version_once(&pdev->dev, DRV_VERSION);
1040 /* The AHCI driver can only drive the SATA ports, the PATA driver
1041 can drive them all so if both drivers are selected make sure
1042 AHCI stays out of the way */
1043 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1047 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1048 * ahci, use ata_generic instead.
1050 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1051 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1052 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1053 pdev->subsystem_device == 0xcb89)
1056 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1057 * At the moment, we can only use the AHCI mode. Let the users know
1058 * that for SAS drives they're out of luck.
1060 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1061 dev_info(&pdev->dev,
1062 "PDC42819 can only drive SATA devices with this driver\n");
1064 /* acquire resources */
1065 rc = pcim_enable_device(pdev);
1069 /* AHCI controllers often implement SFF compatible interface.
1070 * Grab all PCI BARs just in case.
1072 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1074 pcim_pin_device(pdev);
1078 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1079 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1082 /* ICH6s share the same PCI ID for both piix and ahci
1083 * modes. Enabling ahci mode while MAP indicates
1084 * combined mode is a bad idea. Yield to ata_piix.
1086 pci_read_config_byte(pdev, ICH_MAP, &map);
1088 dev_info(&pdev->dev,
1089 "controller is in combined mode, can't enable AHCI mode\n");
1094 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1097 hpriv->flags |= (unsigned long)pi.private_data;
1099 /* MCP65 revision A1 and A2 can't do MSI */
1100 if (board_id == board_ahci_mcp65 &&
1101 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1102 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1104 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1105 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1106 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1108 /* only some SB600s can do 64bit DMA */
1109 if (ahci_sb600_enable_64bit(pdev))
1110 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1112 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1115 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1117 /* save initial config */
1118 ahci_pci_save_initial_config(pdev, hpriv);
1121 if (hpriv->cap & HOST_CAP_NCQ) {
1122 pi.flags |= ATA_FLAG_NCQ;
1124 * Auto-activate optimization is supposed to be
1125 * supported on all AHCI controllers indicating NCQ
1126 * capability, but it seems to be broken on some
1127 * chipsets including NVIDIAs.
1129 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1130 pi.flags |= ATA_FLAG_FPDMA_AA;
1133 if (hpriv->cap & HOST_CAP_PMP)
1134 pi.flags |= ATA_FLAG_PMP;
1136 ahci_set_em_messages(hpriv, &pi);
1138 if (ahci_broken_system_poweroff(pdev)) {
1139 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1140 dev_info(&pdev->dev,
1141 "quirky BIOS, skipping spindown on poweroff\n");
1144 if (ahci_broken_suspend(pdev)) {
1145 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1146 dev_warn(&pdev->dev,
1147 "BIOS update required for suspend/resume\n");
1150 if (ahci_broken_online(pdev)) {
1151 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1152 dev_info(&pdev->dev,
1153 "online status unreliable, applying workaround\n");
1156 /* CAP.NP sometimes indicate the index of the last enabled
1157 * port, at other times, that of the last possible port, so
1158 * determining the maximum port number requires looking at
1159 * both CAP.NP and port_map.
1161 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1163 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1166 host->private_data = hpriv;
1168 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1169 host->flags |= ATA_HOST_PARALLEL_SCAN;
1171 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1173 if (pi.flags & ATA_FLAG_EM)
1174 ahci_reset_em(host);
1176 for (i = 0; i < host->n_ports; i++) {
1177 struct ata_port *ap = host->ports[i];
1179 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1180 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1181 0x100 + ap->port_no * 0x80, "port");
1183 /* set enclosure management message type */
1184 if (ap->flags & ATA_FLAG_EM)
1185 ap->em_message_type = hpriv->em_msg_type;
1188 /* disabled/not-implemented port */
1189 if (!(hpriv->port_map & (1 << i)))
1190 ap->ops = &ata_dummy_port_ops;
1193 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1194 ahci_p5wdh_workaround(host);
1196 /* apply gtf filter quirk */
1197 ahci_gtf_filter_workaround(host);
1199 /* initialize adapter */
1200 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1204 rc = ahci_pci_reset_controller(host);
1208 ahci_pci_init_controller(host);
1209 ahci_pci_print_info(host);
1211 pci_set_master(pdev);
1212 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1216 static int __init ahci_init(void)
1218 return pci_register_driver(&ahci_pci_driver);
1221 static void __exit ahci_exit(void)
1223 pci_unregister_driver(&ahci_pci_driver);
1227 MODULE_AUTHOR("Jeff Garzik");
1228 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1229 MODULE_LICENSE("GPL");
1230 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1231 MODULE_VERSION(DRV_VERSION);
1233 module_init(ahci_init);
1234 module_exit(ahci_exit);