2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
61 /* board IDs by feature in alphabetical order */
67 /* board IDs for specific chipsets in alphabetical order */
73 board_ahci_sb700, /* for SB700 and SB800 */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
93 static struct scsi_host_template ahci_sht = {
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
107 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
109 static const struct ata_port_info ahci_port_info[] = {
113 .flags = AHCI_FLAG_COMMON,
114 .pio_mask = ATA_PIO4,
115 .udma_mask = ATA_UDMA6,
116 .port_ops = &ahci_ops,
118 [board_ahci_ign_iferr] =
120 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
121 .flags = AHCI_FLAG_COMMON,
122 .pio_mask = ATA_PIO4,
123 .udma_mask = ATA_UDMA6,
124 .port_ops = &ahci_ops,
126 [board_ahci_nosntf] =
128 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
129 .flags = AHCI_FLAG_COMMON,
130 .pio_mask = ATA_PIO4,
131 .udma_mask = ATA_UDMA6,
132 .port_ops = &ahci_ops,
134 [board_ahci_yes_fbs] =
136 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
137 .flags = AHCI_FLAG_COMMON,
138 .pio_mask = ATA_PIO4,
139 .udma_mask = ATA_UDMA6,
140 .port_ops = &ahci_ops,
145 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
147 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
154 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
155 .flags = AHCI_FLAG_COMMON,
156 .pio_mask = ATA_PIO4,
157 .udma_mask = ATA_UDMA6,
158 .port_ops = &ahci_ops,
162 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
163 .flags = AHCI_FLAG_COMMON,
164 .pio_mask = ATA_PIO4,
165 .udma_mask = ATA_UDMA6,
166 .port_ops = &ahci_ops,
170 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
171 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
172 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
173 .pio_mask = ATA_PIO4,
174 .udma_mask = ATA_UDMA6,
175 .port_ops = &ahci_ops,
179 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
180 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
181 AHCI_HFLAG_32BIT_ONLY),
182 .flags = AHCI_FLAG_COMMON,
183 .pio_mask = ATA_PIO4,
184 .udma_mask = ATA_UDMA6,
185 .port_ops = &ahci_pmp_retry_srst_ops,
187 [board_ahci_sb700] = /* for SB700 and SB800 */
189 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
190 .flags = AHCI_FLAG_COMMON,
191 .pio_mask = ATA_PIO4,
192 .udma_mask = ATA_UDMA6,
193 .port_ops = &ahci_pmp_retry_srst_ops,
195 [board_ahci_vt8251] =
197 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
198 .flags = AHCI_FLAG_COMMON,
199 .pio_mask = ATA_PIO4,
200 .udma_mask = ATA_UDMA6,
201 .port_ops = &ahci_vt8251_ops,
205 static const struct pci_device_id ahci_pci_tbl[] = {
207 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
208 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
209 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
210 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
211 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
212 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
213 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
214 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
215 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
216 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
217 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
218 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
219 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
220 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
221 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
222 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
223 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
224 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
225 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
226 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
227 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
228 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
229 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
230 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
231 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
232 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
234 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
235 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
236 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
237 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
238 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
239 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
240 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
241 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
242 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
243 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
244 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
245 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
246 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
248 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
249 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
250 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
251 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
252 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
253 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
254 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
255 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
256 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
257 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
258 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
259 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
260 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
261 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
262 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
263 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
264 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
265 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
266 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
267 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
268 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
269 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
270 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
271 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
272 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
274 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
275 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
276 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
279 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
280 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
281 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
282 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
283 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
284 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
285 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
288 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
289 /* AMD is using RAID class only for ahci controllers */
290 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
291 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
294 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
295 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
298 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
299 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
300 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
301 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
302 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
303 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
304 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
305 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
306 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
311 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
312 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
313 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
314 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
315 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
316 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
317 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
318 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
327 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
328 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
329 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
330 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
331 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
332 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
333 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
334 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
339 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
340 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
341 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
342 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
343 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
344 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
345 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
351 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
352 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
353 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
354 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
355 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
356 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
357 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
358 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
363 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
364 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
365 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
366 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
367 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
368 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
369 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
370 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
374 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
375 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
376 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
377 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
378 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
379 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
380 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
381 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
384 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
385 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
386 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
388 /* ST Microelectronics */
389 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
392 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
393 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
394 { PCI_DEVICE(0x1b4b, 0x9123),
395 .class = PCI_CLASS_STORAGE_SATA_AHCI,
396 .class_mask = 0xffffff,
397 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
398 { PCI_DEVICE(0x1b4b, 0x9125),
399 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
400 { PCI_DEVICE(0x1b4b, 0x917a),
401 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
402 { PCI_DEVICE(0x1b4b, 0x9192),
403 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
404 { PCI_DEVICE(0x1b4b, 0x91a3),
405 .driver_data = board_ahci_yes_fbs },
408 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
411 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
412 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
413 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
414 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
417 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
419 /* Generic, PCI class code for AHCI */
420 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
421 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
423 { } /* terminate list */
427 static struct pci_driver ahci_pci_driver = {
429 .id_table = ahci_pci_tbl,
430 .probe = ahci_init_one,
431 .remove = ata_pci_remove_one,
433 .suspend = ahci_pci_device_suspend,
434 .resume = ahci_pci_device_resume,
438 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
439 static int marvell_enable;
441 static int marvell_enable = 1;
443 module_param(marvell_enable, int, 0644);
444 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
447 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
448 struct ahci_host_priv *hpriv)
450 unsigned int force_port_map = 0;
451 unsigned int mask_port_map = 0;
453 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
454 dev_info(&pdev->dev, "JMB361 has only one port\n");
459 * Temporary Marvell 6145 hack: PATA port presence
460 * is asserted through the standard AHCI port
461 * presence register, as bit 4 (counting from 0)
463 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
464 if (pdev->device == 0x6121)
469 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
472 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
476 static int ahci_pci_reset_controller(struct ata_host *host)
478 struct pci_dev *pdev = to_pci_dev(host->dev);
480 ahci_reset_controller(host);
482 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
483 struct ahci_host_priv *hpriv = host->private_data;
487 pci_read_config_word(pdev, 0x92, &tmp16);
488 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
489 tmp16 |= hpriv->port_map;
490 pci_write_config_word(pdev, 0x92, tmp16);
497 static void ahci_pci_init_controller(struct ata_host *host)
499 struct ahci_host_priv *hpriv = host->private_data;
500 struct pci_dev *pdev = to_pci_dev(host->dev);
501 void __iomem *port_mmio;
505 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
506 if (pdev->device == 0x6121)
510 port_mmio = __ahci_port_base(host, mv);
512 writel(0, port_mmio + PORT_IRQ_MASK);
515 tmp = readl(port_mmio + PORT_IRQ_STAT);
516 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
518 writel(tmp, port_mmio + PORT_IRQ_STAT);
521 ahci_init_controller(host);
524 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
525 unsigned long deadline)
527 struct ata_port *ap = link->ap;
533 ahci_stop_engine(ap);
535 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
536 deadline, &online, NULL);
538 ahci_start_engine(ap);
540 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
542 /* vt8251 doesn't clear BSY on signature FIS reception,
543 * request follow-up softreset.
545 return online ? -EAGAIN : rc;
548 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
549 unsigned long deadline)
551 struct ata_port *ap = link->ap;
552 struct ahci_port_priv *pp = ap->private_data;
553 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
554 struct ata_taskfile tf;
558 ahci_stop_engine(ap);
560 /* clear D2H reception area to properly wait for D2H FIS */
561 ata_tf_init(link->device, &tf);
563 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
565 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
566 deadline, &online, NULL);
568 ahci_start_engine(ap);
570 /* The pseudo configuration device on SIMG4726 attached to
571 * ASUS P5W-DH Deluxe doesn't send signature FIS after
572 * hardreset if no device is attached to the first downstream
573 * port && the pseudo device locks up on SRST w/ PMP==0. To
574 * work around this, wait for !BSY only briefly. If BSY isn't
575 * cleared, perform CLO and proceed to IDENTIFY (achieved by
576 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
578 * Wait for two seconds. Devices attached to downstream port
579 * which can't process the following IDENTIFY after this will
580 * have to be reset again. For most cases, this should
581 * suffice while making probing snappish enough.
584 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
587 ahci_kick_engine(ap);
593 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
595 struct ata_host *host = dev_get_drvdata(&pdev->dev);
596 struct ahci_host_priv *hpriv = host->private_data;
597 void __iomem *mmio = hpriv->mmio;
600 if (mesg.event & PM_EVENT_SUSPEND &&
601 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
603 "BIOS update required for suspend/resume\n");
607 if (mesg.event & PM_EVENT_SLEEP) {
608 /* AHCI spec rev1.1 section 8.3.3:
609 * Software must disable interrupts prior to requesting a
610 * transition of the HBA to D3 state.
612 ctl = readl(mmio + HOST_CTL);
614 writel(ctl, mmio + HOST_CTL);
615 readl(mmio + HOST_CTL); /* flush */
618 return ata_pci_device_suspend(pdev, mesg);
621 static int ahci_pci_device_resume(struct pci_dev *pdev)
623 struct ata_host *host = dev_get_drvdata(&pdev->dev);
626 rc = ata_pci_device_do_resume(pdev);
630 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
631 rc = ahci_pci_reset_controller(host);
635 ahci_pci_init_controller(host);
638 ata_host_resume(host);
644 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
649 * If the device fixup already set the dma_mask to some non-standard
650 * value, don't extend it here. This happens on STA2X11, for example.
652 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
656 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
657 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
659 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
662 "64-bit DMA enable failed\n");
667 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
669 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
672 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
675 "32-bit consistent DMA enable failed\n");
682 static void ahci_pci_print_info(struct ata_host *host)
684 struct pci_dev *pdev = to_pci_dev(host->dev);
688 pci_read_config_word(pdev, 0x0a, &cc);
689 if (cc == PCI_CLASS_STORAGE_IDE)
691 else if (cc == PCI_CLASS_STORAGE_SATA)
693 else if (cc == PCI_CLASS_STORAGE_RAID)
698 ahci_print_info(host, scc_s);
701 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
702 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
703 * support PMP and the 4726 either directly exports the device
704 * attached to the first downstream port or acts as a hardware storage
705 * controller and emulate a single ATA device (can be RAID 0/1 or some
706 * other configuration).
708 * When there's no device attached to the first downstream port of the
709 * 4726, "Config Disk" appears, which is a pseudo ATA device to
710 * configure the 4726. However, ATA emulation of the device is very
711 * lame. It doesn't send signature D2H Reg FIS after the initial
712 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
714 * The following function works around the problem by always using
715 * hardreset on the port and not depending on receiving signature FIS
716 * afterward. If signature FIS isn't received soon, ATA class is
717 * assumed without follow-up softreset.
719 static void ahci_p5wdh_workaround(struct ata_host *host)
721 static struct dmi_system_id sysids[] = {
723 .ident = "P5W DH Deluxe",
725 DMI_MATCH(DMI_SYS_VENDOR,
726 "ASUSTEK COMPUTER INC"),
727 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
732 struct pci_dev *pdev = to_pci_dev(host->dev);
734 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
735 dmi_check_system(sysids)) {
736 struct ata_port *ap = host->ports[1];
739 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
741 ap->ops = &ahci_p5wdh_ops;
742 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
746 /* only some SB600 ahci controllers can do 64bit DMA */
747 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
749 static const struct dmi_system_id sysids[] = {
751 * The oldest version known to be broken is 0901 and
752 * working is 1501 which was released on 2007-10-26.
753 * Enable 64bit DMA on 1501 and anything newer.
755 * Please read bko#9412 for more info.
758 .ident = "ASUS M2A-VM",
760 DMI_MATCH(DMI_BOARD_VENDOR,
761 "ASUSTeK Computer INC."),
762 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
764 .driver_data = "20071026", /* yyyymmdd */
767 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
770 * BIOS versions earlier than 1.5 had the Manufacturer DMI
771 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
772 * This spelling mistake was fixed in BIOS version 1.5, so
773 * 1.5 and later have the Manufacturer as
774 * "MICRO-STAR INTERNATIONAL CO.,LTD".
775 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
777 * BIOS versions earlier than 1.9 had a Board Product Name
778 * DMI field of "MS-7376". This was changed to be
779 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
780 * match on DMI_BOARD_NAME of "MS-7376".
783 .ident = "MSI K9A2 Platinum",
785 DMI_MATCH(DMI_BOARD_VENDOR,
787 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
791 * All BIOS versions for the Asus M3A support 64bit DMA.
792 * (all release versions from 0301 to 1206 were tested)
797 DMI_MATCH(DMI_BOARD_VENDOR,
798 "ASUSTeK Computer INC."),
799 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
804 const struct dmi_system_id *match;
805 int year, month, date;
808 match = dmi_first_match(sysids);
809 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
813 if (!match->driver_data)
816 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
817 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
819 if (strcmp(buf, match->driver_data) >= 0)
823 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
829 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
833 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
835 static const struct dmi_system_id broken_systems[] = {
837 .ident = "HP Compaq nx6310",
839 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
840 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
842 /* PCI slot number of the controller */
843 .driver_data = (void *)0x1FUL,
846 .ident = "HP Compaq 6720s",
848 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
849 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
851 /* PCI slot number of the controller */
852 .driver_data = (void *)0x1FUL,
855 { } /* terminate list */
857 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
860 unsigned long slot = (unsigned long)dmi->driver_data;
861 /* apply the quirk only to on-board controllers */
862 return slot == PCI_SLOT(pdev->devfn);
868 static bool ahci_broken_suspend(struct pci_dev *pdev)
870 static const struct dmi_system_id sysids[] = {
872 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
873 * to the harddisk doesn't become online after
874 * resuming from STR. Warn and fail suspend.
876 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
878 * Use dates instead of versions to match as HP is
879 * apparently recycling both product and version
882 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
887 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
888 DMI_MATCH(DMI_PRODUCT_NAME,
889 "HP Pavilion dv4 Notebook PC"),
891 .driver_data = "20090105", /* F.30 */
896 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
897 DMI_MATCH(DMI_PRODUCT_NAME,
898 "HP Pavilion dv5 Notebook PC"),
900 .driver_data = "20090506", /* F.16 */
905 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
906 DMI_MATCH(DMI_PRODUCT_NAME,
907 "HP Pavilion dv6 Notebook PC"),
909 .driver_data = "20090423", /* F.21 */
914 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
915 DMI_MATCH(DMI_PRODUCT_NAME,
916 "HP HDX18 Notebook PC"),
918 .driver_data = "20090430", /* F.23 */
921 * Acer eMachines G725 has the same problem. BIOS
922 * V1.03 is known to be broken. V3.04 is known to
923 * work. Between, there are V1.06, V2.06 and V3.03
924 * that we don't have much idea about. For now,
925 * blacklist anything older than V3.04.
927 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
932 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
933 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
935 .driver_data = "20091216", /* V3.04 */
937 { } /* terminate list */
939 const struct dmi_system_id *dmi = dmi_first_match(sysids);
940 int year, month, date;
943 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
946 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
947 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
949 return strcmp(buf, dmi->driver_data) < 0;
952 static bool ahci_broken_online(struct pci_dev *pdev)
954 #define ENCODE_BUSDEVFN(bus, slot, func) \
955 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
956 static const struct dmi_system_id sysids[] = {
958 * There are several gigabyte boards which use
959 * SIMG5723s configured as hardware RAID. Certain
960 * 5723 firmware revisions shipped there keep the link
961 * online but fail to answer properly to SRST or
962 * IDENTIFY when no device is attached downstream
963 * causing libata to retry quite a few times leading
964 * to excessive detection delay.
966 * As these firmwares respond to the second reset try
967 * with invalid device signature, considering unknown
968 * sig as offline works around the problem acceptably.
973 DMI_MATCH(DMI_BOARD_VENDOR,
974 "Gigabyte Technology Co., Ltd."),
975 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
977 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
982 DMI_MATCH(DMI_BOARD_VENDOR,
983 "Gigabyte Technology Co., Ltd."),
984 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
986 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
988 { } /* terminate list */
990 #undef ENCODE_BUSDEVFN
991 const struct dmi_system_id *dmi = dmi_first_match(sysids);
997 val = (unsigned long)dmi->driver_data;
999 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1002 #ifdef CONFIG_ATA_ACPI
1003 static void ahci_gtf_filter_workaround(struct ata_host *host)
1005 static const struct dmi_system_id sysids[] = {
1007 * Aspire 3810T issues a bunch of SATA enable commands
1008 * via _GTF including an invalid one and one which is
1009 * rejected by the device. Among the successful ones
1010 * is FPDMA non-zero offset enable which when enabled
1011 * only on the drive side leads to NCQ command
1012 * failures. Filter it out.
1015 .ident = "Aspire 3810T",
1017 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1018 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1020 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1024 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1025 unsigned int filter;
1031 filter = (unsigned long)dmi->driver_data;
1032 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1033 filter, dmi->ident);
1035 for (i = 0; i < host->n_ports; i++) {
1036 struct ata_port *ap = host->ports[i];
1037 struct ata_link *link;
1038 struct ata_device *dev;
1040 ata_for_each_link(link, ap, EDGE)
1041 ata_for_each_dev(dev, link, ALL)
1042 dev->gtf_filter |= filter;
1046 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1050 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1052 unsigned int board_id = ent->driver_data;
1053 struct ata_port_info pi = ahci_port_info[board_id];
1054 const struct ata_port_info *ppi[] = { &pi, NULL };
1055 struct device *dev = &pdev->dev;
1056 struct ahci_host_priv *hpriv;
1057 struct ata_host *host;
1059 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1063 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1065 ata_print_version_once(&pdev->dev, DRV_VERSION);
1067 /* The AHCI driver can only drive the SATA ports, the PATA driver
1068 can drive them all so if both drivers are selected make sure
1069 AHCI stays out of the way */
1070 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1074 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1075 * ahci, use ata_generic instead.
1077 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1078 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1079 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1080 pdev->subsystem_device == 0xcb89)
1083 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1084 * At the moment, we can only use the AHCI mode. Let the users know
1085 * that for SAS drives they're out of luck.
1087 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1088 dev_info(&pdev->dev,
1089 "PDC42819 can only drive SATA devices with this driver\n");
1091 /* Both Connext and Enmotus devices use non-standard BARs */
1092 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1093 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1094 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1095 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1097 /* acquire resources */
1098 rc = pcim_enable_device(pdev);
1102 /* AHCI controllers often implement SFF compatible interface.
1103 * Grab all PCI BARs just in case.
1105 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1107 pcim_pin_device(pdev);
1111 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1112 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1115 /* ICH6s share the same PCI ID for both piix and ahci
1116 * modes. Enabling ahci mode while MAP indicates
1117 * combined mode is a bad idea. Yield to ata_piix.
1119 pci_read_config_byte(pdev, ICH_MAP, &map);
1121 dev_info(&pdev->dev,
1122 "controller is in combined mode, can't enable AHCI mode\n");
1127 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1130 hpriv->flags |= (unsigned long)pi.private_data;
1132 /* MCP65 revision A1 and A2 can't do MSI */
1133 if (board_id == board_ahci_mcp65 &&
1134 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1135 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1137 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1138 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1139 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1141 /* only some SB600s can do 64bit DMA */
1142 if (ahci_sb600_enable_64bit(pdev))
1143 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1145 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1148 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1150 /* save initial config */
1151 ahci_pci_save_initial_config(pdev, hpriv);
1154 if (hpriv->cap & HOST_CAP_NCQ) {
1155 pi.flags |= ATA_FLAG_NCQ;
1157 * Auto-activate optimization is supposed to be
1158 * supported on all AHCI controllers indicating NCQ
1159 * capability, but it seems to be broken on some
1160 * chipsets including NVIDIAs.
1162 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1163 pi.flags |= ATA_FLAG_FPDMA_AA;
1166 if (hpriv->cap & HOST_CAP_PMP)
1167 pi.flags |= ATA_FLAG_PMP;
1169 ahci_set_em_messages(hpriv, &pi);
1171 if (ahci_broken_system_poweroff(pdev)) {
1172 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1173 dev_info(&pdev->dev,
1174 "quirky BIOS, skipping spindown on poweroff\n");
1177 if (ahci_broken_suspend(pdev)) {
1178 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1179 dev_warn(&pdev->dev,
1180 "BIOS update required for suspend/resume\n");
1183 if (ahci_broken_online(pdev)) {
1184 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1185 dev_info(&pdev->dev,
1186 "online status unreliable, applying workaround\n");
1189 /* CAP.NP sometimes indicate the index of the last enabled
1190 * port, at other times, that of the last possible port, so
1191 * determining the maximum port number requires looking at
1192 * both CAP.NP and port_map.
1194 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1196 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1199 host->private_data = hpriv;
1201 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1202 host->flags |= ATA_HOST_PARALLEL_SCAN;
1204 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1206 if (pi.flags & ATA_FLAG_EM)
1207 ahci_reset_em(host);
1209 for (i = 0; i < host->n_ports; i++) {
1210 struct ata_port *ap = host->ports[i];
1212 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1213 ata_port_pbar_desc(ap, ahci_pci_bar,
1214 0x100 + ap->port_no * 0x80, "port");
1216 /* set enclosure management message type */
1217 if (ap->flags & ATA_FLAG_EM)
1218 ap->em_message_type = hpriv->em_msg_type;
1221 /* disabled/not-implemented port */
1222 if (!(hpriv->port_map & (1 << i)))
1223 ap->ops = &ata_dummy_port_ops;
1226 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1227 ahci_p5wdh_workaround(host);
1229 /* apply gtf filter quirk */
1230 ahci_gtf_filter_workaround(host);
1232 /* initialize adapter */
1233 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1237 rc = ahci_pci_reset_controller(host);
1241 ahci_pci_init_controller(host);
1242 ahci_pci_print_info(host);
1244 pci_set_master(pdev);
1245 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1249 static int __init ahci_init(void)
1251 return pci_register_driver(&ahci_pci_driver);
1254 static void __exit ahci_exit(void)
1256 pci_unregister_driver(&ahci_pci_driver);
1260 MODULE_AUTHOR("Jeff Garzik");
1261 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1262 MODULE_LICENSE("GPL");
1263 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1264 MODULE_VERSION(DRV_VERSION);
1266 module_init(ahci_init);
1267 module_exit(ahci_exit);