arch/x86_64/kernel/pci-calgary.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright (C) IBM Corporation, 2006
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/init.h>
  34 #include <linux/bitops.h>
  35 #include <linux/pci_ids.h>
  36 #include <linux/pci.h>
  37 #include <linux/delay.h>
  38 #include <asm/proto.h>
  39 #include <asm/calgary.h>
  40 #include <asm/tce.h>
  41 #include <asm/pci-direct.h>
  42 #include <asm/system.h>
  43 #include <asm/dma.h>
  44 #include <asm/rio.h>
  45
  46 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  47 int use_calgary __read_mostly = 1;
  48 #else
  49 int use_calgary __read_mostly = 0;
  50 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  51
  52 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  53 #define PCI_VENDOR_DEVICE_ID_CALGARY \
  54         (PCI_VENDOR_ID_IBM | PCI_DEVICE_ID_IBM_CALGARY << 16)
  55
  56 /* we need these for register space address calculation */
  57 #define START_ADDRESS           0xfe000000
  58 #define CHASSIS_BASE            0
  59 #define ONE_BASED_CHASSIS_NUM   1
  60
  61 /* register offsets inside the host bridge space */
  62 #define CALGARY_CONFIG_REG      0x0108
  63 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  64 #define PHB_PLSSR_OFFSET        0x0120
  65 #define PHB_CONFIG_RW_OFFSET    0x0160
  66 #define PHB_IOBASE_BAR_LOW      0x0170
  67 #define PHB_IOBASE_BAR_HIGH     0x0180
  68 #define PHB_MEM_1_LOW           0x0190
  69 #define PHB_MEM_1_HIGH          0x01A0
  70 #define PHB_IO_ADDR_SIZE        0x01B0
  71 #define PHB_MEM_1_SIZE          0x01C0
  72 #define PHB_MEM_ST_OFFSET       0x01D0
  73 #define PHB_AER_OFFSET          0x0200
  74 #define PHB_CONFIG_0_HIGH       0x0220
  75 #define PHB_CONFIG_0_LOW        0x0230
  76 #define PHB_CONFIG_0_END        0x0240
  77 #define PHB_MEM_2_LOW           0x02B0
  78 #define PHB_MEM_2_HIGH          0x02C0
  79 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  80 #define PHB_MEM_2_SIZE_LOW      0x02E0
  81 #define PHB_DOSHOLE_OFFSET      0x08E0
  82
  83 /* PHB_CONFIG_RW */
  84 #define PHB_TCE_ENABLE          0x20000000
  85 #define PHB_SLOT_DISABLE        0x1C000000
  86 #define PHB_DAC_DISABLE         0x01000000
  87 #define PHB_MEM2_ENABLE         0x00400000
  88 #define PHB_MCSR_ENABLE         0x00100000
  89 /* TAR (Table Address Register) */
  90 #define TAR_SW_BITS             0x0000ffffffff800fUL
  91 #define TAR_VALID               0x0000000000000008UL
  92 /* CSR (Channel/DMA Status Register) */
  93 #define CSR_AGENT_MASK          0xffe0ffff
  94 /* CCR (Calgary Configuration Register) */
  95 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
  96
  97 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
  98 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
  99 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 100 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 101 #define PHBS_PER_CALGARY        4
 102
 103 /* register offsets in Calgary's internal register space */
 104 static const unsigned long tar_offsets[] = {
 105         0x0580 /* TAR0 */,
 106         0x0588 /* TAR1 */,
 107         0x0590 /* TAR2 */,
 108         0x0598 /* TAR3 */
 109 };
 110
 111 static const unsigned long split_queue_offsets[] = {
 112         0x4870 /* SPLIT QUEUE 0 */,
 113         0x5870 /* SPLIT QUEUE 1 */,
 114         0x6870 /* SPLIT QUEUE 2 */,
 115         0x7870 /* SPLIT QUEUE 3 */
 116 };
 117
 118 static const unsigned long phb_offsets[] = {
 119         0x8000 /* PHB0 */,
 120         0x9000 /* PHB1 */,
 121         0xA000 /* PHB2 */,
 122         0xB000 /* PHB3 */
 123 };
 124
 125 /* PHB debug registers */
 126
 127 static const unsigned long phb_debug_offsets[] = {
 128         0x4000  /* PHB 0 DEBUG */,
 129         0x5000  /* PHB 1 DEBUG */,
 130         0x6000  /* PHB 2 DEBUG */,
 131         0x7000  /* PHB 3 DEBUG */
 132 };
 133
 134 /*
 135  * STUFF register for each debug PHB,
 136  * byte 1 = start bus number, byte 2 = end bus number
 137  */
 138
 139 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 140
 141 #define EMERGENCY_PAGES 32 /* = 128KB */
 142
 143 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 144 static int translate_empty_slots __read_mostly = 0;
 145 static int calgary_detected __read_mostly = 0;
 146
 147 static struct rio_table_hdr     *rio_table_hdr __initdata;
 148 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 149 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 150
 151 struct calgary_bus_info {
 152         void *tce_space;
 153         unsigned char translation_disabled;
 154         signed char phbid;
 155         void __iomem *bbar;
 156 };
 157
 158 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 159
 160 static void tce_cache_blast(struct iommu_table *tbl);
 161
 162 /* enable this to stress test the chip's TCE cache */
 163 #ifdef CONFIG_IOMMU_DEBUG
 164 int debugging __read_mostly = 1;
 165
 166 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 167         int expected, unsigned long start, unsigned long end)
 168 {
 169         unsigned long idx = start;
 170
 171         BUG_ON(start >= end);
 172
 173         while (idx < end) {
 174                 if (!!test_bit(idx, bitmap) != expected)
 175                         return idx;
 176                 ++idx;
 177         }
 178
 179         /* all bits have the expected value */
 180         return ~0UL;
 181 }
 182 #else /* debugging is disabled */
 183 int debugging __read_mostly = 0;
 184
 185 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 186         int expected, unsigned long start, unsigned long end)
 187 {
 188         return ~0UL;
 189 }
 190 #endif /* CONFIG_IOMMU_DEBUG */
 191
 192 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 193 {
 194         unsigned int npages;
 195
 196         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 197         npages >>= PAGE_SHIFT;
 198
 199         return npages;
 200 }
 201
 202 static inline int translate_phb(struct pci_dev* dev)
 203 {
 204         int disabled = bus_info[dev->bus->number].translation_disabled;
 205         return !disabled;
 206 }
 207
 208 static void iommu_range_reserve(struct iommu_table *tbl,
 209         unsigned long start_addr, unsigned int npages)
 210 {
 211         unsigned long index;
 212         unsigned long end;
 213         unsigned long badbit;
 214
 215         index = start_addr >> PAGE_SHIFT;
 216
 217         /* bail out if we're asked to reserve a region we don't cover */
 218         if (index >= tbl->it_size)
 219                 return;
 220
 221         end = index + npages;
 222         if (end > tbl->it_size) /* don't go off the table */
 223                 end = tbl->it_size;
 224
 225         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 226         if (badbit != ~0UL) {
 227                 if (printk_ratelimit())
 228                         printk(KERN_ERR "Calgary: entry already allocated at "
 229                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 230                                badbit, tbl, start_addr, npages);
 231         }
 232
 233         set_bit_string(tbl->it_map, index, npages);
 234 }
 235
 236 static unsigned long iommu_range_alloc(struct iommu_table *tbl,
 237         unsigned int npages)
 238 {
 239         unsigned long offset;
 240
 241         BUG_ON(npages == 0);
 242
 243         offset = find_next_zero_string(tbl->it_map, tbl->it_hint,
 244                                        tbl->it_size, npages);
 245         if (offset == ~0UL) {
 246                 tce_cache_blast(tbl);
 247                 offset = find_next_zero_string(tbl->it_map, 0,
 248                                                tbl->it_size, npages);
 249                 if (offset == ~0UL) {
 250                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 251                         if (panic_on_overflow)
 252                                 panic("Calgary: fix the allocator.\n");
 253                         else
 254                                 return bad_dma_address;
 255                 }
 256         }
 257
 258         set_bit_string(tbl->it_map, offset, npages);
 259         tbl->it_hint = offset + npages;
 260         BUG_ON(tbl->it_hint > tbl->it_size);
 261
 262         return offset;
 263 }
 264
 265 static dma_addr_t iommu_alloc(struct iommu_table *tbl, void *vaddr,
 266         unsigned int npages, int direction)
 267 {
 268         unsigned long entry, flags;
 269         dma_addr_t ret = bad_dma_address;
 270
 271         spin_lock_irqsave(&tbl->it_lock, flags);
 272
 273         entry = iommu_range_alloc(tbl, npages);
 274
 275         if (unlikely(entry == bad_dma_address))
 276                 goto error;
 277
 278         /* set the return dma address */
 279         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 280
 281         /* put the TCEs in the HW table */
 282         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 283                   direction);
 284
 285         spin_unlock_irqrestore(&tbl->it_lock, flags);
 286
 287         return ret;
 288
 289 error:
 290         spin_unlock_irqrestore(&tbl->it_lock, flags);
 291         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 292                "iommu %p\n", npages, tbl);
 293         return bad_dma_address;
 294 }
 295
 296 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 297         unsigned int npages)
 298 {
 299         unsigned long entry;
 300         unsigned long badbit;
 301         unsigned long badend;
 302
 303         /* were we called with bad_dma_address? */
 304         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 305         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 306                 printk(KERN_ERR "Calgary: driver tried unmapping bad DMA "
 307                        "address 0x%Lx\n", dma_addr);
 308                 WARN_ON(1);
 309                 return;
 310         }
 311
 312         entry = dma_addr >> PAGE_SHIFT;
 313
 314         BUG_ON(entry + npages > tbl->it_size);
 315
 316         tce_free(tbl, entry, npages);
 317
 318         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 319         if (badbit != ~0UL) {
 320                 if (printk_ratelimit())
 321                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 322                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 323                                badbit, tbl, dma_addr, entry, npages);
 324         }
 325
 326         __clear_bit_string(tbl->it_map, entry, npages);
 327 }
 328
 329 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 330         unsigned int npages)
 331 {
 332         unsigned long flags;
 333
 334         spin_lock_irqsave(&tbl->it_lock, flags);
 335
 336         __iommu_free(tbl, dma_addr, npages);
 337
 338         spin_unlock_irqrestore(&tbl->it_lock, flags);
 339 }
 340
 341 static void __calgary_unmap_sg(struct iommu_table *tbl,
 342         struct scatterlist *sglist, int nelems, int direction)
 343 {
 344         while (nelems--) {
 345                 unsigned int npages;
 346                 dma_addr_t dma = sglist->dma_address;
 347                 unsigned int dmalen = sglist->dma_length;
 348
 349                 if (dmalen == 0)
 350                         break;
 351
 352                 npages = num_dma_pages(dma, dmalen);
 353                 __iommu_free(tbl, dma, npages);
 354                 sglist++;
 355         }
 356 }
 357
 358 void calgary_unmap_sg(struct device *dev, struct scatterlist *sglist,
 359                       int nelems, int direction)
 360 {
 361         unsigned long flags;
 362         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 363
 364         if (!translate_phb(to_pci_dev(dev)))
 365                 return;
 366
 367         spin_lock_irqsave(&tbl->it_lock, flags);
 368
 369         __calgary_unmap_sg(tbl, sglist, nelems, direction);
 370
 371         spin_unlock_irqrestore(&tbl->it_lock, flags);
 372 }
 373
 374 static int calgary_nontranslate_map_sg(struct device* dev,
 375         struct scatterlist *sg, int nelems, int direction)
 376 {
 377         int i;
 378
 379         for (i = 0; i < nelems; i++ ) {
 380                 struct scatterlist *s = &sg[i];
 381                 BUG_ON(!s->page);
 382                 s->dma_address = virt_to_bus(page_address(s->page) +s->offset);
 383                 s->dma_length = s->length;
 384         }
 385         return nelems;
 386 }
 387
 388 int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 389         int nelems, int direction)
 390 {
 391         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 392         unsigned long flags;
 393         unsigned long vaddr;
 394         unsigned int npages;
 395         unsigned long entry;
 396         int i;
 397
 398         if (!translate_phb(to_pci_dev(dev)))
 399                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 400
 401         spin_lock_irqsave(&tbl->it_lock, flags);
 402
 403         for (i = 0; i < nelems; i++ ) {
 404                 struct scatterlist *s = &sg[i];
 405                 BUG_ON(!s->page);
 406
 407                 vaddr = (unsigned long)page_address(s->page) + s->offset;
 408                 npages = num_dma_pages(vaddr, s->length);
 409
 410                 entry = iommu_range_alloc(tbl, npages);
 411                 if (entry == bad_dma_address) {
 412                         /* makes sure unmap knows to stop */
 413                         s->dma_length = 0;
 414                         goto error;
 415                 }
 416
 417                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 418
 419                 /* insert into HW table */
 420                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 421                           direction);
 422
 423                 s->dma_length = s->length;
 424         }
 425
 426         spin_unlock_irqrestore(&tbl->it_lock, flags);
 427
 428         return nelems;
 429 error:
 430         __calgary_unmap_sg(tbl, sg, nelems, direction);
 431         for (i = 0; i < nelems; i++) {
 432                 sg[i].dma_address = bad_dma_address;
 433                 sg[i].dma_length = 0;
 434         }
 435         spin_unlock_irqrestore(&tbl->it_lock, flags);
 436         return 0;
 437 }
 438
 439 dma_addr_t calgary_map_single(struct device *dev, void *vaddr,
 440         size_t size, int direction)
 441 {
 442         dma_addr_t dma_handle = bad_dma_address;
 443         unsigned long uaddr;
 444         unsigned int npages;
 445         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 446
 447         uaddr = (unsigned long)vaddr;
 448         npages = num_dma_pages(uaddr, size);
 449
 450         if (translate_phb(to_pci_dev(dev)))
 451                 dma_handle = iommu_alloc(tbl, vaddr, npages, direction);
 452         else
 453                 dma_handle = virt_to_bus(vaddr);
 454
 455         return dma_handle;
 456 }
 457
 458 void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 459         size_t size, int direction)
 460 {
 461         struct iommu_table *tbl = to_pci_dev(dev)->bus->self->sysdata;
 462         unsigned int npages;
 463
 464         if (!translate_phb(to_pci_dev(dev)))
 465                 return;
 466
 467         npages = num_dma_pages(dma_handle, size);
 468         iommu_free(tbl, dma_handle, npages);
 469 }
 470
 471 void* calgary_alloc_coherent(struct device *dev, size_t size,
 472         dma_addr_t *dma_handle, gfp_t flag)
 473 {
 474         void *ret = NULL;
 475         dma_addr_t mapping;
 476         unsigned int npages, order;
 477         struct iommu_table *tbl;
 478
 479         tbl = to_pci_dev(dev)->bus->self->sysdata;
 480
 481         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 482         npages = size >> PAGE_SHIFT;
 483         order = get_order(size);
 484
 485         /* alloc enough pages (and possibly more) */
 486         ret = (void *)__get_free_pages(flag, order);
 487         if (!ret)
 488                 goto error;
 489         memset(ret, 0, size);
 490
 491         if (translate_phb(to_pci_dev(dev))) {
 492                 /* set up tces to cover the allocated range */
 493                 mapping = iommu_alloc(tbl, ret, npages, DMA_BIDIRECTIONAL);
 494                 if (mapping == bad_dma_address)
 495                         goto free;
 496
 497                 *dma_handle = mapping;
 498         } else /* non translated slot */
 499                 *dma_handle = virt_to_bus(ret);
 500
 501         return ret;
 502
 503 free:
 504         free_pages((unsigned long)ret, get_order(size));
 505         ret = NULL;
 506 error:
 507         return ret;
 508 }
 509
 510 static struct dma_mapping_ops calgary_dma_ops = {
 511         .alloc_coherent = calgary_alloc_coherent,
 512         .map_single = calgary_map_single,
 513         .unmap_single = calgary_unmap_single,
 514         .map_sg = calgary_map_sg,
 515         .unmap_sg = calgary_unmap_sg,
 516 };
 517
 518 static inline void __iomem * busno_to_bbar(unsigned char num)
 519 {
 520         return bus_info[num].bbar;
 521 }
 522
 523 static inline int busno_to_phbid(unsigned char num)
 524 {
 525         return bus_info[num].phbid;
 526 }
 527
 528 static inline unsigned long split_queue_offset(unsigned char num)
 529 {
 530         size_t idx = busno_to_phbid(num);
 531
 532         return split_queue_offsets[idx];
 533 }
 534
 535 static inline unsigned long tar_offset(unsigned char num)
 536 {
 537         size_t idx = busno_to_phbid(num);
 538
 539         return tar_offsets[idx];
 540 }
 541
 542 static inline unsigned long phb_offset(unsigned char num)
 543 {
 544         size_t idx = busno_to_phbid(num);
 545
 546         return phb_offsets[idx];
 547 }
 548
 549 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 550 {
 551         unsigned long target = ((unsigned long)bar) | offset;
 552         return (void __iomem*)target;
 553 }
 554
 555 static void tce_cache_blast(struct iommu_table *tbl)
 556 {
 557         u64 val;
 558         u32 aer;
 559         int i = 0;
 560         void __iomem *bbar = tbl->bbar;
 561         void __iomem *target;
 562
 563         /* disable arbitration on the bus */
 564         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 565         aer = readl(target);
 566         writel(0, target);
 567
 568         /* read plssr to ensure it got there */
 569         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 570         val = readl(target);
 571
 572         /* poll split queues until all DMA activity is done */
 573         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 574         do {
 575                 val = readq(target);
 576                 i++;
 577         } while ((val & 0xff) != 0xff && i < 100);
 578         if (i == 100)
 579                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 580                        "continuing anyway\n");
 581
 582         /* invalidate TCE cache */
 583         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 584         writeq(tbl->tar_val, target);
 585
 586         /* enable arbitration */
 587         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 588         writel(aer, target);
 589         (void)readl(target); /* flush */
 590 }
 591
 592 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 593         u64 limit)
 594 {
 595         unsigned int numpages;
 596
 597         limit = limit | 0xfffff;
 598         limit++;
 599
 600         numpages = ((limit - start) >> PAGE_SHIFT);
 601         iommu_range_reserve(dev->sysdata, start, numpages);
 602 }
 603
 604 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 605 {
 606         void __iomem *target;
 607         u64 low, high, sizelow;
 608         u64 start, limit;
 609         struct iommu_table *tbl = dev->sysdata;
 610         unsigned char busnum = dev->bus->number;
 611         void __iomem *bbar = tbl->bbar;
 612
 613         /* peripheral MEM_1 region */
 614         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 615         low = be32_to_cpu(readl(target));
 616         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 617         high = be32_to_cpu(readl(target));
 618         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 619         sizelow = be32_to_cpu(readl(target));
 620
 621         start = (high << 32) | low;
 622         limit = sizelow;
 623
 624         calgary_reserve_mem_region(dev, start, limit);
 625 }
 626
 627 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 628 {
 629         void __iomem *target;
 630         u32 val32;
 631         u64 low, high, sizelow, sizehigh;
 632         u64 start, limit;
 633         struct iommu_table *tbl = dev->sysdata;
 634         unsigned char busnum = dev->bus->number;
 635         void __iomem *bbar = tbl->bbar;
 636
 637         /* is it enabled? */
 638         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 639         val32 = be32_to_cpu(readl(target));
 640         if (!(val32 & PHB_MEM2_ENABLE))
 641                 return;
 642
 643         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 644         low = be32_to_cpu(readl(target));
 645         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 646         high = be32_to_cpu(readl(target));
 647         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 648         sizelow = be32_to_cpu(readl(target));
 649         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 650         sizehigh = be32_to_cpu(readl(target));
 651
 652         start = (high << 32) | low;
 653         limit = (sizehigh << 32) | sizelow;
 654
 655         calgary_reserve_mem_region(dev, start, limit);
 656 }
 657
 658 /*
 659  * some regions of the IO address space do not get translated, so we
 660  * must not give devices IO addresses in those regions. The regions
 661  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 662  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 663  * later.
 664  */
 665 static void __init calgary_reserve_regions(struct pci_dev *dev)
 666 {
 667         unsigned int npages;
 668         u64 start;
 669         struct iommu_table *tbl = dev->sysdata;
 670
 671         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 672         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 673
 674         /* avoid the BIOS/VGA first 640KB-1MB region */
 675         start = (640 * 1024);
 676         npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 677         iommu_range_reserve(tbl, start, npages);
 678
 679         /* reserve the two PCI peripheral memory regions in IO space */
 680         calgary_reserve_peripheral_mem_1(dev);
 681         calgary_reserve_peripheral_mem_2(dev);
 682 }
 683
 684 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 685 {
 686         u64 val64;
 687         u64 table_phys;
 688         void __iomem *target;
 689         int ret;
 690         struct iommu_table *tbl;
 691
 692         /* build TCE tables for each PHB */
 693         ret = build_tce_table(dev, bbar);
 694         if (ret)
 695                 return ret;
 696
 697         tbl = dev->sysdata;
 698         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 699         tce_free(tbl, 0, tbl->it_size);
 700
 701         calgary_reserve_regions(dev);
 702
 703         /* set TARs for each PHB */
 704         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 705         val64 = be64_to_cpu(readq(target));
 706
 707         /* zero out all TAR bits under sw control */
 708         val64 &= ~TAR_SW_BITS;
 709
 710         tbl = dev->sysdata;
 711         table_phys = (u64)__pa(tbl->it_base);
 712         val64 |= table_phys;
 713
 714         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 715         val64 |= (u64) specified_table_size;
 716
 717         tbl->tar_val = cpu_to_be64(val64);
 718         writeq(tbl->tar_val, target);
 719         readq(target); /* flush */
 720
 721         return 0;
 722 }
 723
 724 static void __init calgary_free_bus(struct pci_dev *dev)
 725 {
 726         u64 val64;
 727         struct iommu_table *tbl = dev->sysdata;
 728         void __iomem *target;
 729         unsigned int bitmapsz;
 730
 731         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 732         val64 = be64_to_cpu(readq(target));
 733         val64 &= ~TAR_SW_BITS;
 734         writeq(cpu_to_be64(val64), target);
 735         readq(target); /* flush */
 736
 737         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 738         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 739         tbl->it_map = NULL;
 740
 741         kfree(tbl);
 742         dev->sysdata = NULL;
 743
 744         /* Can't free bootmem allocated memory after system is up :-( */
 745         bus_info[dev->bus->number].tce_space = NULL;
 746 }
 747
 748 static void calgary_watchdog(unsigned long data)
 749 {
 750         struct pci_dev *dev = (struct pci_dev *)data;
 751         struct iommu_table *tbl = dev->sysdata;
 752         void __iomem *bbar = tbl->bbar;
 753         u32 val32;
 754         void __iomem *target;
 755
 756         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 757         val32 = be32_to_cpu(readl(target));
 758
 759         /* If no error, the agent ID in the CSR is not valid */
 760         if (val32 & CSR_AGENT_MASK) {
 761                 printk(KERN_EMERG "calgary_watchdog: DMA error on PHB %#x, "
 762                                   "CSR = %#x\n", dev->bus->number, val32);
 763                 writel(0, target);
 764
 765                 /* Disable bus that caused the error */
 766                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 767                                            PHB_CONFIG_RW_OFFSET);
 768                 val32 = be32_to_cpu(readl(target));
 769                 val32 |= PHB_SLOT_DISABLE;
 770                 writel(cpu_to_be32(val32), target);
 771                 readl(target); /* flush */
 772         } else {
 773                 /* Reset the timer */
 774                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 775         }
 776 }
 777
 778 static void __init calgary_increase_split_completion_timeout(void __iomem *bbar,
 779         unsigned char busnum)
 780 {
 781         u64 val64;
 782         void __iomem *target;
 783         unsigned int phb_shift = ~0; /* silence gcc */
 784         u64 mask;
 785
 786         switch (busno_to_phbid(busnum)) {
 787         case 0: phb_shift = (63 - 19);
 788                 break;
 789         case 1: phb_shift = (63 - 23);
 790                 break;
 791         case 2: phb_shift = (63 - 27);
 792                 break;
 793         case 3: phb_shift = (63 - 35);
 794                 break;
 795         default:
 796                 BUG_ON(busno_to_phbid(busnum));
 797         }
 798
 799         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
 800         val64 = be64_to_cpu(readq(target));
 801
 802         /* zero out this PHB's timer bits */
 803         mask = ~(0xFUL << phb_shift);
 804         val64 &= mask;
 805         val64 |= (CCR_2SEC_TIMEOUT << phb_shift);
 806         writeq(cpu_to_be64(val64), target);
 807         readq(target); /* flush */
 808 }
 809
 810 static void __init calgary_enable_translation(struct pci_dev *dev)
 811 {
 812         u32 val32;
 813         unsigned char busnum;
 814         void __iomem *target;
 815         void __iomem *bbar;
 816         struct iommu_table *tbl;
 817
 818         busnum = dev->bus->number;
 819         tbl = dev->sysdata;
 820         bbar = tbl->bbar;
 821
 822         /* enable TCE in PHB Config Register */
 823         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 824         val32 = be32_to_cpu(readl(target));
 825         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
 826
 827         printk(KERN_INFO "Calgary: enabling translation on PHB %#x\n", busnum);
 828         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
 829                "bus.\n");
 830
 831         writel(cpu_to_be32(val32), target);
 832         readl(target); /* flush */
 833
 834         /*
 835          * Give split completion a longer timeout on bus 1 for aic94xx
 836          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
 837          */
 838         if (busnum == 1)
 839                 calgary_increase_split_completion_timeout(bbar, busnum);
 840
 841         init_timer(&tbl->watchdog_timer);
 842         tbl->watchdog_timer.function = &calgary_watchdog;
 843         tbl->watchdog_timer.data = (unsigned long)dev;
 844         mod_timer(&tbl->watchdog_timer, jiffies);
 845 }
 846
 847 static void __init calgary_disable_translation(struct pci_dev *dev)
 848 {
 849         u32 val32;
 850         unsigned char busnum;
 851         void __iomem *target;
 852         void __iomem *bbar;
 853         struct iommu_table *tbl;
 854
 855         busnum = dev->bus->number;
 856         tbl = dev->sysdata;
 857         bbar = tbl->bbar;
 858
 859         /* disable TCE in PHB Config Register */
 860         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 861         val32 = be32_to_cpu(readl(target));
 862         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
 863
 864         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
 865         writel(cpu_to_be32(val32), target);
 866         readl(target); /* flush */
 867
 868         del_timer_sync(&tbl->watchdog_timer);
 869 }
 870
 871 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
 872 {
 873         pci_dev_get(dev);
 874         dev->sysdata = NULL;
 875         dev->bus->self = dev;
 876 }
 877
 878 static int __init calgary_init_one(struct pci_dev *dev)
 879 {
 880         void __iomem *bbar;
 881         int ret;
 882
 883         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
 884
 885         bbar = busno_to_bbar(dev->bus->number);
 886         ret = calgary_setup_tar(dev, bbar);
 887         if (ret)
 888                 goto done;
 889
 890         pci_dev_get(dev);
 891         dev->bus->self = dev;
 892         calgary_enable_translation(dev);
 893
 894         return 0;
 895
 896 done:
 897         return ret;
 898 }
 899
 900 static int __init calgary_locate_bbars(void)
 901 {
 902         int ret;
 903         int rioidx, phb, bus;
 904         void __iomem *bbar;
 905         void __iomem *target;
 906         unsigned long offset;
 907         u8 start_bus, end_bus;
 908         u32 val;
 909
 910         ret = -ENODATA;
 911         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
 912                 struct rio_detail *rio = rio_devs[rioidx];
 913
 914                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
 915                         continue;
 916
 917                 /* map entire 1MB of Calgary config space */
 918                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
 919                 if (!bbar)
 920                         goto error;
 921
 922                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
 923                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
 924                         target = calgary_reg(bbar, offset);
 925
 926                         val = be32_to_cpu(readl(target));
 927                         start_bus = (u8)((val & 0x00FF0000) >> 16);
 928                         end_bus = (u8)((val & 0x0000FF00) >> 8);
 929                         for (bus = start_bus; bus <= end_bus; bus++) {
 930                                 bus_info[bus].bbar = bbar;
 931                                 bus_info[bus].phbid = phb;
 932                         }
 933                 }
 934         }
 935
 936         return 0;
 937
 938 error:
 939         /* scan bus_info and iounmap any bbars we previously ioremap'd */
 940         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
 941                 if (bus_info[bus].bbar)
 942                         iounmap(bus_info[bus].bbar);
 943
 944         return ret;
 945 }
 946
 947 static int __init calgary_init(void)
 948 {
 949         int ret;
 950         struct pci_dev *dev = NULL;
 951
 952         ret = calgary_locate_bbars();
 953         if (ret)
 954                 return ret;
 955
 956         do {
 957                 dev = pci_get_device(PCI_VENDOR_ID_IBM,
 958                                      PCI_DEVICE_ID_IBM_CALGARY,
 959                                      dev);
 960                 if (!dev)
 961                         break;
 962                 if (!translate_phb(dev)) {
 963                         calgary_init_one_nontraslated(dev);
 964                         continue;
 965                 }
 966                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
 967                         continue;
 968
 969                 ret = calgary_init_one(dev);
 970                 if (ret)
 971                         goto error;
 972         } while (1);
 973
 974         return ret;
 975
 976 error:
 977         do {
 978                 dev = pci_get_device_reverse(PCI_VENDOR_ID_IBM,
 979                                               PCI_DEVICE_ID_IBM_CALGARY,
 980                                               dev);
 981                 if (!dev)
 982                         break;
 983                 if (!translate_phb(dev)) {
 984                         pci_dev_put(dev);
 985                         continue;
 986                 }
 987                 if (!bus_info[dev->bus->number].tce_space && !translate_empty_slots)
 988                         continue;
 989
 990                 calgary_disable_translation(dev);
 991                 calgary_free_bus(dev);
 992                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
 993         } while (1);
 994
 995         return ret;
 996 }
 997
 998 static inline int __init determine_tce_table_size(u64 ram)
 999 {
1000         int ret;
1001
1002         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1003                 return specified_table_size;
1004
1005         /*
1006          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1007          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1008          * larger table size has twice as many entries, so shift the
1009          * max ram address by 13 to divide by 8K and then look at the
1010          * order of the result to choose between 0-7.
1011          */
1012         ret = get_order(ram >> 13);
1013         if (ret > TCE_TABLE_SIZE_8M)
1014                 ret = TCE_TABLE_SIZE_8M;
1015
1016         return ret;
1017 }
1018
1019 static int __init build_detail_arrays(void)
1020 {
1021         unsigned long ptr;
1022         int i, scal_detail_size, rio_detail_size;
1023
1024         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1025                 printk(KERN_WARNING
1026                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1027                         "but system has %d nodes.\n",
1028                         MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1029                 return -ENODEV;
1030         }
1031
1032         switch (rio_table_hdr->version){
1033         case 2:
1034                 scal_detail_size = 11;
1035                 rio_detail_size = 13;
1036                 break;
1037         case 3:
1038                 scal_detail_size = 12;
1039                 rio_detail_size = 15;
1040                 break;
1041         default:
1042                 printk(KERN_WARNING
1043                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1044                        rio_table_hdr->version);
1045                 return -EPROTO;
1046         }
1047
1048         ptr = ((unsigned long)rio_table_hdr) + 3;
1049         for (i = 0; i < rio_table_hdr->num_scal_dev;
1050                     i++, ptr += scal_detail_size)
1051                 scal_devs[i] = (struct scal_detail *)ptr;
1052
1053         for (i = 0; i < rio_table_hdr->num_rio_dev;
1054                     i++, ptr += rio_detail_size)
1055                 rio_devs[i] = (struct rio_detail *)ptr;
1056
1057         return 0;
1058 }
1059
1060 void __init detect_calgary(void)
1061 {
1062         u32 val;
1063         int bus;
1064         void *tbl;
1065         int calgary_found = 0;
1066         unsigned long ptr;
1067         unsigned int offset, prev_offset;
1068         int ret;
1069
1070         /*
1071          * if the user specified iommu=off or iommu=soft or we found
1072          * another HW IOMMU already, bail out.
1073          */
1074         if (swiotlb || no_iommu || iommu_detected)
1075                 return;
1076
1077         if (!use_calgary)
1078                 return;
1079
1080         if (!early_pci_allowed())
1081                 return;
1082
1083         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1084
1085         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1086
1087         rio_table_hdr = NULL;
1088         prev_offset = 0;
1089         offset = 0x180;
1090         /*
1091          * The next offset is stored in the 1st word.
1092          * Only parse up until the offset increases:
1093          */
1094         while (offset > prev_offset) {
1095                 /* The block id is stored in the 2nd word */
1096                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1097                         /* set the pointer past the offset & block id */
1098                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1099                         break;
1100                 }
1101                 prev_offset = offset;
1102                 offset = *((unsigned short *)(ptr + offset));
1103         }
1104         if (!rio_table_hdr) {
1105                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1106                        "in EBDA - bailing!\n");
1107                 return;
1108         }
1109
1110         ret = build_detail_arrays();
1111         if (ret) {
1112                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1113                 return;
1114         }
1115
1116         specified_table_size = determine_tce_table_size(end_pfn * PAGE_SIZE);
1117
1118         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1119                 int dev;
1120                 struct calgary_bus_info *info = &bus_info[bus];
1121
1122                 if (read_pci_config(bus, 0, 0, 0) != PCI_VENDOR_DEVICE_ID_CALGARY)
1123                         continue;
1124
1125                 if (info->translation_disabled)
1126                         continue;
1127
1128                 /*
1129                  * Scan the slots of the PCI bus to see if there is a device present.
1130                  * The parent bus will be the zero-ith device, so start at 1.
1131                  */
1132                 for (dev = 1; dev < 8; dev++) {
1133                         val = read_pci_config(bus, dev, 0, 0);
1134                         if (val != 0xffffffff || translate_empty_slots) {
1135                                 tbl = alloc_tce_table();
1136                                 if (!tbl)
1137                                         goto cleanup;
1138                                 info->tce_space = tbl;
1139                                 calgary_found = 1;
1140                                 break;
1141                         }
1142                 }
1143         }
1144
1145         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1146                calgary_found ? "found" : "not found");
1147
1148         if (calgary_found) {
1149                 iommu_detected = 1;
1150                 calgary_detected = 1;
1151                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1152                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1153                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1154                        debugging ? "enabled" : "disabled");
1155         }
1156         return;
1157
1158 cleanup:
1159         for (--bus; bus >= 0; --bus) {
1160                 struct calgary_bus_info *info = &bus_info[bus];
1161
1162                 if (info->tce_space)
1163                         free_tce_table(info->tce_space);
1164         }
1165 }
1166
1167 int __init calgary_iommu_init(void)
1168 {
1169         int ret;
1170
1171         if (no_iommu || swiotlb)
1172                 return -ENODEV;
1173
1174         if (!calgary_detected)
1175                 return -ENODEV;
1176
1177         /* ok, we're trying to use Calgary - let's roll */
1178         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1179
1180         ret = calgary_init();
1181         if (ret) {
1182                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1183                        "falling back to no_iommu\n", ret);
1184                 if (end_pfn > MAX_DMA32_PFN)
1185                         printk(KERN_ERR "WARNING more than 4GB of memory, "
1186                                         "32bit PCI may malfunction.\n");
1187                 return ret;
1188         }
1189
1190         force_iommu = 1;
1191         bad_dma_address = 0x0;
1192         dma_ops = &calgary_dma_ops;
1193
1194         return 0;
1195 }
1196
1197 static int __init calgary_parse_options(char *p)
1198 {
1199         unsigned int bridge;
1200         size_t len;
1201         char* endp;
1202
1203         while (*p) {
1204                 if (!strncmp(p, "64k", 3))
1205                         specified_table_size = TCE_TABLE_SIZE_64K;
1206                 else if (!strncmp(p, "128k", 4))
1207                         specified_table_size = TCE_TABLE_SIZE_128K;
1208                 else if (!strncmp(p, "256k", 4))
1209                         specified_table_size = TCE_TABLE_SIZE_256K;
1210                 else if (!strncmp(p, "512k", 4))
1211                         specified_table_size = TCE_TABLE_SIZE_512K;
1212                 else if (!strncmp(p, "1M", 2))
1213                         specified_table_size = TCE_TABLE_SIZE_1M;
1214                 else if (!strncmp(p, "2M", 2))
1215                         specified_table_size = TCE_TABLE_SIZE_2M;
1216                 else if (!strncmp(p, "4M", 2))
1217                         specified_table_size = TCE_TABLE_SIZE_4M;
1218                 else if (!strncmp(p, "8M", 2))
1219                         specified_table_size = TCE_TABLE_SIZE_8M;
1220
1221                 len = strlen("translate_empty_slots");
1222                 if (!strncmp(p, "translate_empty_slots", len))
1223                         translate_empty_slots = 1;
1224
1225                 len = strlen("disable");
1226                 if (!strncmp(p, "disable", len)) {
1227                         p += len;
1228                         if (*p == '=')
1229                                 ++p;
1230                         if (*p == '\0')
1231                                 break;
1232                         bridge = simple_strtol(p, &endp, 0);
1233                         if (p == endp)
1234                                 break;
1235
1236                         if (bridge < MAX_PHB_BUS_NUM) {
1237                                 printk(KERN_INFO "Calgary: disabling "
1238                                        "translation for PHB %#x\n", bridge);
1239                                 bus_info[bridge].translation_disabled = 1;
1240                         }
1241                 }
1242
1243                 p = strpbrk(p, ",");
1244                 if (!p)
1245                         break;
1246
1247                 p++; /* skip ',' */
1248         }
1249         return 1;
1250 }
1251 __setup("calgary=", calgary_parse_options);