arch/x86_64/kernel/nmi.c

   1 /*
   2  *  linux/arch/x86_64/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Pavel Machek and
  12  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  13  */
  14
  15 #include <linux/nmi.h>
  16 #include <linux/mm.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/sysdev.h>
  21 #include <linux/sysctl.h>
  22 #include <linux/kprobes.h>
  23 #include <linux/cpumask.h>
  24
  25 #include <asm/smp.h>
  26 #include <asm/nmi.h>
  27 #include <asm/proto.h>
  28 #include <asm/kdebug.h>
  29 #include <asm/mce.h>
  30 #include <asm/intel_arch_perfmon.h>
  31
  32 int unknown_nmi_panic;
  33 int nmi_watchdog_enabled;
  34 int panic_on_unrecovered_nmi;
  35
  36 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
  37  * evtsel_nmi_owner tracks the ownership of the event selection
  38  * - different performance counters/ event selection may be reserved for
  39  *   different subsystems this reservation system just tries to coordinate
  40  *   things a little
  41  */
  42 static DEFINE_PER_CPU(unsigned, perfctr_nmi_owner);
  43 static DEFINE_PER_CPU(unsigned, evntsel_nmi_owner[2]);
  44
  45 static cpumask_t backtrace_mask = CPU_MASK_NONE;
  46
  47 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
  48  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
  49  */
  50 #define NMI_MAX_COUNTER_BITS 66
  51
  52 /* nmi_active:
  53  * >0: the lapic NMI watchdog is active, but can be disabled
  54  * <0: the lapic NMI watchdog has not been set up, and cannot
  55  *     be enabled
  56  *  0: the lapic NMI watchdog is disabled, but can be enabled
  57  */
  58 atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
  59 int panic_on_timeout;
  60
  61 unsigned int nmi_watchdog = NMI_DEFAULT;
  62 static unsigned int nmi_hz = HZ;
  63
  64 struct nmi_watchdog_ctlblk {
  65         int enabled;
  66         u64 check_bit;
  67         unsigned int cccr_msr;
  68         unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
  69         unsigned int evntsel_msr;  /* the MSR to select the events to handle */
  70 };
  71 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
  72
  73 /* local prototypes */
  74 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
  75
  76 /* converts an msr to an appropriate reservation bit */
  77 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
  78 {
  79         /* returns the bit offset of the performance counter register */
  80         switch (boot_cpu_data.x86_vendor) {
  81         case X86_VENDOR_AMD:
  82                 return (msr - MSR_K7_PERFCTR0);
  83         case X86_VENDOR_INTEL:
  84                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
  85                         return (msr - MSR_ARCH_PERFMON_PERFCTR0);
  86                 else
  87                         return (msr - MSR_P4_BPU_PERFCTR0);
  88         }
  89         return 0;
  90 }
  91
  92 /* converts an msr to an appropriate reservation bit */
  93 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
  94 {
  95         /* returns the bit offset of the event selection register */
  96         switch (boot_cpu_data.x86_vendor) {
  97         case X86_VENDOR_AMD:
  98                 return (msr - MSR_K7_EVNTSEL0);
  99         case X86_VENDOR_INTEL:
 100                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 101                         return (msr - MSR_ARCH_PERFMON_EVENTSEL0);
 102                 else
 103                         return (msr - MSR_P4_BSU_ESCR0);
 104         }
 105         return 0;
 106 }
 107
 108 /* checks for a bit availability (hack for oprofile) */
 109 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
 110 {
 111         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 112
 113         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
 114 }
 115
 116 /* checks the an msr for availability */
 117 int avail_to_resrv_perfctr_nmi(unsigned int msr)
 118 {
 119         unsigned int counter;
 120
 121         counter = nmi_perfctr_msr_to_bit(msr);
 122         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 123
 124         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
 125 }
 126
 127 int reserve_perfctr_nmi(unsigned int msr)
 128 {
 129         unsigned int counter;
 130
 131         counter = nmi_perfctr_msr_to_bit(msr);
 132         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 133
 134         if (!test_and_set_bit(counter, &__get_cpu_var(perfctr_nmi_owner)))
 135                 return 1;
 136         return 0;
 137 }
 138
 139 void release_perfctr_nmi(unsigned int msr)
 140 {
 141         unsigned int counter;
 142
 143         counter = nmi_perfctr_msr_to_bit(msr);
 144         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 145
 146         clear_bit(counter, &__get_cpu_var(perfctr_nmi_owner));
 147 }
 148
 149 int reserve_evntsel_nmi(unsigned int msr)
 150 {
 151         unsigned int counter;
 152
 153         counter = nmi_evntsel_msr_to_bit(msr);
 154         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 155
 156         if (!test_and_set_bit(counter, &__get_cpu_var(evntsel_nmi_owner)))
 157                 return 1;
 158         return 0;
 159 }
 160
 161 void release_evntsel_nmi(unsigned int msr)
 162 {
 163         unsigned int counter;
 164
 165         counter = nmi_evntsel_msr_to_bit(msr);
 166         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 167
 168         clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner));
 169 }
 170
 171 static __cpuinit inline int nmi_known_cpu(void)
 172 {
 173         switch (boot_cpu_data.x86_vendor) {
 174         case X86_VENDOR_AMD:
 175                 return boot_cpu_data.x86 == 15;
 176         case X86_VENDOR_INTEL:
 177                 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
 178                         return 1;
 179                 else
 180                         return (boot_cpu_data.x86 == 15);
 181         }
 182         return 0;
 183 }
 184
 185 /* Run after command line and cpu_init init, but before all other checks */
 186 void nmi_watchdog_default(void)
 187 {
 188         if (nmi_watchdog != NMI_DEFAULT)
 189                 return;
 190         if (nmi_known_cpu())
 191                 nmi_watchdog = NMI_LOCAL_APIC;
 192         else
 193                 nmi_watchdog = NMI_IO_APIC;
 194 }
 195
 196 static int endflag __initdata = 0;
 197
 198 #ifdef CONFIG_SMP
 199 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
 200  * the CPU is idle. To make sure the NMI watchdog really ticks on all
 201  * CPUs during the test make them busy.
 202  */
 203 static __init void nmi_cpu_busy(void *data)
 204 {
 205         local_irq_enable_in_hardirq();
 206         /* Intentionally don't use cpu_relax here. This is
 207            to make sure that the performance counter really ticks,
 208            even if there is a simulator or similar that catches the
 209            pause instruction. On a real HT machine this is fine because
 210            all other CPUs are busy with "useless" delay loops and don't
 211            care if they get somewhat less cycles. */
 212         while (endflag == 0)
 213                 mb();
 214 }
 215 #endif
 216
 217 int __init check_nmi_watchdog (void)
 218 {
 219         int *counts;
 220         int cpu;
 221
 222         if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
 223                 return 0;
 224
 225         if (!atomic_read(&nmi_active))
 226                 return 0;
 227
 228         counts = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
 229         if (!counts)
 230                 return -1;
 231
 232         printk(KERN_INFO "testing NMI watchdog ... ");
 233
 234 #ifdef CONFIG_SMP
 235         if (nmi_watchdog == NMI_LOCAL_APIC)
 236                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
 237 #endif
 238
 239         for (cpu = 0; cpu < NR_CPUS; cpu++)
 240                 counts[cpu] = cpu_pda(cpu)->__nmi_count;
 241         local_irq_enable();
 242         mdelay((10*1000)/nmi_hz); // wait 10 ticks
 243
 244         for_each_online_cpu(cpu) {
 245                 if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
 246                         continue;
 247                 if (cpu_pda(cpu)->__nmi_count - counts[cpu] <= 5) {
 248                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
 249                                cpu,
 250                                counts[cpu],
 251                                cpu_pda(cpu)->__nmi_count);
 252                         per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
 253                         atomic_dec(&nmi_active);
 254                 }
 255         }
 256         if (!atomic_read(&nmi_active)) {
 257                 kfree(counts);
 258                 atomic_set(&nmi_active, -1);
 259                 endflag = 1;
 260                 return -1;
 261         }
 262         endflag = 1;
 263         printk("OK.\n");
 264
 265         /* now that we know it works we can reduce NMI frequency to
 266            something more reasonable; makes a difference in some configs */
 267         if (nmi_watchdog == NMI_LOCAL_APIC) {
 268                 struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 269
 270                 nmi_hz = 1;
 271                 /*
 272                  * On Intel CPUs with ARCH_PERFMON only 32 bits in the counter
 273                  * are writable, with higher bits sign extending from bit 31.
 274                  * So, we can only program the counter with 31 bit values and
 275                  * 32nd bit should be 1, for 33.. to be 1.
 276                  * Find the appropriate nmi_hz
 277                  */
 278                 if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0 &&
 279                         ((u64)cpu_khz * 1000) > 0x7fffffffULL) {
 280                         nmi_hz = ((u64)cpu_khz * 1000) / 0x7fffffffUL + 1;
 281                 }
 282         }
 283
 284         kfree(counts);
 285         return 0;
 286 }
 287
 288 int __init setup_nmi_watchdog(char *str)
 289 {
 290         int nmi;
 291
 292         if (!strncmp(str,"panic",5)) {
 293                 panic_on_timeout = 1;
 294                 str = strchr(str, ',');
 295                 if (!str)
 296                         return 1;
 297                 ++str;
 298         }
 299
 300         get_option(&str, &nmi);
 301
 302         if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
 303                 return 0;
 304
 305         nmi_watchdog = nmi;
 306         return 1;
 307 }
 308
 309 __setup("nmi_watchdog=", setup_nmi_watchdog);
 310
 311 static void disable_lapic_nmi_watchdog(void)
 312 {
 313         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 314
 315         if (atomic_read(&nmi_active) <= 0)
 316                 return;
 317
 318         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 319
 320         BUG_ON(atomic_read(&nmi_active) != 0);
 321 }
 322
 323 static void enable_lapic_nmi_watchdog(void)
 324 {
 325         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 326
 327         /* are we already enabled */
 328         if (atomic_read(&nmi_active) != 0)
 329                 return;
 330
 331         /* are we lapic aware */
 332         if (nmi_known_cpu() <= 0)
 333                 return;
 334
 335         on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 336         touch_nmi_watchdog();
 337 }
 338
 339 void disable_timer_nmi_watchdog(void)
 340 {
 341         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 342
 343         if (atomic_read(&nmi_active) <= 0)
 344                 return;
 345
 346         disable_irq(0);
 347         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 348
 349         BUG_ON(atomic_read(&nmi_active) != 0);
 350 }
 351
 352 void enable_timer_nmi_watchdog(void)
 353 {
 354         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 355
 356         if (atomic_read(&nmi_active) == 0) {
 357                 touch_nmi_watchdog();
 358                 on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 359                 enable_irq(0);
 360         }
 361 }
 362
 363 #ifdef CONFIG_PM
 364
 365 static int nmi_pm_active; /* nmi_active before suspend */
 366
 367 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 368 {
 369         /* only CPU0 goes here, other CPUs should be offline */
 370         nmi_pm_active = atomic_read(&nmi_active);
 371         stop_apic_nmi_watchdog(NULL);
 372         BUG_ON(atomic_read(&nmi_active) != 0);
 373         return 0;
 374 }
 375
 376 static int lapic_nmi_resume(struct sys_device *dev)
 377 {
 378         /* only CPU0 goes here, other CPUs should be offline */
 379         if (nmi_pm_active > 0) {
 380                 setup_apic_nmi_watchdog(NULL);
 381                 touch_nmi_watchdog();
 382         }
 383         return 0;
 384 }
 385
 386 static struct sysdev_class nmi_sysclass = {
 387         set_kset_name("lapic_nmi"),
 388         .resume         = lapic_nmi_resume,
 389         .suspend        = lapic_nmi_suspend,
 390 };
 391
 392 static struct sys_device device_lapic_nmi = {
 393         .id             = 0,
 394         .cls    = &nmi_sysclass,
 395 };
 396
 397 static int __init init_lapic_nmi_sysfs(void)
 398 {
 399         int error;
 400
 401         /* should really be a BUG_ON but b/c this is an
 402          * init call, it just doesn't work.  -dcz
 403          */
 404         if (nmi_watchdog != NMI_LOCAL_APIC)
 405                 return 0;
 406
 407         if ( atomic_read(&nmi_active) < 0 )
 408                 return 0;
 409
 410         error = sysdev_class_register(&nmi_sysclass);
 411         if (!error)
 412                 error = sysdev_register(&device_lapic_nmi);
 413         return error;
 414 }
 415 /* must come after the local APIC's device_initcall() */
 416 late_initcall(init_lapic_nmi_sysfs);
 417
 418 #endif  /* CONFIG_PM */
 419
 420 /*
 421  * Activate the NMI watchdog via the local APIC.
 422  * Original code written by Keith Owens.
 423  */
 424
 425 /* Note that these events don't tick when the CPU idles. This means
 426    the frequency varies with CPU load. */
 427
 428 #define K7_EVNTSEL_ENABLE       (1 << 22)
 429 #define K7_EVNTSEL_INT          (1 << 20)
 430 #define K7_EVNTSEL_OS           (1 << 17)
 431 #define K7_EVNTSEL_USR          (1 << 16)
 432 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
 433 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
 434
 435 static int setup_k7_watchdog(void)
 436 {
 437         unsigned int perfctr_msr, evntsel_msr;
 438         unsigned int evntsel;
 439         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 440
 441         perfctr_msr = MSR_K7_PERFCTR0;
 442         evntsel_msr = MSR_K7_EVNTSEL0;
 443         if (!reserve_perfctr_nmi(perfctr_msr))
 444                 goto fail;
 445
 446         if (!reserve_evntsel_nmi(evntsel_msr))
 447                 goto fail1;
 448
 449         /* Simulator may not support it */
 450         if (checking_wrmsrl(evntsel_msr, 0UL))
 451                 goto fail2;
 452         wrmsrl(perfctr_msr, 0UL);
 453
 454         evntsel = K7_EVNTSEL_INT
 455                 | K7_EVNTSEL_OS
 456                 | K7_EVNTSEL_USR
 457                 | K7_NMI_EVENT;
 458
 459         /* setup the timer */
 460         wrmsr(evntsel_msr, evntsel, 0);
 461         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
 462         apic_write(APIC_LVTPC, APIC_DM_NMI);
 463         evntsel |= K7_EVNTSEL_ENABLE;
 464         wrmsr(evntsel_msr, evntsel, 0);
 465
 466         wd->perfctr_msr = perfctr_msr;
 467         wd->evntsel_msr = evntsel_msr;
 468         wd->cccr_msr = 0;  //unused
 469         wd->check_bit = 1ULL<<63;
 470         return 1;
 471 fail2:
 472         release_evntsel_nmi(evntsel_msr);
 473 fail1:
 474         release_perfctr_nmi(perfctr_msr);
 475 fail:
 476         return 0;
 477 }
 478
 479 static void stop_k7_watchdog(void)
 480 {
 481         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 482
 483         wrmsr(wd->evntsel_msr, 0, 0);
 484
 485         release_evntsel_nmi(wd->evntsel_msr);
 486         release_perfctr_nmi(wd->perfctr_msr);
 487 }
 488
 489 /* Note that these events don't tick when the CPU idles. This means
 490    the frequency varies with CPU load. */
 491
 492 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
 493 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
 494 #define P4_ESCR_OS              (1<<3)
 495 #define P4_ESCR_USR             (1<<2)
 496 #define P4_CCCR_OVF_PMI0        (1<<26)
 497 #define P4_CCCR_OVF_PMI1        (1<<27)
 498 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
 499 #define P4_CCCR_COMPLEMENT      (1<<19)
 500 #define P4_CCCR_COMPARE         (1<<18)
 501 #define P4_CCCR_REQUIRED        (3<<16)
 502 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
 503 #define P4_CCCR_ENABLE          (1<<12)
 504 #define P4_CCCR_OVF             (1<<31)
 505 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
 506    CRU_ESCR0 (with any non-null event selector) through a complemented
 507    max threshold. [IA32-Vol3, Section 14.9.9] */
 508
 509 static int setup_p4_watchdog(void)
 510 {
 511         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
 512         unsigned int evntsel, cccr_val;
 513         unsigned int misc_enable, dummy;
 514         unsigned int ht_num;
 515         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 516
 517         rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
 518         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 519                 return 0;
 520
 521 #ifdef CONFIG_SMP
 522         /* detect which hyperthread we are on */
 523         if (smp_num_siblings == 2) {
 524                 unsigned int ebx, apicid;
 525
 526                 ebx = cpuid_ebx(1);
 527                 apicid = (ebx >> 24) & 0xff;
 528                 ht_num = apicid & 1;
 529         } else
 530 #endif
 531                 ht_num = 0;
 532
 533         /* performance counters are shared resources
 534          * assign each hyperthread its own set
 535          * (re-use the ESCR0 register, seems safe
 536          * and keeps the cccr_val the same)
 537          */
 538         if (!ht_num) {
 539                 /* logical cpu 0 */
 540                 perfctr_msr = MSR_P4_IQ_PERFCTR0;
 541                 evntsel_msr = MSR_P4_CRU_ESCR0;
 542                 cccr_msr = MSR_P4_IQ_CCCR0;
 543                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
 544         } else {
 545                 /* logical cpu 1 */
 546                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
 547                 evntsel_msr = MSR_P4_CRU_ESCR0;
 548                 cccr_msr = MSR_P4_IQ_CCCR1;
 549                 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
 550         }
 551
 552         if (!reserve_perfctr_nmi(perfctr_msr))
 553                 goto fail;
 554
 555         if (!reserve_evntsel_nmi(evntsel_msr))
 556                 goto fail1;
 557
 558         evntsel = P4_ESCR_EVENT_SELECT(0x3F)
 559                 | P4_ESCR_OS
 560                 | P4_ESCR_USR;
 561
 562         cccr_val |= P4_CCCR_THRESHOLD(15)
 563                  | P4_CCCR_COMPLEMENT
 564                  | P4_CCCR_COMPARE
 565                  | P4_CCCR_REQUIRED;
 566
 567         wrmsr(evntsel_msr, evntsel, 0);
 568         wrmsr(cccr_msr, cccr_val, 0);
 569         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
 570         apic_write(APIC_LVTPC, APIC_DM_NMI);
 571         cccr_val |= P4_CCCR_ENABLE;
 572         wrmsr(cccr_msr, cccr_val, 0);
 573
 574         wd->perfctr_msr = perfctr_msr;
 575         wd->evntsel_msr = evntsel_msr;
 576         wd->cccr_msr = cccr_msr;
 577         wd->check_bit = 1ULL<<39;
 578         return 1;
 579 fail1:
 580         release_perfctr_nmi(perfctr_msr);
 581 fail:
 582         return 0;
 583 }
 584
 585 static void stop_p4_watchdog(void)
 586 {
 587         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 588
 589         wrmsr(wd->cccr_msr, 0, 0);
 590         wrmsr(wd->evntsel_msr, 0, 0);
 591
 592         release_evntsel_nmi(wd->evntsel_msr);
 593         release_perfctr_nmi(wd->perfctr_msr);
 594 }
 595
 596 #define ARCH_PERFMON_NMI_EVENT_SEL      ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL
 597 #define ARCH_PERFMON_NMI_EVENT_UMASK    ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK
 598
 599 static int setup_intel_arch_watchdog(void)
 600 {
 601         unsigned int ebx;
 602         union cpuid10_eax eax;
 603         unsigned int unused;
 604         unsigned int perfctr_msr, evntsel_msr;
 605         unsigned int evntsel;
 606         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 607
 608         /*
 609          * Check whether the Architectural PerfMon supports
 610          * Unhalted Core Cycles Event or not.
 611          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 612          */
 613         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 614         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 615             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 616                 goto fail;
 617
 618         perfctr_msr = MSR_ARCH_PERFMON_PERFCTR0;
 619         evntsel_msr = MSR_ARCH_PERFMON_EVENTSEL0;
 620
 621         if (!reserve_perfctr_nmi(perfctr_msr))
 622                 goto fail;
 623
 624         if (!reserve_evntsel_nmi(evntsel_msr))
 625                 goto fail1;
 626
 627         wrmsrl(perfctr_msr, 0UL);
 628
 629         evntsel = ARCH_PERFMON_EVENTSEL_INT
 630                 | ARCH_PERFMON_EVENTSEL_OS
 631                 | ARCH_PERFMON_EVENTSEL_USR
 632                 | ARCH_PERFMON_NMI_EVENT_SEL
 633                 | ARCH_PERFMON_NMI_EVENT_UMASK;
 634
 635         /* setup the timer */
 636         wrmsr(evntsel_msr, evntsel, 0);
 637         wrmsrl(perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
 638
 639         apic_write(APIC_LVTPC, APIC_DM_NMI);
 640         evntsel |= ARCH_PERFMON_EVENTSEL0_ENABLE;
 641         wrmsr(evntsel_msr, evntsel, 0);
 642
 643         wd->perfctr_msr = perfctr_msr;
 644         wd->evntsel_msr = evntsel_msr;
 645         wd->cccr_msr = 0;  //unused
 646         wd->check_bit = 1ULL << (eax.split.bit_width - 1);
 647         return 1;
 648 fail1:
 649         release_perfctr_nmi(perfctr_msr);
 650 fail:
 651         return 0;
 652 }
 653
 654 static void stop_intel_arch_watchdog(void)
 655 {
 656         unsigned int ebx;
 657         union cpuid10_eax eax;
 658         unsigned int unused;
 659         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 660
 661         /*
 662          * Check whether the Architectural PerfMon supports
 663          * Unhalted Core Cycles Event or not.
 664          * NOTE: Corresponding bit = 0 in ebx indicates event present.
 665          */
 666         cpuid(10, &(eax.full), &ebx, &unused, &unused);
 667         if ((eax.split.mask_length < (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX+1)) ||
 668             (ebx & ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT))
 669                 return;
 670
 671         wrmsr(wd->evntsel_msr, 0, 0);
 672
 673         release_evntsel_nmi(wd->evntsel_msr);
 674         release_perfctr_nmi(wd->perfctr_msr);
 675 }
 676
 677 void setup_apic_nmi_watchdog(void *unused)
 678 {
 679         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 680
 681         /* only support LOCAL and IO APICs for now */
 682         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 683             (nmi_watchdog != NMI_IO_APIC))
 684                 return;
 685
 686         if (wd->enabled == 1)
 687                 return;
 688
 689         /* cheap hack to support suspend/resume */
 690         /* if cpu0 is not active neither should the other cpus */
 691         if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
 692                 return;
 693
 694         if (nmi_watchdog == NMI_LOCAL_APIC) {
 695                 switch (boot_cpu_data.x86_vendor) {
 696                 case X86_VENDOR_AMD:
 697                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
 698                                 return;
 699                         if (!setup_k7_watchdog())
 700                                 return;
 701                         break;
 702                 case X86_VENDOR_INTEL:
 703                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 704                                 if (!setup_intel_arch_watchdog())
 705                                         return;
 706                                 break;
 707                         }
 708                         if (!setup_p4_watchdog())
 709                                 return;
 710                         break;
 711                 default:
 712                         return;
 713                 }
 714         }
 715         wd->enabled = 1;
 716         atomic_inc(&nmi_active);
 717 }
 718
 719 void stop_apic_nmi_watchdog(void *unused)
 720 {
 721         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 722
 723         /* only support LOCAL and IO APICs for now */
 724         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 725             (nmi_watchdog != NMI_IO_APIC))
 726                 return;
 727
 728         if (wd->enabled == 0)
 729                 return;
 730
 731         if (nmi_watchdog == NMI_LOCAL_APIC) {
 732                 switch (boot_cpu_data.x86_vendor) {
 733                 case X86_VENDOR_AMD:
 734                         if (strstr(boot_cpu_data.x86_model_id, "Screwdriver"))
 735                                 return;
 736                         stop_k7_watchdog();
 737                         break;
 738                 case X86_VENDOR_INTEL:
 739                         if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 740                                 stop_intel_arch_watchdog();
 741                                 break;
 742                         }
 743                         stop_p4_watchdog();
 744                         break;
 745                 default:
 746                         return;
 747                 }
 748         }
 749         wd->enabled = 0;
 750         atomic_dec(&nmi_active);
 751 }
 752
 753 /*
 754  * the best way to detect whether a CPU has a 'hard lockup' problem
 755  * is to check it's local APIC timer IRQ counts. If they are not
 756  * changing then that CPU has some problem.
 757  *
 758  * as these watchdog NMI IRQs are generated on every CPU, we only
 759  * have to check the current processor.
 760  */
 761
 762 static DEFINE_PER_CPU(unsigned, last_irq_sum);
 763 static DEFINE_PER_CPU(local_t, alert_counter);
 764 static DEFINE_PER_CPU(int, nmi_touch);
 765
 766 void touch_nmi_watchdog (void)
 767 {
 768         if (nmi_watchdog > 0) {
 769                 unsigned cpu;
 770
 771                 /*
 772                  * Tell other CPUs to reset their alert counters. We cannot
 773                  * do it ourselves because the alert count increase is not
 774                  * atomic.
 775                  */
 776                 for_each_present_cpu (cpu)
 777                         per_cpu(nmi_touch, cpu) = 1;
 778         }
 779
 780         touch_softlockup_watchdog();
 781 }
 782
 783 int __kprobes nmi_watchdog_tick(struct pt_regs * regs, unsigned reason)
 784 {
 785         int sum;
 786         int touched = 0;
 787         int cpu = smp_processor_id();
 788         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 789         u64 dummy;
 790         int rc=0;
 791
 792         /* check for other users first */
 793         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
 794                         == NOTIFY_STOP) {
 795                 rc = 1;
 796                 touched = 1;
 797         }
 798
 799         sum = read_pda(apic_timer_irqs);
 800         if (__get_cpu_var(nmi_touch)) {
 801                 __get_cpu_var(nmi_touch) = 0;
 802                 touched = 1;
 803         }
 804
 805         if (cpu_isset(cpu, backtrace_mask)) {
 806                 static DEFINE_SPINLOCK(lock);   /* Serialise the printks */
 807
 808                 spin_lock(&lock);
 809                 printk("NMI backtrace for cpu %d\n", cpu);
 810                 dump_stack();
 811                 spin_unlock(&lock);
 812                 cpu_clear(cpu, backtrace_mask);
 813         }
 814
 815 #ifdef CONFIG_X86_MCE
 816         /* Could check oops_in_progress here too, but it's safer
 817            not too */
 818         if (atomic_read(&mce_entry) > 0)
 819                 touched = 1;
 820 #endif
 821         /* if the apic timer isn't firing, this cpu isn't doing much */
 822         if (!touched && __get_cpu_var(last_irq_sum) == sum) {
 823                 /*
 824                  * Ayiee, looks like this CPU is stuck ...
 825                  * wait a few IRQs (5 seconds) before doing the oops ...
 826                  */
 827                 local_inc(&__get_cpu_var(alert_counter));
 828                 if (local_read(&__get_cpu_var(alert_counter)) == 5*nmi_hz)
 829                         die_nmi("NMI Watchdog detected LOCKUP on CPU %d\n", regs,
 830                                 panic_on_timeout);
 831         } else {
 832                 __get_cpu_var(last_irq_sum) = sum;
 833                 local_set(&__get_cpu_var(alert_counter), 0);
 834         }
 835
 836         /* see if the nmi watchdog went off */
 837         if (wd->enabled) {
 838                 if (nmi_watchdog == NMI_LOCAL_APIC) {
 839                         rdmsrl(wd->perfctr_msr, dummy);
 840                         if (dummy & wd->check_bit){
 841                                 /* this wasn't a watchdog timer interrupt */
 842                                 goto done;
 843                         }
 844
 845                         /* only Intel uses the cccr msr */
 846                         if (wd->cccr_msr != 0) {
 847                                 /*
 848                                  * P4 quirks:
 849                                  * - An overflown perfctr will assert its interrupt
 850                                  *   until the OVF flag in its CCCR is cleared.
 851                                  * - LVTPC is masked on interrupt and must be
 852                                  *   unmasked by the LVTPC handler.
 853                                  */
 854                                 rdmsrl(wd->cccr_msr, dummy);
 855                                 dummy &= ~P4_CCCR_OVF;
 856                                 wrmsrl(wd->cccr_msr, dummy);
 857                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 858                         } else if (wd->perfctr_msr == MSR_ARCH_PERFMON_PERFCTR0) {
 859                                 /*
 860                                  * ArchPerfom/Core Duo needs to re-unmask
 861                                  * the apic vector
 862                                  */
 863                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 864                         }
 865                         /* start the cycle over again */
 866                         wrmsrl(wd->perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
 867                         rc = 1;
 868                 } else  if (nmi_watchdog == NMI_IO_APIC) {
 869                         /* don't know how to accurately check for this.
 870                          * just assume it was a watchdog timer interrupt
 871                          * This matches the old behaviour.
 872                          */
 873                         rc = 1;
 874                 } else
 875                         printk(KERN_WARNING "Unknown enabled NMI hardware?!\n");
 876         }
 877 done:
 878         return rc;
 879 }
 880
 881 asmlinkage __kprobes void do_nmi(struct pt_regs * regs, long error_code)
 882 {
 883         nmi_enter();
 884         add_pda(__nmi_count,1);
 885         default_do_nmi(regs);
 886         nmi_exit();
 887 }
 888
 889 int do_nmi_callback(struct pt_regs * regs, int cpu)
 890 {
 891 #ifdef CONFIG_SYSCTL
 892         if (unknown_nmi_panic)
 893                 return unknown_nmi_panic_callback(regs, cpu);
 894 #endif
 895         return 0;
 896 }
 897
 898 #ifdef CONFIG_SYSCTL
 899
 900 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
 901 {
 902         unsigned char reason = get_nmi_reason();
 903         char buf[64];
 904
 905         sprintf(buf, "NMI received for unknown reason %02x\n", reason);
 906         die_nmi(buf, regs, 1);  /* Always panic here */
 907         return 0;
 908 }
 909
 910 /*
 911  * proc handler for /proc/sys/kernel/nmi
 912  */
 913 int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
 914                         void __user *buffer, size_t *length, loff_t *ppos)
 915 {
 916         int old_state;
 917
 918         nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
 919         old_state = nmi_watchdog_enabled;
 920         proc_dointvec(table, write, file, buffer, length, ppos);
 921         if (!!old_state == !!nmi_watchdog_enabled)
 922                 return 0;
 923
 924         if (atomic_read(&nmi_active) < 0) {
 925                 printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
 926                 return -EIO;
 927         }
 928
 929         /* if nmi_watchdog is not set yet, then set it */
 930         nmi_watchdog_default();
 931
 932         if (nmi_watchdog == NMI_LOCAL_APIC) {
 933                 if (nmi_watchdog_enabled)
 934                         enable_lapic_nmi_watchdog();
 935                 else
 936                         disable_lapic_nmi_watchdog();
 937         } else {
 938                 printk( KERN_WARNING
 939                         "NMI watchdog doesn't know what hardware to touch\n");
 940                 return -EIO;
 941         }
 942         return 0;
 943 }
 944
 945 #endif
 946
 947 void __trigger_all_cpu_backtrace(void)
 948 {
 949         int i;
 950
 951         backtrace_mask = cpu_online_map;
 952         /* Wait for up to 10 seconds for all CPUs to do the backtrace */
 953         for (i = 0; i < 10 * 1000; i++) {
 954                 if (cpus_empty(backtrace_mask))
 955                         break;
 956                 mdelay(1);
 957         }
 958 }
 959
 960 EXPORT_SYMBOL(nmi_active);
 961 EXPORT_SYMBOL(nmi_watchdog);
 962 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
 963 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
 964 EXPORT_SYMBOL(reserve_perfctr_nmi);
 965 EXPORT_SYMBOL(release_perfctr_nmi);
 966 EXPORT_SYMBOL(reserve_evntsel_nmi);
 967 EXPORT_SYMBOL(release_evntsel_nmi);
 968 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
 969 EXPORT_SYMBOL(enable_timer_nmi_watchdog);
 970 EXPORT_SYMBOL(touch_nmi_watchdog);