arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/config.h>
  30 #include <linux/smp_lock.h>
  31 #include <linux/mc146818rtc.h>
  32 #include <linux/acpi.h>
  33 #include <linux/sysdev.h>
  34
  35 #include <asm/io.h>
  36 #include <asm/smp.h>
  37 #include <asm/desc.h>
  38 #include <asm/proto.h>
  39 #include <asm/mach_apic.h>
  40 #include <asm/acpi.h>
  41
  42 #define __apicdebuginit  __init
  43
  44 int sis_apic_bug; /* not actually supported, dummy for compile */
  45
  46 static int no_timer_check;
  47
  48 static DEFINE_SPINLOCK(ioapic_lock);
  49
  50 /*
  51  * # of IRQ routing registers
  52  */
  53 int nr_ioapic_registers[MAX_IO_APICS];
  54
  55 /*
  56  * Rough estimation of how many shared IRQs there are, can
  57  * be changed anytime.
  58  */
  59 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  60 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  61
  62 /*
  63  * This is performance-critical, we want to do it O(1)
  64  *
  65  * the indexing order of this array favors 1:1 mappings
  66  * between pins and IRQs.
  67  */
  68
  69 static struct irq_pin_list {
  70         short apic, pin, next;
  71 } irq_2_pin[PIN_MAP_SIZE];
  72
  73 int vector_irq[NR_VECTORS] __read_mostly = { [0 ... NR_VECTORS - 1] = -1};
  74 #ifdef CONFIG_PCI_MSI
  75 #define vector_to_irq(vector)   \
  76         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  77 #else
  78 #define vector_to_irq(vector)   (vector)
  79 #endif
  80
  81 #define __DO_ACTION(R, ACTION, FINAL)                                   \
  82                                                                         \
  83 {                                                                       \
  84         int pin;                                                        \
  85         struct irq_pin_list *entry = irq_2_pin + irq;                   \
  86                                                                         \
  87         for (;;) {                                                      \
  88                 unsigned int reg;                                       \
  89                 pin = entry->pin;                                       \
  90                 if (pin == -1)                                          \
  91                         break;                                          \
  92                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
  93                 reg ACTION;                                             \
  94                 io_apic_modify(entry->apic, reg);                       \
  95                 if (!entry->next)                                       \
  96                         break;                                          \
  97                 entry = irq_2_pin + entry->next;                        \
  98         }                                                               \
  99         FINAL;                                                          \
 100 }
 101
 102 #ifdef CONFIG_SMP
 103 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
 104 {
 105         unsigned long flags;
 106         unsigned int dest;
 107         cpumask_t tmp;
 108
 109         cpus_and(tmp, mask, cpu_online_map);
 110         if (cpus_empty(tmp))
 111                 tmp = TARGET_CPUS;
 112
 113         cpus_and(mask, tmp, CPU_MASK_ALL);
 114
 115         dest = cpu_mask_to_apicid(mask);
 116
 117         /*
 118          * Only the high 8 bits are valid.
 119          */
 120         dest = SET_APIC_LOGICAL_ID(dest);
 121
 122         spin_lock_irqsave(&ioapic_lock, flags);
 123         __DO_ACTION(1, = dest, )
 124         set_irq_info(irq, mask);
 125         spin_unlock_irqrestore(&ioapic_lock, flags);
 126 }
 127 #endif
 128
 129 /*
 130  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 131  * shared ISA-space IRQs, so we have to support them. We are super
 132  * fast in the common case, and fast for shared ISA-space IRQs.
 133  */
 134 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
 135 {
 136         static int first_free_entry = NR_IRQS;
 137         struct irq_pin_list *entry = irq_2_pin + irq;
 138
 139         while (entry->next)
 140                 entry = irq_2_pin + entry->next;
 141
 142         if (entry->pin != -1) {
 143                 entry->next = first_free_entry;
 144                 entry = irq_2_pin + entry->next;
 145                 if (++first_free_entry >= PIN_MAP_SIZE)
 146                         panic("io_apic.c: whoops");
 147         }
 148         entry->apic = apic;
 149         entry->pin = pin;
 150 }
 151
 152
 153 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 154                                                                         \
 155         static void name##_IO_APIC_irq (unsigned int irq)               \
 156         __DO_ACTION(R, ACTION, FINAL)
 157
 158 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 159                                                 /* mask = 1 */
 160 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 161                                                 /* mask = 0 */
 162
 163 static void mask_IO_APIC_irq (unsigned int irq)
 164 {
 165         unsigned long flags;
 166
 167         spin_lock_irqsave(&ioapic_lock, flags);
 168         __mask_IO_APIC_irq(irq);
 169         spin_unlock_irqrestore(&ioapic_lock, flags);
 170 }
 171
 172 static void unmask_IO_APIC_irq (unsigned int irq)
 173 {
 174         unsigned long flags;
 175
 176         spin_lock_irqsave(&ioapic_lock, flags);
 177         __unmask_IO_APIC_irq(irq);
 178         spin_unlock_irqrestore(&ioapic_lock, flags);
 179 }
 180
 181 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 182 {
 183         struct IO_APIC_route_entry entry;
 184         unsigned long flags;
 185
 186         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 187         spin_lock_irqsave(&ioapic_lock, flags);
 188         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 189         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 190         spin_unlock_irqrestore(&ioapic_lock, flags);
 191         if (entry.delivery_mode == dest_SMI)
 192                 return;
 193         /*
 194          * Disable it in the IO-APIC irq-routing table:
 195          */
 196         memset(&entry, 0, sizeof(entry));
 197         entry.mask = 1;
 198         spin_lock_irqsave(&ioapic_lock, flags);
 199         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 200         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 201         spin_unlock_irqrestore(&ioapic_lock, flags);
 202 }
 203
 204 static void clear_IO_APIC (void)
 205 {
 206         int apic, pin;
 207
 208         for (apic = 0; apic < nr_ioapics; apic++)
 209                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 210                         clear_IO_APIC_pin(apic, pin);
 211 }
 212
 213 /*
 214  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 215  * specific CPU-side IRQs.
 216  */
 217
 218 #define MAX_PIRQS 8
 219 static int pirq_entries [MAX_PIRQS];
 220 static int pirqs_enabled;
 221 int skip_ioapic_setup;
 222 int ioapic_force;
 223
 224 /* dummy parsing: see setup.c */
 225
 226 static int __init disable_ioapic_setup(char *str)
 227 {
 228         skip_ioapic_setup = 1;
 229         return 1;
 230 }
 231
 232 static int __init enable_ioapic_setup(char *str)
 233 {
 234         ioapic_force = 1;
 235         skip_ioapic_setup = 0;
 236         return 1;
 237 }
 238
 239 __setup("noapic", disable_ioapic_setup);
 240 __setup("apic", enable_ioapic_setup);
 241
 242 #include <asm/pci-direct.h>
 243 #include <linux/pci_ids.h>
 244 #include <linux/pci.h>
 245
 246 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 247    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 248    Use pci direct infrastructure because this runs before the PCI subsystem.
 249
 250    Can be overwritten with "apic"
 251
 252    And another hack to disable the IOMMU on VIA chipsets.
 253
 254    Kludge-O-Rama. */
 255 void __init check_ioapic(void)
 256 {
 257         int num,slot,func;
 258         if (ioapic_force)
 259                 return;
 260
 261         /* Poor man's PCI discovery */
 262         for (num = 0; num < 32; num++) {
 263                 for (slot = 0; slot < 32; slot++) {
 264                         for (func = 0; func < 8; func++) {
 265                                 u32 class;
 266                                 u32 vendor;
 267                                 u8 type;
 268                                 class = read_pci_config(num,slot,func,
 269                                                         PCI_CLASS_REVISION);
 270                                 if (class == 0xffffffff)
 271                                         break;
 272
 273                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 274                                         continue;
 275
 276                                 vendor = read_pci_config(num, slot, func,
 277                                                          PCI_VENDOR_ID);
 278                                 vendor &= 0xffff;
 279                                 switch (vendor) {
 280                                 case PCI_VENDOR_ID_VIA:
 281 #ifdef CONFIG_GART_IOMMU
 282                                         if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) ||
 283                                              force_iommu) &&
 284                                             !iommu_aperture_allowed) {
 285                                                 printk(KERN_INFO
 286     "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
 287                                                 iommu_aperture_disabled = 1;
 288                                         }
 289 #endif
 290                                         return;
 291                                 case PCI_VENDOR_ID_NVIDIA:
 292 #ifdef CONFIG_ACPI
 293                                         /* All timer overrides on Nvidia
 294                                            seem to be wrong. Skip them. */
 295                                         acpi_skip_timer_override = 1;
 296                                         printk(KERN_INFO
 297              "Nvidia board detected. Ignoring ACPI timer override.\n");
 298 #endif
 299                                         /* RED-PEN skip them on mptables too? */
 300                                         return;
 301                                 }
 302
 303                                 /* No multi-function device? */
 304                                 type = read_pci_config_byte(num,slot,func,
 305                                                             PCI_HEADER_TYPE);
 306                                 if (!(type & 0x80))
 307                                         break;
 308                         }
 309                 }
 310         }
 311 }
 312
 313 static int __init ioapic_pirq_setup(char *str)
 314 {
 315         int i, max;
 316         int ints[MAX_PIRQS+1];
 317
 318         get_options(str, ARRAY_SIZE(ints), ints);
 319
 320         for (i = 0; i < MAX_PIRQS; i++)
 321                 pirq_entries[i] = -1;
 322
 323         pirqs_enabled = 1;
 324         apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
 325         max = MAX_PIRQS;
 326         if (ints[0] < MAX_PIRQS)
 327                 max = ints[0];
 328
 329         for (i = 0; i < max; i++) {
 330                 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 331                 /*
 332                  * PIRQs are mapped upside down, usually.
 333                  */
 334                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 335         }
 336         return 1;
 337 }
 338
 339 __setup("pirq=", ioapic_pirq_setup);
 340
 341 /*
 342  * Find the IRQ entry number of a certain pin.
 343  */
 344 static int find_irq_entry(int apic, int pin, int type)
 345 {
 346         int i;
 347
 348         for (i = 0; i < mp_irq_entries; i++)
 349                 if (mp_irqs[i].mpc_irqtype == type &&
 350                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 351                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 352                     mp_irqs[i].mpc_dstirq == pin)
 353                         return i;
 354
 355         return -1;
 356 }
 357
 358 /*
 359  * Find the pin to which IRQ[irq] (ISA) is connected
 360  */
 361 static int find_isa_irq_pin(int irq, int type)
 362 {
 363         int i;
 364
 365         for (i = 0; i < mp_irq_entries; i++) {
 366                 int lbus = mp_irqs[i].mpc_srcbus;
 367
 368                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 369                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 370                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 371                     (mp_irqs[i].mpc_irqtype == type) &&
 372                     (mp_irqs[i].mpc_srcbusirq == irq))
 373
 374                         return mp_irqs[i].mpc_dstirq;
 375         }
 376         return -1;
 377 }
 378
 379 /*
 380  * Find a specific PCI IRQ entry.
 381  * Not an __init, possibly needed by modules
 382  */
 383 static int pin_2_irq(int idx, int apic, int pin);
 384
 385 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 386 {
 387         int apic, i, best_guess = -1;
 388
 389         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 390                 bus, slot, pin);
 391         if (mp_bus_id_to_pci_bus[bus] == -1) {
 392                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 393                 return -1;
 394         }
 395         for (i = 0; i < mp_irq_entries; i++) {
 396                 int lbus = mp_irqs[i].mpc_srcbus;
 397
 398                 for (apic = 0; apic < nr_ioapics; apic++)
 399                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 400                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 401                                 break;
 402
 403                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 404                     !mp_irqs[i].mpc_irqtype &&
 405                     (bus == lbus) &&
 406                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 407                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 408
 409                         if (!(apic || IO_APIC_IRQ(irq)))
 410                                 continue;
 411
 412                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 413                                 return irq;
 414                         /*
 415                          * Use the first all-but-pin matching entry as a
 416                          * best-guess fuzzy result for broken mptables.
 417                          */
 418                         if (best_guess < 0)
 419                                 best_guess = irq;
 420                 }
 421         }
 422         return best_guess;
 423 }
 424
 425 /*
 426  * EISA Edge/Level control register, ELCR
 427  */
 428 static int EISA_ELCR(unsigned int irq)
 429 {
 430         if (irq < 16) {
 431                 unsigned int port = 0x4d0 + (irq >> 3);
 432                 return (inb(port) >> (irq & 7)) & 1;
 433         }
 434         apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
 435         return 0;
 436 }
 437
 438 /* EISA interrupts are always polarity zero and can be edge or level
 439  * trigger depending on the ELCR value.  If an interrupt is listed as
 440  * EISA conforming in the MP table, that means its trigger type must
 441  * be read in from the ELCR */
 442
 443 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 444 #define default_EISA_polarity(idx)      (0)
 445
 446 /* ISA interrupts are always polarity zero edge triggered,
 447  * when listed as conforming in the MP table. */
 448
 449 #define default_ISA_trigger(idx)        (0)
 450 #define default_ISA_polarity(idx)       (0)
 451
 452 /* PCI interrupts are always polarity one level triggered,
 453  * when listed as conforming in the MP table. */
 454
 455 #define default_PCI_trigger(idx)        (1)
 456 #define default_PCI_polarity(idx)       (1)
 457
 458 /* MCA interrupts are always polarity zero level triggered,
 459  * when listed as conforming in the MP table. */
 460
 461 #define default_MCA_trigger(idx)        (1)
 462 #define default_MCA_polarity(idx)       (0)
 463
 464 static int __init MPBIOS_polarity(int idx)
 465 {
 466         int bus = mp_irqs[idx].mpc_srcbus;
 467         int polarity;
 468
 469         /*
 470          * Determine IRQ line polarity (high active or low active):
 471          */
 472         switch (mp_irqs[idx].mpc_irqflag & 3)
 473         {
 474                 case 0: /* conforms, ie. bus-type dependent polarity */
 475                 {
 476                         switch (mp_bus_id_to_type[bus])
 477                         {
 478                                 case MP_BUS_ISA: /* ISA pin */
 479                                 {
 480                                         polarity = default_ISA_polarity(idx);
 481                                         break;
 482                                 }
 483                                 case MP_BUS_EISA: /* EISA pin */
 484                                 {
 485                                         polarity = default_EISA_polarity(idx);
 486                                         break;
 487                                 }
 488                                 case MP_BUS_PCI: /* PCI pin */
 489                                 {
 490                                         polarity = default_PCI_polarity(idx);
 491                                         break;
 492                                 }
 493                                 case MP_BUS_MCA: /* MCA pin */
 494                                 {
 495                                         polarity = default_MCA_polarity(idx);
 496                                         break;
 497                                 }
 498                                 default:
 499                                 {
 500                                         printk(KERN_WARNING "broken BIOS!!\n");
 501                                         polarity = 1;
 502                                         break;
 503                                 }
 504                         }
 505                         break;
 506                 }
 507                 case 1: /* high active */
 508                 {
 509                         polarity = 0;
 510                         break;
 511                 }
 512                 case 2: /* reserved */
 513                 {
 514                         printk(KERN_WARNING "broken BIOS!!\n");
 515                         polarity = 1;
 516                         break;
 517                 }
 518                 case 3: /* low active */
 519                 {
 520                         polarity = 1;
 521                         break;
 522                 }
 523                 default: /* invalid */
 524                 {
 525                         printk(KERN_WARNING "broken BIOS!!\n");
 526                         polarity = 1;
 527                         break;
 528                 }
 529         }
 530         return polarity;
 531 }
 532
 533 static int MPBIOS_trigger(int idx)
 534 {
 535         int bus = mp_irqs[idx].mpc_srcbus;
 536         int trigger;
 537
 538         /*
 539          * Determine IRQ trigger mode (edge or level sensitive):
 540          */
 541         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 542         {
 543                 case 0: /* conforms, ie. bus-type dependent */
 544                 {
 545                         switch (mp_bus_id_to_type[bus])
 546                         {
 547                                 case MP_BUS_ISA: /* ISA pin */
 548                                 {
 549                                         trigger = default_ISA_trigger(idx);
 550                                         break;
 551                                 }
 552                                 case MP_BUS_EISA: /* EISA pin */
 553                                 {
 554                                         trigger = default_EISA_trigger(idx);
 555                                         break;
 556                                 }
 557                                 case MP_BUS_PCI: /* PCI pin */
 558                                 {
 559                                         trigger = default_PCI_trigger(idx);
 560                                         break;
 561                                 }
 562                                 case MP_BUS_MCA: /* MCA pin */
 563                                 {
 564                                         trigger = default_MCA_trigger(idx);
 565                                         break;
 566                                 }
 567                                 default:
 568                                 {
 569                                         printk(KERN_WARNING "broken BIOS!!\n");
 570                                         trigger = 1;
 571                                         break;
 572                                 }
 573                         }
 574                         break;
 575                 }
 576                 case 1: /* edge */
 577                 {
 578                         trigger = 0;
 579                         break;
 580                 }
 581                 case 2: /* reserved */
 582                 {
 583                         printk(KERN_WARNING "broken BIOS!!\n");
 584                         trigger = 1;
 585                         break;
 586                 }
 587                 case 3: /* level */
 588                 {
 589                         trigger = 1;
 590                         break;
 591                 }
 592                 default: /* invalid */
 593                 {
 594                         printk(KERN_WARNING "broken BIOS!!\n");
 595                         trigger = 0;
 596                         break;
 597                 }
 598         }
 599         return trigger;
 600 }
 601
 602 static inline int irq_polarity(int idx)
 603 {
 604         return MPBIOS_polarity(idx);
 605 }
 606
 607 static inline int irq_trigger(int idx)
 608 {
 609         return MPBIOS_trigger(idx);
 610 }
 611
 612 static int pin_2_irq(int idx, int apic, int pin)
 613 {
 614         int irq, i;
 615         int bus = mp_irqs[idx].mpc_srcbus;
 616
 617         /*
 618          * Debugging check, we are in big trouble if this message pops up!
 619          */
 620         if (mp_irqs[idx].mpc_dstirq != pin)
 621                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 622
 623         switch (mp_bus_id_to_type[bus])
 624         {
 625                 case MP_BUS_ISA: /* ISA pin */
 626                 case MP_BUS_EISA:
 627                 case MP_BUS_MCA:
 628                 {
 629                         irq = mp_irqs[idx].mpc_srcbusirq;
 630                         break;
 631                 }
 632                 case MP_BUS_PCI: /* PCI pin */
 633                 {
 634                         /*
 635                          * PCI IRQs are mapped in order
 636                          */
 637                         i = irq = 0;
 638                         while (i < apic)
 639                                 irq += nr_ioapic_registers[i++];
 640                         irq += pin;
 641                         break;
 642                 }
 643                 default:
 644                 {
 645                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 646                         irq = 0;
 647                         break;
 648                 }
 649         }
 650
 651         /*
 652          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 653          */
 654         if ((pin >= 16) && (pin <= 23)) {
 655                 if (pirq_entries[pin-16] != -1) {
 656                         if (!pirq_entries[pin-16]) {
 657                                 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
 658                         } else {
 659                                 irq = pirq_entries[pin-16];
 660                                 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
 661                                                 pin-16, irq);
 662                         }
 663                 }
 664         }
 665         return irq;
 666 }
 667
 668 static inline int IO_APIC_irq_trigger(int irq)
 669 {
 670         int apic, idx, pin;
 671
 672         for (apic = 0; apic < nr_ioapics; apic++) {
 673                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 674                         idx = find_irq_entry(apic,pin,mp_INT);
 675                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 676                                 return irq_trigger(idx);
 677                 }
 678         }
 679         /*
 680          * nonexistent IRQs are edge default
 681          */
 682         return 0;
 683 }
 684
 685 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 686 u8 irq_vector[NR_IRQ_VECTORS] __read_mostly = { FIRST_DEVICE_VECTOR , 0 };
 687
 688 int assign_irq_vector(int irq)
 689 {
 690         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 691
 692         BUG_ON(irq >= NR_IRQ_VECTORS);
 693         if (IO_APIC_VECTOR(irq) > 0)
 694                 return IO_APIC_VECTOR(irq);
 695 next:
 696         current_vector += 8;
 697         if (current_vector == IA32_SYSCALL_VECTOR)
 698                 goto next;
 699
 700         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 701                 offset++;
 702                 if (!(offset%8))
 703                         return -ENOSPC;
 704                 current_vector = FIRST_DEVICE_VECTOR + offset;
 705         }
 706
 707         vector_irq[current_vector] = irq;
 708         if (irq != AUTO_ASSIGN)
 709                 IO_APIC_VECTOR(irq) = current_vector;
 710
 711         return current_vector;
 712 }
 713
 714 extern void (*interrupt[NR_IRQS])(void);
 715 static struct hw_interrupt_type ioapic_level_type;
 716 static struct hw_interrupt_type ioapic_edge_type;
 717
 718 #define IOAPIC_AUTO     -1
 719 #define IOAPIC_EDGE     0
 720 #define IOAPIC_LEVEL    1
 721
 722 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 723 {
 724         if (use_pci_vector() && !platform_legacy_irq(irq)) {
 725                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 726                                 trigger == IOAPIC_LEVEL)
 727                         irq_desc[vector].handler = &ioapic_level_type;
 728                 else
 729                         irq_desc[vector].handler = &ioapic_edge_type;
 730                 set_intr_gate(vector, interrupt[vector]);
 731         } else  {
 732                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 733                                 trigger == IOAPIC_LEVEL)
 734                         irq_desc[irq].handler = &ioapic_level_type;
 735                 else
 736                         irq_desc[irq].handler = &ioapic_edge_type;
 737                 set_intr_gate(vector, interrupt[irq]);
 738         }
 739 }
 740
 741 static void __init setup_IO_APIC_irqs(void)
 742 {
 743         struct IO_APIC_route_entry entry;
 744         int apic, pin, idx, irq, first_notcon = 1, vector;
 745         unsigned long flags;
 746
 747         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 748
 749         for (apic = 0; apic < nr_ioapics; apic++) {
 750         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 751
 752                 /*
 753                  * add it to the IO-APIC irq-routing table:
 754                  */
 755                 memset(&entry,0,sizeof(entry));
 756
 757                 entry.delivery_mode = INT_DELIVERY_MODE;
 758                 entry.dest_mode = INT_DEST_MODE;
 759                 entry.mask = 0;                         /* enable IRQ */
 760                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 761
 762                 idx = find_irq_entry(apic,pin,mp_INT);
 763                 if (idx == -1) {
 764                         if (first_notcon) {
 765                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 766                                 first_notcon = 0;
 767                         } else
 768                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 769                         continue;
 770                 }
 771
 772                 entry.trigger = irq_trigger(idx);
 773                 entry.polarity = irq_polarity(idx);
 774
 775                 if (irq_trigger(idx)) {
 776                         entry.trigger = 1;
 777                         entry.mask = 1;
 778                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 779                 }
 780
 781                 irq = pin_2_irq(idx, apic, pin);
 782                 add_pin_to_irq(irq, apic, pin);
 783
 784                 if (!apic && !IO_APIC_IRQ(irq))
 785                         continue;
 786
 787                 if (IO_APIC_IRQ(irq)) {
 788                         vector = assign_irq_vector(irq);
 789                         entry.vector = vector;
 790
 791                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 792                         if (!apic && (irq < 16))
 793                                 disable_8259A_irq(irq);
 794                 }
 795                 spin_lock_irqsave(&ioapic_lock, flags);
 796                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 797                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 798                 set_native_irq_info(irq, TARGET_CPUS);
 799                 spin_unlock_irqrestore(&ioapic_lock, flags);
 800         }
 801         }
 802
 803         if (!first_notcon)
 804                 apic_printk(APIC_VERBOSE," not connected.\n");
 805 }
 806
 807 /*
 808  * Set up the 8259A-master output pin as broadcast to all
 809  * CPUs.
 810  */
 811 static void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
 812 {
 813         struct IO_APIC_route_entry entry;
 814         unsigned long flags;
 815
 816         memset(&entry,0,sizeof(entry));
 817
 818         disable_8259A_irq(0);
 819
 820         /* mask LVT0 */
 821         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 822
 823         /*
 824          * We use logical delivery to get the timer IRQ
 825          * to the first CPU.
 826          */
 827         entry.dest_mode = INT_DEST_MODE;
 828         entry.mask = 0;                                 /* unmask IRQ now */
 829         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 830         entry.delivery_mode = INT_DELIVERY_MODE;
 831         entry.polarity = 0;
 832         entry.trigger = 0;
 833         entry.vector = vector;
 834
 835         /*
 836          * The timer IRQ doesn't have to know that behind the
 837          * scene we have a 8259A-master in AEOI mode ...
 838          */
 839         irq_desc[0].handler = &ioapic_edge_type;
 840
 841         /*
 842          * Add it to the IO-APIC irq-routing table:
 843          */
 844         spin_lock_irqsave(&ioapic_lock, flags);
 845         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
 846         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
 847         spin_unlock_irqrestore(&ioapic_lock, flags);
 848
 849         enable_8259A_irq(0);
 850 }
 851
 852 void __init UNEXPECTED_IO_APIC(void)
 853 {
 854 }
 855
 856 void __apicdebuginit print_IO_APIC(void)
 857 {
 858         int apic, i;
 859         union IO_APIC_reg_00 reg_00;
 860         union IO_APIC_reg_01 reg_01;
 861         union IO_APIC_reg_02 reg_02;
 862         unsigned long flags;
 863
 864         if (apic_verbosity == APIC_QUIET)
 865                 return;
 866
 867         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 868         for (i = 0; i < nr_ioapics; i++)
 869                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 870                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 871
 872         /*
 873          * We are a bit conservative about what we expect.  We have to
 874          * know about every hardware change ASAP.
 875          */
 876         printk(KERN_INFO "testing the IO APIC.......................\n");
 877
 878         for (apic = 0; apic < nr_ioapics; apic++) {
 879
 880         spin_lock_irqsave(&ioapic_lock, flags);
 881         reg_00.raw = io_apic_read(apic, 0);
 882         reg_01.raw = io_apic_read(apic, 1);
 883         if (reg_01.bits.version >= 0x10)
 884                 reg_02.raw = io_apic_read(apic, 2);
 885         spin_unlock_irqrestore(&ioapic_lock, flags);
 886
 887         printk("\n");
 888         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 889         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 890         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 891         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 892                 UNEXPECTED_IO_APIC();
 893
 894         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 895         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 896         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 897                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 898                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 899                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 900                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 901                 (reg_01.bits.entries != 0x2E) &&
 902                 (reg_01.bits.entries != 0x3F) &&
 903                 (reg_01.bits.entries != 0x03)
 904         )
 905                 UNEXPECTED_IO_APIC();
 906
 907         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 908         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 909         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 910                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 911                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 912                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 913                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 914                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 915         )
 916                 UNEXPECTED_IO_APIC();
 917         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 918                 UNEXPECTED_IO_APIC();
 919
 920         if (reg_01.bits.version >= 0x10) {
 921                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 922                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 923                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 924                         UNEXPECTED_IO_APIC();
 925         }
 926
 927         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 928
 929         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 930                           " Stat Dest Deli Vect:   \n");
 931
 932         for (i = 0; i <= reg_01.bits.entries; i++) {
 933                 struct IO_APIC_route_entry entry;
 934
 935                 spin_lock_irqsave(&ioapic_lock, flags);
 936                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
 937                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
 938                 spin_unlock_irqrestore(&ioapic_lock, flags);
 939
 940                 printk(KERN_DEBUG " %02x %03X %02X  ",
 941                         i,
 942                         entry.dest.logical.logical_dest,
 943                         entry.dest.physical.physical_dest
 944                 );
 945
 946                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 947                         entry.mask,
 948                         entry.trigger,
 949                         entry.irr,
 950                         entry.polarity,
 951                         entry.delivery_status,
 952                         entry.dest_mode,
 953                         entry.delivery_mode,
 954                         entry.vector
 955                 );
 956         }
 957         }
 958         if (use_pci_vector())
 959                 printk(KERN_INFO "Using vector-based indexing\n");
 960         printk(KERN_DEBUG "IRQ to pin mappings:\n");
 961         for (i = 0; i < NR_IRQS; i++) {
 962                 struct irq_pin_list *entry = irq_2_pin + i;
 963                 if (entry->pin < 0)
 964                         continue;
 965                 if (use_pci_vector() && !platform_legacy_irq(i))
 966                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
 967                 else
 968                         printk(KERN_DEBUG "IRQ%d ", i);
 969                 for (;;) {
 970                         printk("-> %d:%d", entry->apic, entry->pin);
 971                         if (!entry->next)
 972                                 break;
 973                         entry = irq_2_pin + entry->next;
 974                 }
 975                 printk("\n");
 976         }
 977
 978         printk(KERN_INFO ".................................... done.\n");
 979
 980         return;
 981 }
 982
 983 #if 0
 984
 985 static __apicdebuginit void print_APIC_bitfield (int base)
 986 {
 987         unsigned int v;
 988         int i, j;
 989
 990         if (apic_verbosity == APIC_QUIET)
 991                 return;
 992
 993         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
 994         for (i = 0; i < 8; i++) {
 995                 v = apic_read(base + i*0x10);
 996                 for (j = 0; j < 32; j++) {
 997                         if (v & (1<<j))
 998                                 printk("1");
 999                         else
1000                                 printk("0");
1001                 }
1002                 printk("\n");
1003         }
1004 }
1005
1006 void __apicdebuginit print_local_APIC(void * dummy)
1007 {
1008         unsigned int v, ver, maxlvt;
1009
1010         if (apic_verbosity == APIC_QUIET)
1011                 return;
1012
1013         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1014                 smp_processor_id(), hard_smp_processor_id());
1015         v = apic_read(APIC_ID);
1016         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
1017         v = apic_read(APIC_LVR);
1018         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1019         ver = GET_APIC_VERSION(v);
1020         maxlvt = get_maxlvt();
1021
1022         v = apic_read(APIC_TASKPRI);
1023         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1024
1025         v = apic_read(APIC_ARBPRI);
1026         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1027                 v & APIC_ARBPRI_MASK);
1028         v = apic_read(APIC_PROCPRI);
1029         printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1030
1031         v = apic_read(APIC_EOI);
1032         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1033         v = apic_read(APIC_RRR);
1034         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1035         v = apic_read(APIC_LDR);
1036         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1037         v = apic_read(APIC_DFR);
1038         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1039         v = apic_read(APIC_SPIV);
1040         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1041
1042         printk(KERN_DEBUG "... APIC ISR field:\n");
1043         print_APIC_bitfield(APIC_ISR);
1044         printk(KERN_DEBUG "... APIC TMR field:\n");
1045         print_APIC_bitfield(APIC_TMR);
1046         printk(KERN_DEBUG "... APIC IRR field:\n");
1047         print_APIC_bitfield(APIC_IRR);
1048
1049         v = apic_read(APIC_ESR);
1050         printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1051
1052         v = apic_read(APIC_ICR);
1053         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1054         v = apic_read(APIC_ICR2);
1055         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1056
1057         v = apic_read(APIC_LVTT);
1058         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1059
1060         if (maxlvt > 3) {                       /* PC is LVT#4. */
1061                 v = apic_read(APIC_LVTPC);
1062                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1063         }
1064         v = apic_read(APIC_LVT0);
1065         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1066         v = apic_read(APIC_LVT1);
1067         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1068
1069         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1070                 v = apic_read(APIC_LVTERR);
1071                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1072         }
1073
1074         v = apic_read(APIC_TMICT);
1075         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1076         v = apic_read(APIC_TMCCT);
1077         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1078         v = apic_read(APIC_TDCR);
1079         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1080         printk("\n");
1081 }
1082
1083 void print_all_local_APICs (void)
1084 {
1085         on_each_cpu(print_local_APIC, NULL, 1, 1);
1086 }
1087
1088 void __apicdebuginit print_PIC(void)
1089 {
1090         unsigned int v;
1091         unsigned long flags;
1092
1093         if (apic_verbosity == APIC_QUIET)
1094                 return;
1095
1096         printk(KERN_DEBUG "\nprinting PIC contents\n");
1097
1098         spin_lock_irqsave(&i8259A_lock, flags);
1099
1100         v = inb(0xa1) << 8 | inb(0x21);
1101         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1102
1103         v = inb(0xa0) << 8 | inb(0x20);
1104         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1105
1106         outb(0x0b,0xa0);
1107         outb(0x0b,0x20);
1108         v = inb(0xa0) << 8 | inb(0x20);
1109         outb(0x0a,0xa0);
1110         outb(0x0a,0x20);
1111
1112         spin_unlock_irqrestore(&i8259A_lock, flags);
1113
1114         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1115
1116         v = inb(0x4d1) << 8 | inb(0x4d0);
1117         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1118 }
1119
1120 #endif  /*  0  */
1121
1122 static void __init enable_IO_APIC(void)
1123 {
1124         union IO_APIC_reg_01 reg_01;
1125         int i;
1126         unsigned long flags;
1127
1128         for (i = 0; i < PIN_MAP_SIZE; i++) {
1129                 irq_2_pin[i].pin = -1;
1130                 irq_2_pin[i].next = 0;
1131         }
1132         if (!pirqs_enabled)
1133                 for (i = 0; i < MAX_PIRQS; i++)
1134                         pirq_entries[i] = -1;
1135
1136         /*
1137          * The number of IO-APIC IRQ registers (== #pins):
1138          */
1139         for (i = 0; i < nr_ioapics; i++) {
1140                 spin_lock_irqsave(&ioapic_lock, flags);
1141                 reg_01.raw = io_apic_read(i, 1);
1142                 spin_unlock_irqrestore(&ioapic_lock, flags);
1143                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1144         }
1145
1146         /*
1147          * Do not trust the IO-APIC being empty at bootup
1148          */
1149         clear_IO_APIC();
1150 }
1151
1152 /*
1153  * Not an __init, needed by the reboot code
1154  */
1155 void disable_IO_APIC(void)
1156 {
1157         int pin;
1158         /*
1159          * Clear the IO-APIC before rebooting:
1160          */
1161         clear_IO_APIC();
1162
1163         /*
1164          * If the i8259 is routed through an IOAPIC
1165          * Put that IOAPIC in virtual wire mode
1166          * so legacy interrupts can be delivered.
1167          */
1168         pin = find_isa_irq_pin(0, mp_ExtINT);
1169         if (pin != -1) {
1170                 struct IO_APIC_route_entry entry;
1171                 unsigned long flags;
1172
1173                 memset(&entry, 0, sizeof(entry));
1174                 entry.mask            = 0; /* Enabled */
1175                 entry.trigger         = 0; /* Edge */
1176                 entry.irr             = 0;
1177                 entry.polarity        = 0; /* High */
1178                 entry.delivery_status = 0;
1179                 entry.dest_mode       = 0; /* Physical */
1180                 entry.delivery_mode   = 7; /* ExtInt */
1181                 entry.vector          = 0;
1182                 entry.dest.physical.physical_dest = 0;
1183
1184
1185                 /*
1186                  * Add it to the IO-APIC irq-routing table:
1187                  */
1188                 spin_lock_irqsave(&ioapic_lock, flags);
1189                 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
1190                 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
1191                 spin_unlock_irqrestore(&ioapic_lock, flags);
1192         }
1193
1194         disconnect_bsp_APIC(pin != -1);
1195 }
1196
1197 /*
1198  * function to set the IO-APIC physical IDs based on the
1199  * values stored in the MPC table.
1200  *
1201  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1202  */
1203
1204 static void __init setup_ioapic_ids_from_mpc (void)
1205 {
1206         union IO_APIC_reg_00 reg_00;
1207         int apic;
1208         int i;
1209         unsigned char old_id;
1210         unsigned long flags;
1211
1212         /*
1213          * Set the IOAPIC ID to the value stored in the MPC table.
1214          */
1215         for (apic = 0; apic < nr_ioapics; apic++) {
1216
1217                 /* Read the register 0 value */
1218                 spin_lock_irqsave(&ioapic_lock, flags);
1219                 reg_00.raw = io_apic_read(apic, 0);
1220                 spin_unlock_irqrestore(&ioapic_lock, flags);
1221
1222                 old_id = mp_ioapics[apic].mpc_apicid;
1223
1224
1225                 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1226
1227
1228                 /*
1229                  * We need to adjust the IRQ routing table
1230                  * if the ID changed.
1231                  */
1232                 if (old_id != mp_ioapics[apic].mpc_apicid)
1233                         for (i = 0; i < mp_irq_entries; i++)
1234                                 if (mp_irqs[i].mpc_dstapic == old_id)
1235                                         mp_irqs[i].mpc_dstapic
1236                                                 = mp_ioapics[apic].mpc_apicid;
1237
1238                 /*
1239                  * Read the right value from the MPC table and
1240                  * write it into the ID register.
1241                  */
1242                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1243                                 mp_ioapics[apic].mpc_apicid);
1244
1245                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1246                 spin_lock_irqsave(&ioapic_lock, flags);
1247                 io_apic_write(apic, 0, reg_00.raw);
1248                 spin_unlock_irqrestore(&ioapic_lock, flags);
1249
1250                 /*
1251                  * Sanity check
1252                  */
1253                 spin_lock_irqsave(&ioapic_lock, flags);
1254                 reg_00.raw = io_apic_read(apic, 0);
1255                 spin_unlock_irqrestore(&ioapic_lock, flags);
1256                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1257                         printk("could not set ID!\n");
1258                 else
1259                         apic_printk(APIC_VERBOSE," ok.\n");
1260         }
1261 }
1262
1263 /*
1264  * There is a nasty bug in some older SMP boards, their mptable lies
1265  * about the timer IRQ. We do the following to work around the situation:
1266  *
1267  *      - timer IRQ defaults to IO-APIC IRQ
1268  *      - if this function detects that timer IRQs are defunct, then we fall
1269  *        back to ISA timer IRQs
1270  */
1271 static int __init timer_irq_works(void)
1272 {
1273         unsigned long t1 = jiffies;
1274
1275         local_irq_enable();
1276         /* Let ten ticks pass... */
1277         mdelay((10 * 1000) / HZ);
1278
1279         /*
1280          * Expect a few ticks at least, to be sure some possible
1281          * glue logic does not lock up after one or two first
1282          * ticks in a non-ExtINT mode.  Also the local APIC
1283          * might have cached one ExtINT interrupt.  Finally, at
1284          * least one tick may be lost due to delays.
1285          */
1286
1287         /* jiffies wrap? */
1288         if (jiffies - t1 > 4)
1289                 return 1;
1290         return 0;
1291 }
1292
1293 /*
1294  * In the SMP+IOAPIC case it might happen that there are an unspecified
1295  * number of pending IRQ events unhandled. These cases are very rare,
1296  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1297  * better to do it this way as thus we do not have to be aware of
1298  * 'pending' interrupts in the IRQ path, except at this point.
1299  */
1300 /*
1301  * Edge triggered needs to resend any interrupt
1302  * that was delayed but this is now handled in the device
1303  * independent code.
1304  */
1305
1306 /*
1307  * Starting up a edge-triggered IO-APIC interrupt is
1308  * nasty - we need to make sure that we get the edge.
1309  * If it is already asserted for some reason, we need
1310  * return 1 to indicate that is was pending.
1311  *
1312  * This is not complete - we should be able to fake
1313  * an edge even if it isn't on the 8259A...
1314  */
1315
1316 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1317 {
1318         int was_pending = 0;
1319         unsigned long flags;
1320
1321         spin_lock_irqsave(&ioapic_lock, flags);
1322         if (irq < 16) {
1323                 disable_8259A_irq(irq);
1324                 if (i8259A_irq_pending(irq))
1325                         was_pending = 1;
1326         }
1327         __unmask_IO_APIC_irq(irq);
1328         spin_unlock_irqrestore(&ioapic_lock, flags);
1329
1330         return was_pending;
1331 }
1332
1333 /*
1334  * Once we have recorded IRQ_PENDING already, we can mask the
1335  * interrupt for real. This prevents IRQ storms from unhandled
1336  * devices.
1337  */
1338 static void ack_edge_ioapic_irq(unsigned int irq)
1339 {
1340         move_irq(irq);
1341         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1342                                         == (IRQ_PENDING | IRQ_DISABLED))
1343                 mask_IO_APIC_irq(irq);
1344         ack_APIC_irq();
1345 }
1346
1347 /*
1348  * Level triggered interrupts can just be masked,
1349  * and shutting down and starting up the interrupt
1350  * is the same as enabling and disabling them -- except
1351  * with a startup need to return a "was pending" value.
1352  *
1353  * Level triggered interrupts are special because we
1354  * do not touch any IO-APIC register while handling
1355  * them. We ack the APIC in the end-IRQ handler, not
1356  * in the start-IRQ-handler. Protection against reentrance
1357  * from the same interrupt is still provided, both by the
1358  * generic IRQ layer and by the fact that an unacked local
1359  * APIC does not accept IRQs.
1360  */
1361 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1362 {
1363         unmask_IO_APIC_irq(irq);
1364
1365         return 0; /* don't check for pending */
1366 }
1367
1368 static void end_level_ioapic_irq (unsigned int irq)
1369 {
1370         move_irq(irq);
1371         ack_APIC_irq();
1372 }
1373
1374 #ifdef CONFIG_PCI_MSI
1375 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1376 {
1377         int irq = vector_to_irq(vector);
1378
1379         return startup_edge_ioapic_irq(irq);
1380 }
1381
1382 static void ack_edge_ioapic_vector(unsigned int vector)
1383 {
1384         int irq = vector_to_irq(vector);
1385
1386         move_native_irq(vector);
1387         ack_edge_ioapic_irq(irq);
1388 }
1389
1390 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1391 {
1392         int irq = vector_to_irq(vector);
1393
1394         return startup_level_ioapic_irq (irq);
1395 }
1396
1397 static void end_level_ioapic_vector (unsigned int vector)
1398 {
1399         int irq = vector_to_irq(vector);
1400
1401         move_native_irq(vector);
1402         end_level_ioapic_irq(irq);
1403 }
1404
1405 static void mask_IO_APIC_vector (unsigned int vector)
1406 {
1407         int irq = vector_to_irq(vector);
1408
1409         mask_IO_APIC_irq(irq);
1410 }
1411
1412 static void unmask_IO_APIC_vector (unsigned int vector)
1413 {
1414         int irq = vector_to_irq(vector);
1415
1416         unmask_IO_APIC_irq(irq);
1417 }
1418
1419 #ifdef CONFIG_SMP
1420 static void set_ioapic_affinity_vector (unsigned int vector,
1421                                         cpumask_t cpu_mask)
1422 {
1423         int irq = vector_to_irq(vector);
1424
1425         set_native_irq_info(vector, cpu_mask);
1426         set_ioapic_affinity_irq(irq, cpu_mask);
1427 }
1428 #endif // CONFIG_SMP
1429 #endif // CONFIG_PCI_MSI
1430
1431 /*
1432  * Level and edge triggered IO-APIC interrupts need different handling,
1433  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1434  * handled with the level-triggered descriptor, but that one has slightly
1435  * more overhead. Level-triggered interrupts cannot be handled with the
1436  * edge-triggered handler, without risking IRQ storms and other ugly
1437  * races.
1438  */
1439
1440 static struct hw_interrupt_type ioapic_edge_type __read_mostly = {
1441         .typename = "IO-APIC-edge",
1442         .startup        = startup_edge_ioapic,
1443         .shutdown       = shutdown_edge_ioapic,
1444         .enable         = enable_edge_ioapic,
1445         .disable        = disable_edge_ioapic,
1446         .ack            = ack_edge_ioapic,
1447         .end            = end_edge_ioapic,
1448 #ifdef CONFIG_SMP
1449         .set_affinity = set_ioapic_affinity,
1450 #endif
1451 };
1452
1453 static struct hw_interrupt_type ioapic_level_type __read_mostly = {
1454         .typename = "IO-APIC-level",
1455         .startup        = startup_level_ioapic,
1456         .shutdown       = shutdown_level_ioapic,
1457         .enable         = enable_level_ioapic,
1458         .disable        = disable_level_ioapic,
1459         .ack            = mask_and_ack_level_ioapic,
1460         .end            = end_level_ioapic,
1461 #ifdef CONFIG_SMP
1462         .set_affinity = set_ioapic_affinity,
1463 #endif
1464 };
1465
1466 static inline void init_IO_APIC_traps(void)
1467 {
1468         int irq;
1469
1470         /*
1471          * NOTE! The local APIC isn't very good at handling
1472          * multiple interrupts at the same interrupt level.
1473          * As the interrupt level is determined by taking the
1474          * vector number and shifting that right by 4, we
1475          * want to spread these out a bit so that they don't
1476          * all fall in the same interrupt level.
1477          *
1478          * Also, we've got to be careful not to trash gate
1479          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1480          */
1481         for (irq = 0; irq < NR_IRQS ; irq++) {
1482                 int tmp = irq;
1483                 if (use_pci_vector()) {
1484                         if (!platform_legacy_irq(tmp))
1485                                 if ((tmp = vector_to_irq(tmp)) == -1)
1486                                         continue;
1487                 }
1488                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1489                         /*
1490                          * Hmm.. We don't have an entry for this,
1491                          * so default to an old-fashioned 8259
1492                          * interrupt if we can..
1493                          */
1494                         if (irq < 16)
1495                                 make_8259A_irq(irq);
1496                         else
1497                                 /* Strange. Oh, well.. */
1498                                 irq_desc[irq].handler = &no_irq_type;
1499                 }
1500         }
1501 }
1502
1503 static void enable_lapic_irq (unsigned int irq)
1504 {
1505         unsigned long v;
1506
1507         v = apic_read(APIC_LVT0);
1508         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1509 }
1510
1511 static void disable_lapic_irq (unsigned int irq)
1512 {
1513         unsigned long v;
1514
1515         v = apic_read(APIC_LVT0);
1516         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1517 }
1518
1519 static void ack_lapic_irq (unsigned int irq)
1520 {
1521         ack_APIC_irq();
1522 }
1523
1524 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1525
1526 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1527         .typename = "local-APIC-edge",
1528         .startup = NULL, /* startup_irq() not used for IRQ0 */
1529         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1530         .enable = enable_lapic_irq,
1531         .disable = disable_lapic_irq,
1532         .ack = ack_lapic_irq,
1533         .end = end_lapic_irq,
1534 };
1535
1536 static void setup_nmi (void)
1537 {
1538         /*
1539          * Dirty trick to enable the NMI watchdog ...
1540          * We put the 8259A master into AEOI mode and
1541          * unmask on all local APICs LVT0 as NMI.
1542          *
1543          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1544          * is from Maciej W. Rozycki - so we do not have to EOI from
1545          * the NMI handler or the timer interrupt.
1546          */
1547         printk(KERN_INFO "activating NMI Watchdog ...");
1548
1549         enable_NMI_through_LVT0(NULL);
1550
1551         printk(" done.\n");
1552 }
1553
1554 /*
1555  * This looks a bit hackish but it's about the only one way of sending
1556  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1557  * not support the ExtINT mode, unfortunately.  We need to send these
1558  * cycles as some i82489DX-based boards have glue logic that keeps the
1559  * 8259A interrupt line asserted until INTA.  --macro
1560  */
1561 static inline void unlock_ExtINT_logic(void)
1562 {
1563         int pin, i;
1564         struct IO_APIC_route_entry entry0, entry1;
1565         unsigned char save_control, save_freq_select;
1566         unsigned long flags;
1567
1568         pin = find_isa_irq_pin(8, mp_INT);
1569         if (pin == -1)
1570                 return;
1571
1572         spin_lock_irqsave(&ioapic_lock, flags);
1573         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1574         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1575         spin_unlock_irqrestore(&ioapic_lock, flags);
1576         clear_IO_APIC_pin(0, pin);
1577
1578         memset(&entry1, 0, sizeof(entry1));
1579
1580         entry1.dest_mode = 0;                   /* physical delivery */
1581         entry1.mask = 0;                        /* unmask IRQ now */
1582         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1583         entry1.delivery_mode = dest_ExtINT;
1584         entry1.polarity = entry0.polarity;
1585         entry1.trigger = 0;
1586         entry1.vector = 0;
1587
1588         spin_lock_irqsave(&ioapic_lock, flags);
1589         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1590         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1591         spin_unlock_irqrestore(&ioapic_lock, flags);
1592
1593         save_control = CMOS_READ(RTC_CONTROL);
1594         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1595         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1596                    RTC_FREQ_SELECT);
1597         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1598
1599         i = 100;
1600         while (i-- > 0) {
1601                 mdelay(10);
1602                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1603                         i -= 10;
1604         }
1605
1606         CMOS_WRITE(save_control, RTC_CONTROL);
1607         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1608         clear_IO_APIC_pin(0, pin);
1609
1610         spin_lock_irqsave(&ioapic_lock, flags);
1611         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1612         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1613         spin_unlock_irqrestore(&ioapic_lock, flags);
1614 }
1615
1616 /*
1617  * This code may look a bit paranoid, but it's supposed to cooperate with
1618  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1619  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1620  * fanatically on his truly buggy board.
1621  */
1622 static inline void check_timer(void)
1623 {
1624         int pin1, pin2;
1625         int vector;
1626
1627         /*
1628          * get/set the timer IRQ vector:
1629          */
1630         disable_8259A_irq(0);
1631         vector = assign_irq_vector(0);
1632         set_intr_gate(vector, interrupt[0]);
1633
1634         /*
1635          * Subtle, code in do_timer_interrupt() expects an AEOI
1636          * mode for the 8259A whenever interrupts are routed
1637          * through I/O APICs.  Also IRQ0 has to be enabled in
1638          * the 8259A which implies the virtual wire has to be
1639          * disabled in the local APIC.
1640          */
1641         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1642         init_8259A(1);
1643         enable_8259A_irq(0);
1644
1645         pin1 = find_isa_irq_pin(0, mp_INT);
1646         pin2 = find_isa_irq_pin(0, mp_ExtINT);
1647
1648         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1649
1650         if (pin1 != -1) {
1651                 /*
1652                  * Ok, does IRQ0 through the IOAPIC work?
1653                  */
1654                 unmask_IO_APIC_irq(0);
1655                 if (!no_timer_check && timer_irq_works()) {
1656                         nmi_watchdog_default();
1657                         if (nmi_watchdog == NMI_IO_APIC) {
1658                                 disable_8259A_irq(0);
1659                                 setup_nmi();
1660                                 enable_8259A_irq(0);
1661                         }
1662                         return;
1663                 }
1664                 clear_IO_APIC_pin(0, pin1);
1665                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1666         }
1667
1668         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1669         if (pin2 != -1) {
1670                 apic_printk(APIC_VERBOSE,"\n..... (found pin %d) ...", pin2);
1671                 /*
1672                  * legacy devices should be connected to IO APIC #0
1673                  */
1674                 setup_ExtINT_IRQ0_pin(pin2, vector);
1675                 if (timer_irq_works()) {
1676                         printk("works.\n");
1677                         nmi_watchdog_default();
1678                         if (nmi_watchdog == NMI_IO_APIC) {
1679                                 setup_nmi();
1680                         }
1681                         return;
1682                 }
1683                 /*
1684                  * Cleanup, just in case ...
1685                  */
1686                 clear_IO_APIC_pin(0, pin2);
1687         }
1688         printk(" failed.\n");
1689
1690         if (nmi_watchdog) {
1691                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1692                 nmi_watchdog = 0;
1693         }
1694
1695         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1696
1697         disable_8259A_irq(0);
1698         irq_desc[0].handler = &lapic_irq_type;
1699         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
1700         enable_8259A_irq(0);
1701
1702         if (timer_irq_works()) {
1703                 apic_printk(APIC_QUIET, " works.\n");
1704                 return;
1705         }
1706         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1707         apic_printk(APIC_VERBOSE," failed.\n");
1708
1709         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1710
1711         init_8259A(0);
1712         make_8259A_irq(0);
1713         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1714
1715         unlock_ExtINT_logic();
1716
1717         if (timer_irq_works()) {
1718                 apic_printk(APIC_VERBOSE," works.\n");
1719                 return;
1720         }
1721         apic_printk(APIC_VERBOSE," failed :(.\n");
1722         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1723 }
1724
1725 static int __init notimercheck(char *s)
1726 {
1727         no_timer_check = 1;
1728         return 1;
1729 }
1730 __setup("no_timer_check", notimercheck);
1731
1732 /*
1733  *
1734  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1735  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1736  *   Linux doesn't really care, as it's not actually used
1737  *   for any interrupt handling anyway.
1738  */
1739 #define PIC_IRQS        (1<<2)
1740
1741 void __init setup_IO_APIC(void)
1742 {
1743         enable_IO_APIC();
1744
1745         if (acpi_ioapic)
1746                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1747         else
1748                 io_apic_irqs = ~PIC_IRQS;
1749
1750         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1751
1752         /*
1753          * Set up the IO-APIC IRQ routing table.
1754          */
1755         if (!acpi_ioapic)
1756                 setup_ioapic_ids_from_mpc();
1757         sync_Arb_IDs();
1758         setup_IO_APIC_irqs();
1759         init_IO_APIC_traps();
1760         check_timer();
1761         if (!acpi_ioapic)
1762                 print_IO_APIC();
1763 }
1764
1765 struct sysfs_ioapic_data {
1766         struct sys_device dev;
1767         struct IO_APIC_route_entry entry[0];
1768 };
1769 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1770
1771 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1772 {
1773         struct IO_APIC_route_entry *entry;
1774         struct sysfs_ioapic_data *data;
1775         unsigned long flags;
1776         int i;
1777
1778         data = container_of(dev, struct sysfs_ioapic_data, dev);
1779         entry = data->entry;
1780         spin_lock_irqsave(&ioapic_lock, flags);
1781         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1782                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1783                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1784         }
1785         spin_unlock_irqrestore(&ioapic_lock, flags);
1786
1787         return 0;
1788 }
1789
1790 static int ioapic_resume(struct sys_device *dev)
1791 {
1792         struct IO_APIC_route_entry *entry;
1793         struct sysfs_ioapic_data *data;
1794         unsigned long flags;
1795         union IO_APIC_reg_00 reg_00;
1796         int i;
1797
1798         data = container_of(dev, struct sysfs_ioapic_data, dev);
1799         entry = data->entry;
1800
1801         spin_lock_irqsave(&ioapic_lock, flags);
1802         reg_00.raw = io_apic_read(dev->id, 0);
1803         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1804                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1805                 io_apic_write(dev->id, 0, reg_00.raw);
1806         }
1807         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1808                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1809                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1810         }
1811         spin_unlock_irqrestore(&ioapic_lock, flags);
1812
1813         return 0;
1814 }
1815
1816 static struct sysdev_class ioapic_sysdev_class = {
1817         set_kset_name("ioapic"),
1818         .suspend = ioapic_suspend,
1819         .resume = ioapic_resume,
1820 };
1821
1822 static int __init ioapic_init_sysfs(void)
1823 {
1824         struct sys_device * dev;
1825         int i, size, error = 0;
1826
1827         error = sysdev_class_register(&ioapic_sysdev_class);
1828         if (error)
1829                 return error;
1830
1831         for (i = 0; i < nr_ioapics; i++ ) {
1832                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1833                         * sizeof(struct IO_APIC_route_entry);
1834                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1835                 if (!mp_ioapic_data[i]) {
1836                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1837                         continue;
1838                 }
1839                 memset(mp_ioapic_data[i], 0, size);
1840                 dev = &mp_ioapic_data[i]->dev;
1841                 dev->id = i;
1842                 dev->cls = &ioapic_sysdev_class;
1843                 error = sysdev_register(dev);
1844                 if (error) {
1845                         kfree(mp_ioapic_data[i]);
1846                         mp_ioapic_data[i] = NULL;
1847                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1848                         continue;
1849                 }
1850         }
1851
1852         return 0;
1853 }
1854
1855 device_initcall(ioapic_init_sysfs);
1856
1857 /* --------------------------------------------------------------------------
1858                           ACPI-based IOAPIC Configuration
1859    -------------------------------------------------------------------------- */
1860
1861 #ifdef CONFIG_ACPI
1862
1863 #define IO_APIC_MAX_ID          0xFE
1864
1865 int __init io_apic_get_version (int ioapic)
1866 {
1867         union IO_APIC_reg_01    reg_01;
1868         unsigned long flags;
1869
1870         spin_lock_irqsave(&ioapic_lock, flags);
1871         reg_01.raw = io_apic_read(ioapic, 1);
1872         spin_unlock_irqrestore(&ioapic_lock, flags);
1873
1874         return reg_01.bits.version;
1875 }
1876
1877
1878 int __init io_apic_get_redir_entries (int ioapic)
1879 {
1880         union IO_APIC_reg_01    reg_01;
1881         unsigned long flags;
1882
1883         spin_lock_irqsave(&ioapic_lock, flags);
1884         reg_01.raw = io_apic_read(ioapic, 1);
1885         spin_unlock_irqrestore(&ioapic_lock, flags);
1886
1887         return reg_01.bits.entries;
1888 }
1889
1890
1891 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1892 {
1893         struct IO_APIC_route_entry entry;
1894         unsigned long flags;
1895
1896         if (!IO_APIC_IRQ(irq)) {
1897                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1898                         ioapic);
1899                 return -EINVAL;
1900         }
1901
1902         /*
1903          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1904          * Note that we mask (disable) IRQs now -- these get enabled when the
1905          * corresponding device driver registers for this IRQ.
1906          */
1907
1908         memset(&entry,0,sizeof(entry));
1909
1910         entry.delivery_mode = INT_DELIVERY_MODE;
1911         entry.dest_mode = INT_DEST_MODE;
1912         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1913         entry.trigger = edge_level;
1914         entry.polarity = active_high_low;
1915         entry.mask = 1;                                  /* Disabled (masked) */
1916
1917         /*
1918          * IRQs < 16 are already in the irq_2_pin[] map
1919          */
1920         if (irq >= 16)
1921                 add_pin_to_irq(irq, ioapic, pin);
1922
1923         entry.vector = assign_irq_vector(irq);
1924
1925         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1926                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1927                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1928                edge_level, active_high_low);
1929
1930         ioapic_register_intr(irq, entry.vector, edge_level);
1931
1932         if (!ioapic && (irq < 16))
1933                 disable_8259A_irq(irq);
1934
1935         spin_lock_irqsave(&ioapic_lock, flags);
1936         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1937         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1938         set_native_irq_info(use_pci_vector() ?  entry.vector : irq, TARGET_CPUS);
1939         spin_unlock_irqrestore(&ioapic_lock, flags);
1940
1941         return 0;
1942 }
1943
1944 #endif /* CONFIG_ACPI */
1945
1946
1947 /*
1948  * This function currently is only a helper for the i386 smp boot process where
1949  * we need to reprogram the ioredtbls to cater for the cpus which have come online
1950  * so mask in all cases should simply be TARGET_CPUS
1951  */
1952 #ifdef CONFIG_SMP
1953 void __init setup_ioapic_dest(void)
1954 {
1955         int pin, ioapic, irq, irq_entry;
1956
1957         if (skip_ioapic_setup == 1)
1958                 return;
1959
1960         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1961                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1962                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1963                         if (irq_entry == -1)
1964                                 continue;
1965                         irq = pin_2_irq(irq_entry, ioapic, pin);
1966                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
1967                 }
1968
1969         }
1970 }
1971 #endif