arch/x86/platform/mrst/pmu.c

   1 /*
   2  * mrst/pmu.c - driver for MRST Power Management Unit
   3  *
   4  * Copyright (c) 2011, Intel Corporation.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program; if not, write to the Free Software Foundation, Inc.,
  17  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18  */
  19
  20 #include <linux/cpuidle.h>
  21 #include <linux/debugfs.h>
  22 #include <linux/delay.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/module.h>
  25 #include <linux/pci.h>
  26 #include <linux/seq_file.h>
  27 #include <linux/sfi.h>
  28 #include <asm/intel_scu_ipc.h>
  29 #include "pmu.h"
  30
  31 #define IPCMSG_FW_REVISION      0xF4
  32
  33 struct mrst_device {
  34         u16 pci_dev_num;        /* DEBUG only */
  35         u16 lss;
  36         u16 latest_request;
  37         unsigned int pci_state_counts[PCI_D3cold + 1]; /* DEBUG only */
  38 };
  39
  40 /*
  41  * comlete list of MRST PCI devices
  42  */
  43 static struct mrst_device mrst_devs[] = {
  44 /*  0 */ { 0x0800, LSS_SPI0 },          /* Moorestown SPI Ctrl 0 */
  45 /*  1 */ { 0x0801, LSS_SPI1 },          /* Moorestown SPI Ctrl 1 */
  46 /*  2 */ { 0x0802, LSS_I2C0 },          /* Moorestown I2C 0 */
  47 /*  3 */ { 0x0803, LSS_I2C1 },          /* Moorestown I2C 1 */
  48 /*  4 */ { 0x0804, LSS_I2C2 },          /* Moorestown I2C 2 */
  49 /*  5 */ { 0x0805, LSS_KBD },           /* Moorestown Keyboard Ctrl */
  50 /*  6 */ { 0x0806, LSS_USB_HC },        /* Moorestown USB Ctrl */
  51 /*  7 */ { 0x0807, LSS_SD_HC0 },        /* Moorestown SD Host Ctrl 0 */
  52 /*  8 */ { 0x0808, LSS_SD_HC1 },        /* Moorestown SD Host Ctrl 1 */
  53 /*  9 */ { 0x0809, LSS_NAND },          /* Moorestown NAND Ctrl */
  54 /* 10 */ { 0x080a, LSS_AUDIO },         /* Moorestown Audio Ctrl */
  55 /* 11 */ { 0x080b, LSS_IMAGING },       /* Moorestown ISP */
  56 /* 12 */ { 0x080c, LSS_SECURITY },      /* Moorestown Security Controller */
  57 /* 13 */ { 0x080d, LSS_DISPLAY },       /* Moorestown External Displays */
  58 /* 14 */ { 0x080e, 0 },                 /* Moorestown SCU IPC */
  59 /* 15 */ { 0x080f, LSS_GPIO },          /* Moorestown GPIO Controller */
  60 /* 16 */ { 0x0810, 0 },                 /* Moorestown Power Management Unit */
  61 /* 17 */ { 0x0811, LSS_USB_OTG },       /* Moorestown OTG Ctrl */
  62 /* 18 */ { 0x0812, LSS_SPI2 },          /* Moorestown SPI Ctrl 2 */
  63 /* 19 */ { 0x0813, 0 },                 /* Moorestown SC DMA */
  64 /* 20 */ { 0x0814, LSS_AUDIO_LPE },     /* Moorestown LPE DMA */
  65 /* 21 */ { 0x0815, LSS_AUDIO_SSP },     /* Moorestown SSP0 */
  66
  67 /* 22 */ { 0x084F, LSS_SD_HC2 },        /* Moorestown SD Host Ctrl 2 */
  68
  69 /* 23 */ { 0x4102, 0 },                 /* Lincroft */
  70 /* 24 */ { 0x4110, 0 },                 /* Lincroft */
  71 };
  72
  73 /* n.b. We ignore PCI-id 0x815 in LSS9 b/c MeeGo has no driver for it */
  74 static u16 mrst_lss9_pci_ids[] = {0x080a, 0x0814, 0};
  75 static u16 mrst_lss10_pci_ids[] = {0x0800, 0x0801, 0x0802, 0x0803,
  76                                         0x0804, 0x0805, 0x080f, 0};
  77
  78 /* handle concurrent SMP invokations of pmu_pci_set_power_state() */
  79 static spinlock_t mrst_pmu_power_state_lock;
  80
  81 static unsigned int wake_counters[MRST_NUM_LSS];        /* DEBUG only */
  82 static unsigned int pmu_irq_stats[INT_INVALID + 1];     /* DEBUG only */
  83
  84 static int graphics_is_off;
  85 static int lss_s0i3_enabled;
  86 static bool mrst_pmu_s0i3_enable;
  87
  88 /*  debug counters */
  89 static u32 pmu_wait_ready_calls;
  90 static u32 pmu_wait_ready_udelays;
  91 static u32 pmu_wait_ready_udelays_max;
  92 static u32 pmu_wait_done_calls;
  93 static u32 pmu_wait_done_udelays;
  94 static u32 pmu_wait_done_udelays_max;
  95 static u32 pmu_set_power_state_entry;
  96 static u32 pmu_set_power_state_send_cmd;
  97
  98 static struct mrst_device *pci_id_2_mrst_dev(u16 pci_dev_num)
  99 {
 100         int index = 0;
 101
 102         if ((pci_dev_num >= 0x0800) && (pci_dev_num <= 0x815))
 103                 index = pci_dev_num - 0x800;
 104         else if (pci_dev_num == 0x084F)
 105                 index = 22;
 106         else if (pci_dev_num == 0x4102)
 107                 index = 23;
 108         else if (pci_dev_num == 0x4110)
 109                 index = 24;
 110
 111         if (pci_dev_num != mrst_devs[index].pci_dev_num) {
 112                 WARN_ONCE(1, FW_BUG "Unknown PCI device 0x%04X\n", pci_dev_num);
 113                 return 0;
 114         }
 115
 116         return &mrst_devs[index];
 117 }
 118
 119 /**
 120  * mrst_pmu_validate_cstates
 121  * @dev: cpuidle_device
 122  *
 123  * Certain states are not appropriate for governor to pick in some cases.
 124  * This function will be called as cpuidle_device's prepare callback and
 125  * thus tells governor to ignore such states when selecting the next state
 126  * to enter.
 127  */
 128
 129 #define IDLE_STATE4_IS_C6       4
 130 #define IDLE_STATE5_IS_S0I3     5
 131
 132 int mrst_pmu_invalid_cstates(void)
 133 {
 134         int cpu = smp_processor_id();
 135
 136         /*
 137          * Demote to C4 if the PMU is busy.
 138          * Since LSS changes leave the busy bit clear...
 139          * busy means either the PMU is waiting for an ACK-C6 that
 140          * isn't coming due to an MWAIT that returned immediately;
 141          * or we returned from S0i3 successfully, and the PMU
 142          * is not done sending us interrupts.
 143          */
 144         if (pmu_read_busy_status())
 145                 return 1 << IDLE_STATE4_IS_C6 | 1 << IDLE_STATE5_IS_S0I3;
 146
 147         /*
 148          * Disallow S0i3 if: PMU is not initialized, or CPU1 is active,
 149          * or if device LSS is insufficient, or the GPU is active,
 150          * or if it has been explicitly disabled.
 151          */
 152         if (!pmu_reg || !cpumask_equal(cpu_online_mask, cpumask_of(cpu)) ||
 153             !lss_s0i3_enabled || !graphics_is_off || !mrst_pmu_s0i3_enable)
 154                 return 1 << IDLE_STATE5_IS_S0I3;
 155         else
 156                 return 0;
 157 }
 158
 159 /*
 160  * pmu_update_wake_counters(): read PM_WKS, update wake_counters[]
 161  * DEBUG only.
 162  */
 163 static void pmu_update_wake_counters(void)
 164 {
 165         int lss;
 166         u32 wake_status;
 167
 168         wake_status = pmu_read_wks();
 169
 170         for (lss = 0; lss < MRST_NUM_LSS; ++lss) {
 171                 if (wake_status & (1 << lss))
 172                         wake_counters[lss]++;
 173         }
 174 }
 175
 176 int mrst_pmu_s0i3_entry(void)
 177 {
 178         int status;
 179
 180         /* Clear any possible error conditions */
 181         pmu_write_ics(0x300);
 182
 183         /* set wake control to current D-states */
 184         pmu_write_wssc(S0I3_SSS_TARGET);
 185
 186         status = mrst_s0i3_entry(PM_S0I3_COMMAND, &pmu_reg->pm_cmd);
 187         pmu_update_wake_counters();
 188         return status;
 189 }
 190
 191 /* poll for maximum of 5ms for busy bit to clear */
 192 static int pmu_wait_ready(void)
 193 {
 194         int udelays;
 195
 196         pmu_wait_ready_calls++;
 197
 198         for (udelays = 0; udelays < 500; ++udelays) {
 199                 if (udelays > pmu_wait_ready_udelays_max)
 200                         pmu_wait_ready_udelays_max = udelays;
 201
 202                 if (pmu_read_busy_status() == 0)
 203                         return 0;
 204
 205                 udelay(10);
 206                 pmu_wait_ready_udelays++;
 207         }
 208
 209         /*
 210          * if this fires, observe
 211          * /sys/kernel/debug/mrst_pmu_wait_ready_calls
 212          * /sys/kernel/debug/mrst_pmu_wait_ready_udelays
 213          */
 214         WARN_ONCE(1, "SCU not ready for 5ms");
 215         return -EBUSY;
 216 }
 217 /* poll for maximum of 50ms us for busy bit to clear */
 218 static int pmu_wait_done(void)
 219 {
 220         int udelays;
 221
 222         pmu_wait_done_calls++;
 223
 224         for (udelays = 0; udelays < 500; ++udelays) {
 225                 if (udelays > pmu_wait_done_udelays_max)
 226                         pmu_wait_done_udelays_max = udelays;
 227
 228                 if (pmu_read_busy_status() == 0)
 229                         return 0;
 230
 231                 udelay(100);
 232                 pmu_wait_done_udelays++;
 233         }
 234
 235         /*
 236          * if this fires, observe
 237          * /sys/kernel/debug/mrst_pmu_wait_done_calls
 238          * /sys/kernel/debug/mrst_pmu_wait_done_udelays
 239          */
 240         WARN_ONCE(1, "SCU not done for 50ms");
 241         return -EBUSY;
 242 }
 243
 244 u32 mrst_pmu_msi_is_disabled(void)
 245 {
 246         return pmu_msi_is_disabled();
 247 }
 248
 249 void mrst_pmu_enable_msi(void)
 250 {
 251         pmu_msi_enable();
 252 }
 253
 254 /**
 255  * pmu_irq - pmu driver interrupt handler
 256  * Context: interrupt context
 257  */
 258 static irqreturn_t pmu_irq(int irq, void *dummy)
 259 {
 260         union pmu_pm_ics pmu_ics;
 261
 262         pmu_ics.value = pmu_read_ics();
 263
 264         if (!pmu_ics.bits.pending)
 265                 return IRQ_NONE;
 266
 267         switch (pmu_ics.bits.cause) {
 268         case INT_SPURIOUS:
 269         case INT_CMD_DONE:
 270         case INT_CMD_ERR:
 271         case INT_WAKE_RX:
 272         case INT_SS_ERROR:
 273         case INT_S0IX_MISS:
 274         case INT_NO_ACKC6:
 275                 pmu_irq_stats[pmu_ics.bits.cause]++;
 276                 break;
 277         default:
 278                 pmu_irq_stats[INT_INVALID]++;
 279         }
 280
 281         pmu_write_ics(pmu_ics.value); /* Clear pending interrupt */
 282
 283         return IRQ_HANDLED;
 284 }
 285
 286 /*
 287  * Translate PCI power management to MRST LSS D-states
 288  */
 289 static int pci_2_mrst_state(int lss, pci_power_t pci_state)
 290 {
 291         switch (pci_state) {
 292         case PCI_D0:
 293                 if (SSMSK(D0i1, lss) & D0I1_ACG_SSS_TARGET)
 294                         return D0i1;
 295                 else
 296                         return D0;
 297         case PCI_D1:
 298                 return D0i1;
 299         case PCI_D2:
 300                 return D0i2;
 301         case PCI_D3hot:
 302         case PCI_D3cold:
 303                 return D0i3;
 304         default:
 305                 WARN(1, "pci_state %d\n", pci_state);
 306                 return 0;
 307         }
 308 }
 309
 310 static int pmu_issue_command(u32 pm_ssc)
 311 {
 312         union pmu_pm_set_cfg_cmd_t command;
 313
 314         if (pmu_read_busy_status()) {
 315                 pr_debug("pmu is busy, Operation not permitted\n");
 316                 return -1;
 317         }
 318
 319         /*
 320          * enable interrupts in PMU so that interrupts are
 321          * propagated when ioc bit for a particular set
 322          * command is set
 323          */
 324
 325         pmu_irq_enable();
 326
 327         /* Configure the sub systems for pmu2 */
 328
 329         pmu_write_ssc(pm_ssc);
 330
 331         /*
 332          * Send the set config command for pmu its configured
 333          * for mode CM_IMMEDIATE & hence with No Trigger
 334          */
 335
 336         command.pmu2_params.d_param.cfg_mode = CM_IMMEDIATE;
 337         command.pmu2_params.d_param.cfg_delay = 0;
 338         command.pmu2_params.d_param.rsvd = 0;
 339
 340         /* construct the command to send SET_CFG to particular PMU */
 341         command.pmu2_params.d_param.cmd = SET_CFG_CMD;
 342         command.pmu2_params.d_param.ioc = 0;
 343         command.pmu2_params.d_param.mode_id = 0;
 344         command.pmu2_params.d_param.sys_state = SYS_STATE_S0I0;
 345
 346         /* write the value of PM_CMD into particular PMU */
 347         pr_debug("pmu command being written %x\n",
 348                         command.pmu_pm_set_cfg_cmd_value);
 349
 350         pmu_write_cmd(command.pmu_pm_set_cfg_cmd_value);
 351
 352         return 0;
 353 }
 354
 355 static u16 pmu_min_lss_pci_req(u16 *ids, u16 pci_state)
 356 {
 357         u16 existing_request;
 358         int i;
 359
 360         for (i = 0; ids[i]; ++i) {
 361                 struct mrst_device *mrst_dev;
 362
 363                 mrst_dev = pci_id_2_mrst_dev(ids[i]);
 364                 if (unlikely(!mrst_dev))
 365                         continue;
 366
 367                 existing_request = mrst_dev->latest_request;
 368                 if (existing_request < pci_state)
 369                         pci_state = existing_request;
 370         }
 371         return pci_state;
 372 }
 373
 374 /**
 375  * pmu_pci_set_power_state - Callback function is used by all the PCI devices
 376  *                      for a platform  specific device power on/shutdown.
 377  */
 378
 379 int pmu_pci_set_power_state(struct pci_dev *pdev, pci_power_t pci_state)
 380 {
 381         u32 old_sss, new_sss;
 382         int status = 0;
 383         struct mrst_device *mrst_dev;
 384
 385         pmu_set_power_state_entry++;
 386
 387         BUG_ON(pdev->vendor != PCI_VENDOR_ID_INTEL);
 388         BUG_ON(pci_state < PCI_D0 || pci_state > PCI_D3cold);
 389
 390         mrst_dev = pci_id_2_mrst_dev(pdev->device);
 391         if (unlikely(!mrst_dev))
 392                 return -ENODEV;
 393
 394         mrst_dev->pci_state_counts[pci_state]++;        /* count invocations */
 395
 396         /* PMU driver calls self as part of PCI initialization, ignore */
 397         if (pdev->device == PCI_DEV_ID_MRST_PMU)
 398                 return 0;
 399
 400         BUG_ON(!pmu_reg); /* SW bug if called before initialized */
 401
 402         spin_lock(&mrst_pmu_power_state_lock);
 403
 404         if (pdev->d3_delay) {
 405                 dev_dbg(&pdev->dev, "d3_delay %d, should be 0\n",
 406                         pdev->d3_delay);
 407                 pdev->d3_delay = 0;
 408         }
 409         /*
 410          * If Lincroft graphics, simply remember state
 411          */
 412         if ((pdev->class >> 16) == PCI_BASE_CLASS_DISPLAY
 413                 && !((pdev->class & PCI_SUB_CLASS_MASK) >> 8)) {
 414                 if (pci_state == PCI_D0)
 415                         graphics_is_off = 0;
 416                 else
 417                         graphics_is_off = 1;
 418                 goto ret;
 419         }
 420
 421         if (!mrst_dev->lss)
 422                 goto ret;       /* device with no LSS */
 423
 424         if (mrst_dev->latest_request == pci_state)
 425                 goto ret;       /* no change */
 426
 427         mrst_dev->latest_request = pci_state;   /* record latest request */
 428
 429         /*
 430          * LSS9 and LSS10 contain multiple PCI devices.
 431          * Use the lowest numbered (highest power) state in the LSS
 432          */
 433         if (mrst_dev->lss == 9)
 434                 pci_state = pmu_min_lss_pci_req(mrst_lss9_pci_ids, pci_state);
 435         else if (mrst_dev->lss == 10)
 436                 pci_state = pmu_min_lss_pci_req(mrst_lss10_pci_ids, pci_state);
 437
 438         status = pmu_wait_ready();
 439         if (status)
 440                 goto ret;
 441
 442         old_sss = pmu_read_sss();
 443         new_sss = old_sss & ~SSMSK(3, mrst_dev->lss);
 444         new_sss |= SSMSK(pci_2_mrst_state(mrst_dev->lss, pci_state),
 445                         mrst_dev->lss);
 446
 447         if (new_sss == old_sss)
 448                 goto ret;       /* nothing to do */
 449
 450         pmu_set_power_state_send_cmd++;
 451
 452         status = pmu_issue_command(new_sss);
 453
 454         if (unlikely(status != 0)) {
 455                 dev_err(&pdev->dev, "Failed to Issue a PM command\n");
 456                 goto ret;
 457         }
 458
 459         if (pmu_wait_done())
 460                 goto ret;
 461
 462         lss_s0i3_enabled =
 463         ((pmu_read_sss() & S0I3_SSS_TARGET) == S0I3_SSS_TARGET);
 464 ret:
 465         spin_unlock(&mrst_pmu_power_state_lock);
 466         return status;
 467 }
 468
 469 #ifdef CONFIG_DEBUG_FS
 470 static char *d0ix_names[] = {"D0", "D0i1", "D0i2", "D0i3"};
 471
 472 static inline const char *d0ix_name(int state)
 473 {
 474         return d0ix_names[(int) state];
 475 }
 476
 477 static int debug_mrst_pmu_show(struct seq_file *s, void *unused)
 478 {
 479         struct pci_dev *pdev = NULL;
 480         u32 cur_pmsss;
 481         int lss;
 482
 483         seq_printf(s, "0x%08X D0I1_ACG_SSS_TARGET\n", D0I1_ACG_SSS_TARGET);
 484
 485         cur_pmsss = pmu_read_sss();
 486
 487         seq_printf(s, "0x%08X S0I3_SSS_TARGET\n", S0I3_SSS_TARGET);
 488
 489         seq_printf(s, "0x%08X Current SSS ", cur_pmsss);
 490         seq_printf(s, lss_s0i3_enabled ? "\n" : "[BLOCKS s0i3]\n");
 491
 492         if (cpumask_equal(cpu_online_mask, cpumask_of(0)))
 493                 seq_printf(s, "cpu0 is only cpu online\n");
 494         else
 495                 seq_printf(s, "cpu0 is NOT only cpu online [BLOCKS S0i3]\n");
 496
 497         seq_printf(s, "GFX: %s\n", graphics_is_off ? "" : "[BLOCKS s0i3]");
 498
 499
 500         for_each_pci_dev(pdev) {
 501                 int pos;
 502                 u16 pmcsr;
 503                 struct mrst_device *mrst_dev;
 504                 int i;
 505
 506                 mrst_dev = pci_id_2_mrst_dev(pdev->device);
 507
 508                 seq_printf(s, "%s %04x/%04X %-16.16s ",
 509                         dev_name(&pdev->dev),
 510                         pdev->vendor, pdev->device,
 511                         dev_driver_string(&pdev->dev));
 512
 513                 if (unlikely (!mrst_dev)) {
 514                         seq_printf(s, " UNKNOWN\n");
 515                         continue;
 516                 }
 517
 518                 if (mrst_dev->lss)
 519                         seq_printf(s, "LSS %2d %-4s ", mrst_dev->lss,
 520                                 d0ix_name(((cur_pmsss >>
 521                                         (mrst_dev->lss * 2)) & 0x3)));
 522                 else
 523                         seq_printf(s, "            ");
 524
 525                 /* PCI PM config space setting */
 526                 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
 527                 if (pos != 0) {
 528                         pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
 529                 seq_printf(s, "PCI-%-4s",
 530                         pci_power_name(pmcsr & PCI_PM_CTRL_STATE_MASK));
 531                 } else {
 532                         seq_printf(s, "        ");
 533                 }
 534
 535                 seq_printf(s, " %s ", pci_power_name(mrst_dev->latest_request));
 536                 for (i = 0; i <= PCI_D3cold; ++i)
 537                         seq_printf(s, "%d ", mrst_dev->pci_state_counts[i]);
 538
 539                 if (mrst_dev->lss) {
 540                         unsigned int lssmask;
 541
 542                         lssmask = SSMSK(D0i3, mrst_dev->lss);
 543
 544                         if ((lssmask & S0I3_SSS_TARGET) &&
 545                                 ((lssmask & cur_pmsss) !=
 546                                         (lssmask & S0I3_SSS_TARGET)))
 547                                                 seq_printf(s , "[BLOCKS s0i3]");
 548                 }
 549
 550                 seq_printf(s, "\n");
 551         }
 552         seq_printf(s, "Wake Counters:\n");
 553         for (lss = 0; lss < MRST_NUM_LSS; ++lss)
 554                 seq_printf(s, "LSS%d %d\n", lss, wake_counters[lss]);
 555
 556         seq_printf(s, "Interrupt Counters:\n");
 557         seq_printf(s,
 558                 "INT_SPURIOUS \t%8u\n" "INT_CMD_DONE \t%8u\n"
 559                 "INT_CMD_ERR  \t%8u\n" "INT_WAKE_RX  \t%8u\n"
 560                 "INT_SS_ERROR \t%8u\n" "INT_S0IX_MISS\t%8u\n"
 561                 "INT_NO_ACKC6 \t%8u\n" "INT_INVALID  \t%8u\n",
 562                 pmu_irq_stats[INT_SPURIOUS], pmu_irq_stats[INT_CMD_DONE],
 563                 pmu_irq_stats[INT_CMD_ERR], pmu_irq_stats[INT_WAKE_RX],
 564                 pmu_irq_stats[INT_SS_ERROR], pmu_irq_stats[INT_S0IX_MISS],
 565                 pmu_irq_stats[INT_NO_ACKC6], pmu_irq_stats[INT_INVALID]);
 566
 567         seq_printf(s, "mrst_pmu_wait_ready_calls          %8d\n",
 568                         pmu_wait_ready_calls);
 569         seq_printf(s, "mrst_pmu_wait_ready_udelays        %8d\n",
 570                         pmu_wait_ready_udelays);
 571         seq_printf(s, "mrst_pmu_wait_ready_udelays_max    %8d\n",
 572                         pmu_wait_ready_udelays_max);
 573         seq_printf(s, "mrst_pmu_wait_done_calls           %8d\n",
 574                         pmu_wait_done_calls);
 575         seq_printf(s, "mrst_pmu_wait_done_udelays         %8d\n",
 576                         pmu_wait_done_udelays);
 577         seq_printf(s, "mrst_pmu_wait_done_udelays_max     %8d\n",
 578                         pmu_wait_done_udelays_max);
 579         seq_printf(s, "mrst_pmu_set_power_state_entry     %8d\n",
 580                         pmu_set_power_state_entry);
 581         seq_printf(s, "mrst_pmu_set_power_state_send_cmd  %8d\n",
 582                         pmu_set_power_state_send_cmd);
 583         seq_printf(s, "SCU busy: %d\n", pmu_read_busy_status());
 584
 585         return 0;
 586 }
 587
 588 static int debug_mrst_pmu_open(struct inode *inode, struct file *file)
 589 {
 590         return single_open(file, debug_mrst_pmu_show, NULL);
 591 }
 592
 593 static const struct file_operations devices_state_operations = {
 594         .open           = debug_mrst_pmu_open,
 595         .read           = seq_read,
 596         .llseek         = seq_lseek,
 597         .release        = single_release,
 598 };
 599 #endif  /* DEBUG_FS */
 600
 601 /*
 602  * Validate SCU PCI shim PCI vendor capability byte
 603  * against LSS hard-coded in mrst_devs[] above.
 604  * DEBUG only.
 605  */
 606 static void pmu_scu_firmware_debug(void)
 607 {
 608         struct pci_dev *pdev = NULL;
 609
 610         for_each_pci_dev(pdev) {
 611                 struct mrst_device *mrst_dev;
 612                 u8 pci_config_lss;
 613                 int pos;
 614
 615                 mrst_dev = pci_id_2_mrst_dev(pdev->device);
 616                 if (unlikely(!mrst_dev)) {
 617                         printk(KERN_ERR FW_BUG "pmu: Unknown "
 618                                 "PCI device 0x%04X\n", pdev->device);
 619                         continue;
 620                 }
 621
 622                 if (mrst_dev->lss == 0)
 623                         continue;        /* no LSS in our table */
 624
 625                 pos = pci_find_capability(pdev, PCI_CAP_ID_VNDR);
 626                 if (!pos != 0) {
 627                         printk(KERN_ERR FW_BUG "pmu: 0x%04X "
 628                                 "missing PCI Vendor Capability\n",
 629                                 pdev->device);
 630                         continue;
 631                 }
 632                 pci_read_config_byte(pdev, pos + 4, &pci_config_lss);
 633                 if (!(pci_config_lss & PCI_VENDOR_CAP_LOG_SS_MASK)) {
 634                         printk(KERN_ERR FW_BUG "pmu: 0x%04X "
 635                                 "invalid PCI Vendor Capability 0x%x "
 636                                 " expected LSS 0x%X\n",
 637                                 pdev->device, pci_config_lss, mrst_dev->lss);
 638                         continue;
 639                 }
 640                 pci_config_lss &= PCI_VENDOR_CAP_LOG_ID_MASK;
 641
 642                 if (mrst_dev->lss == pci_config_lss)
 643                         continue;
 644
 645                 printk(KERN_ERR FW_BUG "pmu: 0x%04X LSS = %d, expected %d\n",
 646                         pdev->device, pci_config_lss, mrst_dev->lss);
 647         }
 648 }
 649
 650 /**
 651  * pmu_probe
 652  */
 653 static int __devinit pmu_probe(struct pci_dev *pdev,
 654                                    const struct pci_device_id *pci_id)
 655 {
 656         int ret;
 657         struct mrst_pmu_reg *pmu;
 658
 659         /* Init the device */
 660         ret = pci_enable_device(pdev);
 661         if (ret) {
 662                 dev_err(&pdev->dev, "Unable to Enable PCI device\n");
 663                 return ret;
 664         }
 665
 666         ret = pci_request_regions(pdev, MRST_PMU_DRV_NAME);
 667         if (ret < 0) {
 668                 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n");
 669                 goto out_err1;
 670         }
 671
 672         /* Map the memory of PMU reg base */
 673         pmu = pci_iomap(pdev, 0, 0);
 674         if (!pmu) {
 675                 dev_err(&pdev->dev, "Unable to map the PMU address space\n");
 676                 ret = -ENOMEM;
 677                 goto out_err2;
 678         }
 679
 680 #ifdef CONFIG_DEBUG_FS
 681         /* /sys/kernel/debug/mrst_pmu */
 682         (void) debugfs_create_file("mrst_pmu", S_IFREG | S_IRUGO,
 683                                 NULL, NULL, &devices_state_operations);
 684 #endif
 685         pmu_reg = pmu;  /* success */
 686
 687         if (request_irq(pdev->irq, pmu_irq, 0, MRST_PMU_DRV_NAME, NULL)) {
 688                 dev_err(&pdev->dev, "Registering isr has failed\n");
 689                 ret = -1;
 690                 goto out_err3;
 691         }
 692
 693         pmu_scu_firmware_debug();
 694
 695         pmu_write_wkc(S0I3_WAKE_SOURCES);       /* Enable S0i3 wakeup sources */
 696
 697         pmu_wait_ready();
 698
 699         pmu_write_ssc(D0I1_ACG_SSS_TARGET);     /* Enable Auto-Clock_Gating */
 700         pmu_write_cmd(0x201);
 701
 702         spin_lock_init(&mrst_pmu_power_state_lock);
 703
 704         /* Enable the hardware interrupt */
 705         pmu_irq_enable();
 706         return 0;
 707
 708 out_err3:
 709         free_irq(pdev->irq, NULL);
 710         pci_iounmap(pdev, pmu_reg);
 711         pmu_reg = NULL;
 712 out_err2:
 713         pci_release_region(pdev, 0);
 714 out_err1:
 715         pci_disable_device(pdev);
 716         return ret;
 717 }
 718
 719 static void __devexit pmu_remove(struct pci_dev *pdev)
 720 {
 721         dev_err(&pdev->dev, "Mid PM pmu_remove called\n");
 722
 723         /* Freeing up the irq */
 724         free_irq(pdev->irq, NULL);
 725
 726         pci_iounmap(pdev, pmu_reg);
 727         pmu_reg = NULL;
 728
 729         /* disable the current PCI device */
 730         pci_release_region(pdev, 0);
 731         pci_disable_device(pdev);
 732 }
 733
 734 static DEFINE_PCI_DEVICE_TABLE(pmu_pci_ids) = {
 735         { PCI_VDEVICE(INTEL, PCI_DEV_ID_MRST_PMU), 0 },
 736         { }
 737 };
 738
 739 MODULE_DEVICE_TABLE(pci, pmu_pci_ids);
 740
 741 static struct pci_driver driver = {
 742         .name = MRST_PMU_DRV_NAME,
 743         .id_table = pmu_pci_ids,
 744         .probe = pmu_probe,
 745         .remove = __devexit_p(pmu_remove),
 746 };
 747
 748 /**
 749  * pmu_pci_register - register the PMU driver as PCI device
 750  */
 751 static int __init pmu_pci_register(void)
 752 {
 753         return pci_register_driver(&driver);
 754 }
 755
 756 /* Register and probe via fs_initcall() to preceed device_initcall() */
 757 fs_initcall(pmu_pci_register);
 758
 759 static void __exit mid_pci_cleanup(void)
 760 {
 761         pci_unregister_driver(&driver);
 762 }
 763
 764 static int ia_major;
 765 static int ia_minor;
 766
 767 static int pmu_sfi_parse_oem(struct sfi_table_header *table)
 768 {
 769         struct sfi_table_simple *sb;
 770
 771         sb = (struct sfi_table_simple *)table;
 772         ia_major = (sb->pentry[1] >> 0) & 0xFFFF;
 773         ia_minor = (sb->pentry[1] >> 16) & 0xFFFF;
 774         printk(KERN_INFO "mrst_pmu: IA FW version v%x.%x\n",
 775                 ia_major, ia_minor);
 776
 777         return 0;
 778 }
 779
 780 static int __init scu_fw_check(void)
 781 {
 782         int ret;
 783         u32 fw_version;
 784
 785         if (!pmu_reg)
 786                 return 0;       /* this driver didn't probe-out */
 787
 788         sfi_table_parse("OEMB", NULL, NULL, pmu_sfi_parse_oem);
 789
 790         if (ia_major < 0x6005 || ia_minor < 0x1525) {
 791                 WARN(1, "mrst_pmu: IA FW version too old\n");
 792                 return -1;
 793         }
 794
 795         ret = intel_scu_ipc_command(IPCMSG_FW_REVISION, 0, NULL, 0,
 796                                         &fw_version, 1);
 797
 798         if (ret) {
 799                 WARN(1, "mrst_pmu: IPC FW version? %d\n", ret);
 800         } else {
 801                 int scu_major = (fw_version >> 8) & 0xFF;
 802                 int scu_minor = (fw_version >> 0) & 0xFF;
 803
 804                 printk(KERN_INFO "mrst_pmu: firmware v%x\n", fw_version);
 805
 806                 if ((scu_major >= 0xC0) && (scu_minor >= 0x49)) {
 807                         printk(KERN_INFO "mrst_pmu: enabling S0i3\n");
 808                         mrst_pmu_s0i3_enable = true;
 809                 } else {
 810                         WARN(1, "mrst_pmu: S0i3 disabled, old firmware %X.%X",
 811                                         scu_major, scu_minor);
 812                 }
 813         }
 814         return 0;
 815 }
 816 late_initcall(scu_fw_check);
 817 module_exit(mid_pci_cleanup);