2 * mrst.c: Intel Moorestown platform specific setup code
4 * (C) Copyright 2008 Intel Corporation
5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) "mrst: " fmt
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/interrupt.h>
18 #include <linux/scatterlist.h>
19 #include <linux/sfi.h>
20 #include <linux/intel_pmic_gpio.h>
21 #include <linux/spi/spi.h>
22 #include <linux/i2c.h>
23 #include <linux/i2c/pca953x.h>
24 #include <linux/gpio_keys.h>
25 #include <linux/input.h>
26 #include <linux/platform_device.h>
27 #include <linux/irq.h>
28 #include <linux/module.h>
29 #include <linux/notifier.h>
30 #include <linux/mfd/intel_msic.h>
32 #include <asm/setup.h>
33 #include <asm/mpspec_def.h>
34 #include <asm/hw_irq.h>
36 #include <asm/io_apic.h>
38 #include <asm/mrst-vrtc.h>
40 #include <asm/i8259.h>
41 #include <asm/intel_scu_ipc.h>
42 #include <asm/apb_timer.h>
43 #include <asm/reboot.h>
46 * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
47 * cmdline option x86_mrst_timer can be used to override the configuration
48 * to prefer one or the other.
49 * at runtime, there are basically three timer configurations:
50 * 1. per cpu apbt clock only
51 * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
52 * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
54 * by default (without cmdline option), platform code first detects cpu type
55 * to see if we are on lincroft or penwell, then set up both lapic or apbt
57 * i.e. by default, medfield uses configuration #2, moorestown uses #1.
58 * config #3 is supported but not recommended on medfield.
60 * rating and feature summary:
61 * lapic (with C3STOP) --------- 100
62 * apbt (always-on) ------------ 110
63 * lapic (always-on,ARAT) ------ 150
66 __cpuinitdata enum mrst_timer_options mrst_timer_options;
68 static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
69 static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
70 enum mrst_cpu_type __mrst_cpu_chip;
71 EXPORT_SYMBOL_GPL(__mrst_cpu_chip);
75 struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
76 EXPORT_SYMBOL_GPL(sfi_mrtc_array);
79 /* parse all the mtimer info to a static mtimer array */
80 static int __init sfi_parse_mtmr(struct sfi_table_header *table)
82 struct sfi_table_simple *sb;
83 struct sfi_timer_table_entry *pentry;
84 struct mpc_intsrc mp_irq;
87 sb = (struct sfi_table_simple *)table;
88 if (!sfi_mtimer_num) {
89 sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
90 struct sfi_timer_table_entry);
91 pentry = (struct sfi_timer_table_entry *) sb->pentry;
92 totallen = sfi_mtimer_num * sizeof(*pentry);
93 memcpy(sfi_mtimer_array, pentry, totallen);
96 pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
97 pentry = sfi_mtimer_array;
98 for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
99 pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz,"
100 " irq = %d\n", totallen, (u32)pentry->phys_addr,
101 pentry->freq_hz, pentry->irq);
104 mp_irq.type = MP_INTSRC;
105 mp_irq.irqtype = mp_INT;
106 /* triggering mode edge bit 2-3, active high polarity bit 0-1 */
108 mp_irq.srcbus = MP_BUS_ISA;
109 mp_irq.srcbusirq = pentry->irq; /* IRQ */
110 mp_irq.dstapic = MP_APIC_ALL;
111 mp_irq.dstirq = pentry->irq;
112 mp_save_irq(&mp_irq);
118 struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
121 if (hint < sfi_mtimer_num) {
122 if (!sfi_mtimer_usage[hint]) {
123 pr_debug("hint taken for timer %d irq %d\n",\
124 hint, sfi_mtimer_array[hint].irq);
125 sfi_mtimer_usage[hint] = 1;
126 return &sfi_mtimer_array[hint];
129 /* take the first timer available */
130 for (i = 0; i < sfi_mtimer_num;) {
131 if (!sfi_mtimer_usage[i]) {
132 sfi_mtimer_usage[i] = 1;
133 return &sfi_mtimer_array[i];
140 void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
143 for (i = 0; i < sfi_mtimer_num;) {
144 if (mtmr->irq == sfi_mtimer_array[i].irq) {
145 sfi_mtimer_usage[i] = 0;
152 /* parse all the mrtc info to a global mrtc array */
153 int __init sfi_parse_mrtc(struct sfi_table_header *table)
155 struct sfi_table_simple *sb;
156 struct sfi_rtc_table_entry *pentry;
157 struct mpc_intsrc mp_irq;
161 sb = (struct sfi_table_simple *)table;
163 sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
164 struct sfi_rtc_table_entry);
165 pentry = (struct sfi_rtc_table_entry *)sb->pentry;
166 totallen = sfi_mrtc_num * sizeof(*pentry);
167 memcpy(sfi_mrtc_array, pentry, totallen);
170 pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
171 pentry = sfi_mrtc_array;
172 for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
173 pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
174 totallen, (u32)pentry->phys_addr, pentry->irq);
175 mp_irq.type = MP_INTSRC;
176 mp_irq.irqtype = mp_INT;
177 mp_irq.irqflag = 0xf; /* level trigger and active low */
178 mp_irq.srcbus = MP_BUS_ISA;
179 mp_irq.srcbusirq = pentry->irq; /* IRQ */
180 mp_irq.dstapic = MP_APIC_ALL;
181 mp_irq.dstirq = pentry->irq;
182 mp_save_irq(&mp_irq);
187 static unsigned long __init mrst_calibrate_tsc(void)
189 unsigned long flags, fast_calibrate;
190 if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) {
191 u32 lo, hi, ratio, fsb;
193 rdmsr(MSR_IA32_PERF_STATUS, lo, hi);
194 pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi);
195 ratio = (hi >> 8) & 0x1f;
196 pr_debug("ratio is %d\n", ratio);
198 pr_err("read a zero ratio, should be incorrect!\n");
199 pr_err("force tsc ratio to 16 ...\n");
202 rdmsr(MSR_FSB_FREQ, lo, hi);
203 if ((lo & 0x7) == 0x7)
204 fsb = PENWELL_FSB_FREQ_83SKU;
206 fsb = PENWELL_FSB_FREQ_100SKU;
207 fast_calibrate = ratio * fsb;
208 pr_debug("read penwell tsc %lu khz\n", fast_calibrate);
209 lapic_timer_frequency = fsb * 1000 / HZ;
210 /* mark tsc clocksource as reliable */
211 set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE);
213 local_irq_save(flags);
214 fast_calibrate = apbt_quick_calibrate();
215 local_irq_restore(flags);
219 return fast_calibrate;
224 static void __init mrst_time_init(void)
226 sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
227 switch (mrst_timer_options) {
228 case MRST_TIMER_APBT_ONLY:
230 case MRST_TIMER_LAPIC_APBT:
231 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
232 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
235 if (!boot_cpu_has(X86_FEATURE_ARAT))
237 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
238 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
241 /* we need at least one APB timer */
242 pre_init_apic_IRQ0();
246 static void __cpuinit mrst_arch_setup(void)
248 if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
249 __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
250 else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
251 __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
253 pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
254 boot_cpu_data.x86, boot_cpu_data.x86_model);
255 __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
257 pr_debug("Moorestown CPU %s identified\n",
258 (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
259 "Lincroft" : "Penwell");
262 /* MID systems don't have i8042 controller */
263 static int mrst_i8042_detect(void)
268 /* Reboot and power off are handled by the SCU on a MID device */
269 static void mrst_power_off(void)
271 intel_scu_ipc_simple_command(0xf1, 1);
274 static void mrst_reboot(void)
276 intel_scu_ipc_simple_command(0xf1, 0);
280 * Moorestown specific x86_init function overrides and early setup
283 void __init x86_mrst_early_setup(void)
285 x86_init.resources.probe_roms = x86_init_noop;
286 x86_init.resources.reserve_resources = x86_init_noop;
288 x86_init.timers.timer_init = mrst_time_init;
289 x86_init.timers.setup_percpu_clockev = x86_init_noop;
291 x86_init.irqs.pre_vector_init = x86_init_noop;
293 x86_init.oem.arch_setup = mrst_arch_setup;
295 x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
297 x86_platform.calibrate_tsc = mrst_calibrate_tsc;
298 x86_platform.i8042_detect = mrst_i8042_detect;
299 x86_init.timers.wallclock_init = mrst_rtc_init;
300 x86_init.pci.init = pci_mrst_init;
301 x86_init.pci.fixup_irqs = x86_init_noop;
303 legacy_pic = &null_legacy_pic;
305 /* Moorestown specific power_off/restart method */
306 pm_power_off = mrst_power_off;
307 machine_ops.emergency_restart = mrst_reboot;
309 /* Avoid searching for BIOS MP tables */
310 x86_init.mpparse.find_smp_config = x86_init_noop;
311 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
312 set_bit(MP_BUS_ISA, mp_bus_not_pci);
316 * if user does not want to use per CPU apb timer, just give it a lower rating
317 * than local apic timer and skip the late per cpu timer init.
319 static inline int __init setup_x86_mrst_timer(char *arg)
324 if (strcmp("apbt_only", arg) == 0)
325 mrst_timer_options = MRST_TIMER_APBT_ONLY;
326 else if (strcmp("lapic_and_apbt", arg) == 0)
327 mrst_timer_options = MRST_TIMER_LAPIC_APBT;
329 pr_warning("X86 MRST timer option %s not recognised"
330 " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
336 __setup("x86_mrst_timer=", setup_x86_mrst_timer);
339 * Parsing GPIO table first, since the DEVS table will need this table
340 * to map the pin name to the actual pin.
342 static struct sfi_gpio_table_entry *gpio_table;
343 static int gpio_num_entry;
345 static int __init sfi_parse_gpio(struct sfi_table_header *table)
347 struct sfi_table_simple *sb;
348 struct sfi_gpio_table_entry *pentry;
353 sb = (struct sfi_table_simple *)table;
354 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
355 pentry = (struct sfi_gpio_table_entry *)sb->pentry;
357 gpio_table = (struct sfi_gpio_table_entry *)
358 kmalloc(num * sizeof(*pentry), GFP_KERNEL);
361 memcpy(gpio_table, pentry, num * sizeof(*pentry));
362 gpio_num_entry = num;
364 pr_debug("GPIO pin info:\n");
365 for (i = 0; i < num; i++, pentry++)
366 pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
368 pentry->controller_name,
374 static int get_gpio_by_name(const char *name)
376 struct sfi_gpio_table_entry *pentry = gpio_table;
381 for (i = 0; i < gpio_num_entry; i++, pentry++) {
382 if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
383 return pentry->pin_no;
389 * Here defines the array of devices platform data that IAFW would export
390 * through SFI "DEVS" table, we use name and type to match the device and
394 char name[SFI_NAME_LEN + 1];
397 void *(*get_platform_data)(void *info);
400 /* the offset for the mapping of global gpio pin to irq */
401 #define MRST_IRQ_OFFSET 0x100
403 static void __init *pmic_gpio_platform_data(void *info)
405 static struct intel_pmic_gpio_platform_data pmic_gpio_pdata;
406 int gpio_base = get_gpio_by_name("pmic_gpio_base");
410 pmic_gpio_pdata.gpio_base = gpio_base;
411 pmic_gpio_pdata.irq_base = gpio_base + MRST_IRQ_OFFSET;
412 pmic_gpio_pdata.gpiointr = 0xffffeff8;
414 return &pmic_gpio_pdata;
417 static void __init *max3111_platform_data(void *info)
419 struct spi_board_info *spi_info = info;
420 int intr = get_gpio_by_name("max3111_int");
422 spi_info->mode = SPI_MODE_0;
425 spi_info->irq = intr + MRST_IRQ_OFFSET;
429 /* we have multiple max7315 on the board ... */
430 #define MAX7315_NUM 2
431 static void __init *max7315_platform_data(void *info)
433 static struct pca953x_platform_data max7315_pdata[MAX7315_NUM];
435 struct pca953x_platform_data *max7315 = &max7315_pdata[nr];
436 struct i2c_board_info *i2c_info = info;
438 char base_pin_name[SFI_NAME_LEN + 1];
439 char intr_pin_name[SFI_NAME_LEN + 1];
441 if (nr == MAX7315_NUM) {
442 pr_err("too many max7315s, we only support %d\n",
446 /* we have several max7315 on the board, we only need load several
447 * instances of the same pca953x driver to cover them
449 strcpy(i2c_info->type, "max7315");
451 sprintf(base_pin_name, "max7315_%d_base", nr);
452 sprintf(intr_pin_name, "max7315_%d_int", nr);
454 strcpy(base_pin_name, "max7315_base");
455 strcpy(intr_pin_name, "max7315_int");
458 gpio_base = get_gpio_by_name(base_pin_name);
459 intr = get_gpio_by_name(intr_pin_name);
463 max7315->gpio_base = gpio_base;
465 i2c_info->irq = intr + MRST_IRQ_OFFSET;
466 max7315->irq_base = gpio_base + MRST_IRQ_OFFSET;
469 max7315->irq_base = -1;
474 static void __init *emc1403_platform_data(void *info)
476 static short intr2nd_pdata;
477 struct i2c_board_info *i2c_info = info;
478 int intr = get_gpio_by_name("thermal_int");
479 int intr2nd = get_gpio_by_name("thermal_alert");
481 if (intr == -1 || intr2nd == -1)
484 i2c_info->irq = intr + MRST_IRQ_OFFSET;
485 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
487 return &intr2nd_pdata;
490 static void __init *lis331dl_platform_data(void *info)
492 static short intr2nd_pdata;
493 struct i2c_board_info *i2c_info = info;
494 int intr = get_gpio_by_name("accel_int");
495 int intr2nd = get_gpio_by_name("accel_2");
497 if (intr == -1 || intr2nd == -1)
500 i2c_info->irq = intr + MRST_IRQ_OFFSET;
501 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
503 return &intr2nd_pdata;
506 static void __init *no_platform_data(void *info)
511 static struct resource msic_resources[] = {
513 .start = INTEL_MSIC_IRQ_PHYS_BASE,
514 .end = INTEL_MSIC_IRQ_PHYS_BASE + 64 - 1,
515 .flags = IORESOURCE_MEM,
519 static struct intel_msic_platform_data msic_pdata;
521 static struct platform_device msic_device = {
522 .name = "intel_msic",
525 .platform_data = &msic_pdata,
527 .num_resources = ARRAY_SIZE(msic_resources),
528 .resource = msic_resources,
531 static inline bool mrst_has_msic(void)
533 return mrst_identify_cpu() == MRST_CPU_CHIP_PENWELL;
536 static int msic_scu_status_change(struct notifier_block *nb,
537 unsigned long code, void *data)
539 if (code == SCU_DOWN) {
540 platform_device_unregister(&msic_device);
544 return platform_device_register(&msic_device);
547 static int __init msic_init(void)
549 static struct notifier_block msic_scu_notifier = {
550 .notifier_call = msic_scu_status_change,
554 * We need to be sure that the SCU IPC is ready before MSIC device
558 intel_scu_notifier_add(&msic_scu_notifier);
562 arch_initcall(msic_init);
565 * msic_generic_platform_data - sets generic platform data for the block
566 * @info: pointer to the SFI device table entry for this block
569 * Function sets IRQ number from the SFI table entry for given device to
570 * the MSIC platform data.
572 static void *msic_generic_platform_data(void *info, enum intel_msic_block block)
574 struct sfi_device_table_entry *entry = info;
576 BUG_ON(block < 0 || block >= INTEL_MSIC_BLOCK_LAST);
577 msic_pdata.irq[block] = entry->irq;
579 return no_platform_data(info);
582 static void *msic_battery_platform_data(void *info)
584 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_BATTERY);
587 static void *msic_gpio_platform_data(void *info)
589 static struct intel_msic_gpio_pdata pdata;
590 int gpio = get_gpio_by_name("msic_gpio_base");
595 pdata.gpio_base = gpio;
596 msic_pdata.gpio = &pdata;
598 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_GPIO);
601 static void *msic_audio_platform_data(void *info)
603 struct platform_device *pdev;
605 pdev = platform_device_register_simple("sst-platform", -1, NULL, 0);
607 pr_err("failed to create audio platform device\n");
611 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_AUDIO);
614 static void *msic_power_btn_platform_data(void *info)
616 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_POWER_BTN);
619 static void *msic_ocd_platform_data(void *info)
621 static struct intel_msic_ocd_pdata pdata;
622 int gpio = get_gpio_by_name("ocd_gpio");
628 msic_pdata.ocd = &pdata;
630 return msic_generic_platform_data(info, INTEL_MSIC_BLOCK_OCD);
633 static const struct devs_id __initconst device_ids[] = {
634 {"pmic_gpio", SFI_DEV_TYPE_SPI, 1, &pmic_gpio_platform_data},
635 {"spi_max3111", SFI_DEV_TYPE_SPI, 0, &max3111_platform_data},
636 {"i2c_max7315", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
637 {"i2c_max7315_2", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
638 {"emc1403", SFI_DEV_TYPE_I2C, 1, &emc1403_platform_data},
639 {"i2c_accel", SFI_DEV_TYPE_I2C, 0, &lis331dl_platform_data},
640 {"pmic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
642 /* MSIC subdevices */
643 {"msic_battery", SFI_DEV_TYPE_IPC, 1, &msic_battery_platform_data},
644 {"msic_gpio", SFI_DEV_TYPE_IPC, 1, &msic_gpio_platform_data},
645 {"msic_audio", SFI_DEV_TYPE_IPC, 1, &msic_audio_platform_data},
646 {"msic_power_btn", SFI_DEV_TYPE_IPC, 1, &msic_power_btn_platform_data},
647 {"msic_ocd", SFI_DEV_TYPE_IPC, 1, &msic_ocd_platform_data},
652 #define MAX_IPCDEVS 24
653 static struct platform_device *ipc_devs[MAX_IPCDEVS];
654 static int ipc_next_dev;
656 #define MAX_SCU_SPI 24
657 static struct spi_board_info *spi_devs[MAX_SCU_SPI];
658 static int spi_next_dev;
660 #define MAX_SCU_I2C 24
661 static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
662 static int i2c_bus[MAX_SCU_I2C];
663 static int i2c_next_dev;
665 static void __init intel_scu_device_register(struct platform_device *pdev)
667 if(ipc_next_dev == MAX_IPCDEVS)
668 pr_err("too many SCU IPC devices");
670 ipc_devs[ipc_next_dev++] = pdev;
673 static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
675 struct spi_board_info *new_dev;
677 if (spi_next_dev == MAX_SCU_SPI) {
678 pr_err("too many SCU SPI devices");
682 new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
684 pr_err("failed to alloc mem for delayed spi dev %s\n",
688 memcpy(new_dev, sdev, sizeof(*sdev));
690 spi_devs[spi_next_dev++] = new_dev;
693 static void __init intel_scu_i2c_device_register(int bus,
694 struct i2c_board_info *idev)
696 struct i2c_board_info *new_dev;
698 if (i2c_next_dev == MAX_SCU_I2C) {
699 pr_err("too many SCU I2C devices");
703 new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
705 pr_err("failed to alloc mem for delayed i2c dev %s\n",
709 memcpy(new_dev, idev, sizeof(*idev));
711 i2c_bus[i2c_next_dev] = bus;
712 i2c_devs[i2c_next_dev++] = new_dev;
715 BLOCKING_NOTIFIER_HEAD(intel_scu_notifier);
716 EXPORT_SYMBOL_GPL(intel_scu_notifier);
718 /* Called by IPC driver */
719 void intel_scu_devices_create(void)
723 for (i = 0; i < ipc_next_dev; i++)
724 platform_device_add(ipc_devs[i]);
726 for (i = 0; i < spi_next_dev; i++)
727 spi_register_board_info(spi_devs[i], 1);
729 for (i = 0; i < i2c_next_dev; i++) {
730 struct i2c_adapter *adapter;
731 struct i2c_client *client;
733 adapter = i2c_get_adapter(i2c_bus[i]);
735 client = i2c_new_device(adapter, i2c_devs[i]);
737 pr_err("can't create i2c device %s\n",
740 i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
742 intel_scu_notifier_post(SCU_AVAILABLE, 0L);
744 EXPORT_SYMBOL_GPL(intel_scu_devices_create);
746 /* Called by IPC driver */
747 void intel_scu_devices_destroy(void)
751 intel_scu_notifier_post(SCU_DOWN, 0L);
753 for (i = 0; i < ipc_next_dev; i++)
754 platform_device_del(ipc_devs[i]);
756 EXPORT_SYMBOL_GPL(intel_scu_devices_destroy);
758 static void __init install_irq_resource(struct platform_device *pdev, int irq)
760 /* Single threaded */
761 static struct resource __initdata res = {
763 .flags = IORESOURCE_IRQ,
766 platform_device_add_resources(pdev, &res, 1);
769 static void __init sfi_handle_ipc_dev(struct sfi_device_table_entry *entry)
771 const struct devs_id *dev = device_ids;
772 struct platform_device *pdev;
775 while (dev->name[0]) {
776 if (dev->type == SFI_DEV_TYPE_IPC &&
777 !strncmp(dev->name, entry->name, SFI_NAME_LEN)) {
778 pdata = dev->get_platform_data(entry);
785 * On Medfield the platform device creation is handled by the MSIC
786 * MFD driver so we don't need to do it here.
791 /* ID as IRQ is a hack that will go away */
792 pdev = platform_device_alloc(entry->name, entry->irq);
794 pr_err("out of memory for SFI platform device '%s'.\n",
798 install_irq_resource(pdev, entry->irq);
800 pdev->dev.platform_data = pdata;
801 intel_scu_device_register(pdev);
804 static void __init sfi_handle_spi_dev(struct spi_board_info *spi_info)
806 const struct devs_id *dev = device_ids;
809 while (dev->name[0]) {
810 if (dev->type == SFI_DEV_TYPE_SPI &&
811 !strncmp(dev->name, spi_info->modalias, SFI_NAME_LEN)) {
812 pdata = dev->get_platform_data(spi_info);
817 spi_info->platform_data = pdata;
819 intel_scu_spi_device_register(spi_info);
821 spi_register_board_info(spi_info, 1);
824 static void __init sfi_handle_i2c_dev(int bus, struct i2c_board_info *i2c_info)
826 const struct devs_id *dev = device_ids;
829 while (dev->name[0]) {
830 if (dev->type == SFI_DEV_TYPE_I2C &&
831 !strncmp(dev->name, i2c_info->type, SFI_NAME_LEN)) {
832 pdata = dev->get_platform_data(i2c_info);
837 i2c_info->platform_data = pdata;
840 intel_scu_i2c_device_register(bus, i2c_info);
842 i2c_register_board_info(bus, i2c_info, 1);
846 static int __init sfi_parse_devs(struct sfi_table_header *table)
848 struct sfi_table_simple *sb;
849 struct sfi_device_table_entry *pentry;
850 struct spi_board_info spi_info;
851 struct i2c_board_info i2c_info;
854 struct io_apic_irq_attr irq_attr;
856 sb = (struct sfi_table_simple *)table;
857 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
858 pentry = (struct sfi_device_table_entry *)sb->pentry;
860 for (i = 0; i < num; i++, pentry++) {
861 int irq = pentry->irq;
863 if (irq != (u8)0xff) { /* native RTE case */
864 /* these SPI2 devices are not exposed to system as PCI
865 * devices, but they have separate RTE entry in IOAPIC
866 * so we have to enable them one by one here
868 ioapic = mp_find_ioapic(irq);
869 irq_attr.ioapic = ioapic;
870 irq_attr.ioapic_pin = irq;
871 irq_attr.trigger = 1;
872 irq_attr.polarity = 1;
873 io_apic_set_pci_routing(NULL, irq, &irq_attr);
875 irq = 0; /* No irq */
877 switch (pentry->type) {
878 case SFI_DEV_TYPE_IPC:
879 pr_debug("info[%2d]: IPC bus, name = %16.16s, "
880 "irq = 0x%2x\n", i, pentry->name, pentry->irq);
881 sfi_handle_ipc_dev(pentry);
883 case SFI_DEV_TYPE_SPI:
884 memset(&spi_info, 0, sizeof(spi_info));
885 strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
887 spi_info.bus_num = pentry->host_num;
888 spi_info.chip_select = pentry->addr;
889 spi_info.max_speed_hz = pentry->max_freq;
890 pr_debug("info[%2d]: SPI bus = %d, name = %16.16s, "
891 "irq = 0x%2x, max_freq = %d, cs = %d\n", i,
895 spi_info.max_speed_hz,
896 spi_info.chip_select);
897 sfi_handle_spi_dev(&spi_info);
899 case SFI_DEV_TYPE_I2C:
900 memset(&i2c_info, 0, sizeof(i2c_info));
901 bus = pentry->host_num;
902 strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
904 i2c_info.addr = pentry->addr;
905 pr_debug("info[%2d]: I2C bus = %d, name = %16.16s, "
906 "irq = 0x%2x, addr = 0x%x\n", i, bus,
910 sfi_handle_i2c_dev(bus, &i2c_info);
912 case SFI_DEV_TYPE_UART:
913 case SFI_DEV_TYPE_HSI:
921 static int __init mrst_platform_init(void)
923 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
924 sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
927 arch_initcall(mrst_platform_init);
930 * we will search these buttons in SFI GPIO table (by name)
931 * and register them dynamically. Please add all possible
932 * buttons here, we will shrink them if no GPIO found.
934 static struct gpio_keys_button gpio_button[] = {
935 {KEY_POWER, -1, 1, "power_btn", EV_KEY, 0, 3000},
936 {KEY_PROG1, -1, 1, "prog_btn1", EV_KEY, 0, 20},
937 {KEY_PROG2, -1, 1, "prog_btn2", EV_KEY, 0, 20},
938 {SW_LID, -1, 1, "lid_switch", EV_SW, 0, 20},
939 {KEY_VOLUMEUP, -1, 1, "vol_up", EV_KEY, 0, 20},
940 {KEY_VOLUMEDOWN, -1, 1, "vol_down", EV_KEY, 0, 20},
941 {KEY_CAMERA, -1, 1, "camera_full", EV_KEY, 0, 20},
942 {KEY_CAMERA_FOCUS, -1, 1, "camera_half", EV_KEY, 0, 20},
943 {SW_KEYPAD_SLIDE, -1, 1, "MagSw1", EV_SW, 0, 20},
944 {SW_KEYPAD_SLIDE, -1, 1, "MagSw2", EV_SW, 0, 20},
947 static struct gpio_keys_platform_data mrst_gpio_keys = {
948 .buttons = gpio_button,
950 .nbuttons = -1, /* will fill it after search */
953 static struct platform_device pb_device = {
957 .platform_data = &mrst_gpio_keys,
962 * Shrink the non-existent buttons, register the gpio button
963 * device if there is some
965 static int __init pb_keys_init(void)
967 struct gpio_keys_button *gb = gpio_button;
968 int i, num, good = 0;
970 num = sizeof(gpio_button) / sizeof(struct gpio_keys_button);
971 for (i = 0; i < num; i++) {
972 gb[i].gpio = get_gpio_by_name(gb[i].desc);
973 if (gb[i].gpio == -1)
982 mrst_gpio_keys.nbuttons = good;
983 return platform_device_register(&pb_device);
987 late_initcall(pb_keys_init);