2 * mrst.c: Intel Moorestown platform specific setup code
4 * (C) Copyright 2008 Intel Corporation
5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 #define pr_fmt(fmt) "mrst: " fmt
15 #include <linux/init.h>
16 #include <linux/kernel.h>
17 #include <linux/sfi.h>
18 #include <linux/intel_pmic_gpio.h>
19 #include <linux/spi/spi.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c/pca953x.h>
22 #include <linux/gpio_keys.h>
23 #include <linux/input.h>
24 #include <linux/platform_device.h>
25 #include <linux/irq.h>
26 #include <linux/module.h>
28 #include <asm/setup.h>
29 #include <asm/mpspec_def.h>
30 #include <asm/hw_irq.h>
32 #include <asm/io_apic.h>
35 #include <asm/i8259.h>
36 #include <asm/intel_scu_ipc.h>
37 #include <asm/apb_timer.h>
38 #include <asm/reboot.h>
41 * the clockevent devices on Moorestown/Medfield can be APBT or LAPIC clock,
42 * cmdline option x86_mrst_timer can be used to override the configuration
43 * to prefer one or the other.
44 * at runtime, there are basically three timer configurations:
45 * 1. per cpu apbt clock only
46 * 2. per cpu always-on lapic clocks only, this is Penwell/Medfield only
47 * 3. per cpu lapic clock (C3STOP) and one apbt clock, with broadcast.
49 * by default (without cmdline option), platform code first detects cpu type
50 * to see if we are on lincroft or penwell, then set up both lapic or apbt
52 * i.e. by default, medfield uses configuration #2, moorestown uses #1.
53 * config #3 is supported but not recommended on medfield.
55 * rating and feature summary:
56 * lapic (with C3STOP) --------- 100
57 * apbt (always-on) ------------ 110
58 * lapic (always-on,ARAT) ------ 150
61 __cpuinitdata enum mrst_timer_options mrst_timer_options;
63 static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
64 static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
65 enum mrst_cpu_type __mrst_cpu_chip;
66 EXPORT_SYMBOL_GPL(__mrst_cpu_chip);
70 struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
71 EXPORT_SYMBOL_GPL(sfi_mrtc_array);
74 /* parse all the mtimer info to a static mtimer array */
75 static int __init sfi_parse_mtmr(struct sfi_table_header *table)
77 struct sfi_table_simple *sb;
78 struct sfi_timer_table_entry *pentry;
79 struct mpc_intsrc mp_irq;
82 sb = (struct sfi_table_simple *)table;
83 if (!sfi_mtimer_num) {
84 sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
85 struct sfi_timer_table_entry);
86 pentry = (struct sfi_timer_table_entry *) sb->pentry;
87 totallen = sfi_mtimer_num * sizeof(*pentry);
88 memcpy(sfi_mtimer_array, pentry, totallen);
91 pr_debug("SFI MTIMER info (num = %d):\n", sfi_mtimer_num);
92 pentry = sfi_mtimer_array;
93 for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
94 pr_debug("timer[%d]: paddr = 0x%08x, freq = %dHz,"
95 " irq = %d\n", totallen, (u32)pentry->phys_addr,
96 pentry->freq_hz, pentry->irq);
99 mp_irq.type = MP_IOAPIC;
100 mp_irq.irqtype = mp_INT;
101 /* triggering mode edge bit 2-3, active high polarity bit 0-1 */
104 mp_irq.srcbusirq = pentry->irq; /* IRQ */
105 mp_irq.dstapic = MP_APIC_ALL;
106 mp_irq.dstirq = pentry->irq;
107 mp_save_irq(&mp_irq);
113 struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
116 if (hint < sfi_mtimer_num) {
117 if (!sfi_mtimer_usage[hint]) {
118 pr_debug("hint taken for timer %d irq %d\n",\
119 hint, sfi_mtimer_array[hint].irq);
120 sfi_mtimer_usage[hint] = 1;
121 return &sfi_mtimer_array[hint];
124 /* take the first timer available */
125 for (i = 0; i < sfi_mtimer_num;) {
126 if (!sfi_mtimer_usage[i]) {
127 sfi_mtimer_usage[i] = 1;
128 return &sfi_mtimer_array[i];
135 void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
138 for (i = 0; i < sfi_mtimer_num;) {
139 if (mtmr->irq == sfi_mtimer_array[i].irq) {
140 sfi_mtimer_usage[i] = 0;
147 /* parse all the mrtc info to a global mrtc array */
148 int __init sfi_parse_mrtc(struct sfi_table_header *table)
150 struct sfi_table_simple *sb;
151 struct sfi_rtc_table_entry *pentry;
152 struct mpc_intsrc mp_irq;
156 sb = (struct sfi_table_simple *)table;
158 sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
159 struct sfi_rtc_table_entry);
160 pentry = (struct sfi_rtc_table_entry *)sb->pentry;
161 totallen = sfi_mrtc_num * sizeof(*pentry);
162 memcpy(sfi_mrtc_array, pentry, totallen);
165 pr_debug("SFI RTC info (num = %d):\n", sfi_mrtc_num);
166 pentry = sfi_mrtc_array;
167 for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
168 pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
169 totallen, (u32)pentry->phys_addr, pentry->irq);
170 mp_irq.type = MP_IOAPIC;
171 mp_irq.irqtype = mp_INT;
172 mp_irq.irqflag = 0xf; /* level trigger and active low */
174 mp_irq.srcbusirq = pentry->irq; /* IRQ */
175 mp_irq.dstapic = MP_APIC_ALL;
176 mp_irq.dstirq = pentry->irq;
177 mp_save_irq(&mp_irq);
182 static unsigned long __init mrst_calibrate_tsc(void)
184 unsigned long flags, fast_calibrate;
186 local_irq_save(flags);
187 fast_calibrate = apbt_quick_calibrate();
188 local_irq_restore(flags);
191 return fast_calibrate;
196 void __init mrst_time_init(void)
198 sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
199 switch (mrst_timer_options) {
200 case MRST_TIMER_APBT_ONLY:
202 case MRST_TIMER_LAPIC_APBT:
203 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
204 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
207 if (!boot_cpu_has(X86_FEATURE_ARAT))
209 x86_init.timers.setup_percpu_clockev = setup_boot_APIC_clock;
210 x86_cpuinit.setup_percpu_clockev = setup_secondary_APIC_clock;
213 /* we need at least one APB timer */
214 pre_init_apic_IRQ0();
218 void __cpuinit mrst_arch_setup(void)
220 if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x27)
221 __mrst_cpu_chip = MRST_CPU_CHIP_PENWELL;
222 else if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 0x26)
223 __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
225 pr_err("Unknown Moorestown CPU (%d:%d), default to Lincroft\n",
226 boot_cpu_data.x86, boot_cpu_data.x86_model);
227 __mrst_cpu_chip = MRST_CPU_CHIP_LINCROFT;
229 pr_debug("Moorestown CPU %s identified\n",
230 (__mrst_cpu_chip == MRST_CPU_CHIP_LINCROFT) ?
231 "Lincroft" : "Penwell");
234 /* MID systems don't have i8042 controller */
235 static int mrst_i8042_detect(void)
240 /* Reboot and power off are handled by the SCU on a MID device */
241 static void mrst_power_off(void)
243 intel_scu_ipc_simple_command(0xf1, 1);
246 static void mrst_reboot(void)
248 intel_scu_ipc_simple_command(0xf1, 0);
252 * Moorestown specific x86_init function overrides and early setup
255 void __init x86_mrst_early_setup(void)
257 x86_init.resources.probe_roms = x86_init_noop;
258 x86_init.resources.reserve_resources = x86_init_noop;
260 x86_init.timers.timer_init = mrst_time_init;
261 x86_init.timers.setup_percpu_clockev = x86_init_noop;
263 x86_init.irqs.pre_vector_init = x86_init_noop;
265 x86_init.oem.arch_setup = mrst_arch_setup;
267 x86_cpuinit.setup_percpu_clockev = apbt_setup_secondary_clock;
269 x86_platform.calibrate_tsc = mrst_calibrate_tsc;
270 x86_platform.i8042_detect = mrst_i8042_detect;
271 x86_init.pci.init = pci_mrst_init;
272 x86_init.pci.fixup_irqs = x86_init_noop;
274 legacy_pic = &null_legacy_pic;
276 /* Moorestown specific power_off/restart method */
277 pm_power_off = mrst_power_off;
278 machine_ops.emergency_restart = mrst_reboot;
280 /* Avoid searching for BIOS MP tables */
281 x86_init.mpparse.find_smp_config = x86_init_noop;
282 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
287 * if user does not want to use per CPU apb timer, just give it a lower rating
288 * than local apic timer and skip the late per cpu timer init.
290 static inline int __init setup_x86_mrst_timer(char *arg)
295 if (strcmp("apbt_only", arg) == 0)
296 mrst_timer_options = MRST_TIMER_APBT_ONLY;
297 else if (strcmp("lapic_and_apbt", arg) == 0)
298 mrst_timer_options = MRST_TIMER_LAPIC_APBT;
300 pr_warning("X86 MRST timer option %s not recognised"
301 " use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
307 __setup("x86_mrst_timer=", setup_x86_mrst_timer);
310 * Parsing GPIO table first, since the DEVS table will need this table
311 * to map the pin name to the actual pin.
313 static struct sfi_gpio_table_entry *gpio_table;
314 static int gpio_num_entry;
316 static int __init sfi_parse_gpio(struct sfi_table_header *table)
318 struct sfi_table_simple *sb;
319 struct sfi_gpio_table_entry *pentry;
324 sb = (struct sfi_table_simple *)table;
325 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_gpio_table_entry);
326 pentry = (struct sfi_gpio_table_entry *)sb->pentry;
328 gpio_table = (struct sfi_gpio_table_entry *)
329 kmalloc(num * sizeof(*pentry), GFP_KERNEL);
332 memcpy(gpio_table, pentry, num * sizeof(*pentry));
333 gpio_num_entry = num;
335 pr_debug("GPIO pin info:\n");
336 for (i = 0; i < num; i++, pentry++)
337 pr_debug("info[%2d]: controller = %16.16s, pin_name = %16.16s,"
339 pentry->controller_name,
345 static int get_gpio_by_name(const char *name)
347 struct sfi_gpio_table_entry *pentry = gpio_table;
352 for (i = 0; i < gpio_num_entry; i++, pentry++) {
353 if (!strncmp(name, pentry->pin_name, SFI_NAME_LEN))
354 return pentry->pin_no;
360 * Here defines the array of devices platform data that IAFW would export
361 * through SFI "DEVS" table, we use name and type to match the device and
365 char name[SFI_NAME_LEN + 1];
368 void *(*get_platform_data)(void *info);
371 /* the offset for the mapping of global gpio pin to irq */
372 #define MRST_IRQ_OFFSET 0x100
374 static void __init *pmic_gpio_platform_data(void *info)
376 static struct intel_pmic_gpio_platform_data pmic_gpio_pdata;
377 int gpio_base = get_gpio_by_name("pmic_gpio_base");
381 pmic_gpio_pdata.gpio_base = gpio_base;
382 pmic_gpio_pdata.irq_base = gpio_base + MRST_IRQ_OFFSET;
383 pmic_gpio_pdata.gpiointr = 0xffffeff8;
385 return &pmic_gpio_pdata;
388 static void __init *max3111_platform_data(void *info)
390 struct spi_board_info *spi_info = info;
391 int intr = get_gpio_by_name("max3111_int");
395 spi_info->irq = intr + MRST_IRQ_OFFSET;
399 /* we have multiple max7315 on the board ... */
400 #define MAX7315_NUM 2
401 static void __init *max7315_platform_data(void *info)
403 static struct pca953x_platform_data max7315_pdata[MAX7315_NUM];
405 struct pca953x_platform_data *max7315 = &max7315_pdata[nr];
406 struct i2c_board_info *i2c_info = info;
408 char base_pin_name[SFI_NAME_LEN + 1];
409 char intr_pin_name[SFI_NAME_LEN + 1];
411 if (nr == MAX7315_NUM) {
412 pr_err("too many max7315s, we only support %d\n",
416 /* we have several max7315 on the board, we only need load several
417 * instances of the same pca953x driver to cover them
419 strcpy(i2c_info->type, "max7315");
421 sprintf(base_pin_name, "max7315_%d_base", nr);
422 sprintf(intr_pin_name, "max7315_%d_int", nr);
424 strcpy(base_pin_name, "max7315_base");
425 strcpy(intr_pin_name, "max7315_int");
428 gpio_base = get_gpio_by_name(base_pin_name);
429 intr = get_gpio_by_name(intr_pin_name);
433 max7315->gpio_base = gpio_base;
435 i2c_info->irq = intr + MRST_IRQ_OFFSET;
436 max7315->irq_base = gpio_base + MRST_IRQ_OFFSET;
439 max7315->irq_base = -1;
444 static void __init *emc1403_platform_data(void *info)
446 static short intr2nd_pdata;
447 struct i2c_board_info *i2c_info = info;
448 int intr = get_gpio_by_name("thermal_int");
449 int intr2nd = get_gpio_by_name("thermal_alert");
451 if (intr == -1 || intr2nd == -1)
454 i2c_info->irq = intr + MRST_IRQ_OFFSET;
455 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
457 return &intr2nd_pdata;
460 static void __init *lis331dl_platform_data(void *info)
462 static short intr2nd_pdata;
463 struct i2c_board_info *i2c_info = info;
464 int intr = get_gpio_by_name("accel_int");
465 int intr2nd = get_gpio_by_name("accel_2");
467 if (intr == -1 || intr2nd == -1)
470 i2c_info->irq = intr + MRST_IRQ_OFFSET;
471 intr2nd_pdata = intr2nd + MRST_IRQ_OFFSET;
473 return &intr2nd_pdata;
476 static void __init *no_platform_data(void *info)
481 static const struct devs_id __initconst device_ids[] = {
482 {"pmic_gpio", SFI_DEV_TYPE_SPI, 1, &pmic_gpio_platform_data},
483 {"spi_max3111", SFI_DEV_TYPE_SPI, 0, &max3111_platform_data},
484 {"i2c_max7315", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
485 {"i2c_max7315_2", SFI_DEV_TYPE_I2C, 1, &max7315_platform_data},
486 {"emc1403", SFI_DEV_TYPE_I2C, 1, &emc1403_platform_data},
487 {"i2c_accel", SFI_DEV_TYPE_I2C, 0, &lis331dl_platform_data},
488 {"pmic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
489 {"msic_audio", SFI_DEV_TYPE_IPC, 1, &no_platform_data},
493 #define MAX_IPCDEVS 24
494 static struct platform_device *ipc_devs[MAX_IPCDEVS];
495 static int ipc_next_dev;
497 #define MAX_SCU_SPI 24
498 static struct spi_board_info *spi_devs[MAX_SCU_SPI];
499 static int spi_next_dev;
501 #define MAX_SCU_I2C 24
502 static struct i2c_board_info *i2c_devs[MAX_SCU_I2C];
503 static int i2c_bus[MAX_SCU_I2C];
504 static int i2c_next_dev;
506 static void __init intel_scu_device_register(struct platform_device *pdev)
508 if(ipc_next_dev == MAX_IPCDEVS)
509 pr_err("too many SCU IPC devices");
511 ipc_devs[ipc_next_dev++] = pdev;
514 static void __init intel_scu_spi_device_register(struct spi_board_info *sdev)
516 struct spi_board_info *new_dev;
518 if (spi_next_dev == MAX_SCU_SPI) {
519 pr_err("too many SCU SPI devices");
523 new_dev = kzalloc(sizeof(*sdev), GFP_KERNEL);
525 pr_err("failed to alloc mem for delayed spi dev %s\n",
529 memcpy(new_dev, sdev, sizeof(*sdev));
531 spi_devs[spi_next_dev++] = new_dev;
534 static void __init intel_scu_i2c_device_register(int bus,
535 struct i2c_board_info *idev)
537 struct i2c_board_info *new_dev;
539 if (i2c_next_dev == MAX_SCU_I2C) {
540 pr_err("too many SCU I2C devices");
544 new_dev = kzalloc(sizeof(*idev), GFP_KERNEL);
546 pr_err("failed to alloc mem for delayed i2c dev %s\n",
550 memcpy(new_dev, idev, sizeof(*idev));
552 i2c_bus[i2c_next_dev] = bus;
553 i2c_devs[i2c_next_dev++] = new_dev;
556 /* Called by IPC driver */
557 void intel_scu_devices_create(void)
561 for (i = 0; i < ipc_next_dev; i++)
562 platform_device_add(ipc_devs[i]);
564 for (i = 0; i < spi_next_dev; i++)
565 spi_register_board_info(spi_devs[i], 1);
567 for (i = 0; i < i2c_next_dev; i++) {
568 struct i2c_adapter *adapter;
569 struct i2c_client *client;
571 adapter = i2c_get_adapter(i2c_bus[i]);
573 client = i2c_new_device(adapter, i2c_devs[i]);
575 pr_err("can't create i2c device %s\n",
578 i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
581 EXPORT_SYMBOL_GPL(intel_scu_devices_create);
583 /* Called by IPC driver */
584 void intel_scu_devices_destroy(void)
588 for (i = 0; i < ipc_next_dev; i++)
589 platform_device_del(ipc_devs[i]);
591 EXPORT_SYMBOL_GPL(intel_scu_devices_destroy);
593 static void __init install_irq_resource(struct platform_device *pdev, int irq)
595 /* Single threaded */
596 static struct resource __initdata res = {
598 .flags = IORESOURCE_IRQ,
601 platform_device_add_resources(pdev, &res, 1);
604 static void __init sfi_handle_ipc_dev(struct platform_device *pdev)
606 const struct devs_id *dev = device_ids;
609 while (dev->name[0]) {
610 if (dev->type == SFI_DEV_TYPE_IPC &&
611 !strncmp(dev->name, pdev->name, SFI_NAME_LEN)) {
612 pdata = dev->get_platform_data(pdev);
617 pdev->dev.platform_data = pdata;
618 intel_scu_device_register(pdev);
621 static void __init sfi_handle_spi_dev(struct spi_board_info *spi_info)
623 const struct devs_id *dev = device_ids;
626 while (dev->name[0]) {
627 if (dev->type == SFI_DEV_TYPE_SPI &&
628 !strncmp(dev->name, spi_info->modalias, SFI_NAME_LEN)) {
629 pdata = dev->get_platform_data(spi_info);
634 spi_info->platform_data = pdata;
636 intel_scu_spi_device_register(spi_info);
638 spi_register_board_info(spi_info, 1);
641 static void __init sfi_handle_i2c_dev(int bus, struct i2c_board_info *i2c_info)
643 const struct devs_id *dev = device_ids;
646 while (dev->name[0]) {
647 if (dev->type == SFI_DEV_TYPE_I2C &&
648 !strncmp(dev->name, i2c_info->type, SFI_NAME_LEN)) {
649 pdata = dev->get_platform_data(i2c_info);
654 i2c_info->platform_data = pdata;
657 intel_scu_i2c_device_register(bus, i2c_info);
659 i2c_register_board_info(bus, i2c_info, 1);
663 static int __init sfi_parse_devs(struct sfi_table_header *table)
665 struct sfi_table_simple *sb;
666 struct sfi_device_table_entry *pentry;
667 struct spi_board_info spi_info;
668 struct i2c_board_info i2c_info;
669 struct platform_device *pdev;
672 struct io_apic_irq_attr irq_attr;
674 sb = (struct sfi_table_simple *)table;
675 num = SFI_GET_NUM_ENTRIES(sb, struct sfi_device_table_entry);
676 pentry = (struct sfi_device_table_entry *)sb->pentry;
678 for (i = 0; i < num; i++, pentry++) {
679 if (pentry->irq != (u8)0xff) { /* native RTE case */
680 /* these SPI2 devices are not exposed to system as PCI
681 * devices, but they have separate RTE entry in IOAPIC
682 * so we have to enable them one by one here
684 ioapic = mp_find_ioapic(pentry->irq);
685 irq_attr.ioapic = ioapic;
686 irq_attr.ioapic_pin = pentry->irq;
687 irq_attr.trigger = 1;
688 irq_attr.polarity = 1;
689 io_apic_set_pci_routing(NULL, pentry->irq, &irq_attr);
691 switch (pentry->type) {
692 case SFI_DEV_TYPE_IPC:
693 /* ID as IRQ is a hack that will go away */
694 pdev = platform_device_alloc(pentry->name, pentry->irq);
696 pr_err("out of memory for SFI platform device '%s'.\n",
700 install_irq_resource(pdev, pentry->irq);
701 pr_debug("info[%2d]: IPC bus, name = %16.16s, "
702 "irq = 0x%2x\n", i, pentry->name, pentry->irq);
703 sfi_handle_ipc_dev(pdev);
705 case SFI_DEV_TYPE_SPI:
706 memset(&spi_info, 0, sizeof(spi_info));
707 strncpy(spi_info.modalias, pentry->name, SFI_NAME_LEN);
708 spi_info.irq = pentry->irq;
709 spi_info.bus_num = pentry->host_num;
710 spi_info.chip_select = pentry->addr;
711 spi_info.max_speed_hz = pentry->max_freq;
712 pr_debug("info[%2d]: SPI bus = %d, name = %16.16s, "
713 "irq = 0x%2x, max_freq = %d, cs = %d\n", i,
717 spi_info.max_speed_hz,
718 spi_info.chip_select);
719 sfi_handle_spi_dev(&spi_info);
721 case SFI_DEV_TYPE_I2C:
722 memset(&i2c_info, 0, sizeof(i2c_info));
723 bus = pentry->host_num;
724 strncpy(i2c_info.type, pentry->name, SFI_NAME_LEN);
725 i2c_info.irq = pentry->irq;
726 i2c_info.addr = pentry->addr;
727 pr_debug("info[%2d]: I2C bus = %d, name = %16.16s, "
728 "irq = 0x%2x, addr = 0x%x\n", i, bus,
732 sfi_handle_i2c_dev(bus, &i2c_info);
734 case SFI_DEV_TYPE_UART:
735 case SFI_DEV_TYPE_HSI:
743 static int __init mrst_platform_init(void)
745 sfi_table_parse(SFI_SIG_GPIO, NULL, NULL, sfi_parse_gpio);
746 sfi_table_parse(SFI_SIG_DEVS, NULL, NULL, sfi_parse_devs);
749 arch_initcall(mrst_platform_init);
752 * we will search these buttons in SFI GPIO table (by name)
753 * and register them dynamically. Please add all possible
754 * buttons here, we will shrink them if no GPIO found.
756 static struct gpio_keys_button gpio_button[] = {
757 {KEY_POWER, -1, 1, "power_btn", EV_KEY, 0, 3000},
758 {KEY_PROG1, -1, 1, "prog_btn1", EV_KEY, 0, 20},
759 {KEY_PROG2, -1, 1, "prog_btn2", EV_KEY, 0, 20},
760 {SW_LID, -1, 1, "lid_switch", EV_SW, 0, 20},
761 {KEY_VOLUMEUP, -1, 1, "vol_up", EV_KEY, 0, 20},
762 {KEY_VOLUMEDOWN, -1, 1, "vol_down", EV_KEY, 0, 20},
763 {KEY_CAMERA, -1, 1, "camera_full", EV_KEY, 0, 20},
764 {KEY_CAMERA_FOCUS, -1, 1, "camera_half", EV_KEY, 0, 20},
765 {SW_KEYPAD_SLIDE, -1, 1, "MagSw1", EV_SW, 0, 20},
766 {SW_KEYPAD_SLIDE, -1, 1, "MagSw2", EV_SW, 0, 20},
769 static struct gpio_keys_platform_data mrst_gpio_keys = {
770 .buttons = gpio_button,
772 .nbuttons = -1, /* will fill it after search */
775 static struct platform_device pb_device = {
779 .platform_data = &mrst_gpio_keys,
784 * Shrink the non-existent buttons, register the gpio button
785 * device if there is some
787 static int __init pb_keys_init(void)
789 struct gpio_keys_button *gb = gpio_button;
790 int i, num, good = 0;
792 num = sizeof(gpio_button) / sizeof(struct gpio_keys_button);
793 for (i = 0; i < num; i++) {
794 gb[i].gpio = get_gpio_by_name(gb[i].desc);
795 if (gb[i].gpio == -1)
804 mrst_gpio_keys.nbuttons = good;
805 return platform_device_register(&pb_device);
809 late_initcall(pb_keys_init);