arch/x86/oprofile/nmi_int.c

   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002-2009 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  * @author Robert Richter <robert.richter@amd.com>
   9  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  10  * @author Jason Yeh <jason.yeh@amd.com>
  11  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/notifier.h>
  16 #include <linux/smp.h>
  17 #include <linux/oprofile.h>
  18 #include <linux/syscore_ops.h>
  19 #include <linux/slab.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/cpu.h>
  23 #include <asm/nmi.h>
  24 #include <asm/msr.h>
  25 #include <asm/apic.h>
  26
  27 #include "op_counter.h"
  28 #include "op_x86_model.h"
  29
  30 static struct op_x86_model_spec *model;
  31 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
  32 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
  33
  34 /* must be protected with get_online_cpus()/put_online_cpus(): */
  35 static int nmi_enabled;
  36 static int ctr_running;
  37
  38 struct op_counter_config counter_config[OP_MAX_COUNTER];
  39
  40 /* common functions */
  41
  42 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
  43                     struct op_counter_config *counter_config)
  44 {
  45         u64 val = 0;
  46         u16 event = (u16)counter_config->event;
  47
  48         val |= ARCH_PERFMON_EVENTSEL_INT;
  49         val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
  50         val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
  51         val |= (counter_config->unit_mask & 0xFF) << 8;
  52         counter_config->extra &= (ARCH_PERFMON_EVENTSEL_INV |
  53                                   ARCH_PERFMON_EVENTSEL_EDGE |
  54                                   ARCH_PERFMON_EVENTSEL_CMASK);
  55         val |= counter_config->extra;
  56         event &= model->event_mask ? model->event_mask : 0xFF;
  57         val |= event & 0xFF;
  58         val |= (event & 0x0F00) << 24;
  59
  60         return val;
  61 }
  62
  63
  64 static int profile_exceptions_notify(struct notifier_block *self,
  65                                      unsigned long val, void *data)
  66 {
  67         struct die_args *args = (struct die_args *)data;
  68         int ret = NOTIFY_DONE;
  69
  70         switch (val) {
  71         case DIE_NMI:
  72                 if (ctr_running)
  73                         model->check_ctrs(args->regs, &__get_cpu_var(cpu_msrs));
  74                 else if (!nmi_enabled)
  75                         break;
  76                 else
  77                         model->stop(&__get_cpu_var(cpu_msrs));
  78                 ret = NOTIFY_STOP;
  79                 break;
  80         default:
  81                 break;
  82         }
  83         return ret;
  84 }
  85
  86 static void nmi_cpu_save_registers(struct op_msrs *msrs)
  87 {
  88         struct op_msr *counters = msrs->counters;
  89         struct op_msr *controls = msrs->controls;
  90         unsigned int i;
  91
  92         for (i = 0; i < model->num_counters; ++i) {
  93                 if (counters[i].addr)
  94                         rdmsrl(counters[i].addr, counters[i].saved);
  95         }
  96
  97         for (i = 0; i < model->num_controls; ++i) {
  98                 if (controls[i].addr)
  99                         rdmsrl(controls[i].addr, controls[i].saved);
 100         }
 101 }
 102
 103 static void nmi_cpu_start(void *dummy)
 104 {
 105         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 106         if (!msrs->controls)
 107                 WARN_ON_ONCE(1);
 108         else
 109                 model->start(msrs);
 110 }
 111
 112 static int nmi_start(void)
 113 {
 114         get_online_cpus();
 115         on_each_cpu(nmi_cpu_start, NULL, 1);
 116         ctr_running = 1;
 117         put_online_cpus();
 118         return 0;
 119 }
 120
 121 static void nmi_cpu_stop(void *dummy)
 122 {
 123         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 124         if (!msrs->controls)
 125                 WARN_ON_ONCE(1);
 126         else
 127                 model->stop(msrs);
 128 }
 129
 130 static void nmi_stop(void)
 131 {
 132         get_online_cpus();
 133         on_each_cpu(nmi_cpu_stop, NULL, 1);
 134         ctr_running = 0;
 135         put_online_cpus();
 136 }
 137
 138 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 139
 140 static DEFINE_PER_CPU(int, switch_index);
 141
 142 static inline int has_mux(void)
 143 {
 144         return !!model->switch_ctrl;
 145 }
 146
 147 inline int op_x86_phys_to_virt(int phys)
 148 {
 149         return __this_cpu_read(switch_index) + phys;
 150 }
 151
 152 inline int op_x86_virt_to_phys(int virt)
 153 {
 154         return virt % model->num_counters;
 155 }
 156
 157 static void nmi_shutdown_mux(void)
 158 {
 159         int i;
 160
 161         if (!has_mux())
 162                 return;
 163
 164         for_each_possible_cpu(i) {
 165                 kfree(per_cpu(cpu_msrs, i).multiplex);
 166                 per_cpu(cpu_msrs, i).multiplex = NULL;
 167                 per_cpu(switch_index, i) = 0;
 168         }
 169 }
 170
 171 static int nmi_setup_mux(void)
 172 {
 173         size_t multiplex_size =
 174                 sizeof(struct op_msr) * model->num_virt_counters;
 175         int i;
 176
 177         if (!has_mux())
 178                 return 1;
 179
 180         for_each_possible_cpu(i) {
 181                 per_cpu(cpu_msrs, i).multiplex =
 182                         kzalloc(multiplex_size, GFP_KERNEL);
 183                 if (!per_cpu(cpu_msrs, i).multiplex)
 184                         return 0;
 185         }
 186
 187         return 1;
 188 }
 189
 190 static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
 191 {
 192         int i;
 193         struct op_msr *multiplex = msrs->multiplex;
 194
 195         if (!has_mux())
 196                 return;
 197
 198         for (i = 0; i < model->num_virt_counters; ++i) {
 199                 if (counter_config[i].enabled) {
 200                         multiplex[i].saved = -(u64)counter_config[i].count;
 201                 } else {
 202                         multiplex[i].saved = 0;
 203                 }
 204         }
 205
 206         per_cpu(switch_index, cpu) = 0;
 207 }
 208
 209 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
 210 {
 211         struct op_msr *counters = msrs->counters;
 212         struct op_msr *multiplex = msrs->multiplex;
 213         int i;
 214
 215         for (i = 0; i < model->num_counters; ++i) {
 216                 int virt = op_x86_phys_to_virt(i);
 217                 if (counters[i].addr)
 218                         rdmsrl(counters[i].addr, multiplex[virt].saved);
 219         }
 220 }
 221
 222 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
 223 {
 224         struct op_msr *counters = msrs->counters;
 225         struct op_msr *multiplex = msrs->multiplex;
 226         int i;
 227
 228         for (i = 0; i < model->num_counters; ++i) {
 229                 int virt = op_x86_phys_to_virt(i);
 230                 if (counters[i].addr)
 231                         wrmsrl(counters[i].addr, multiplex[virt].saved);
 232         }
 233 }
 234
 235 static void nmi_cpu_switch(void *dummy)
 236 {
 237         int cpu = smp_processor_id();
 238         int si = per_cpu(switch_index, cpu);
 239         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 240
 241         nmi_cpu_stop(NULL);
 242         nmi_cpu_save_mpx_registers(msrs);
 243
 244         /* move to next set */
 245         si += model->num_counters;
 246         if ((si >= model->num_virt_counters) || (counter_config[si].count == 0))
 247                 per_cpu(switch_index, cpu) = 0;
 248         else
 249                 per_cpu(switch_index, cpu) = si;
 250
 251         model->switch_ctrl(model, msrs);
 252         nmi_cpu_restore_mpx_registers(msrs);
 253
 254         nmi_cpu_start(NULL);
 255 }
 256
 257
 258 /*
 259  * Quick check to see if multiplexing is necessary.
 260  * The check should be sufficient since counters are used
 261  * in ordre.
 262  */
 263 static int nmi_multiplex_on(void)
 264 {
 265         return counter_config[model->num_counters].count ? 0 : -EINVAL;
 266 }
 267
 268 static int nmi_switch_event(void)
 269 {
 270         if (!has_mux())
 271                 return -ENOSYS;         /* not implemented */
 272         if (nmi_multiplex_on() < 0)
 273                 return -EINVAL;         /* not necessary */
 274
 275         get_online_cpus();
 276         if (ctr_running)
 277                 on_each_cpu(nmi_cpu_switch, NULL, 1);
 278         put_online_cpus();
 279
 280         return 0;
 281 }
 282
 283 static inline void mux_init(struct oprofile_operations *ops)
 284 {
 285         if (has_mux())
 286                 ops->switch_events = nmi_switch_event;
 287 }
 288
 289 static void mux_clone(int cpu)
 290 {
 291         if (!has_mux())
 292                 return;
 293
 294         memcpy(per_cpu(cpu_msrs, cpu).multiplex,
 295                per_cpu(cpu_msrs, 0).multiplex,
 296                sizeof(struct op_msr) * model->num_virt_counters);
 297 }
 298
 299 #else
 300
 301 inline int op_x86_phys_to_virt(int phys) { return phys; }
 302 inline int op_x86_virt_to_phys(int virt) { return virt; }
 303 static inline void nmi_shutdown_mux(void) { }
 304 static inline int nmi_setup_mux(void) { return 1; }
 305 static inline void
 306 nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
 307 static inline void mux_init(struct oprofile_operations *ops) { }
 308 static void mux_clone(int cpu) { }
 309
 310 #endif
 311
 312 static void free_msrs(void)
 313 {
 314         int i;
 315         for_each_possible_cpu(i) {
 316                 kfree(per_cpu(cpu_msrs, i).counters);
 317                 per_cpu(cpu_msrs, i).counters = NULL;
 318                 kfree(per_cpu(cpu_msrs, i).controls);
 319                 per_cpu(cpu_msrs, i).controls = NULL;
 320         }
 321         nmi_shutdown_mux();
 322 }
 323
 324 static int allocate_msrs(void)
 325 {
 326         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 327         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 328
 329         int i;
 330         for_each_possible_cpu(i) {
 331                 per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
 332                                                         GFP_KERNEL);
 333                 if (!per_cpu(cpu_msrs, i).counters)
 334                         goto fail;
 335                 per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
 336                                                         GFP_KERNEL);
 337                 if (!per_cpu(cpu_msrs, i).controls)
 338                         goto fail;
 339         }
 340
 341         if (!nmi_setup_mux())
 342                 goto fail;
 343
 344         return 1;
 345
 346 fail:
 347         free_msrs();
 348         return 0;
 349 }
 350
 351 static void nmi_cpu_setup(void *dummy)
 352 {
 353         int cpu = smp_processor_id();
 354         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 355         nmi_cpu_save_registers(msrs);
 356         spin_lock(&oprofilefs_lock);
 357         model->setup_ctrs(model, msrs);
 358         nmi_cpu_setup_mux(cpu, msrs);
 359         spin_unlock(&oprofilefs_lock);
 360         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
 361         apic_write(APIC_LVTPC, APIC_DM_NMI);
 362 }
 363
 364 static struct notifier_block profile_exceptions_nb = {
 365         .notifier_call = profile_exceptions_notify,
 366         .next = NULL,
 367         .priority = NMI_LOCAL_LOW_PRIOR,
 368 };
 369
 370 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
 371 {
 372         struct op_msr *counters = msrs->counters;
 373         struct op_msr *controls = msrs->controls;
 374         unsigned int i;
 375
 376         for (i = 0; i < model->num_controls; ++i) {
 377                 if (controls[i].addr)
 378                         wrmsrl(controls[i].addr, controls[i].saved);
 379         }
 380
 381         for (i = 0; i < model->num_counters; ++i) {
 382                 if (counters[i].addr)
 383                         wrmsrl(counters[i].addr, counters[i].saved);
 384         }
 385 }
 386
 387 static void nmi_cpu_shutdown(void *dummy)
 388 {
 389         unsigned int v;
 390         int cpu = smp_processor_id();
 391         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 392
 393         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 394          * mode and vector nr combination can be illegal. That's by design: on
 395          * power on apic lvt contain a zero vector nr which are legal only for
 396          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 397          */
 398         v = apic_read(APIC_LVTERR);
 399         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 400         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
 401         apic_write(APIC_LVTERR, v);
 402         nmi_cpu_restore_registers(msrs);
 403         if (model->cpu_down)
 404                 model->cpu_down();
 405 }
 406
 407 static void nmi_cpu_up(void *dummy)
 408 {
 409         if (nmi_enabled)
 410                 nmi_cpu_setup(dummy);
 411         if (ctr_running)
 412                 nmi_cpu_start(dummy);
 413 }
 414
 415 static void nmi_cpu_down(void *dummy)
 416 {
 417         if (ctr_running)
 418                 nmi_cpu_stop(dummy);
 419         if (nmi_enabled)
 420                 nmi_cpu_shutdown(dummy);
 421 }
 422
 423 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 424 {
 425         unsigned int i;
 426
 427         for (i = 0; i < model->num_virt_counters; ++i) {
 428                 struct dentry *dir;
 429                 char buf[4];
 430
 431                 /* quick little hack to _not_ expose a counter if it is not
 432                  * available for use.  This should protect userspace app.
 433                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 434                  *        sequentially in their struct assignment).
 435                  */
 436                 if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i)))
 437                         continue;
 438
 439                 snprintf(buf,  sizeof(buf), "%d", i);
 440                 dir = oprofilefs_mkdir(sb, root, buf);
 441                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 442                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 443                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 444                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 445                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 446                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 447                 oprofilefs_create_ulong(sb, dir, "extra", &counter_config[i].extra);
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
 454                                  void *data)
 455 {
 456         int cpu = (unsigned long)data;
 457         switch (action) {
 458         case CPU_DOWN_FAILED:
 459         case CPU_ONLINE:
 460                 smp_call_function_single(cpu, nmi_cpu_up, NULL, 0);
 461                 break;
 462         case CPU_DOWN_PREPARE:
 463                 smp_call_function_single(cpu, nmi_cpu_down, NULL, 1);
 464                 break;
 465         }
 466         return NOTIFY_DONE;
 467 }
 468
 469 static struct notifier_block oprofile_cpu_nb = {
 470         .notifier_call = oprofile_cpu_notifier
 471 };
 472
 473 static int nmi_setup(void)
 474 {
 475         int err = 0;
 476         int cpu;
 477
 478         if (!allocate_msrs())
 479                 return -ENOMEM;
 480
 481         /* We need to serialize save and setup for HT because the subset
 482          * of msrs are distinct for save and setup operations
 483          */
 484
 485         /* Assume saved/restored counters are the same on all CPUs */
 486         err = model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
 487         if (err)
 488                 goto fail;
 489
 490         for_each_possible_cpu(cpu) {
 491                 if (!cpu)
 492                         continue;
 493
 494                 memcpy(per_cpu(cpu_msrs, cpu).counters,
 495                        per_cpu(cpu_msrs, 0).counters,
 496                        sizeof(struct op_msr) * model->num_counters);
 497
 498                 memcpy(per_cpu(cpu_msrs, cpu).controls,
 499                        per_cpu(cpu_msrs, 0).controls,
 500                        sizeof(struct op_msr) * model->num_controls);
 501
 502                 mux_clone(cpu);
 503         }
 504
 505         nmi_enabled = 0;
 506         ctr_running = 0;
 507         barrier();
 508         err = register_die_notifier(&profile_exceptions_nb);
 509         if (err)
 510                 goto fail;
 511
 512         get_online_cpus();
 513         register_cpu_notifier(&oprofile_cpu_nb);
 514         on_each_cpu(nmi_cpu_setup, NULL, 1);
 515         nmi_enabled = 1;
 516         put_online_cpus();
 517
 518         return 0;
 519 fail:
 520         free_msrs();
 521         return err;
 522 }
 523
 524 static void nmi_shutdown(void)
 525 {
 526         struct op_msrs *msrs;
 527
 528         get_online_cpus();
 529         unregister_cpu_notifier(&oprofile_cpu_nb);
 530         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
 531         nmi_enabled = 0;
 532         ctr_running = 0;
 533         put_online_cpus();
 534         barrier();
 535         unregister_die_notifier(&profile_exceptions_nb);
 536         msrs = &get_cpu_var(cpu_msrs);
 537         model->shutdown(msrs);
 538         free_msrs();
 539         put_cpu_var(cpu_msrs);
 540 }
 541
 542 #ifdef CONFIG_PM
 543
 544 static int nmi_suspend(void)
 545 {
 546         /* Only one CPU left, just stop that one */
 547         if (nmi_enabled == 1)
 548                 nmi_cpu_stop(NULL);
 549         return 0;
 550 }
 551
 552 static void nmi_resume(void)
 553 {
 554         if (nmi_enabled == 1)
 555                 nmi_cpu_start(NULL);
 556 }
 557
 558 static struct syscore_ops oprofile_syscore_ops = {
 559         .resume         = nmi_resume,
 560         .suspend        = nmi_suspend,
 561 };
 562
 563 static void __init init_suspend_resume(void)
 564 {
 565         register_syscore_ops(&oprofile_syscore_ops);
 566 }
 567
 568 static void exit_suspend_resume(void)
 569 {
 570         unregister_syscore_ops(&oprofile_syscore_ops);
 571 }
 572
 573 #else
 574
 575 static inline void init_suspend_resume(void) { }
 576 static inline void exit_suspend_resume(void) { }
 577
 578 #endif /* CONFIG_PM */
 579
 580 static int __init p4_init(char **cpu_type)
 581 {
 582         __u8 cpu_model = boot_cpu_data.x86_model;
 583
 584         if (cpu_model > 6 || cpu_model == 5)
 585                 return 0;
 586
 587 #ifndef CONFIG_SMP
 588         *cpu_type = "i386/p4";
 589         model = &op_p4_spec;
 590         return 1;
 591 #else
 592         switch (smp_num_siblings) {
 593         case 1:
 594                 *cpu_type = "i386/p4";
 595                 model = &op_p4_spec;
 596                 return 1;
 597
 598         case 2:
 599                 *cpu_type = "i386/p4-ht";
 600                 model = &op_p4_ht2_spec;
 601                 return 1;
 602         }
 603 #endif
 604
 605         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 606         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 607         return 0;
 608 }
 609
 610 static int force_arch_perfmon;
 611 static int force_cpu_type(const char *str, struct kernel_param *kp)
 612 {
 613         if (!strcmp(str, "arch_perfmon")) {
 614                 force_arch_perfmon = 1;
 615                 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
 616         }
 617
 618         return 0;
 619 }
 620 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
 621
 622 static int __init ppro_init(char **cpu_type)
 623 {
 624         __u8 cpu_model = boot_cpu_data.x86_model;
 625         struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
 626
 627         if (force_arch_perfmon && cpu_has_arch_perfmon)
 628                 return 0;
 629
 630         /*
 631          * Documentation on identifying Intel processors by CPU family
 632          * and model can be found in the Intel Software Developer's
 633          * Manuals (SDM):
 634          *
 635          *  http://www.intel.com/products/processor/manuals/
 636          *
 637          * As of May 2010 the documentation for this was in the:
 638          * "Intel 64 and IA-32 Architectures Software Developer's
 639          * Manual Volume 3B: System Programming Guide", "Table B-1
 640          * CPUID Signature Values of DisplayFamily_DisplayModel".
 641          */
 642         switch (cpu_model) {
 643         case 0 ... 2:
 644                 *cpu_type = "i386/ppro";
 645                 break;
 646         case 3 ... 5:
 647                 *cpu_type = "i386/pii";
 648                 break;
 649         case 6 ... 8:
 650         case 10 ... 11:
 651                 *cpu_type = "i386/piii";
 652                 break;
 653         case 9:
 654         case 13:
 655                 *cpu_type = "i386/p6_mobile";
 656                 break;
 657         case 14:
 658                 *cpu_type = "i386/core";
 659                 break;
 660         case 0x0f:
 661         case 0x16:
 662         case 0x17:
 663         case 0x1d:
 664                 *cpu_type = "i386/core_2";
 665                 break;
 666         case 0x1a:
 667         case 0x1e:
 668         case 0x2e:
 669                 spec = &op_arch_perfmon_spec;
 670                 *cpu_type = "i386/core_i7";
 671                 break;
 672         case 0x1c:
 673                 *cpu_type = "i386/atom";
 674                 break;
 675         default:
 676                 /* Unknown */
 677                 return 0;
 678         }
 679
 680         model = spec;
 681         return 1;
 682 }
 683
 684 int __init op_nmi_init(struct oprofile_operations *ops)
 685 {
 686         __u8 vendor = boot_cpu_data.x86_vendor;
 687         __u8 family = boot_cpu_data.x86;
 688         char *cpu_type = NULL;
 689         int ret = 0;
 690
 691         if (!cpu_has_apic)
 692                 return -ENODEV;
 693
 694         switch (vendor) {
 695         case X86_VENDOR_AMD:
 696                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 697
 698                 switch (family) {
 699                 case 6:
 700                         cpu_type = "i386/athlon";
 701                         break;
 702                 case 0xf:
 703                         /*
 704                          * Actually it could be i386/hammer too, but
 705                          * give user space an consistent name.
 706                          */
 707                         cpu_type = "x86-64/hammer";
 708                         break;
 709                 case 0x10:
 710                         cpu_type = "x86-64/family10";
 711                         break;
 712                 case 0x11:
 713                         cpu_type = "x86-64/family11h";
 714                         break;
 715                 case 0x12:
 716                         cpu_type = "x86-64/family12h";
 717                         break;
 718                 case 0x14:
 719                         cpu_type = "x86-64/family14h";
 720                         break;
 721                 case 0x15:
 722                         cpu_type = "x86-64/family15h";
 723                         break;
 724                 default:
 725                         return -ENODEV;
 726                 }
 727                 model = &op_amd_spec;
 728                 break;
 729
 730         case X86_VENDOR_INTEL:
 731                 switch (family) {
 732                         /* Pentium IV */
 733                 case 0xf:
 734                         p4_init(&cpu_type);
 735                         break;
 736
 737                         /* A P6-class processor */
 738                 case 6:
 739                         ppro_init(&cpu_type);
 740                         break;
 741
 742                 default:
 743                         break;
 744                 }
 745
 746                 if (cpu_type)
 747                         break;
 748
 749                 if (!cpu_has_arch_perfmon)
 750                         return -ENODEV;
 751
 752                 /* use arch perfmon as fallback */
 753                 cpu_type = "i386/arch_perfmon";
 754                 model = &op_arch_perfmon_spec;
 755                 break;
 756
 757         default:
 758                 return -ENODEV;
 759         }
 760
 761         /* default values, can be overwritten by model */
 762         ops->create_files       = nmi_create_files;
 763         ops->setup              = nmi_setup;
 764         ops->shutdown           = nmi_shutdown;
 765         ops->start              = nmi_start;
 766         ops->stop               = nmi_stop;
 767         ops->cpu_type           = cpu_type;
 768
 769         if (model->init)
 770                 ret = model->init(ops);
 771         if (ret)
 772                 return ret;
 773
 774         if (!model->num_virt_counters)
 775                 model->num_virt_counters = model->num_counters;
 776
 777         mux_init(ops);
 778
 779         init_suspend_resume();
 780
 781         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 782         return 0;
 783 }
 784
 785 void op_nmi_exit(void)
 786 {
 787         exit_suspend_resume();
 788 }