arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42
  43 #include "trace.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46 #define __ex_clear(x, reg) \
  47         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  48
  49 MODULE_AUTHOR("Qumranet");
  50 MODULE_LICENSE("GPL");
  51
  52 static int __read_mostly enable_vpid = 1;
  53 module_param_named(vpid, enable_vpid, bool, 0444);
  54
  55 static int __read_mostly flexpriority_enabled = 1;
  56 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  57
  58 static int __read_mostly enable_ept = 1;
  59 module_param_named(ept, enable_ept, bool, S_IRUGO);
  60
  61 static int __read_mostly enable_unrestricted_guest = 1;
  62 module_param_named(unrestricted_guest,
  63                         enable_unrestricted_guest, bool, S_IRUGO);
  64
  65 static int __read_mostly emulate_invalid_guest_state = 0;
  66 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  67
  68 static int __read_mostly vmm_exclusive = 1;
  69 module_param(vmm_exclusive, bool, S_IRUGO);
  70
  71 static int __read_mostly yield_on_hlt = 1;
  72 module_param(yield_on_hlt, bool, S_IRUGO);
  73
  74 static int __read_mostly fasteoi = 1;
  75 module_param(fasteoi, bool, S_IRUGO);
  76
  77 /*
  78  * If nested=1, nested virtualization is supported, i.e., guests may use
  79  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  80  * use VMX instructions.
  81  */
  82 static int __read_mostly nested = 0;
  83 module_param(nested, bool, S_IRUGO);
  84
  85 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  86         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  87 #define KVM_GUEST_CR0_MASK                                              \
  88         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  89 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  90         (X86_CR0_WP | X86_CR0_NE)
  91 #define KVM_VM_CR0_ALWAYS_ON                                            \
  92         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  93 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  94         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  95          | X86_CR4_OSXMMEXCPT)
  96
  97 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  98 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  99
 100 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 101
 102 /*
 103  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 104  * ple_gap:    upper bound on the amount of time between two successive
 105  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 106  *             According to test, this time is usually smaller than 128 cycles.
 107  * ple_window: upper bound on the amount of time a guest is allowed to execute
 108  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 109  *             less than 2^12 cycles
 110  * Time is measured based on a counter that runs at the same rate as the TSC,
 111  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 112  */
 113 #define KVM_VMX_DEFAULT_PLE_GAP    128
 114 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 115 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 116 module_param(ple_gap, int, S_IRUGO);
 117
 118 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 119 module_param(ple_window, int, S_IRUGO);
 120
 121 #define NR_AUTOLOAD_MSRS 1
 122 #define VMCS02_POOL_SIZE 1
 123
 124 struct vmcs {
 125         u32 revision_id;
 126         u32 abort;
 127         char data[0];
 128 };
 129
 130 /*
 131  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 132  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 133  * loaded on this CPU (so we can clear them if the CPU goes down).
 134  */
 135 struct loaded_vmcs {
 136         struct vmcs *vmcs;
 137         int cpu;
 138         int launched;
 139         struct list_head loaded_vmcss_on_cpu_link;
 140 };
 141
 142 struct shared_msr_entry {
 143         unsigned index;
 144         u64 data;
 145         u64 mask;
 146 };
 147
 148 /*
 149  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 150  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 151  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 152  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 153  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 154  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 155  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 156  * underlying hardware which will be used to run L2.
 157  * This structure is packed to ensure that its layout is identical across
 158  * machines (necessary for live migration).
 159  * If there are changes in this struct, VMCS12_REVISION must be changed.
 160  */
 161 typedef u64 natural_width;
 162 struct __packed vmcs12 {
 163         /* According to the Intel spec, a VMCS region must start with the
 164          * following two fields. Then follow implementation-specific data.
 165          */
 166         u32 revision_id;
 167         u32 abort;
 168
 169         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 170         u32 padding[7]; /* room for future expansion */
 171
 172         u64 io_bitmap_a;
 173         u64 io_bitmap_b;
 174         u64 msr_bitmap;
 175         u64 vm_exit_msr_store_addr;
 176         u64 vm_exit_msr_load_addr;
 177         u64 vm_entry_msr_load_addr;
 178         u64 tsc_offset;
 179         u64 virtual_apic_page_addr;
 180         u64 apic_access_addr;
 181         u64 ept_pointer;
 182         u64 guest_physical_address;
 183         u64 vmcs_link_pointer;
 184         u64 guest_ia32_debugctl;
 185         u64 guest_ia32_pat;
 186         u64 guest_ia32_efer;
 187         u64 guest_ia32_perf_global_ctrl;
 188         u64 guest_pdptr0;
 189         u64 guest_pdptr1;
 190         u64 guest_pdptr2;
 191         u64 guest_pdptr3;
 192         u64 host_ia32_pat;
 193         u64 host_ia32_efer;
 194         u64 host_ia32_perf_global_ctrl;
 195         u64 padding64[8]; /* room for future expansion */
 196         /*
 197          * To allow migration of L1 (complete with its L2 guests) between
 198          * machines of different natural widths (32 or 64 bit), we cannot have
 199          * unsigned long fields with no explict size. We use u64 (aliased
 200          * natural_width) instead. Luckily, x86 is little-endian.
 201          */
 202         natural_width cr0_guest_host_mask;
 203         natural_width cr4_guest_host_mask;
 204         natural_width cr0_read_shadow;
 205         natural_width cr4_read_shadow;
 206         natural_width cr3_target_value0;
 207         natural_width cr3_target_value1;
 208         natural_width cr3_target_value2;
 209         natural_width cr3_target_value3;
 210         natural_width exit_qualification;
 211         natural_width guest_linear_address;
 212         natural_width guest_cr0;
 213         natural_width guest_cr3;
 214         natural_width guest_cr4;
 215         natural_width guest_es_base;
 216         natural_width guest_cs_base;
 217         natural_width guest_ss_base;
 218         natural_width guest_ds_base;
 219         natural_width guest_fs_base;
 220         natural_width guest_gs_base;
 221         natural_width guest_ldtr_base;
 222         natural_width guest_tr_base;
 223         natural_width guest_gdtr_base;
 224         natural_width guest_idtr_base;
 225         natural_width guest_dr7;
 226         natural_width guest_rsp;
 227         natural_width guest_rip;
 228         natural_width guest_rflags;
 229         natural_width guest_pending_dbg_exceptions;
 230         natural_width guest_sysenter_esp;
 231         natural_width guest_sysenter_eip;
 232         natural_width host_cr0;
 233         natural_width host_cr3;
 234         natural_width host_cr4;
 235         natural_width host_fs_base;
 236         natural_width host_gs_base;
 237         natural_width host_tr_base;
 238         natural_width host_gdtr_base;
 239         natural_width host_idtr_base;
 240         natural_width host_ia32_sysenter_esp;
 241         natural_width host_ia32_sysenter_eip;
 242         natural_width host_rsp;
 243         natural_width host_rip;
 244         natural_width paddingl[8]; /* room for future expansion */
 245         u32 pin_based_vm_exec_control;
 246         u32 cpu_based_vm_exec_control;
 247         u32 exception_bitmap;
 248         u32 page_fault_error_code_mask;
 249         u32 page_fault_error_code_match;
 250         u32 cr3_target_count;
 251         u32 vm_exit_controls;
 252         u32 vm_exit_msr_store_count;
 253         u32 vm_exit_msr_load_count;
 254         u32 vm_entry_controls;
 255         u32 vm_entry_msr_load_count;
 256         u32 vm_entry_intr_info_field;
 257         u32 vm_entry_exception_error_code;
 258         u32 vm_entry_instruction_len;
 259         u32 tpr_threshold;
 260         u32 secondary_vm_exec_control;
 261         u32 vm_instruction_error;
 262         u32 vm_exit_reason;
 263         u32 vm_exit_intr_info;
 264         u32 vm_exit_intr_error_code;
 265         u32 idt_vectoring_info_field;
 266         u32 idt_vectoring_error_code;
 267         u32 vm_exit_instruction_len;
 268         u32 vmx_instruction_info;
 269         u32 guest_es_limit;
 270         u32 guest_cs_limit;
 271         u32 guest_ss_limit;
 272         u32 guest_ds_limit;
 273         u32 guest_fs_limit;
 274         u32 guest_gs_limit;
 275         u32 guest_ldtr_limit;
 276         u32 guest_tr_limit;
 277         u32 guest_gdtr_limit;
 278         u32 guest_idtr_limit;
 279         u32 guest_es_ar_bytes;
 280         u32 guest_cs_ar_bytes;
 281         u32 guest_ss_ar_bytes;
 282         u32 guest_ds_ar_bytes;
 283         u32 guest_fs_ar_bytes;
 284         u32 guest_gs_ar_bytes;
 285         u32 guest_ldtr_ar_bytes;
 286         u32 guest_tr_ar_bytes;
 287         u32 guest_interruptibility_info;
 288         u32 guest_activity_state;
 289         u32 guest_sysenter_cs;
 290         u32 host_ia32_sysenter_cs;
 291         u32 padding32[8]; /* room for future expansion */
 292         u16 virtual_processor_id;
 293         u16 guest_es_selector;
 294         u16 guest_cs_selector;
 295         u16 guest_ss_selector;
 296         u16 guest_ds_selector;
 297         u16 guest_fs_selector;
 298         u16 guest_gs_selector;
 299         u16 guest_ldtr_selector;
 300         u16 guest_tr_selector;
 301         u16 host_es_selector;
 302         u16 host_cs_selector;
 303         u16 host_ss_selector;
 304         u16 host_ds_selector;
 305         u16 host_fs_selector;
 306         u16 host_gs_selector;
 307         u16 host_tr_selector;
 308 };
 309
 310 /*
 311  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 312  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 313  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 314  */
 315 #define VMCS12_REVISION 0x11e57ed0
 316
 317 /*
 318  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 319  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 320  * current implementation, 4K are reserved to avoid future complications.
 321  */
 322 #define VMCS12_SIZE 0x1000
 323
 324 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 325 struct vmcs02_list {
 326         struct list_head list;
 327         gpa_t vmptr;
 328         struct loaded_vmcs vmcs02;
 329 };
 330
 331 /*
 332  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 333  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 334  */
 335 struct nested_vmx {
 336         /* Has the level1 guest done vmxon? */
 337         bool vmxon;
 338
 339         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 340         gpa_t current_vmptr;
 341         /* The host-usable pointer to the above */
 342         struct page *current_vmcs12_page;
 343         struct vmcs12 *current_vmcs12;
 344
 345         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 346         struct list_head vmcs02_pool;
 347         int vmcs02_num;
 348         u64 vmcs01_tsc_offset;
 349         /* L2 must run next, and mustn't decide to exit to L1. */
 350         bool nested_run_pending;
 351         /*
 352          * Guest pages referred to in vmcs02 with host-physical pointers, so
 353          * we must keep them pinned while L2 runs.
 354          */
 355         struct page *apic_access_page;
 356 };
 357
 358 struct vcpu_vmx {
 359         struct kvm_vcpu       vcpu;
 360         unsigned long         host_rsp;
 361         u8                    fail;
 362         u8                    cpl;
 363         bool                  nmi_known_unmasked;
 364         u32                   exit_intr_info;
 365         u32                   idt_vectoring_info;
 366         ulong                 rflags;
 367         struct shared_msr_entry *guest_msrs;
 368         int                   nmsrs;
 369         int                   save_nmsrs;
 370 #ifdef CONFIG_X86_64
 371         u64                   msr_host_kernel_gs_base;
 372         u64                   msr_guest_kernel_gs_base;
 373 #endif
 374         /*
 375          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 376          * non-nested (L1) guest, it always points to vmcs01. For a nested
 377          * guest (L2), it points to a different VMCS.
 378          */
 379         struct loaded_vmcs    vmcs01;
 380         struct loaded_vmcs   *loaded_vmcs;
 381         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 382         struct msr_autoload {
 383                 unsigned nr;
 384                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 385                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 386         } msr_autoload;
 387         struct {
 388                 int           loaded;
 389                 u16           fs_sel, gs_sel, ldt_sel;
 390                 int           gs_ldt_reload_needed;
 391                 int           fs_reload_needed;
 392         } host_state;
 393         struct {
 394                 int vm86_active;
 395                 ulong save_rflags;
 396                 struct kvm_save_segment {
 397                         u16 selector;
 398                         unsigned long base;
 399                         u32 limit;
 400                         u32 ar;
 401                 } tr, es, ds, fs, gs;
 402         } rmode;
 403         struct {
 404                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 405                 struct kvm_save_segment seg[8];
 406         } segment_cache;
 407         int vpid;
 408         bool emulation_required;
 409
 410         /* Support for vnmi-less CPUs */
 411         int soft_vnmi_blocked;
 412         ktime_t entry_time;
 413         s64 vnmi_blocked_time;
 414         u32 exit_reason;
 415
 416         bool rdtscp_enabled;
 417
 418         /* Support for a guest hypervisor (nested VMX) */
 419         struct nested_vmx nested;
 420 };
 421
 422 enum segment_cache_field {
 423         SEG_FIELD_SEL = 0,
 424         SEG_FIELD_BASE = 1,
 425         SEG_FIELD_LIMIT = 2,
 426         SEG_FIELD_AR = 3,
 427
 428         SEG_FIELD_NR = 4
 429 };
 430
 431 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 432 {
 433         return container_of(vcpu, struct vcpu_vmx, vcpu);
 434 }
 435
 436 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 437 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 438 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 439                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 440
 441 static unsigned short vmcs_field_to_offset_table[] = {
 442         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 443         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 444         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 445         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 446         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 447         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 448         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 449         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 450         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 451         FIELD(HOST_ES_SELECTOR, host_es_selector),
 452         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 453         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 454         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 455         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 456         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 457         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 458         FIELD64(IO_BITMAP_A, io_bitmap_a),
 459         FIELD64(IO_BITMAP_B, io_bitmap_b),
 460         FIELD64(MSR_BITMAP, msr_bitmap),
 461         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 462         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 463         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 464         FIELD64(TSC_OFFSET, tsc_offset),
 465         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 466         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 467         FIELD64(EPT_POINTER, ept_pointer),
 468         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 469         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 470         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 471         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 472         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 473         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 474         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 475         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 476         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 477         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 478         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 479         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 480         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 481         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 482         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 483         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 484         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 485         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 486         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 487         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 488         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 489         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 490         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 491         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 492         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 493         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 494         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 495         FIELD(TPR_THRESHOLD, tpr_threshold),
 496         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 497         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 498         FIELD(VM_EXIT_REASON, vm_exit_reason),
 499         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 500         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 501         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 502         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 503         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 504         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 505         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 506         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 507         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 508         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 509         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 510         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 511         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 512         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 513         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 514         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 515         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 516         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 517         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 518         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 519         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 520         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 521         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 522         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 523         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 524         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 525         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 526         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 527         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 528         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 529         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 530         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 531         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 532         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 533         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 534         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 535         FIELD(EXIT_QUALIFICATION, exit_qualification),
 536         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 537         FIELD(GUEST_CR0, guest_cr0),
 538         FIELD(GUEST_CR3, guest_cr3),
 539         FIELD(GUEST_CR4, guest_cr4),
 540         FIELD(GUEST_ES_BASE, guest_es_base),
 541         FIELD(GUEST_CS_BASE, guest_cs_base),
 542         FIELD(GUEST_SS_BASE, guest_ss_base),
 543         FIELD(GUEST_DS_BASE, guest_ds_base),
 544         FIELD(GUEST_FS_BASE, guest_fs_base),
 545         FIELD(GUEST_GS_BASE, guest_gs_base),
 546         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 547         FIELD(GUEST_TR_BASE, guest_tr_base),
 548         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 549         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 550         FIELD(GUEST_DR7, guest_dr7),
 551         FIELD(GUEST_RSP, guest_rsp),
 552         FIELD(GUEST_RIP, guest_rip),
 553         FIELD(GUEST_RFLAGS, guest_rflags),
 554         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 555         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 556         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 557         FIELD(HOST_CR0, host_cr0),
 558         FIELD(HOST_CR3, host_cr3),
 559         FIELD(HOST_CR4, host_cr4),
 560         FIELD(HOST_FS_BASE, host_fs_base),
 561         FIELD(HOST_GS_BASE, host_gs_base),
 562         FIELD(HOST_TR_BASE, host_tr_base),
 563         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 564         FIELD(HOST_IDTR_BASE, host_idtr_base),
 565         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 566         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 567         FIELD(HOST_RSP, host_rsp),
 568         FIELD(HOST_RIP, host_rip),
 569 };
 570 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 571
 572 static inline short vmcs_field_to_offset(unsigned long field)
 573 {
 574         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 575                 return -1;
 576         return vmcs_field_to_offset_table[field];
 577 }
 578
 579 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 580 {
 581         return to_vmx(vcpu)->nested.current_vmcs12;
 582 }
 583
 584 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 585 {
 586         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 587         if (is_error_page(page)) {
 588                 kvm_release_page_clean(page);
 589                 return NULL;
 590         }
 591         return page;
 592 }
 593
 594 static void nested_release_page(struct page *page)
 595 {
 596         kvm_release_page_dirty(page);
 597 }
 598
 599 static void nested_release_page_clean(struct page *page)
 600 {
 601         kvm_release_page_clean(page);
 602 }
 603
 604 static u64 construct_eptp(unsigned long root_hpa);
 605 static void kvm_cpu_vmxon(u64 addr);
 606 static void kvm_cpu_vmxoff(void);
 607 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 608 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 609
 610 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 611 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 612 /*
 613  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 614  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 615  */
 616 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 617 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 618
 619 static unsigned long *vmx_io_bitmap_a;
 620 static unsigned long *vmx_io_bitmap_b;
 621 static unsigned long *vmx_msr_bitmap_legacy;
 622 static unsigned long *vmx_msr_bitmap_longmode;
 623
 624 static bool cpu_has_load_ia32_efer;
 625
 626 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 627 static DEFINE_SPINLOCK(vmx_vpid_lock);
 628
 629 static struct vmcs_config {
 630         int size;
 631         int order;
 632         u32 revision_id;
 633         u32 pin_based_exec_ctrl;
 634         u32 cpu_based_exec_ctrl;
 635         u32 cpu_based_2nd_exec_ctrl;
 636         u32 vmexit_ctrl;
 637         u32 vmentry_ctrl;
 638 } vmcs_config;
 639
 640 static struct vmx_capability {
 641         u32 ept;
 642         u32 vpid;
 643 } vmx_capability;
 644
 645 #define VMX_SEGMENT_FIELD(seg)                                  \
 646         [VCPU_SREG_##seg] = {                                   \
 647                 .selector = GUEST_##seg##_SELECTOR,             \
 648                 .base = GUEST_##seg##_BASE,                     \
 649                 .limit = GUEST_##seg##_LIMIT,                   \
 650                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 651         }
 652
 653 static struct kvm_vmx_segment_field {
 654         unsigned selector;
 655         unsigned base;
 656         unsigned limit;
 657         unsigned ar_bytes;
 658 } kvm_vmx_segment_fields[] = {
 659         VMX_SEGMENT_FIELD(CS),
 660         VMX_SEGMENT_FIELD(DS),
 661         VMX_SEGMENT_FIELD(ES),
 662         VMX_SEGMENT_FIELD(FS),
 663         VMX_SEGMENT_FIELD(GS),
 664         VMX_SEGMENT_FIELD(SS),
 665         VMX_SEGMENT_FIELD(TR),
 666         VMX_SEGMENT_FIELD(LDTR),
 667 };
 668
 669 static u64 host_efer;
 670
 671 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 672
 673 /*
 674  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 675  * away by decrementing the array size.
 676  */
 677 static const u32 vmx_msr_index[] = {
 678 #ifdef CONFIG_X86_64
 679         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 680 #endif
 681         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 682 };
 683 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 684
 685 static inline bool is_page_fault(u32 intr_info)
 686 {
 687         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 688                              INTR_INFO_VALID_MASK)) ==
 689                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 690 }
 691
 692 static inline bool is_no_device(u32 intr_info)
 693 {
 694         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 695                              INTR_INFO_VALID_MASK)) ==
 696                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 697 }
 698
 699 static inline bool is_invalid_opcode(u32 intr_info)
 700 {
 701         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 702                              INTR_INFO_VALID_MASK)) ==
 703                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 704 }
 705
 706 static inline bool is_external_interrupt(u32 intr_info)
 707 {
 708         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 709                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 710 }
 711
 712 static inline bool is_machine_check(u32 intr_info)
 713 {
 714         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 715                              INTR_INFO_VALID_MASK)) ==
 716                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 717 }
 718
 719 static inline bool cpu_has_vmx_msr_bitmap(void)
 720 {
 721         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 722 }
 723
 724 static inline bool cpu_has_vmx_tpr_shadow(void)
 725 {
 726         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 727 }
 728
 729 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 730 {
 731         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 732 }
 733
 734 static inline bool cpu_has_secondary_exec_ctrls(void)
 735 {
 736         return vmcs_config.cpu_based_exec_ctrl &
 737                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 738 }
 739
 740 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 741 {
 742         return vmcs_config.cpu_based_2nd_exec_ctrl &
 743                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 744 }
 745
 746 static inline bool cpu_has_vmx_flexpriority(void)
 747 {
 748         return cpu_has_vmx_tpr_shadow() &&
 749                 cpu_has_vmx_virtualize_apic_accesses();
 750 }
 751
 752 static inline bool cpu_has_vmx_ept_execute_only(void)
 753 {
 754         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 755 }
 756
 757 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 758 {
 759         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 760 }
 761
 762 static inline bool cpu_has_vmx_eptp_writeback(void)
 763 {
 764         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 765 }
 766
 767 static inline bool cpu_has_vmx_ept_2m_page(void)
 768 {
 769         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 770 }
 771
 772 static inline bool cpu_has_vmx_ept_1g_page(void)
 773 {
 774         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 775 }
 776
 777 static inline bool cpu_has_vmx_ept_4levels(void)
 778 {
 779         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 780 }
 781
 782 static inline bool cpu_has_vmx_invept_individual_addr(void)
 783 {
 784         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 785 }
 786
 787 static inline bool cpu_has_vmx_invept_context(void)
 788 {
 789         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 790 }
 791
 792 static inline bool cpu_has_vmx_invept_global(void)
 793 {
 794         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 795 }
 796
 797 static inline bool cpu_has_vmx_invvpid_single(void)
 798 {
 799         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 800 }
 801
 802 static inline bool cpu_has_vmx_invvpid_global(void)
 803 {
 804         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 805 }
 806
 807 static inline bool cpu_has_vmx_ept(void)
 808 {
 809         return vmcs_config.cpu_based_2nd_exec_ctrl &
 810                 SECONDARY_EXEC_ENABLE_EPT;
 811 }
 812
 813 static inline bool cpu_has_vmx_unrestricted_guest(void)
 814 {
 815         return vmcs_config.cpu_based_2nd_exec_ctrl &
 816                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 817 }
 818
 819 static inline bool cpu_has_vmx_ple(void)
 820 {
 821         return vmcs_config.cpu_based_2nd_exec_ctrl &
 822                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 823 }
 824
 825 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 826 {
 827         return flexpriority_enabled && irqchip_in_kernel(kvm);
 828 }
 829
 830 static inline bool cpu_has_vmx_vpid(void)
 831 {
 832         return vmcs_config.cpu_based_2nd_exec_ctrl &
 833                 SECONDARY_EXEC_ENABLE_VPID;
 834 }
 835
 836 static inline bool cpu_has_vmx_rdtscp(void)
 837 {
 838         return vmcs_config.cpu_based_2nd_exec_ctrl &
 839                 SECONDARY_EXEC_RDTSCP;
 840 }
 841
 842 static inline bool cpu_has_virtual_nmis(void)
 843 {
 844         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 845 }
 846
 847 static inline bool cpu_has_vmx_wbinvd_exit(void)
 848 {
 849         return vmcs_config.cpu_based_2nd_exec_ctrl &
 850                 SECONDARY_EXEC_WBINVD_EXITING;
 851 }
 852
 853 static inline bool report_flexpriority(void)
 854 {
 855         return flexpriority_enabled;
 856 }
 857
 858 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 859 {
 860         return vmcs12->cpu_based_vm_exec_control & bit;
 861 }
 862
 863 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 864 {
 865         return (vmcs12->cpu_based_vm_exec_control &
 866                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 867                 (vmcs12->secondary_vm_exec_control & bit);
 868 }
 869
 870 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 871         struct kvm_vcpu *vcpu)
 872 {
 873         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 874 }
 875
 876 static inline bool is_exception(u32 intr_info)
 877 {
 878         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 879                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 880 }
 881
 882 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 883 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 884                         struct vmcs12 *vmcs12,
 885                         u32 reason, unsigned long qualification);
 886
 887 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 888 {
 889         int i;
 890
 891         for (i = 0; i < vmx->nmsrs; ++i)
 892                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 893                         return i;
 894         return -1;
 895 }
 896
 897 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 898 {
 899     struct {
 900         u64 vpid : 16;
 901         u64 rsvd : 48;
 902         u64 gva;
 903     } operand = { vpid, 0, gva };
 904
 905     asm volatile (__ex(ASM_VMX_INVVPID)
 906                   /* CF==1 or ZF==1 --> rc = -1 */
 907                   "; ja 1f ; ud2 ; 1:"
 908                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 909 }
 910
 911 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 912 {
 913         struct {
 914                 u64 eptp, gpa;
 915         } operand = {eptp, gpa};
 916
 917         asm volatile (__ex(ASM_VMX_INVEPT)
 918                         /* CF==1 or ZF==1 --> rc = -1 */
 919                         "; ja 1f ; ud2 ; 1:\n"
 920                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 921 }
 922
 923 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 924 {
 925         int i;
 926
 927         i = __find_msr_index(vmx, msr);
 928         if (i >= 0)
 929                 return &vmx->guest_msrs[i];
 930         return NULL;
 931 }
 932
 933 static void vmcs_clear(struct vmcs *vmcs)
 934 {
 935         u64 phys_addr = __pa(vmcs);
 936         u8 error;
 937
 938         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 939                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 940                       : "cc", "memory");
 941         if (error)
 942                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 943                        vmcs, phys_addr);
 944 }
 945
 946 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 947 {
 948         vmcs_clear(loaded_vmcs->vmcs);
 949         loaded_vmcs->cpu = -1;
 950         loaded_vmcs->launched = 0;
 951 }
 952
 953 static void vmcs_load(struct vmcs *vmcs)
 954 {
 955         u64 phys_addr = __pa(vmcs);
 956         u8 error;
 957
 958         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 959                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 960                         : "cc", "memory");
 961         if (error)
 962                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 963                        vmcs, phys_addr);
 964 }
 965
 966 static void __loaded_vmcs_clear(void *arg)
 967 {
 968         struct loaded_vmcs *loaded_vmcs = arg;
 969         int cpu = raw_smp_processor_id();
 970
 971         if (loaded_vmcs->cpu != cpu)
 972                 return; /* vcpu migration can race with cpu offline */
 973         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 974                 per_cpu(current_vmcs, cpu) = NULL;
 975         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 976         loaded_vmcs_init(loaded_vmcs);
 977 }
 978
 979 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 980 {
 981         if (loaded_vmcs->cpu != -1)
 982                 smp_call_function_single(
 983                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 984 }
 985
 986 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 987 {
 988         if (vmx->vpid == 0)
 989                 return;
 990
 991         if (cpu_has_vmx_invvpid_single())
 992                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 993 }
 994
 995 static inline void vpid_sync_vcpu_global(void)
 996 {
 997         if (cpu_has_vmx_invvpid_global())
 998                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
 999 }
1000
1001 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1002 {
1003         if (cpu_has_vmx_invvpid_single())
1004                 vpid_sync_vcpu_single(vmx);
1005         else
1006                 vpid_sync_vcpu_global();
1007 }
1008
1009 static inline void ept_sync_global(void)
1010 {
1011         if (cpu_has_vmx_invept_global())
1012                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1013 }
1014
1015 static inline void ept_sync_context(u64 eptp)
1016 {
1017         if (enable_ept) {
1018                 if (cpu_has_vmx_invept_context())
1019                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1020                 else
1021                         ept_sync_global();
1022         }
1023 }
1024
1025 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1026 {
1027         if (enable_ept) {
1028                 if (cpu_has_vmx_invept_individual_addr())
1029                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1030                                         eptp, gpa);
1031                 else
1032                         ept_sync_context(eptp);
1033         }
1034 }
1035
1036 static __always_inline unsigned long vmcs_readl(unsigned long field)
1037 {
1038         unsigned long value;
1039
1040         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1041                       : "=a"(value) : "d"(field) : "cc");
1042         return value;
1043 }
1044
1045 static __always_inline u16 vmcs_read16(unsigned long field)
1046 {
1047         return vmcs_readl(field);
1048 }
1049
1050 static __always_inline u32 vmcs_read32(unsigned long field)
1051 {
1052         return vmcs_readl(field);
1053 }
1054
1055 static __always_inline u64 vmcs_read64(unsigned long field)
1056 {
1057 #ifdef CONFIG_X86_64
1058         return vmcs_readl(field);
1059 #else
1060         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1061 #endif
1062 }
1063
1064 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1065 {
1066         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1067                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1068         dump_stack();
1069 }
1070
1071 static void vmcs_writel(unsigned long field, unsigned long value)
1072 {
1073         u8 error;
1074
1075         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1076                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1077         if (unlikely(error))
1078                 vmwrite_error(field, value);
1079 }
1080
1081 static void vmcs_write16(unsigned long field, u16 value)
1082 {
1083         vmcs_writel(field, value);
1084 }
1085
1086 static void vmcs_write32(unsigned long field, u32 value)
1087 {
1088         vmcs_writel(field, value);
1089 }
1090
1091 static void vmcs_write64(unsigned long field, u64 value)
1092 {
1093         vmcs_writel(field, value);
1094 #ifndef CONFIG_X86_64
1095         asm volatile ("");
1096         vmcs_writel(field+1, value >> 32);
1097 #endif
1098 }
1099
1100 static void vmcs_clear_bits(unsigned long field, u32 mask)
1101 {
1102         vmcs_writel(field, vmcs_readl(field) & ~mask);
1103 }
1104
1105 static void vmcs_set_bits(unsigned long field, u32 mask)
1106 {
1107         vmcs_writel(field, vmcs_readl(field) | mask);
1108 }
1109
1110 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1111 {
1112         vmx->segment_cache.bitmask = 0;
1113 }
1114
1115 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1116                                        unsigned field)
1117 {
1118         bool ret;
1119         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1120
1121         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1122                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1123                 vmx->segment_cache.bitmask = 0;
1124         }
1125         ret = vmx->segment_cache.bitmask & mask;
1126         vmx->segment_cache.bitmask |= mask;
1127         return ret;
1128 }
1129
1130 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1131 {
1132         u16 *p = &vmx->segment_cache.seg[seg].selector;
1133
1134         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1135                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1136         return *p;
1137 }
1138
1139 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1140 {
1141         ulong *p = &vmx->segment_cache.seg[seg].base;
1142
1143         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1144                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1145         return *p;
1146 }
1147
1148 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1149 {
1150         u32 *p = &vmx->segment_cache.seg[seg].limit;
1151
1152         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1153                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1154         return *p;
1155 }
1156
1157 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1158 {
1159         u32 *p = &vmx->segment_cache.seg[seg].ar;
1160
1161         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1162                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1163         return *p;
1164 }
1165
1166 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1167 {
1168         u32 eb;
1169
1170         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1171              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1172         if ((vcpu->guest_debug &
1173              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1174             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1175                 eb |= 1u << BP_VECTOR;
1176         if (to_vmx(vcpu)->rmode.vm86_active)
1177                 eb = ~0;
1178         if (enable_ept)
1179                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1180         if (vcpu->fpu_active)
1181                 eb &= ~(1u << NM_VECTOR);
1182
1183         /* When we are running a nested L2 guest and L1 specified for it a
1184          * certain exception bitmap, we must trap the same exceptions and pass
1185          * them to L1. When running L2, we will only handle the exceptions
1186          * specified above if L1 did not want them.
1187          */
1188         if (is_guest_mode(vcpu))
1189                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1190
1191         vmcs_write32(EXCEPTION_BITMAP, eb);
1192 }
1193
1194 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1195 {
1196         unsigned i;
1197         struct msr_autoload *m = &vmx->msr_autoload;
1198
1199         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1200                 vmcs_clear_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1201                 vmcs_clear_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1202                 return;
1203         }
1204
1205         for (i = 0; i < m->nr; ++i)
1206                 if (m->guest[i].index == msr)
1207                         break;
1208
1209         if (i == m->nr)
1210                 return;
1211         --m->nr;
1212         m->guest[i] = m->guest[m->nr];
1213         m->host[i] = m->host[m->nr];
1214         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1215         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1216 }
1217
1218 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1219                                   u64 guest_val, u64 host_val)
1220 {
1221         unsigned i;
1222         struct msr_autoload *m = &vmx->msr_autoload;
1223
1224         if (msr == MSR_EFER && cpu_has_load_ia32_efer) {
1225                 vmcs_write64(GUEST_IA32_EFER, guest_val);
1226                 vmcs_write64(HOST_IA32_EFER, host_val);
1227                 vmcs_set_bits(VM_ENTRY_CONTROLS, VM_ENTRY_LOAD_IA32_EFER);
1228                 vmcs_set_bits(VM_EXIT_CONTROLS, VM_EXIT_LOAD_IA32_EFER);
1229                 return;
1230         }
1231
1232         for (i = 0; i < m->nr; ++i)
1233                 if (m->guest[i].index == msr)
1234                         break;
1235
1236         if (i == m->nr) {
1237                 ++m->nr;
1238                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1239                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1240         }
1241
1242         m->guest[i].index = msr;
1243         m->guest[i].value = guest_val;
1244         m->host[i].index = msr;
1245         m->host[i].value = host_val;
1246 }
1247
1248 static void reload_tss(void)
1249 {
1250         /*
1251          * VT restores TR but not its size.  Useless.
1252          */
1253         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1254         struct desc_struct *descs;
1255
1256         descs = (void *)gdt->address;
1257         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1258         load_TR_desc();
1259 }
1260
1261 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1262 {
1263         u64 guest_efer;
1264         u64 ignore_bits;
1265
1266         guest_efer = vmx->vcpu.arch.efer;
1267
1268         /*
1269          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1270          * outside long mode
1271          */
1272         ignore_bits = EFER_NX | EFER_SCE;
1273 #ifdef CONFIG_X86_64
1274         ignore_bits |= EFER_LMA | EFER_LME;
1275         /* SCE is meaningful only in long mode on Intel */
1276         if (guest_efer & EFER_LMA)
1277                 ignore_bits &= ~(u64)EFER_SCE;
1278 #endif
1279         guest_efer &= ~ignore_bits;
1280         guest_efer |= host_efer & ignore_bits;
1281         vmx->guest_msrs[efer_offset].data = guest_efer;
1282         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1283
1284         clear_atomic_switch_msr(vmx, MSR_EFER);
1285         /* On ept, can't emulate nx, and must switch nx atomically */
1286         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1287                 guest_efer = vmx->vcpu.arch.efer;
1288                 if (!(guest_efer & EFER_LMA))
1289                         guest_efer &= ~EFER_LME;
1290                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1291                 return false;
1292         }
1293
1294         return true;
1295 }
1296
1297 static unsigned long segment_base(u16 selector)
1298 {
1299         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1300         struct desc_struct *d;
1301         unsigned long table_base;
1302         unsigned long v;
1303
1304         if (!(selector & ~3))
1305                 return 0;
1306
1307         table_base = gdt->address;
1308
1309         if (selector & 4) {           /* from ldt */
1310                 u16 ldt_selector = kvm_read_ldt();
1311
1312                 if (!(ldt_selector & ~3))
1313                         return 0;
1314
1315                 table_base = segment_base(ldt_selector);
1316         }
1317         d = (struct desc_struct *)(table_base + (selector & ~7));
1318         v = get_desc_base(d);
1319 #ifdef CONFIG_X86_64
1320        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1321                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1322 #endif
1323         return v;
1324 }
1325
1326 static inline unsigned long kvm_read_tr_base(void)
1327 {
1328         u16 tr;
1329         asm("str %0" : "=g"(tr));
1330         return segment_base(tr);
1331 }
1332
1333 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1334 {
1335         struct vcpu_vmx *vmx = to_vmx(vcpu);
1336         int i;
1337
1338         if (vmx->host_state.loaded)
1339                 return;
1340
1341         vmx->host_state.loaded = 1;
1342         /*
1343          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1344          * allow segment selectors with cpl > 0 or ti == 1.
1345          */
1346         vmx->host_state.ldt_sel = kvm_read_ldt();
1347         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1348         savesegment(fs, vmx->host_state.fs_sel);
1349         if (!(vmx->host_state.fs_sel & 7)) {
1350                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1351                 vmx->host_state.fs_reload_needed = 0;
1352         } else {
1353                 vmcs_write16(HOST_FS_SELECTOR, 0);
1354                 vmx->host_state.fs_reload_needed = 1;
1355         }
1356         savesegment(gs, vmx->host_state.gs_sel);
1357         if (!(vmx->host_state.gs_sel & 7))
1358                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1359         else {
1360                 vmcs_write16(HOST_GS_SELECTOR, 0);
1361                 vmx->host_state.gs_ldt_reload_needed = 1;
1362         }
1363
1364 #ifdef CONFIG_X86_64
1365         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1366         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1367 #else
1368         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1369         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1370 #endif
1371
1372 #ifdef CONFIG_X86_64
1373         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1374         if (is_long_mode(&vmx->vcpu))
1375                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1376 #endif
1377         for (i = 0; i < vmx->save_nmsrs; ++i)
1378                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1379                                    vmx->guest_msrs[i].data,
1380                                    vmx->guest_msrs[i].mask);
1381 }
1382
1383 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1384 {
1385         if (!vmx->host_state.loaded)
1386                 return;
1387
1388         ++vmx->vcpu.stat.host_state_reload;
1389         vmx->host_state.loaded = 0;
1390 #ifdef CONFIG_X86_64
1391         if (is_long_mode(&vmx->vcpu))
1392                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1393 #endif
1394         if (vmx->host_state.gs_ldt_reload_needed) {
1395                 kvm_load_ldt(vmx->host_state.ldt_sel);
1396 #ifdef CONFIG_X86_64
1397                 load_gs_index(vmx->host_state.gs_sel);
1398 #else
1399                 loadsegment(gs, vmx->host_state.gs_sel);
1400 #endif
1401         }
1402         if (vmx->host_state.fs_reload_needed)
1403                 loadsegment(fs, vmx->host_state.fs_sel);
1404         reload_tss();
1405 #ifdef CONFIG_X86_64
1406         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1407 #endif
1408         if (current_thread_info()->status & TS_USEDFPU)
1409                 clts();
1410         load_gdt(&__get_cpu_var(host_gdt));
1411 }
1412
1413 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1414 {
1415         preempt_disable();
1416         __vmx_load_host_state(vmx);
1417         preempt_enable();
1418 }
1419
1420 /*
1421  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1422  * vcpu mutex is already taken.
1423  */
1424 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1425 {
1426         struct vcpu_vmx *vmx = to_vmx(vcpu);
1427         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1428
1429         if (!vmm_exclusive)
1430                 kvm_cpu_vmxon(phys_addr);
1431         else if (vmx->loaded_vmcs->cpu != cpu)
1432                 loaded_vmcs_clear(vmx->loaded_vmcs);
1433
1434         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1435                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1436                 vmcs_load(vmx->loaded_vmcs->vmcs);
1437         }
1438
1439         if (vmx->loaded_vmcs->cpu != cpu) {
1440                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1441                 unsigned long sysenter_esp;
1442
1443                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1444                 local_irq_disable();
1445                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1446                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1447                 local_irq_enable();
1448
1449                 /*
1450                  * Linux uses per-cpu TSS and GDT, so set these when switching
1451                  * processors.
1452                  */
1453                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1454                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1455
1456                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1457                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1458                 vmx->loaded_vmcs->cpu = cpu;
1459         }
1460 }
1461
1462 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1463 {
1464         __vmx_load_host_state(to_vmx(vcpu));
1465         if (!vmm_exclusive) {
1466                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1467                 vcpu->cpu = -1;
1468                 kvm_cpu_vmxoff();
1469         }
1470 }
1471
1472 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1473 {
1474         ulong cr0;
1475
1476         if (vcpu->fpu_active)
1477                 return;
1478         vcpu->fpu_active = 1;
1479         cr0 = vmcs_readl(GUEST_CR0);
1480         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1481         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1482         vmcs_writel(GUEST_CR0, cr0);
1483         update_exception_bitmap(vcpu);
1484         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1485         if (is_guest_mode(vcpu))
1486                 vcpu->arch.cr0_guest_owned_bits &=
1487                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1488         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1489 }
1490
1491 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1492
1493 /*
1494  * Return the cr0 value that a nested guest would read. This is a combination
1495  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1496  * its hypervisor (cr0_read_shadow).
1497  */
1498 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1499 {
1500         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1501                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1502 }
1503 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1504 {
1505         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1506                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1507 }
1508
1509 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1510 {
1511         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1512          * set this *before* calling this function.
1513          */
1514         vmx_decache_cr0_guest_bits(vcpu);
1515         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1516         update_exception_bitmap(vcpu);
1517         vcpu->arch.cr0_guest_owned_bits = 0;
1518         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1519         if (is_guest_mode(vcpu)) {
1520                 /*
1521                  * L1's specified read shadow might not contain the TS bit,
1522                  * so now that we turned on shadowing of this bit, we need to
1523                  * set this bit of the shadow. Like in nested_vmx_run we need
1524                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1525                  * up-to-date here because we just decached cr0.TS (and we'll
1526                  * only update vmcs12->guest_cr0 on nested exit).
1527                  */
1528                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1529                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1530                         (vcpu->arch.cr0 & X86_CR0_TS);
1531                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1532         } else
1533                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1534 }
1535
1536 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1537 {
1538         unsigned long rflags, save_rflags;
1539
1540         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1541                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1542                 rflags = vmcs_readl(GUEST_RFLAGS);
1543                 if (to_vmx(vcpu)->rmode.vm86_active) {
1544                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1545                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1546                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1547                 }
1548                 to_vmx(vcpu)->rflags = rflags;
1549         }
1550         return to_vmx(vcpu)->rflags;
1551 }
1552
1553 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1554 {
1555         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1556         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1557         to_vmx(vcpu)->rflags = rflags;
1558         if (to_vmx(vcpu)->rmode.vm86_active) {
1559                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1560                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1561         }
1562         vmcs_writel(GUEST_RFLAGS, rflags);
1563 }
1564
1565 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1566 {
1567         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1568         int ret = 0;
1569
1570         if (interruptibility & GUEST_INTR_STATE_STI)
1571                 ret |= KVM_X86_SHADOW_INT_STI;
1572         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1573                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1574
1575         return ret & mask;
1576 }
1577
1578 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1579 {
1580         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1581         u32 interruptibility = interruptibility_old;
1582
1583         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1584
1585         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1586                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1587         else if (mask & KVM_X86_SHADOW_INT_STI)
1588                 interruptibility |= GUEST_INTR_STATE_STI;
1589
1590         if ((interruptibility != interruptibility_old))
1591                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1592 }
1593
1594 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1595 {
1596         unsigned long rip;
1597
1598         rip = kvm_rip_read(vcpu);
1599         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1600         kvm_rip_write(vcpu, rip);
1601
1602         /* skipping an emulated instruction also counts */
1603         vmx_set_interrupt_shadow(vcpu, 0);
1604 }
1605
1606 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1607 {
1608         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1609          * explicitly skip the instruction because if the HLT state is set, then
1610          * the instruction is already executing and RIP has already been
1611          * advanced. */
1612         if (!yield_on_hlt &&
1613             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1614                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1615 }
1616
1617 /*
1618  * KVM wants to inject page-faults which it got to the guest. This function
1619  * checks whether in a nested guest, we need to inject them to L1 or L2.
1620  * This function assumes it is called with the exit reason in vmcs02 being
1621  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1622  * is running).
1623  */
1624 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1625 {
1626         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1627
1628         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1629         if (!(vmcs12->exception_bitmap & PF_VECTOR))
1630                 return 0;
1631
1632         nested_vmx_vmexit(vcpu);
1633         return 1;
1634 }
1635
1636 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1637                                 bool has_error_code, u32 error_code,
1638                                 bool reinject)
1639 {
1640         struct vcpu_vmx *vmx = to_vmx(vcpu);
1641         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1642
1643         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1644                 nested_pf_handled(vcpu))
1645                 return;
1646
1647         if (has_error_code) {
1648                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1649                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1650         }
1651
1652         if (vmx->rmode.vm86_active) {
1653                 int inc_eip = 0;
1654                 if (kvm_exception_is_soft(nr))
1655                         inc_eip = vcpu->arch.event_exit_inst_len;
1656                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1657                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1658                 return;
1659         }
1660
1661         if (kvm_exception_is_soft(nr)) {
1662                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1663                              vmx->vcpu.arch.event_exit_inst_len);
1664                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1665         } else
1666                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1667
1668         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1669         vmx_clear_hlt(vcpu);
1670 }
1671
1672 static bool vmx_rdtscp_supported(void)
1673 {
1674         return cpu_has_vmx_rdtscp();
1675 }
1676
1677 /*
1678  * Swap MSR entry in host/guest MSR entry array.
1679  */
1680 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1681 {
1682         struct shared_msr_entry tmp;
1683
1684         tmp = vmx->guest_msrs[to];
1685         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1686         vmx->guest_msrs[from] = tmp;
1687 }
1688
1689 /*
1690  * Set up the vmcs to automatically save and restore system
1691  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1692  * mode, as fiddling with msrs is very expensive.
1693  */
1694 static void setup_msrs(struct vcpu_vmx *vmx)
1695 {
1696         int save_nmsrs, index;
1697         unsigned long *msr_bitmap;
1698
1699         vmx_load_host_state(vmx);
1700         save_nmsrs = 0;
1701 #ifdef CONFIG_X86_64
1702         if (is_long_mode(&vmx->vcpu)) {
1703                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1704                 if (index >= 0)
1705                         move_msr_up(vmx, index, save_nmsrs++);
1706                 index = __find_msr_index(vmx, MSR_LSTAR);
1707                 if (index >= 0)
1708                         move_msr_up(vmx, index, save_nmsrs++);
1709                 index = __find_msr_index(vmx, MSR_CSTAR);
1710                 if (index >= 0)
1711                         move_msr_up(vmx, index, save_nmsrs++);
1712                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1713                 if (index >= 0 && vmx->rdtscp_enabled)
1714                         move_msr_up(vmx, index, save_nmsrs++);
1715                 /*
1716                  * MSR_STAR is only needed on long mode guests, and only
1717                  * if efer.sce is enabled.
1718                  */
1719                 index = __find_msr_index(vmx, MSR_STAR);
1720                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1721                         move_msr_up(vmx, index, save_nmsrs++);
1722         }
1723 #endif
1724         index = __find_msr_index(vmx, MSR_EFER);
1725         if (index >= 0 && update_transition_efer(vmx, index))
1726                 move_msr_up(vmx, index, save_nmsrs++);
1727
1728         vmx->save_nmsrs = save_nmsrs;
1729
1730         if (cpu_has_vmx_msr_bitmap()) {
1731                 if (is_long_mode(&vmx->vcpu))
1732                         msr_bitmap = vmx_msr_bitmap_longmode;
1733                 else
1734                         msr_bitmap = vmx_msr_bitmap_legacy;
1735
1736                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1737         }
1738 }
1739
1740 /*
1741  * reads and returns guest's timestamp counter "register"
1742  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1743  */
1744 static u64 guest_read_tsc(void)
1745 {
1746         u64 host_tsc, tsc_offset;
1747
1748         rdtscll(host_tsc);
1749         tsc_offset = vmcs_read64(TSC_OFFSET);
1750         return host_tsc + tsc_offset;
1751 }
1752
1753 /*
1754  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1755  * counter, even if a nested guest (L2) is currently running.
1756  */
1757 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1758 {
1759         u64 host_tsc, tsc_offset;
1760
1761         rdtscll(host_tsc);
1762         tsc_offset = is_guest_mode(vcpu) ?
1763                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1764                 vmcs_read64(TSC_OFFSET);
1765         return host_tsc + tsc_offset;
1766 }
1767
1768 /*
1769  * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1770  * ioctl. In this case the call-back should update internal vmx state to make
1771  * the changes effective.
1772  */
1773 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1774 {
1775         /* Nothing to do here */
1776 }
1777
1778 /*
1779  * writes 'offset' into guest's timestamp counter offset register
1780  */
1781 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1782 {
1783         if (is_guest_mode(vcpu)) {
1784                 /*
1785                  * We're here if L1 chose not to trap WRMSR to TSC. According
1786                  * to the spec, this should set L1's TSC; The offset that L1
1787                  * set for L2 remains unchanged, and still needs to be added
1788                  * to the newly set TSC to get L2's TSC.
1789                  */
1790                 struct vmcs12 *vmcs12;
1791                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1792                 /* recalculate vmcs02.TSC_OFFSET: */
1793                 vmcs12 = get_vmcs12(vcpu);
1794                 vmcs_write64(TSC_OFFSET, offset +
1795                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1796                          vmcs12->tsc_offset : 0));
1797         } else {
1798                 vmcs_write64(TSC_OFFSET, offset);
1799         }
1800 }
1801
1802 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1803 {
1804         u64 offset = vmcs_read64(TSC_OFFSET);
1805         vmcs_write64(TSC_OFFSET, offset + adjustment);
1806         if (is_guest_mode(vcpu)) {
1807                 /* Even when running L2, the adjustment needs to apply to L1 */
1808                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1809         }
1810 }
1811
1812 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1813 {
1814         return target_tsc - native_read_tsc();
1815 }
1816
1817 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1818 {
1819         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1820         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1821 }
1822
1823 /*
1824  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1825  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1826  * all guests if the "nested" module option is off, and can also be disabled
1827  * for a single guest by disabling its VMX cpuid bit.
1828  */
1829 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1830 {
1831         return nested && guest_cpuid_has_vmx(vcpu);
1832 }
1833
1834 /*
1835  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1836  * returned for the various VMX controls MSRs when nested VMX is enabled.
1837  * The same values should also be used to verify that vmcs12 control fields are
1838  * valid during nested entry from L1 to L2.
1839  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1840  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1841  * bit in the high half is on if the corresponding bit in the control field
1842  * may be on. See also vmx_control_verify().
1843  * TODO: allow these variables to be modified (downgraded) by module options
1844  * or other means.
1845  */
1846 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1847 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1848 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1849 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1850 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1851 static __init void nested_vmx_setup_ctls_msrs(void)
1852 {
1853         /*
1854          * Note that as a general rule, the high half of the MSRs (bits in
1855          * the control fields which may be 1) should be initialized by the
1856          * intersection of the underlying hardware's MSR (i.e., features which
1857          * can be supported) and the list of features we want to expose -
1858          * because they are known to be properly supported in our code.
1859          * Also, usually, the low half of the MSRs (bits which must be 1) can
1860          * be set to 0, meaning that L1 may turn off any of these bits. The
1861          * reason is that if one of these bits is necessary, it will appear
1862          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1863          * fields of vmcs01 and vmcs02, will turn these bits off - and
1864          * nested_vmx_exit_handled() will not pass related exits to L1.
1865          * These rules have exceptions below.
1866          */
1867
1868         /* pin-based controls */
1869         /*
1870          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1871          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1872          */
1873         nested_vmx_pinbased_ctls_low = 0x16 ;
1874         nested_vmx_pinbased_ctls_high = 0x16 |
1875                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1876                 PIN_BASED_VIRTUAL_NMIS;
1877
1878         /* exit controls */
1879         nested_vmx_exit_ctls_low = 0;
1880         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1881 #ifdef CONFIG_X86_64
1882         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1883 #else
1884         nested_vmx_exit_ctls_high = 0;
1885 #endif
1886
1887         /* entry controls */
1888         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1889                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1890         nested_vmx_entry_ctls_low = 0;
1891         nested_vmx_entry_ctls_high &=
1892                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1893
1894         /* cpu-based controls */
1895         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1896                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1897         nested_vmx_procbased_ctls_low = 0;
1898         nested_vmx_procbased_ctls_high &=
1899                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1900                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1901                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1902                 CPU_BASED_CR3_STORE_EXITING |
1903 #ifdef CONFIG_X86_64
1904                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1905 #endif
1906                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1907                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1908                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1909         /*
1910          * We can allow some features even when not supported by the
1911          * hardware. For example, L1 can specify an MSR bitmap - and we
1912          * can use it to avoid exits to L1 - even when L0 runs L2
1913          * without MSR bitmaps.
1914          */
1915         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1916
1917         /* secondary cpu-based controls */
1918         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1919                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1920         nested_vmx_secondary_ctls_low = 0;
1921         nested_vmx_secondary_ctls_high &=
1922                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1923 }
1924
1925 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1926 {
1927         /*
1928          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1929          */
1930         return ((control & high) | low) == control;
1931 }
1932
1933 static inline u64 vmx_control_msr(u32 low, u32 high)
1934 {
1935         return low | ((u64)high << 32);
1936 }
1937
1938 /*
1939  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1940  * also let it use VMX-specific MSRs.
1941  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1942  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1943  * like all other MSRs).
1944  */
1945 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1946 {
1947         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1948                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
1949                 /*
1950                  * According to the spec, processors which do not support VMX
1951                  * should throw a #GP(0) when VMX capability MSRs are read.
1952                  */
1953                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
1954                 return 1;
1955         }
1956
1957         switch (msr_index) {
1958         case MSR_IA32_FEATURE_CONTROL:
1959                 *pdata = 0;
1960                 break;
1961         case MSR_IA32_VMX_BASIC:
1962                 /*
1963                  * This MSR reports some information about VMX support. We
1964                  * should return information about the VMX we emulate for the
1965                  * guest, and the VMCS structure we give it - not about the
1966                  * VMX support of the underlying hardware.
1967                  */
1968                 *pdata = VMCS12_REVISION |
1969                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
1970                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
1971                 break;
1972         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
1973         case MSR_IA32_VMX_PINBASED_CTLS:
1974                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
1975                                         nested_vmx_pinbased_ctls_high);
1976                 break;
1977         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
1978         case MSR_IA32_VMX_PROCBASED_CTLS:
1979                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
1980                                         nested_vmx_procbased_ctls_high);
1981                 break;
1982         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
1983         case MSR_IA32_VMX_EXIT_CTLS:
1984                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
1985                                         nested_vmx_exit_ctls_high);
1986                 break;
1987         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
1988         case MSR_IA32_VMX_ENTRY_CTLS:
1989                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
1990                                         nested_vmx_entry_ctls_high);
1991                 break;
1992         case MSR_IA32_VMX_MISC:
1993                 *pdata = 0;
1994                 break;
1995         /*
1996          * These MSRs specify bits which the guest must keep fixed (on or off)
1997          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
1998          * We picked the standard core2 setting.
1999          */
2000 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2001 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2002         case MSR_IA32_VMX_CR0_FIXED0:
2003                 *pdata = VMXON_CR0_ALWAYSON;
2004                 break;
2005         case MSR_IA32_VMX_CR0_FIXED1:
2006                 *pdata = -1ULL;
2007                 break;
2008         case MSR_IA32_VMX_CR4_FIXED0:
2009                 *pdata = VMXON_CR4_ALWAYSON;
2010                 break;
2011         case MSR_IA32_VMX_CR4_FIXED1:
2012                 *pdata = -1ULL;
2013                 break;
2014         case MSR_IA32_VMX_VMCS_ENUM:
2015                 *pdata = 0x1f;
2016                 break;
2017         case MSR_IA32_VMX_PROCBASED_CTLS2:
2018                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2019                                         nested_vmx_secondary_ctls_high);
2020                 break;
2021         case MSR_IA32_VMX_EPT_VPID_CAP:
2022                 /* Currently, no nested ept or nested vpid */
2023                 *pdata = 0;
2024                 break;
2025         default:
2026                 return 0;
2027         }
2028
2029         return 1;
2030 }
2031
2032 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2033 {
2034         if (!nested_vmx_allowed(vcpu))
2035                 return 0;
2036
2037         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2038                 /* TODO: the right thing. */
2039                 return 1;
2040         /*
2041          * No need to treat VMX capability MSRs specially: If we don't handle
2042          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2043          */
2044         return 0;
2045 }
2046
2047 /*
2048  * Reads an msr value (of 'msr_index') into 'pdata'.
2049  * Returns 0 on success, non-0 otherwise.
2050  * Assumes vcpu_load() was already called.
2051  */
2052 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2053 {
2054         u64 data;
2055         struct shared_msr_entry *msr;
2056
2057         if (!pdata) {
2058                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2059                 return -EINVAL;
2060         }
2061
2062         switch (msr_index) {
2063 #ifdef CONFIG_X86_64
2064         case MSR_FS_BASE:
2065                 data = vmcs_readl(GUEST_FS_BASE);
2066                 break;
2067         case MSR_GS_BASE:
2068                 data = vmcs_readl(GUEST_GS_BASE);
2069                 break;
2070         case MSR_KERNEL_GS_BASE:
2071                 vmx_load_host_state(to_vmx(vcpu));
2072                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2073                 break;
2074 #endif
2075         case MSR_EFER:
2076                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2077         case MSR_IA32_TSC:
2078                 data = guest_read_tsc();
2079                 break;
2080         case MSR_IA32_SYSENTER_CS:
2081                 data = vmcs_read32(GUEST_SYSENTER_CS);
2082                 break;
2083         case MSR_IA32_SYSENTER_EIP:
2084                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2085                 break;
2086         case MSR_IA32_SYSENTER_ESP:
2087                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2088                 break;
2089         case MSR_TSC_AUX:
2090                 if (!to_vmx(vcpu)->rdtscp_enabled)
2091                         return 1;
2092                 /* Otherwise falls through */
2093         default:
2094                 vmx_load_host_state(to_vmx(vcpu));
2095                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2096                         return 0;
2097                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2098                 if (msr) {
2099                         vmx_load_host_state(to_vmx(vcpu));
2100                         data = msr->data;
2101                         break;
2102                 }
2103                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2104         }
2105
2106         *pdata = data;
2107         return 0;
2108 }
2109
2110 /*
2111  * Writes msr value into into the appropriate "register".
2112  * Returns 0 on success, non-0 otherwise.
2113  * Assumes vcpu_load() was already called.
2114  */
2115 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2116 {
2117         struct vcpu_vmx *vmx = to_vmx(vcpu);
2118         struct shared_msr_entry *msr;
2119         int ret = 0;
2120
2121         switch (msr_index) {
2122         case MSR_EFER:
2123                 vmx_load_host_state(vmx);
2124                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2125                 break;
2126 #ifdef CONFIG_X86_64
2127         case MSR_FS_BASE:
2128                 vmx_segment_cache_clear(vmx);
2129                 vmcs_writel(GUEST_FS_BASE, data);
2130                 break;
2131         case MSR_GS_BASE:
2132                 vmx_segment_cache_clear(vmx);
2133                 vmcs_writel(GUEST_GS_BASE, data);
2134                 break;
2135         case MSR_KERNEL_GS_BASE:
2136                 vmx_load_host_state(vmx);
2137                 vmx->msr_guest_kernel_gs_base = data;
2138                 break;
2139 #endif
2140         case MSR_IA32_SYSENTER_CS:
2141                 vmcs_write32(GUEST_SYSENTER_CS, data);
2142                 break;
2143         case MSR_IA32_SYSENTER_EIP:
2144                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2145                 break;
2146         case MSR_IA32_SYSENTER_ESP:
2147                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2148                 break;
2149         case MSR_IA32_TSC:
2150                 kvm_write_tsc(vcpu, data);
2151                 break;
2152         case MSR_IA32_CR_PAT:
2153                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2154                         vmcs_write64(GUEST_IA32_PAT, data);
2155                         vcpu->arch.pat = data;
2156                         break;
2157                 }
2158                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2159                 break;
2160         case MSR_TSC_AUX:
2161                 if (!vmx->rdtscp_enabled)
2162                         return 1;
2163                 /* Check reserved bit, higher 32 bits should be zero */
2164                 if ((data >> 32) != 0)
2165                         return 1;
2166                 /* Otherwise falls through */
2167         default:
2168                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2169                         break;
2170                 msr = find_msr_entry(vmx, msr_index);
2171                 if (msr) {
2172                         vmx_load_host_state(vmx);
2173                         msr->data = data;
2174                         break;
2175                 }
2176                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2177         }
2178
2179         return ret;
2180 }
2181
2182 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2183 {
2184         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2185         switch (reg) {
2186         case VCPU_REGS_RSP:
2187                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2188                 break;
2189         case VCPU_REGS_RIP:
2190                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2191                 break;
2192         case VCPU_EXREG_PDPTR:
2193                 if (enable_ept)
2194                         ept_save_pdptrs(vcpu);
2195                 break;
2196         default:
2197                 break;
2198         }
2199 }
2200
2201 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2202 {
2203         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2204                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2205         else
2206                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2207
2208         update_exception_bitmap(vcpu);
2209 }
2210
2211 static __init int cpu_has_kvm_support(void)
2212 {
2213         return cpu_has_vmx();
2214 }
2215
2216 static __init int vmx_disabled_by_bios(void)
2217 {
2218         u64 msr;
2219
2220         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2221         if (msr & FEATURE_CONTROL_LOCKED) {
2222                 /* launched w/ TXT and VMX disabled */
2223                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2224                         && tboot_enabled())
2225                         return 1;
2226                 /* launched w/o TXT and VMX only enabled w/ TXT */
2227                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2228                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2229                         && !tboot_enabled()) {
2230                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2231                                 "activate TXT before enabling KVM\n");
2232                         return 1;
2233                 }
2234                 /* launched w/o TXT and VMX disabled */
2235                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2236                         && !tboot_enabled())
2237                         return 1;
2238         }
2239
2240         return 0;
2241 }
2242
2243 static void kvm_cpu_vmxon(u64 addr)
2244 {
2245         asm volatile (ASM_VMX_VMXON_RAX
2246                         : : "a"(&addr), "m"(addr)
2247                         : "memory", "cc");
2248 }
2249
2250 static int hardware_enable(void *garbage)
2251 {
2252         int cpu = raw_smp_processor_id();
2253         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2254         u64 old, test_bits;
2255
2256         if (read_cr4() & X86_CR4_VMXE)
2257                 return -EBUSY;
2258
2259         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2260         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2261
2262         test_bits = FEATURE_CONTROL_LOCKED;
2263         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2264         if (tboot_enabled())
2265                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2266
2267         if ((old & test_bits) != test_bits) {
2268                 /* enable and lock */
2269                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2270         }
2271         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2272
2273         if (vmm_exclusive) {
2274                 kvm_cpu_vmxon(phys_addr);
2275                 ept_sync_global();
2276         }
2277
2278         store_gdt(&__get_cpu_var(host_gdt));
2279
2280         return 0;
2281 }
2282
2283 static void vmclear_local_loaded_vmcss(void)
2284 {
2285         int cpu = raw_smp_processor_id();
2286         struct loaded_vmcs *v, *n;
2287
2288         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2289                                  loaded_vmcss_on_cpu_link)
2290                 __loaded_vmcs_clear(v);
2291 }
2292
2293
2294 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2295  * tricks.
2296  */
2297 static void kvm_cpu_vmxoff(void)
2298 {
2299         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2300 }
2301
2302 static void hardware_disable(void *garbage)
2303 {
2304         if (vmm_exclusive) {
2305                 vmclear_local_loaded_vmcss();
2306                 kvm_cpu_vmxoff();
2307         }
2308         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2309 }
2310
2311 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2312                                       u32 msr, u32 *result)
2313 {
2314         u32 vmx_msr_low, vmx_msr_high;
2315         u32 ctl = ctl_min | ctl_opt;
2316
2317         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2318
2319         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2320         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2321
2322         /* Ensure minimum (required) set of control bits are supported. */
2323         if (ctl_min & ~ctl)
2324                 return -EIO;
2325
2326         *result = ctl;
2327         return 0;
2328 }
2329
2330 static __init bool allow_1_setting(u32 msr, u32 ctl)
2331 {
2332         u32 vmx_msr_low, vmx_msr_high;
2333
2334         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2335         return vmx_msr_high & ctl;
2336 }
2337
2338 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2339 {
2340         u32 vmx_msr_low, vmx_msr_high;
2341         u32 min, opt, min2, opt2;
2342         u32 _pin_based_exec_control = 0;
2343         u32 _cpu_based_exec_control = 0;
2344         u32 _cpu_based_2nd_exec_control = 0;
2345         u32 _vmexit_control = 0;
2346         u32 _vmentry_control = 0;
2347
2348         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2349         opt = PIN_BASED_VIRTUAL_NMIS;
2350         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2351                                 &_pin_based_exec_control) < 0)
2352                 return -EIO;
2353
2354         min =
2355 #ifdef CONFIG_X86_64
2356               CPU_BASED_CR8_LOAD_EXITING |
2357               CPU_BASED_CR8_STORE_EXITING |
2358 #endif
2359               CPU_BASED_CR3_LOAD_EXITING |
2360               CPU_BASED_CR3_STORE_EXITING |
2361               CPU_BASED_USE_IO_BITMAPS |
2362               CPU_BASED_MOV_DR_EXITING |
2363               CPU_BASED_USE_TSC_OFFSETING |
2364               CPU_BASED_MWAIT_EXITING |
2365               CPU_BASED_MONITOR_EXITING |
2366               CPU_BASED_INVLPG_EXITING;
2367
2368         if (yield_on_hlt)
2369                 min |= CPU_BASED_HLT_EXITING;
2370
2371         opt = CPU_BASED_TPR_SHADOW |
2372               CPU_BASED_USE_MSR_BITMAPS |
2373               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2374         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2375                                 &_cpu_based_exec_control) < 0)
2376                 return -EIO;
2377 #ifdef CONFIG_X86_64
2378         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2379                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2380                                            ~CPU_BASED_CR8_STORE_EXITING;
2381 #endif
2382         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2383                 min2 = 0;
2384                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2385                         SECONDARY_EXEC_WBINVD_EXITING |
2386                         SECONDARY_EXEC_ENABLE_VPID |
2387                         SECONDARY_EXEC_ENABLE_EPT |
2388                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2389                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2390                         SECONDARY_EXEC_RDTSCP;
2391                 if (adjust_vmx_controls(min2, opt2,
2392                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2393                                         &_cpu_based_2nd_exec_control) < 0)
2394                         return -EIO;
2395         }
2396 #ifndef CONFIG_X86_64
2397         if (!(_cpu_based_2nd_exec_control &
2398                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2399                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2400 #endif
2401         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2402                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2403                    enabled */
2404                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2405                                              CPU_BASED_CR3_STORE_EXITING |
2406                                              CPU_BASED_INVLPG_EXITING);
2407                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2408                       vmx_capability.ept, vmx_capability.vpid);
2409         }
2410
2411         min = 0;
2412 #ifdef CONFIG_X86_64
2413         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2414 #endif
2415         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2416         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2417                                 &_vmexit_control) < 0)
2418                 return -EIO;
2419
2420         min = 0;
2421         opt = VM_ENTRY_LOAD_IA32_PAT;
2422         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2423                                 &_vmentry_control) < 0)
2424                 return -EIO;
2425
2426         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2427
2428         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2429         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2430                 return -EIO;
2431
2432 #ifdef CONFIG_X86_64
2433         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2434         if (vmx_msr_high & (1u<<16))
2435                 return -EIO;
2436 #endif
2437
2438         /* Require Write-Back (WB) memory type for VMCS accesses. */
2439         if (((vmx_msr_high >> 18) & 15) != 6)
2440                 return -EIO;
2441
2442         vmcs_conf->size = vmx_msr_high & 0x1fff;
2443         vmcs_conf->order = get_order(vmcs_config.size);
2444         vmcs_conf->revision_id = vmx_msr_low;
2445
2446         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2447         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2448         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2449         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2450         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2451
2452         cpu_has_load_ia32_efer =
2453                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2454                                 VM_ENTRY_LOAD_IA32_EFER)
2455                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2456                                    VM_EXIT_LOAD_IA32_EFER);
2457
2458         return 0;
2459 }
2460
2461 static struct vmcs *alloc_vmcs_cpu(int cpu)
2462 {
2463         int node = cpu_to_node(cpu);
2464         struct page *pages;
2465         struct vmcs *vmcs;
2466
2467         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2468         if (!pages)
2469                 return NULL;
2470         vmcs = page_address(pages);
2471         memset(vmcs, 0, vmcs_config.size);
2472         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2473         return vmcs;
2474 }
2475
2476 static struct vmcs *alloc_vmcs(void)
2477 {
2478         return alloc_vmcs_cpu(raw_smp_processor_id());
2479 }
2480
2481 static void free_vmcs(struct vmcs *vmcs)
2482 {
2483         free_pages((unsigned long)vmcs, vmcs_config.order);
2484 }
2485
2486 /*
2487  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2488  */
2489 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2490 {
2491         if (!loaded_vmcs->vmcs)
2492                 return;
2493         loaded_vmcs_clear(loaded_vmcs);
2494         free_vmcs(loaded_vmcs->vmcs);
2495         loaded_vmcs->vmcs = NULL;
2496 }
2497
2498 static void free_kvm_area(void)
2499 {
2500         int cpu;
2501
2502         for_each_possible_cpu(cpu) {
2503                 free_vmcs(per_cpu(vmxarea, cpu));
2504                 per_cpu(vmxarea, cpu) = NULL;
2505         }
2506 }
2507
2508 static __init int alloc_kvm_area(void)
2509 {
2510         int cpu;
2511
2512         for_each_possible_cpu(cpu) {
2513                 struct vmcs *vmcs;
2514
2515                 vmcs = alloc_vmcs_cpu(cpu);
2516                 if (!vmcs) {
2517                         free_kvm_area();
2518                         return -ENOMEM;
2519                 }
2520
2521                 per_cpu(vmxarea, cpu) = vmcs;
2522         }
2523         return 0;
2524 }
2525
2526 static __init int hardware_setup(void)
2527 {
2528         if (setup_vmcs_config(&vmcs_config) < 0)
2529                 return -EIO;
2530
2531         if (boot_cpu_has(X86_FEATURE_NX))
2532                 kvm_enable_efer_bits(EFER_NX);
2533
2534         if (!cpu_has_vmx_vpid())
2535                 enable_vpid = 0;
2536
2537         if (!cpu_has_vmx_ept() ||
2538             !cpu_has_vmx_ept_4levels()) {
2539                 enable_ept = 0;
2540                 enable_unrestricted_guest = 0;
2541         }
2542
2543         if (!cpu_has_vmx_unrestricted_guest())
2544                 enable_unrestricted_guest = 0;
2545
2546         if (!cpu_has_vmx_flexpriority())
2547                 flexpriority_enabled = 0;
2548
2549         if (!cpu_has_vmx_tpr_shadow())
2550                 kvm_x86_ops->update_cr8_intercept = NULL;
2551
2552         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2553                 kvm_disable_largepages();
2554
2555         if (!cpu_has_vmx_ple())
2556                 ple_gap = 0;
2557
2558         if (nested)
2559                 nested_vmx_setup_ctls_msrs();
2560
2561         return alloc_kvm_area();
2562 }
2563
2564 static __exit void hardware_unsetup(void)
2565 {
2566         free_kvm_area();
2567 }
2568
2569 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2570 {
2571         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2572
2573         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2574                 vmcs_write16(sf->selector, save->selector);
2575                 vmcs_writel(sf->base, save->base);
2576                 vmcs_write32(sf->limit, save->limit);
2577                 vmcs_write32(sf->ar_bytes, save->ar);
2578         } else {
2579                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2580                         << AR_DPL_SHIFT;
2581                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2582         }
2583 }
2584
2585 static void enter_pmode(struct kvm_vcpu *vcpu)
2586 {
2587         unsigned long flags;
2588         struct vcpu_vmx *vmx = to_vmx(vcpu);
2589
2590         vmx->emulation_required = 1;
2591         vmx->rmode.vm86_active = 0;
2592
2593         vmx_segment_cache_clear(vmx);
2594
2595         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2596         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2597         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2598         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2599
2600         flags = vmcs_readl(GUEST_RFLAGS);
2601         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2602         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2603         vmcs_writel(GUEST_RFLAGS, flags);
2604
2605         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2606                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2607
2608         update_exception_bitmap(vcpu);
2609
2610         if (emulate_invalid_guest_state)
2611                 return;
2612
2613         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2614         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2615         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2616         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2617
2618         vmx_segment_cache_clear(vmx);
2619
2620         vmcs_write16(GUEST_SS_SELECTOR, 0);
2621         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2622
2623         vmcs_write16(GUEST_CS_SELECTOR,
2624                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2625         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2626 }
2627
2628 static gva_t rmode_tss_base(struct kvm *kvm)
2629 {
2630         if (!kvm->arch.tss_addr) {
2631                 struct kvm_memslots *slots;
2632                 gfn_t base_gfn;
2633
2634                 slots = kvm_memslots(kvm);
2635                 base_gfn = slots->memslots[0].base_gfn +
2636                                  kvm->memslots->memslots[0].npages - 3;
2637                 return base_gfn << PAGE_SHIFT;
2638         }
2639         return kvm->arch.tss_addr;
2640 }
2641
2642 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2643 {
2644         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2645
2646         save->selector = vmcs_read16(sf->selector);
2647         save->base = vmcs_readl(sf->base);
2648         save->limit = vmcs_read32(sf->limit);
2649         save->ar = vmcs_read32(sf->ar_bytes);
2650         vmcs_write16(sf->selector, save->base >> 4);
2651         vmcs_write32(sf->base, save->base & 0xffff0);
2652         vmcs_write32(sf->limit, 0xffff);
2653         vmcs_write32(sf->ar_bytes, 0xf3);
2654         if (save->base & 0xf)
2655                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2656                             " aligned when entering protected mode (seg=%d)",
2657                             seg);
2658 }
2659
2660 static void enter_rmode(struct kvm_vcpu *vcpu)
2661 {
2662         unsigned long flags;
2663         struct vcpu_vmx *vmx = to_vmx(vcpu);
2664
2665         if (enable_unrestricted_guest)
2666                 return;
2667
2668         vmx->emulation_required = 1;
2669         vmx->rmode.vm86_active = 1;
2670
2671         /*
2672          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2673          * vcpu. Call it here with phys address pointing 16M below 4G.
2674          */
2675         if (!vcpu->kvm->arch.tss_addr) {
2676                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2677                              "called before entering vcpu\n");
2678                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2679                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2680                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2681         }
2682
2683         vmx_segment_cache_clear(vmx);
2684
2685         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2686         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2687         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2688
2689         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2690         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2691
2692         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2693         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2694
2695         flags = vmcs_readl(GUEST_RFLAGS);
2696         vmx->rmode.save_rflags = flags;
2697
2698         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2699
2700         vmcs_writel(GUEST_RFLAGS, flags);
2701         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2702         update_exception_bitmap(vcpu);
2703
2704         if (emulate_invalid_guest_state)
2705                 goto continue_rmode;
2706
2707         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2708         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2709         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2710
2711         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2712         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2713         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2714                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2715         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2716
2717         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2718         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2719         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2720         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2721
2722 continue_rmode:
2723         kvm_mmu_reset_context(vcpu);
2724 }
2725
2726 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2727 {
2728         struct vcpu_vmx *vmx = to_vmx(vcpu);
2729         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2730
2731         if (!msr)
2732                 return;
2733
2734         /*
2735          * Force kernel_gs_base reloading before EFER changes, as control
2736          * of this msr depends on is_long_mode().
2737          */
2738         vmx_load_host_state(to_vmx(vcpu));
2739         vcpu->arch.efer = efer;
2740         if (efer & EFER_LMA) {
2741                 vmcs_write32(VM_ENTRY_CONTROLS,
2742                              vmcs_read32(VM_ENTRY_CONTROLS) |
2743                              VM_ENTRY_IA32E_MODE);
2744                 msr->data = efer;
2745         } else {
2746                 vmcs_write32(VM_ENTRY_CONTROLS,
2747                              vmcs_read32(VM_ENTRY_CONTROLS) &
2748                              ~VM_ENTRY_IA32E_MODE);
2749
2750                 msr->data = efer & ~EFER_LME;
2751         }
2752         setup_msrs(vmx);
2753 }
2754
2755 #ifdef CONFIG_X86_64
2756
2757 static void enter_lmode(struct kvm_vcpu *vcpu)
2758 {
2759         u32 guest_tr_ar;
2760
2761         vmx_segment_cache_clear(to_vmx(vcpu));
2762
2763         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2764         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2765                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2766                                      __func__);
2767                 vmcs_write32(GUEST_TR_AR_BYTES,
2768                              (guest_tr_ar & ~AR_TYPE_MASK)
2769                              | AR_TYPE_BUSY_64_TSS);
2770         }
2771         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2772 }
2773
2774 static void exit_lmode(struct kvm_vcpu *vcpu)
2775 {
2776         vmcs_write32(VM_ENTRY_CONTROLS,
2777                      vmcs_read32(VM_ENTRY_CONTROLS)
2778                      & ~VM_ENTRY_IA32E_MODE);
2779         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2780 }
2781
2782 #endif
2783
2784 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2785 {
2786         vpid_sync_context(to_vmx(vcpu));
2787         if (enable_ept) {
2788                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2789                         return;
2790                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2791         }
2792 }
2793
2794 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2795 {
2796         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2797
2798         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2799         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2800 }
2801
2802 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2803 {
2804         if (enable_ept && is_paging(vcpu))
2805                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2806         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2807 }
2808
2809 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2810 {
2811         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2812
2813         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2814         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2815 }
2816
2817 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2818 {
2819         if (!test_bit(VCPU_EXREG_PDPTR,
2820                       (unsigned long *)&vcpu->arch.regs_dirty))
2821                 return;
2822
2823         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2824                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2825                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2826                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2827                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2828         }
2829 }
2830
2831 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2832 {
2833         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2834                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2835                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2836                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2837                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2838         }
2839
2840         __set_bit(VCPU_EXREG_PDPTR,
2841                   (unsigned long *)&vcpu->arch.regs_avail);
2842         __set_bit(VCPU_EXREG_PDPTR,
2843                   (unsigned long *)&vcpu->arch.regs_dirty);
2844 }
2845
2846 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2847
2848 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2849                                         unsigned long cr0,
2850                                         struct kvm_vcpu *vcpu)
2851 {
2852         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2853                 vmx_decache_cr3(vcpu);
2854         if (!(cr0 & X86_CR0_PG)) {
2855                 /* From paging/starting to nonpaging */
2856                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2857                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2858                              (CPU_BASED_CR3_LOAD_EXITING |
2859                               CPU_BASED_CR3_STORE_EXITING));
2860                 vcpu->arch.cr0 = cr0;
2861                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2862         } else if (!is_paging(vcpu)) {
2863                 /* From nonpaging to paging */
2864                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2865                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2866                              ~(CPU_BASED_CR3_LOAD_EXITING |
2867                                CPU_BASED_CR3_STORE_EXITING));
2868                 vcpu->arch.cr0 = cr0;
2869                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2870         }
2871
2872         if (!(cr0 & X86_CR0_WP))
2873                 *hw_cr0 &= ~X86_CR0_WP;
2874 }
2875
2876 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2877 {
2878         struct vcpu_vmx *vmx = to_vmx(vcpu);
2879         unsigned long hw_cr0;
2880
2881         if (enable_unrestricted_guest)
2882                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2883                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2884         else
2885                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2886
2887         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2888                 enter_pmode(vcpu);
2889
2890         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2891                 enter_rmode(vcpu);
2892
2893 #ifdef CONFIG_X86_64
2894         if (vcpu->arch.efer & EFER_LME) {
2895                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2896                         enter_lmode(vcpu);
2897                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2898                         exit_lmode(vcpu);
2899         }
2900 #endif
2901
2902         if (enable_ept)
2903                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2904
2905         if (!vcpu->fpu_active)
2906                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2907
2908         vmcs_writel(CR0_READ_SHADOW, cr0);
2909         vmcs_writel(GUEST_CR0, hw_cr0);
2910         vcpu->arch.cr0 = cr0;
2911         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2912 }
2913
2914 static u64 construct_eptp(unsigned long root_hpa)
2915 {
2916         u64 eptp;
2917
2918         /* TODO write the value reading from MSR */
2919         eptp = VMX_EPT_DEFAULT_MT |
2920                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
2921         eptp |= (root_hpa & PAGE_MASK);
2922
2923         return eptp;
2924 }
2925
2926 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
2927 {
2928         unsigned long guest_cr3;
2929         u64 eptp;
2930
2931         guest_cr3 = cr3;
2932         if (enable_ept) {
2933                 eptp = construct_eptp(cr3);
2934                 vmcs_write64(EPT_POINTER, eptp);
2935                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
2936                         vcpu->kvm->arch.ept_identity_map_addr;
2937                 ept_load_pdptrs(vcpu);
2938         }
2939
2940         vmx_flush_tlb(vcpu);
2941         vmcs_writel(GUEST_CR3, guest_cr3);
2942 }
2943
2944 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
2945 {
2946         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
2947                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
2948
2949         if (cr4 & X86_CR4_VMXE) {
2950                 /*
2951                  * To use VMXON (and later other VMX instructions), a guest
2952                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
2953                  * So basically the check on whether to allow nested VMX
2954                  * is here.
2955                  */
2956                 if (!nested_vmx_allowed(vcpu))
2957                         return 1;
2958         } else if (to_vmx(vcpu)->nested.vmxon)
2959                 return 1;
2960
2961         vcpu->arch.cr4 = cr4;
2962         if (enable_ept) {
2963                 if (!is_paging(vcpu)) {
2964                         hw_cr4 &= ~X86_CR4_PAE;
2965                         hw_cr4 |= X86_CR4_PSE;
2966                 } else if (!(cr4 & X86_CR4_PAE)) {
2967                         hw_cr4 &= ~X86_CR4_PAE;
2968                 }
2969         }
2970
2971         vmcs_writel(CR4_READ_SHADOW, cr4);
2972         vmcs_writel(GUEST_CR4, hw_cr4);
2973         return 0;
2974 }
2975
2976 static void vmx_get_segment(struct kvm_vcpu *vcpu,
2977                             struct kvm_segment *var, int seg)
2978 {
2979         struct vcpu_vmx *vmx = to_vmx(vcpu);
2980         struct kvm_save_segment *save;
2981         u32 ar;
2982
2983         if (vmx->rmode.vm86_active
2984             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
2985                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
2986                 || seg == VCPU_SREG_GS)
2987             && !emulate_invalid_guest_state) {
2988                 switch (seg) {
2989                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
2990                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
2991                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
2992                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
2993                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
2994                 default: BUG();
2995                 }
2996                 var->selector = save->selector;
2997                 var->base = save->base;
2998                 var->limit = save->limit;
2999                 ar = save->ar;
3000                 if (seg == VCPU_SREG_TR
3001                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3002                         goto use_saved_rmode_seg;
3003         }
3004         var->base = vmx_read_guest_seg_base(vmx, seg);
3005         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3006         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3007         ar = vmx_read_guest_seg_ar(vmx, seg);
3008 use_saved_rmode_seg:
3009         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3010                 ar = 0;
3011         var->type = ar & 15;
3012         var->s = (ar >> 4) & 1;
3013         var->dpl = (ar >> 5) & 3;
3014         var->present = (ar >> 7) & 1;
3015         var->avl = (ar >> 12) & 1;
3016         var->l = (ar >> 13) & 1;
3017         var->db = (ar >> 14) & 1;
3018         var->g = (ar >> 15) & 1;
3019         var->unusable = (ar >> 16) & 1;
3020 }
3021
3022 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3023 {
3024         struct kvm_segment s;
3025
3026         if (to_vmx(vcpu)->rmode.vm86_active) {
3027                 vmx_get_segment(vcpu, &s, seg);
3028                 return s.base;
3029         }
3030         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3031 }
3032
3033 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3034 {
3035         if (!is_protmode(vcpu))
3036                 return 0;
3037
3038         if (!is_long_mode(vcpu)
3039             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3040                 return 3;
3041
3042         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3043 }
3044
3045 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3046 {
3047         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3048                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3049                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3050         }
3051         return to_vmx(vcpu)->cpl;
3052 }
3053
3054
3055 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3056 {
3057         u32 ar;
3058
3059         if (var->unusable)
3060                 ar = 1 << 16;
3061         else {
3062                 ar = var->type & 15;
3063                 ar |= (var->s & 1) << 4;
3064                 ar |= (var->dpl & 3) << 5;
3065                 ar |= (var->present & 1) << 7;
3066                 ar |= (var->avl & 1) << 12;
3067                 ar |= (var->l & 1) << 13;
3068                 ar |= (var->db & 1) << 14;
3069                 ar |= (var->g & 1) << 15;
3070         }
3071         if (ar == 0) /* a 0 value means unusable */
3072                 ar = AR_UNUSABLE_MASK;
3073
3074         return ar;
3075 }
3076
3077 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3078                             struct kvm_segment *var, int seg)
3079 {
3080         struct vcpu_vmx *vmx = to_vmx(vcpu);
3081         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3082         u32 ar;
3083
3084         vmx_segment_cache_clear(vmx);
3085
3086         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3087                 vmcs_write16(sf->selector, var->selector);
3088                 vmx->rmode.tr.selector = var->selector;
3089                 vmx->rmode.tr.base = var->base;
3090                 vmx->rmode.tr.limit = var->limit;
3091                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3092                 return;
3093         }
3094         vmcs_writel(sf->base, var->base);
3095         vmcs_write32(sf->limit, var->limit);
3096         vmcs_write16(sf->selector, var->selector);
3097         if (vmx->rmode.vm86_active && var->s) {
3098                 /*
3099                  * Hack real-mode segments into vm86 compatibility.
3100                  */
3101                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3102                         vmcs_writel(sf->base, 0xf0000);
3103                 ar = 0xf3;
3104         } else
3105                 ar = vmx_segment_access_rights(var);
3106
3107         /*
3108          *   Fix the "Accessed" bit in AR field of segment registers for older
3109          * qemu binaries.
3110          *   IA32 arch specifies that at the time of processor reset the
3111          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3112          * is setting it to 0 in the usedland code. This causes invalid guest
3113          * state vmexit when "unrestricted guest" mode is turned on.
3114          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3115          * tree. Newer qemu binaries with that qemu fix would not need this
3116          * kvm hack.
3117          */
3118         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3119                 ar |= 0x1; /* Accessed */
3120
3121         vmcs_write32(sf->ar_bytes, ar);
3122         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3123 }
3124
3125 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3126 {
3127         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3128
3129         *db = (ar >> 14) & 1;
3130         *l = (ar >> 13) & 1;
3131 }
3132
3133 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3134 {
3135         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3136         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3137 }
3138
3139 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3140 {
3141         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3142         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3143 }
3144
3145 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3146 {
3147         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3148         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3149 }
3150
3151 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3152 {
3153         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3154         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3155 }
3156
3157 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3158 {
3159         struct kvm_segment var;
3160         u32 ar;
3161
3162         vmx_get_segment(vcpu, &var, seg);
3163         ar = vmx_segment_access_rights(&var);
3164
3165         if (var.base != (var.selector << 4))
3166                 return false;
3167         if (var.limit != 0xffff)
3168                 return false;
3169         if (ar != 0xf3)
3170                 return false;
3171
3172         return true;
3173 }
3174
3175 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3176 {
3177         struct kvm_segment cs;
3178         unsigned int cs_rpl;
3179
3180         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3181         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3182
3183         if (cs.unusable)
3184                 return false;
3185         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3186                 return false;
3187         if (!cs.s)
3188                 return false;
3189         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3190                 if (cs.dpl > cs_rpl)
3191                         return false;
3192         } else {
3193                 if (cs.dpl != cs_rpl)
3194                         return false;
3195         }
3196         if (!cs.present)
3197                 return false;
3198
3199         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3200         return true;
3201 }
3202
3203 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3204 {
3205         struct kvm_segment ss;
3206         unsigned int ss_rpl;
3207
3208         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3209         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3210
3211         if (ss.unusable)
3212                 return true;
3213         if (ss.type != 3 && ss.type != 7)
3214                 return false;
3215         if (!ss.s)
3216                 return false;
3217         if (ss.dpl != ss_rpl) /* DPL != RPL */
3218                 return false;
3219         if (!ss.present)
3220                 return false;
3221
3222         return true;
3223 }
3224
3225 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3226 {
3227         struct kvm_segment var;
3228         unsigned int rpl;
3229
3230         vmx_get_segment(vcpu, &var, seg);
3231         rpl = var.selector & SELECTOR_RPL_MASK;
3232
3233         if (var.unusable)
3234                 return true;
3235         if (!var.s)
3236                 return false;
3237         if (!var.present)
3238                 return false;
3239         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3240                 if (var.dpl < rpl) /* DPL < RPL */
3241                         return false;
3242         }
3243
3244         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3245          * rights flags
3246          */
3247         return true;
3248 }
3249
3250 static bool tr_valid(struct kvm_vcpu *vcpu)
3251 {
3252         struct kvm_segment tr;
3253
3254         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3255
3256         if (tr.unusable)
3257                 return false;
3258         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3259                 return false;
3260         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3261                 return false;
3262         if (!tr.present)
3263                 return false;
3264
3265         return true;
3266 }
3267
3268 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3269 {
3270         struct kvm_segment ldtr;
3271
3272         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3273
3274         if (ldtr.unusable)
3275                 return true;
3276         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3277                 return false;
3278         if (ldtr.type != 2)
3279                 return false;
3280         if (!ldtr.present)
3281                 return false;
3282
3283         return true;
3284 }
3285
3286 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3287 {
3288         struct kvm_segment cs, ss;
3289
3290         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3291         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3292
3293         return ((cs.selector & SELECTOR_RPL_MASK) ==
3294                  (ss.selector & SELECTOR_RPL_MASK));
3295 }
3296
3297 /*
3298  * Check if guest state is valid. Returns true if valid, false if
3299  * not.
3300  * We assume that registers are always usable
3301  */
3302 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3303 {
3304         /* real mode guest state checks */
3305         if (!is_protmode(vcpu)) {
3306                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3307                         return false;
3308                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3309                         return false;
3310                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3311                         return false;
3312                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3313                         return false;
3314                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3315                         return false;
3316                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3317                         return false;
3318         } else {
3319         /* protected mode guest state checks */
3320                 if (!cs_ss_rpl_check(vcpu))
3321                         return false;
3322                 if (!code_segment_valid(vcpu))
3323                         return false;
3324                 if (!stack_segment_valid(vcpu))
3325                         return false;
3326                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3327                         return false;
3328                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3329                         return false;
3330                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3331                         return false;
3332                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3333                         return false;
3334                 if (!tr_valid(vcpu))
3335                         return false;
3336                 if (!ldtr_valid(vcpu))
3337                         return false;
3338         }
3339         /* TODO:
3340          * - Add checks on RIP
3341          * - Add checks on RFLAGS
3342          */
3343
3344         return true;
3345 }
3346
3347 static int init_rmode_tss(struct kvm *kvm)
3348 {
3349         gfn_t fn;
3350         u16 data = 0;
3351         int r, idx, ret = 0;
3352
3353         idx = srcu_read_lock(&kvm->srcu);
3354         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3355         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3356         if (r < 0)
3357                 goto out;
3358         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3359         r = kvm_write_guest_page(kvm, fn++, &data,
3360                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3361         if (r < 0)
3362                 goto out;
3363         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3364         if (r < 0)
3365                 goto out;
3366         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3367         if (r < 0)
3368                 goto out;
3369         data = ~0;
3370         r = kvm_write_guest_page(kvm, fn, &data,
3371                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3372                                  sizeof(u8));
3373         if (r < 0)
3374                 goto out;
3375
3376         ret = 1;
3377 out:
3378         srcu_read_unlock(&kvm->srcu, idx);
3379         return ret;
3380 }
3381
3382 static int init_rmode_identity_map(struct kvm *kvm)
3383 {
3384         int i, idx, r, ret;
3385         pfn_t identity_map_pfn;
3386         u32 tmp;
3387
3388         if (!enable_ept)
3389                 return 1;
3390         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3391                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3392                         "haven't been allocated!\n");
3393                 return 0;
3394         }
3395         if (likely(kvm->arch.ept_identity_pagetable_done))
3396                 return 1;
3397         ret = 0;
3398         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3399         idx = srcu_read_lock(&kvm->srcu);
3400         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3401         if (r < 0)
3402                 goto out;
3403         /* Set up identity-mapping pagetable for EPT in real mode */
3404         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3405                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3406                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3407                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3408                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3409                 if (r < 0)
3410                         goto out;
3411         }
3412         kvm->arch.ept_identity_pagetable_done = true;
3413         ret = 1;
3414 out:
3415         srcu_read_unlock(&kvm->srcu, idx);
3416         return ret;
3417 }
3418
3419 static void seg_setup(int seg)
3420 {
3421         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3422         unsigned int ar;
3423
3424         vmcs_write16(sf->selector, 0);
3425         vmcs_writel(sf->base, 0);
3426         vmcs_write32(sf->limit, 0xffff);
3427         if (enable_unrestricted_guest) {
3428                 ar = 0x93;
3429                 if (seg == VCPU_SREG_CS)
3430                         ar |= 0x08; /* code segment */
3431         } else
3432                 ar = 0xf3;
3433
3434         vmcs_write32(sf->ar_bytes, ar);
3435 }
3436
3437 static int alloc_apic_access_page(struct kvm *kvm)
3438 {
3439         struct kvm_userspace_memory_region kvm_userspace_mem;
3440         int r = 0;
3441
3442         mutex_lock(&kvm->slots_lock);
3443         if (kvm->arch.apic_access_page)
3444                 goto out;
3445         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3446         kvm_userspace_mem.flags = 0;
3447         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3448         kvm_userspace_mem.memory_size = PAGE_SIZE;
3449         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3450         if (r)
3451                 goto out;
3452
3453         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3454 out:
3455         mutex_unlock(&kvm->slots_lock);
3456         return r;
3457 }
3458
3459 static int alloc_identity_pagetable(struct kvm *kvm)
3460 {
3461         struct kvm_userspace_memory_region kvm_userspace_mem;
3462         int r = 0;
3463
3464         mutex_lock(&kvm->slots_lock);
3465         if (kvm->arch.ept_identity_pagetable)
3466                 goto out;
3467         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3468         kvm_userspace_mem.flags = 0;
3469         kvm_userspace_mem.guest_phys_addr =
3470                 kvm->arch.ept_identity_map_addr;
3471         kvm_userspace_mem.memory_size = PAGE_SIZE;
3472         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3473         if (r)
3474                 goto out;
3475
3476         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3477                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3478 out:
3479         mutex_unlock(&kvm->slots_lock);
3480         return r;
3481 }
3482
3483 static void allocate_vpid(struct vcpu_vmx *vmx)
3484 {
3485         int vpid;
3486
3487         vmx->vpid = 0;
3488         if (!enable_vpid)
3489                 return;
3490         spin_lock(&vmx_vpid_lock);
3491         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3492         if (vpid < VMX_NR_VPIDS) {
3493                 vmx->vpid = vpid;
3494                 __set_bit(vpid, vmx_vpid_bitmap);
3495         }
3496         spin_unlock(&vmx_vpid_lock);
3497 }
3498
3499 static void free_vpid(struct vcpu_vmx *vmx)
3500 {
3501         if (!enable_vpid)
3502                 return;
3503         spin_lock(&vmx_vpid_lock);
3504         if (vmx->vpid != 0)
3505                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3506         spin_unlock(&vmx_vpid_lock);
3507 }
3508
3509 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3510 {
3511         int f = sizeof(unsigned long);
3512
3513         if (!cpu_has_vmx_msr_bitmap())
3514                 return;
3515
3516         /*
3517          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3518          * have the write-low and read-high bitmap offsets the wrong way round.
3519          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3520          */
3521         if (msr <= 0x1fff) {
3522                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3523                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3524         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3525                 msr &= 0x1fff;
3526                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3527                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3528         }
3529 }
3530
3531 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3532 {
3533         if (!longmode_only)
3534                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3535         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3536 }
3537
3538 /*
3539  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3540  * will not change in the lifetime of the guest.
3541  * Note that host-state that does change is set elsewhere. E.g., host-state
3542  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3543  */
3544 static void vmx_set_constant_host_state(void)
3545 {
3546         u32 low32, high32;
3547         unsigned long tmpl;
3548         struct desc_ptr dt;
3549
3550         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3551         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3552         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3553
3554         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3555         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3556         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3557         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3558         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3559
3560         native_store_idt(&dt);
3561         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3562
3563         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3564         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3565
3566         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3567         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3568         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3569         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3570
3571         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3572                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3573                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3574         }
3575 }
3576
3577 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3578 {
3579         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3580         if (enable_ept)
3581                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3582         if (is_guest_mode(&vmx->vcpu))
3583                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3584                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3585         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3586 }
3587
3588 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3589 {
3590         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3591         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3592                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3593 #ifdef CONFIG_X86_64
3594                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3595                                 CPU_BASED_CR8_LOAD_EXITING;
3596 #endif
3597         }
3598         if (!enable_ept)
3599                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3600                                 CPU_BASED_CR3_LOAD_EXITING  |
3601                                 CPU_BASED_INVLPG_EXITING;
3602         return exec_control;
3603 }
3604
3605 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3606 {
3607         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3608         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3609                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3610         if (vmx->vpid == 0)
3611                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3612         if (!enable_ept) {
3613                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3614                 enable_unrestricted_guest = 0;
3615         }
3616         if (!enable_unrestricted_guest)
3617                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3618         if (!ple_gap)
3619                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3620         return exec_control;
3621 }
3622
3623 static void ept_set_mmio_spte_mask(void)
3624 {
3625         /*
3626          * EPT Misconfigurations can be generated if the value of bits 2:0
3627          * of an EPT paging-structure entry is 110b (write/execute).
3628          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3629          * spte.
3630          */
3631         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3632 }
3633
3634 /*
3635  * Sets up the vmcs for emulated real mode.
3636  */
3637 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3638 {
3639 #ifdef CONFIG_X86_64
3640         unsigned long a;
3641 #endif
3642         int i;
3643
3644         /* I/O */
3645         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3646         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3647
3648         if (cpu_has_vmx_msr_bitmap())
3649                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3650
3651         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3652
3653         /* Control */
3654         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3655                 vmcs_config.pin_based_exec_ctrl);
3656
3657         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3658
3659         if (cpu_has_secondary_exec_ctrls()) {
3660                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3661                                 vmx_secondary_exec_control(vmx));
3662         }
3663
3664         if (ple_gap) {
3665                 vmcs_write32(PLE_GAP, ple_gap);
3666                 vmcs_write32(PLE_WINDOW, ple_window);
3667         }
3668
3669         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3670         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3671         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3672
3673         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3674         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3675         vmx_set_constant_host_state();
3676 #ifdef CONFIG_X86_64
3677         rdmsrl(MSR_FS_BASE, a);
3678         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3679         rdmsrl(MSR_GS_BASE, a);
3680         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3681 #else
3682         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3683         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3684 #endif
3685
3686         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3687         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3688         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3689         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3690         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3691
3692         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3693                 u32 msr_low, msr_high;
3694                 u64 host_pat;
3695                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3696                 host_pat = msr_low | ((u64) msr_high << 32);
3697                 /* Write the default value follow host pat */
3698                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3699                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3700                 vmx->vcpu.arch.pat = host_pat;
3701         }
3702
3703         for (i = 0; i < NR_VMX_MSR; ++i) {
3704                 u32 index = vmx_msr_index[i];
3705                 u32 data_low, data_high;
3706                 int j = vmx->nmsrs;
3707
3708                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3709                         continue;
3710                 if (wrmsr_safe(index, data_low, data_high) < 0)
3711                         continue;
3712                 vmx->guest_msrs[j].index = i;
3713                 vmx->guest_msrs[j].data = 0;
3714                 vmx->guest_msrs[j].mask = -1ull;
3715                 ++vmx->nmsrs;
3716         }
3717
3718         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3719
3720         /* 22.2.1, 20.8.1 */
3721         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3722
3723         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3724         set_cr4_guest_host_mask(vmx);
3725
3726         kvm_write_tsc(&vmx->vcpu, 0);
3727
3728         return 0;
3729 }
3730
3731 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3732 {
3733         struct vcpu_vmx *vmx = to_vmx(vcpu);
3734         u64 msr;
3735         int ret;
3736
3737         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3738
3739         vmx->rmode.vm86_active = 0;
3740
3741         vmx->soft_vnmi_blocked = 0;
3742
3743         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3744         kvm_set_cr8(&vmx->vcpu, 0);
3745         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3746         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3747                 msr |= MSR_IA32_APICBASE_BSP;
3748         kvm_set_apic_base(&vmx->vcpu, msr);
3749
3750         ret = fx_init(&vmx->vcpu);
3751         if (ret != 0)
3752                 goto out;
3753
3754         vmx_segment_cache_clear(vmx);
3755
3756         seg_setup(VCPU_SREG_CS);
3757         /*
3758          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3759          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3760          */
3761         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3762                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3763                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3764         } else {
3765                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3766                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3767         }
3768
3769         seg_setup(VCPU_SREG_DS);
3770         seg_setup(VCPU_SREG_ES);
3771         seg_setup(VCPU_SREG_FS);
3772         seg_setup(VCPU_SREG_GS);
3773         seg_setup(VCPU_SREG_SS);
3774
3775         vmcs_write16(GUEST_TR_SELECTOR, 0);
3776         vmcs_writel(GUEST_TR_BASE, 0);
3777         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3778         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3779
3780         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3781         vmcs_writel(GUEST_LDTR_BASE, 0);
3782         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3783         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3784
3785         vmcs_write32(GUEST_SYSENTER_CS, 0);
3786         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3787         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3788
3789         vmcs_writel(GUEST_RFLAGS, 0x02);
3790         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3791                 kvm_rip_write(vcpu, 0xfff0);
3792         else
3793                 kvm_rip_write(vcpu, 0);
3794         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3795
3796         vmcs_writel(GUEST_DR7, 0x400);
3797
3798         vmcs_writel(GUEST_GDTR_BASE, 0);
3799         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3800
3801         vmcs_writel(GUEST_IDTR_BASE, 0);
3802         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3803
3804         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3805         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3806         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3807
3808         /* Special registers */
3809         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3810
3811         setup_msrs(vmx);
3812
3813         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3814
3815         if (cpu_has_vmx_tpr_shadow()) {
3816                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3817                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3818                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3819                                      __pa(vmx->vcpu.arch.apic->regs));
3820                 vmcs_write32(TPR_THRESHOLD, 0);
3821         }
3822
3823         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3824                 vmcs_write64(APIC_ACCESS_ADDR,
3825                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3826
3827         if (vmx->vpid != 0)
3828                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3829
3830         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3831         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3832         vmx_set_cr4(&vmx->vcpu, 0);
3833         vmx_set_efer(&vmx->vcpu, 0);
3834         vmx_fpu_activate(&vmx->vcpu);
3835         update_exception_bitmap(&vmx->vcpu);
3836
3837         vpid_sync_context(vmx);
3838
3839         ret = 0;
3840
3841         /* HACK: Don't enable emulation on guest boot/reset */
3842         vmx->emulation_required = 0;
3843
3844 out:
3845         return ret;
3846 }
3847
3848 /*
3849  * In nested virtualization, check if L1 asked to exit on external interrupts.
3850  * For most existing hypervisors, this will always return true.
3851  */
3852 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3853 {
3854         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3855                 PIN_BASED_EXT_INTR_MASK;
3856 }
3857
3858 static void enable_irq_window(struct kvm_vcpu *vcpu)
3859 {
3860         u32 cpu_based_vm_exec_control;
3861         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3862                 /* We can get here when nested_run_pending caused
3863                  * vmx_interrupt_allowed() to return false. In this case, do
3864                  * nothing - the interrupt will be injected later.
3865                  */
3866                 return;
3867
3868         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3869         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3870         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3871 }
3872
3873 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3874 {
3875         u32 cpu_based_vm_exec_control;
3876
3877         if (!cpu_has_virtual_nmis()) {
3878                 enable_irq_window(vcpu);
3879                 return;
3880         }
3881
3882         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3883                 enable_irq_window(vcpu);
3884                 return;
3885         }
3886         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3887         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3888         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3889 }
3890
3891 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3892 {
3893         struct vcpu_vmx *vmx = to_vmx(vcpu);
3894         uint32_t intr;
3895         int irq = vcpu->arch.interrupt.nr;
3896
3897         trace_kvm_inj_virq(irq);
3898
3899         ++vcpu->stat.irq_injections;
3900         if (vmx->rmode.vm86_active) {
3901                 int inc_eip = 0;
3902                 if (vcpu->arch.interrupt.soft)
3903                         inc_eip = vcpu->arch.event_exit_inst_len;
3904                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3905                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3906                 return;
3907         }
3908         intr = irq | INTR_INFO_VALID_MASK;
3909         if (vcpu->arch.interrupt.soft) {
3910                 intr |= INTR_TYPE_SOFT_INTR;
3911                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3912                              vmx->vcpu.arch.event_exit_inst_len);
3913         } else
3914                 intr |= INTR_TYPE_EXT_INTR;
3915         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
3916         vmx_clear_hlt(vcpu);
3917 }
3918
3919 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3920 {
3921         struct vcpu_vmx *vmx = to_vmx(vcpu);
3922
3923         if (is_guest_mode(vcpu))
3924                 return;
3925
3926         if (!cpu_has_virtual_nmis()) {
3927                 /*
3928                  * Tracking the NMI-blocked state in software is built upon
3929                  * finding the next open IRQ window. This, in turn, depends on
3930                  * well-behaving guests: They have to keep IRQs disabled at
3931                  * least as long as the NMI handler runs. Otherwise we may
3932                  * cause NMI nesting, maybe breaking the guest. But as this is
3933                  * highly unlikely, we can live with the residual risk.
3934                  */
3935                 vmx->soft_vnmi_blocked = 1;
3936                 vmx->vnmi_blocked_time = 0;
3937         }
3938
3939         ++vcpu->stat.nmi_injections;
3940         vmx->nmi_known_unmasked = false;
3941         if (vmx->rmode.vm86_active) {
3942                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
3943                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3944                 return;
3945         }
3946         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3947                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
3948         vmx_clear_hlt(vcpu);
3949 }
3950
3951 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
3952 {
3953         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
3954                 return 0;
3955
3956         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
3957                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
3958                    | GUEST_INTR_STATE_NMI));
3959 }
3960
3961 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3962 {
3963         if (!cpu_has_virtual_nmis())
3964                 return to_vmx(vcpu)->soft_vnmi_blocked;
3965         if (to_vmx(vcpu)->nmi_known_unmasked)
3966                 return false;
3967         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3968 }
3969
3970 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3971 {
3972         struct vcpu_vmx *vmx = to_vmx(vcpu);
3973
3974         if (!cpu_has_virtual_nmis()) {
3975                 if (vmx->soft_vnmi_blocked != masked) {
3976                         vmx->soft_vnmi_blocked = masked;
3977                         vmx->vnmi_blocked_time = 0;
3978                 }
3979         } else {
3980                 vmx->nmi_known_unmasked = !masked;
3981                 if (masked)
3982                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3983                                       GUEST_INTR_STATE_NMI);
3984                 else
3985                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3986                                         GUEST_INTR_STATE_NMI);
3987         }
3988 }
3989
3990 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
3991 {
3992         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
3993                 struct vmcs12 *vmcs12;
3994                 if (to_vmx(vcpu)->nested.nested_run_pending)
3995                         return 0;
3996                 nested_vmx_vmexit(vcpu);
3997                 vmcs12 = get_vmcs12(vcpu);
3998                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
3999                 vmcs12->vm_exit_intr_info = 0;
4000                 /* fall through to normal code, but now in L1, not L2 */
4001         }
4002
4003         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4004                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4005                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4006 }
4007
4008 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4009 {
4010         int ret;
4011         struct kvm_userspace_memory_region tss_mem = {
4012                 .slot = TSS_PRIVATE_MEMSLOT,
4013                 .guest_phys_addr = addr,
4014                 .memory_size = PAGE_SIZE * 3,
4015                 .flags = 0,
4016         };
4017
4018         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4019         if (ret)
4020                 return ret;
4021         kvm->arch.tss_addr = addr;
4022         if (!init_rmode_tss(kvm))
4023                 return  -ENOMEM;
4024
4025         return 0;
4026 }
4027
4028 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4029                                   int vec, u32 err_code)
4030 {
4031         /*
4032          * Instruction with address size override prefix opcode 0x67
4033          * Cause the #SS fault with 0 error code in VM86 mode.
4034          */
4035         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4036                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4037                         return 1;
4038         /*
4039          * Forward all other exceptions that are valid in real mode.
4040          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4041          *        the required debugging infrastructure rework.
4042          */
4043         switch (vec) {
4044         case DB_VECTOR:
4045                 if (vcpu->guest_debug &
4046                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4047                         return 0;
4048                 kvm_queue_exception(vcpu, vec);
4049                 return 1;
4050         case BP_VECTOR:
4051                 /*
4052                  * Update instruction length as we may reinject the exception
4053                  * from user space while in guest debugging mode.
4054                  */
4055                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4056                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4057                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4058                         return 0;
4059                 /* fall through */
4060         case DE_VECTOR:
4061         case OF_VECTOR:
4062         case BR_VECTOR:
4063         case UD_VECTOR:
4064         case DF_VECTOR:
4065         case SS_VECTOR:
4066         case GP_VECTOR:
4067         case MF_VECTOR:
4068                 kvm_queue_exception(vcpu, vec);
4069                 return 1;
4070         }
4071         return 0;
4072 }
4073
4074 /*
4075  * Trigger machine check on the host. We assume all the MSRs are already set up
4076  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4077  * We pass a fake environment to the machine check handler because we want
4078  * the guest to be always treated like user space, no matter what context
4079  * it used internally.
4080  */
4081 static void kvm_machine_check(void)
4082 {
4083 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4084         struct pt_regs regs = {
4085                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4086                 .flags = X86_EFLAGS_IF,
4087         };
4088
4089         do_machine_check(&regs, 0);
4090 #endif
4091 }
4092
4093 static int handle_machine_check(struct kvm_vcpu *vcpu)
4094 {
4095         /* already handled by vcpu_run */
4096         return 1;
4097 }
4098
4099 static int handle_exception(struct kvm_vcpu *vcpu)
4100 {
4101         struct vcpu_vmx *vmx = to_vmx(vcpu);
4102         struct kvm_run *kvm_run = vcpu->run;
4103         u32 intr_info, ex_no, error_code;
4104         unsigned long cr2, rip, dr6;
4105         u32 vect_info;
4106         enum emulation_result er;
4107
4108         vect_info = vmx->idt_vectoring_info;
4109         intr_info = vmx->exit_intr_info;
4110
4111         if (is_machine_check(intr_info))
4112                 return handle_machine_check(vcpu);
4113
4114         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4115             !is_page_fault(intr_info)) {
4116                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4117                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4118                 vcpu->run->internal.ndata = 2;
4119                 vcpu->run->internal.data[0] = vect_info;
4120                 vcpu->run->internal.data[1] = intr_info;
4121                 return 0;
4122         }
4123
4124         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4125                 return 1;  /* already handled by vmx_vcpu_run() */
4126
4127         if (is_no_device(intr_info)) {
4128                 vmx_fpu_activate(vcpu);
4129                 return 1;
4130         }
4131
4132         if (is_invalid_opcode(intr_info)) {
4133                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4134                 if (er != EMULATE_DONE)
4135                         kvm_queue_exception(vcpu, UD_VECTOR);
4136                 return 1;
4137         }
4138
4139         error_code = 0;
4140         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4141                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4142         if (is_page_fault(intr_info)) {
4143                 /* EPT won't cause page fault directly */
4144                 BUG_ON(enable_ept);
4145                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4146                 trace_kvm_page_fault(cr2, error_code);
4147
4148                 if (kvm_event_needs_reinjection(vcpu))
4149                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4150                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4151         }
4152
4153         if (vmx->rmode.vm86_active &&
4154             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4155                                                                 error_code)) {
4156                 if (vcpu->arch.halt_request) {
4157                         vcpu->arch.halt_request = 0;
4158                         return kvm_emulate_halt(vcpu);
4159                 }
4160                 return 1;
4161         }
4162
4163         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4164         switch (ex_no) {
4165         case DB_VECTOR:
4166                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4167                 if (!(vcpu->guest_debug &
4168                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4169                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4170                         kvm_queue_exception(vcpu, DB_VECTOR);
4171                         return 1;
4172                 }
4173                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4174                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4175                 /* fall through */
4176         case BP_VECTOR:
4177                 /*
4178                  * Update instruction length as we may reinject #BP from
4179                  * user space while in guest debugging mode. Reading it for
4180                  * #DB as well causes no harm, it is not used in that case.
4181                  */
4182                 vmx->vcpu.arch.event_exit_inst_len =
4183                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4184                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4185                 rip = kvm_rip_read(vcpu);
4186                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4187                 kvm_run->debug.arch.exception = ex_no;
4188                 break;
4189         default:
4190                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4191                 kvm_run->ex.exception = ex_no;
4192                 kvm_run->ex.error_code = error_code;
4193                 break;
4194         }
4195         return 0;
4196 }
4197
4198 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4199 {
4200         ++vcpu->stat.irq_exits;
4201         return 1;
4202 }
4203
4204 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4205 {
4206         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4207         return 0;
4208 }
4209
4210 static int handle_io(struct kvm_vcpu *vcpu)
4211 {
4212         unsigned long exit_qualification;
4213         int size, in, string;
4214         unsigned port;
4215
4216         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4217         string = (exit_qualification & 16) != 0;
4218         in = (exit_qualification & 8) != 0;
4219
4220         ++vcpu->stat.io_exits;
4221
4222         if (string || in)
4223                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4224
4225         port = exit_qualification >> 16;
4226         size = (exit_qualification & 7) + 1;
4227         skip_emulated_instruction(vcpu);
4228
4229         return kvm_fast_pio_out(vcpu, size, port);
4230 }
4231
4232 static void
4233 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4234 {
4235         /*
4236          * Patch in the VMCALL instruction:
4237          */
4238         hypercall[0] = 0x0f;
4239         hypercall[1] = 0x01;
4240         hypercall[2] = 0xc1;
4241 }
4242
4243 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4244 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4245 {
4246         if (to_vmx(vcpu)->nested.vmxon &&
4247             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4248                 return 1;
4249
4250         if (is_guest_mode(vcpu)) {
4251                 /*
4252                  * We get here when L2 changed cr0 in a way that did not change
4253                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4254                  * but did change L0 shadowed bits. This can currently happen
4255                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4256                  * loading) while pretending to allow the guest to change it.
4257                  */
4258                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4259                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4260                         return 1;
4261                 vmcs_writel(CR0_READ_SHADOW, val);
4262                 return 0;
4263         } else
4264                 return kvm_set_cr0(vcpu, val);
4265 }
4266
4267 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4268 {
4269         if (is_guest_mode(vcpu)) {
4270                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4271                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4272                         return 1;
4273                 vmcs_writel(CR4_READ_SHADOW, val);
4274                 return 0;
4275         } else
4276                 return kvm_set_cr4(vcpu, val);
4277 }
4278
4279 /* called to set cr0 as approriate for clts instruction exit. */
4280 static void handle_clts(struct kvm_vcpu *vcpu)
4281 {
4282         if (is_guest_mode(vcpu)) {
4283                 /*
4284                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4285                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4286                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4287                  */
4288                 vmcs_writel(CR0_READ_SHADOW,
4289                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4290                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4291         } else
4292                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4293 }
4294
4295 static int handle_cr(struct kvm_vcpu *vcpu)
4296 {
4297         unsigned long exit_qualification, val;
4298         int cr;
4299         int reg;
4300         int err;
4301
4302         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4303         cr = exit_qualification & 15;
4304         reg = (exit_qualification >> 8) & 15;
4305         switch ((exit_qualification >> 4) & 3) {
4306         case 0: /* mov to cr */
4307                 val = kvm_register_read(vcpu, reg);
4308                 trace_kvm_cr_write(cr, val);
4309                 switch (cr) {
4310                 case 0:
4311                         err = handle_set_cr0(vcpu, val);
4312                         kvm_complete_insn_gp(vcpu, err);
4313                         return 1;
4314                 case 3:
4315                         err = kvm_set_cr3(vcpu, val);
4316                         kvm_complete_insn_gp(vcpu, err);
4317                         return 1;
4318                 case 4:
4319                         err = handle_set_cr4(vcpu, val);
4320                         kvm_complete_insn_gp(vcpu, err);
4321                         return 1;
4322                 case 8: {
4323                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4324                                 u8 cr8 = kvm_register_read(vcpu, reg);
4325                                 err = kvm_set_cr8(vcpu, cr8);
4326                                 kvm_complete_insn_gp(vcpu, err);
4327                                 if (irqchip_in_kernel(vcpu->kvm))
4328                                         return 1;
4329                                 if (cr8_prev <= cr8)
4330                                         return 1;
4331                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4332                                 return 0;
4333                         }
4334                 };
4335                 break;
4336         case 2: /* clts */
4337                 handle_clts(vcpu);
4338                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4339                 skip_emulated_instruction(vcpu);
4340                 vmx_fpu_activate(vcpu);
4341                 return 1;
4342         case 1: /*mov from cr*/
4343                 switch (cr) {
4344                 case 3:
4345                         val = kvm_read_cr3(vcpu);
4346                         kvm_register_write(vcpu, reg, val);
4347                         trace_kvm_cr_read(cr, val);
4348                         skip_emulated_instruction(vcpu);
4349                         return 1;
4350                 case 8:
4351                         val = kvm_get_cr8(vcpu);
4352                         kvm_register_write(vcpu, reg, val);
4353                         trace_kvm_cr_read(cr, val);
4354                         skip_emulated_instruction(vcpu);
4355                         return 1;
4356                 }
4357                 break;
4358         case 3: /* lmsw */
4359                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4360                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4361                 kvm_lmsw(vcpu, val);
4362
4363                 skip_emulated_instruction(vcpu);
4364                 return 1;
4365         default:
4366                 break;
4367         }
4368         vcpu->run->exit_reason = 0;
4369         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4370                (int)(exit_qualification >> 4) & 3, cr);
4371         return 0;
4372 }
4373
4374 static int handle_dr(struct kvm_vcpu *vcpu)
4375 {
4376         unsigned long exit_qualification;
4377         int dr, reg;
4378
4379         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4380         if (!kvm_require_cpl(vcpu, 0))
4381                 return 1;
4382         dr = vmcs_readl(GUEST_DR7);
4383         if (dr & DR7_GD) {
4384                 /*
4385                  * As the vm-exit takes precedence over the debug trap, we
4386                  * need to emulate the latter, either for the host or the
4387                  * guest debugging itself.
4388                  */
4389                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4390                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4391                         vcpu->run->debug.arch.dr7 = dr;
4392                         vcpu->run->debug.arch.pc =
4393                                 vmcs_readl(GUEST_CS_BASE) +
4394                                 vmcs_readl(GUEST_RIP);
4395                         vcpu->run->debug.arch.exception = DB_VECTOR;
4396                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4397                         return 0;
4398                 } else {
4399                         vcpu->arch.dr7 &= ~DR7_GD;
4400                         vcpu->arch.dr6 |= DR6_BD;
4401                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4402                         kvm_queue_exception(vcpu, DB_VECTOR);
4403                         return 1;
4404                 }
4405         }
4406
4407         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4408         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4409         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4410         if (exit_qualification & TYPE_MOV_FROM_DR) {
4411                 unsigned long val;
4412                 if (!kvm_get_dr(vcpu, dr, &val))
4413                         kvm_register_write(vcpu, reg, val);
4414         } else
4415                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4416         skip_emulated_instruction(vcpu);
4417         return 1;
4418 }
4419
4420 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4421 {
4422         vmcs_writel(GUEST_DR7, val);
4423 }
4424
4425 static int handle_cpuid(struct kvm_vcpu *vcpu)
4426 {
4427         kvm_emulate_cpuid(vcpu);
4428         return 1;
4429 }
4430
4431 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4432 {
4433         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4434         u64 data;
4435
4436         if (vmx_get_msr(vcpu, ecx, &data)) {
4437                 trace_kvm_msr_read_ex(ecx);
4438                 kvm_inject_gp(vcpu, 0);
4439                 return 1;
4440         }
4441
4442         trace_kvm_msr_read(ecx, data);
4443
4444         /* FIXME: handling of bits 32:63 of rax, rdx */
4445         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4446         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4447         skip_emulated_instruction(vcpu);
4448         return 1;
4449 }
4450
4451 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4452 {
4453         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4454         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4455                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4456
4457         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4458                 trace_kvm_msr_write_ex(ecx, data);
4459                 kvm_inject_gp(vcpu, 0);
4460                 return 1;
4461         }
4462
4463         trace_kvm_msr_write(ecx, data);
4464         skip_emulated_instruction(vcpu);
4465         return 1;
4466 }
4467
4468 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4469 {
4470         kvm_make_request(KVM_REQ_EVENT, vcpu);
4471         return 1;
4472 }
4473
4474 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4475 {
4476         u32 cpu_based_vm_exec_control;
4477
4478         /* clear pending irq */
4479         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4480         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4481         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4482
4483         kvm_make_request(KVM_REQ_EVENT, vcpu);
4484
4485         ++vcpu->stat.irq_window_exits;
4486
4487         /*
4488          * If the user space waits to inject interrupts, exit as soon as
4489          * possible
4490          */
4491         if (!irqchip_in_kernel(vcpu->kvm) &&
4492             vcpu->run->request_interrupt_window &&
4493             !kvm_cpu_has_interrupt(vcpu)) {
4494                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4495                 return 0;
4496         }
4497         return 1;
4498 }
4499
4500 static int handle_halt(struct kvm_vcpu *vcpu)
4501 {
4502         skip_emulated_instruction(vcpu);
4503         return kvm_emulate_halt(vcpu);
4504 }
4505
4506 static int handle_vmcall(struct kvm_vcpu *vcpu)
4507 {
4508         skip_emulated_instruction(vcpu);
4509         kvm_emulate_hypercall(vcpu);
4510         return 1;
4511 }
4512
4513 static int handle_invd(struct kvm_vcpu *vcpu)
4514 {
4515         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4516 }
4517
4518 static int handle_invlpg(struct kvm_vcpu *vcpu)
4519 {
4520         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4521
4522         kvm_mmu_invlpg(vcpu, exit_qualification);
4523         skip_emulated_instruction(vcpu);
4524         return 1;
4525 }
4526
4527 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4528 {
4529         skip_emulated_instruction(vcpu);
4530         kvm_emulate_wbinvd(vcpu);
4531         return 1;
4532 }
4533
4534 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4535 {
4536         u64 new_bv = kvm_read_edx_eax(vcpu);
4537         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4538
4539         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4540                 skip_emulated_instruction(vcpu);
4541         return 1;
4542 }
4543
4544 static int handle_apic_access(struct kvm_vcpu *vcpu)
4545 {
4546         if (likely(fasteoi)) {
4547                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4548                 int access_type, offset;
4549
4550                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4551                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4552                 /*
4553                  * Sane guest uses MOV to write EOI, with written value
4554                  * not cared. So make a short-circuit here by avoiding
4555                  * heavy instruction emulation.
4556                  */
4557                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4558                     (offset == APIC_EOI)) {
4559                         kvm_lapic_set_eoi(vcpu);
4560                         skip_emulated_instruction(vcpu);
4561                         return 1;
4562                 }
4563         }
4564         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4565 }
4566
4567 static int handle_task_switch(struct kvm_vcpu *vcpu)
4568 {
4569         struct vcpu_vmx *vmx = to_vmx(vcpu);
4570         unsigned long exit_qualification;
4571         bool has_error_code = false;
4572         u32 error_code = 0;
4573         u16 tss_selector;
4574         int reason, type, idt_v;
4575
4576         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4577         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4578
4579         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4580
4581         reason = (u32)exit_qualification >> 30;
4582         if (reason == TASK_SWITCH_GATE && idt_v) {
4583                 switch (type) {
4584                 case INTR_TYPE_NMI_INTR:
4585                         vcpu->arch.nmi_injected = false;
4586                         vmx_set_nmi_mask(vcpu, true);
4587                         break;
4588                 case INTR_TYPE_EXT_INTR:
4589                 case INTR_TYPE_SOFT_INTR:
4590                         kvm_clear_interrupt_queue(vcpu);
4591                         break;
4592                 case INTR_TYPE_HARD_EXCEPTION:
4593                         if (vmx->idt_vectoring_info &
4594                             VECTORING_INFO_DELIVER_CODE_MASK) {
4595                                 has_error_code = true;
4596                                 error_code =
4597                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4598                         }
4599                         /* fall through */
4600                 case INTR_TYPE_SOFT_EXCEPTION:
4601                         kvm_clear_exception_queue(vcpu);
4602                         break;
4603                 default:
4604                         break;
4605                 }
4606         }
4607         tss_selector = exit_qualification;
4608
4609         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4610                        type != INTR_TYPE_EXT_INTR &&
4611                        type != INTR_TYPE_NMI_INTR))
4612                 skip_emulated_instruction(vcpu);
4613
4614         if (kvm_task_switch(vcpu, tss_selector, reason,
4615                                 has_error_code, error_code) == EMULATE_FAIL) {
4616                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4617                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4618                 vcpu->run->internal.ndata = 0;
4619                 return 0;
4620         }
4621
4622         /* clear all local breakpoint enable flags */
4623         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4624
4625         /*
4626          * TODO: What about debug traps on tss switch?
4627          *       Are we supposed to inject them and update dr6?
4628          */
4629
4630         return 1;
4631 }
4632
4633 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4634 {
4635         unsigned long exit_qualification;
4636         gpa_t gpa;
4637         int gla_validity;
4638
4639         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4640
4641         if (exit_qualification & (1 << 6)) {
4642                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4643                 return -EINVAL;
4644         }
4645
4646         gla_validity = (exit_qualification >> 7) & 0x3;
4647         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4648                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4649                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4650                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4651                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4652                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4653                         (long unsigned int)exit_qualification);
4654                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4655                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4656                 return 0;
4657         }
4658
4659         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4660         trace_kvm_page_fault(gpa, exit_qualification);
4661         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4662 }
4663
4664 static u64 ept_rsvd_mask(u64 spte, int level)
4665 {
4666         int i;
4667         u64 mask = 0;
4668
4669         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4670                 mask |= (1ULL << i);
4671
4672         if (level > 2)
4673                 /* bits 7:3 reserved */
4674                 mask |= 0xf8;
4675         else if (level == 2) {
4676                 if (spte & (1ULL << 7))
4677                         /* 2MB ref, bits 20:12 reserved */
4678                         mask |= 0x1ff000;
4679                 else
4680                         /* bits 6:3 reserved */
4681                         mask |= 0x78;
4682         }
4683
4684         return mask;
4685 }
4686
4687 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4688                                        int level)
4689 {
4690         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4691
4692         /* 010b (write-only) */
4693         WARN_ON((spte & 0x7) == 0x2);
4694
4695         /* 110b (write/execute) */
4696         WARN_ON((spte & 0x7) == 0x6);
4697
4698         /* 100b (execute-only) and value not supported by logical processor */
4699         if (!cpu_has_vmx_ept_execute_only())
4700                 WARN_ON((spte & 0x7) == 0x4);
4701
4702         /* not 000b */
4703         if ((spte & 0x7)) {
4704                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4705
4706                 if (rsvd_bits != 0) {
4707                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4708                                          __func__, rsvd_bits);
4709                         WARN_ON(1);
4710                 }
4711
4712                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4713                         u64 ept_mem_type = (spte & 0x38) >> 3;
4714
4715                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4716                             ept_mem_type == 7) {
4717                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4718                                                 __func__, ept_mem_type);
4719                                 WARN_ON(1);
4720                         }
4721                 }
4722         }
4723 }
4724
4725 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4726 {
4727         u64 sptes[4];
4728         int nr_sptes, i, ret;
4729         gpa_t gpa;
4730
4731         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4732
4733         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4734         if (likely(ret == 1))
4735                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4736                                               EMULATE_DONE;
4737         if (unlikely(!ret))
4738                 return 1;
4739
4740         /* It is the real ept misconfig */
4741         printk(KERN_ERR "EPT: Misconfiguration.\n");
4742         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4743
4744         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4745
4746         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4747                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4748
4749         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4750         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4751
4752         return 0;
4753 }
4754
4755 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4756 {
4757         u32 cpu_based_vm_exec_control;
4758
4759         /* clear pending NMI */
4760         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4761         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4762         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4763         ++vcpu->stat.nmi_window_exits;
4764         kvm_make_request(KVM_REQ_EVENT, vcpu);
4765
4766         return 1;
4767 }
4768
4769 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4770 {
4771         struct vcpu_vmx *vmx = to_vmx(vcpu);
4772         enum emulation_result err = EMULATE_DONE;
4773         int ret = 1;
4774         u32 cpu_exec_ctrl;
4775         bool intr_window_requested;
4776
4777         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4778         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4779
4780         while (!guest_state_valid(vcpu)) {
4781                 if (intr_window_requested
4782                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4783                         return handle_interrupt_window(&vmx->vcpu);
4784
4785                 err = emulate_instruction(vcpu, 0);
4786
4787                 if (err == EMULATE_DO_MMIO) {
4788                         ret = 0;
4789                         goto out;
4790                 }
4791
4792                 if (err != EMULATE_DONE)
4793                         return 0;
4794
4795                 if (signal_pending(current))
4796                         goto out;
4797                 if (need_resched())
4798                         schedule();
4799         }
4800
4801         vmx->emulation_required = 0;
4802 out:
4803         return ret;
4804 }
4805
4806 /*
4807  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4808  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4809  */
4810 static int handle_pause(struct kvm_vcpu *vcpu)
4811 {
4812         skip_emulated_instruction(vcpu);
4813         kvm_vcpu_on_spin(vcpu);
4814
4815         return 1;
4816 }
4817
4818 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4819 {
4820         kvm_queue_exception(vcpu, UD_VECTOR);
4821         return 1;
4822 }
4823
4824 /*
4825  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4826  * We could reuse a single VMCS for all the L2 guests, but we also want the
4827  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4828  * allows keeping them loaded on the processor, and in the future will allow
4829  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4830  * every entry if they never change.
4831  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4832  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4833  *
4834  * The following functions allocate and free a vmcs02 in this pool.
4835  */
4836
4837 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4838 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4839 {
4840         struct vmcs02_list *item;
4841         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4842                 if (item->vmptr == vmx->nested.current_vmptr) {
4843                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4844                         return &item->vmcs02;
4845                 }
4846
4847         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4848                 /* Recycle the least recently used VMCS. */
4849                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4850                         struct vmcs02_list, list);
4851                 item->vmptr = vmx->nested.current_vmptr;
4852                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4853                 return &item->vmcs02;
4854         }
4855
4856         /* Create a new VMCS */
4857         item = (struct vmcs02_list *)
4858                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4859         if (!item)
4860                 return NULL;
4861         item->vmcs02.vmcs = alloc_vmcs();
4862         if (!item->vmcs02.vmcs) {
4863                 kfree(item);
4864                 return NULL;
4865         }
4866         loaded_vmcs_init(&item->vmcs02);
4867         item->vmptr = vmx->nested.current_vmptr;
4868         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4869         vmx->nested.vmcs02_num++;
4870         return &item->vmcs02;
4871 }
4872
4873 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4874 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4875 {
4876         struct vmcs02_list *item;
4877         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4878                 if (item->vmptr == vmptr) {
4879                         free_loaded_vmcs(&item->vmcs02);
4880                         list_del(&item->list);
4881                         kfree(item);
4882                         vmx->nested.vmcs02_num--;
4883                         return;
4884                 }
4885 }
4886
4887 /*
4888  * Free all VMCSs saved for this vcpu, except the one pointed by
4889  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4890  * currently used, if running L2), and vmcs01 when running L2.
4891  */
4892 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4893 {
4894         struct vmcs02_list *item, *n;
4895         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4896                 if (vmx->loaded_vmcs != &item->vmcs02)
4897                         free_loaded_vmcs(&item->vmcs02);
4898                 list_del(&item->list);
4899                 kfree(item);
4900         }
4901         vmx->nested.vmcs02_num = 0;
4902
4903         if (vmx->loaded_vmcs != &vmx->vmcs01)
4904                 free_loaded_vmcs(&vmx->vmcs01);
4905 }
4906
4907 /*
4908  * Emulate the VMXON instruction.
4909  * Currently, we just remember that VMX is active, and do not save or even
4910  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
4911  * do not currently need to store anything in that guest-allocated memory
4912  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
4913  * argument is different from the VMXON pointer (which the spec says they do).
4914  */
4915 static int handle_vmon(struct kvm_vcpu *vcpu)
4916 {
4917         struct kvm_segment cs;
4918         struct vcpu_vmx *vmx = to_vmx(vcpu);
4919
4920         /* The Intel VMX Instruction Reference lists a bunch of bits that
4921          * are prerequisite to running VMXON, most notably cr4.VMXE must be
4922          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
4923          * Otherwise, we should fail with #UD. We test these now:
4924          */
4925         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
4926             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
4927             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
4928                 kvm_queue_exception(vcpu, UD_VECTOR);
4929                 return 1;
4930         }
4931
4932         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4933         if (is_long_mode(vcpu) && !cs.l) {
4934                 kvm_queue_exception(vcpu, UD_VECTOR);
4935                 return 1;
4936         }
4937
4938         if (vmx_get_cpl(vcpu)) {
4939                 kvm_inject_gp(vcpu, 0);
4940                 return 1;
4941         }
4942
4943         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
4944         vmx->nested.vmcs02_num = 0;
4945
4946         vmx->nested.vmxon = true;
4947
4948         skip_emulated_instruction(vcpu);
4949         return 1;
4950 }
4951
4952 /*
4953  * Intel's VMX Instruction Reference specifies a common set of prerequisites
4954  * for running VMX instructions (except VMXON, whose prerequisites are
4955  * slightly different). It also specifies what exception to inject otherwise.
4956  */
4957 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
4958 {
4959         struct kvm_segment cs;
4960         struct vcpu_vmx *vmx = to_vmx(vcpu);
4961
4962         if (!vmx->nested.vmxon) {
4963                 kvm_queue_exception(vcpu, UD_VECTOR);
4964                 return 0;
4965         }
4966
4967         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
4968         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
4969             (is_long_mode(vcpu) && !cs.l)) {
4970                 kvm_queue_exception(vcpu, UD_VECTOR);
4971                 return 0;
4972         }
4973
4974         if (vmx_get_cpl(vcpu)) {
4975                 kvm_inject_gp(vcpu, 0);
4976                 return 0;
4977         }
4978
4979         return 1;
4980 }
4981
4982 /*
4983  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
4984  * just stops using VMX.
4985  */
4986 static void free_nested(struct vcpu_vmx *vmx)
4987 {
4988         if (!vmx->nested.vmxon)
4989                 return;
4990         vmx->nested.vmxon = false;
4991         if (vmx->nested.current_vmptr != -1ull) {
4992                 kunmap(vmx->nested.current_vmcs12_page);
4993                 nested_release_page(vmx->nested.current_vmcs12_page);
4994                 vmx->nested.current_vmptr = -1ull;
4995                 vmx->nested.current_vmcs12 = NULL;
4996         }
4997         /* Unpin physical memory we referred to in current vmcs02 */
4998         if (vmx->nested.apic_access_page) {
4999                 nested_release_page(vmx->nested.apic_access_page);
5000                 vmx->nested.apic_access_page = 0;
5001         }
5002
5003         nested_free_all_saved_vmcss(vmx);
5004 }
5005
5006 /* Emulate the VMXOFF instruction */
5007 static int handle_vmoff(struct kvm_vcpu *vcpu)
5008 {
5009         if (!nested_vmx_check_permission(vcpu))
5010                 return 1;
5011         free_nested(to_vmx(vcpu));
5012         skip_emulated_instruction(vcpu);
5013         return 1;
5014 }
5015
5016 /*
5017  * Decode the memory-address operand of a vmx instruction, as recorded on an
5018  * exit caused by such an instruction (run by a guest hypervisor).
5019  * On success, returns 0. When the operand is invalid, returns 1 and throws
5020  * #UD or #GP.
5021  */
5022 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5023                                  unsigned long exit_qualification,
5024                                  u32 vmx_instruction_info, gva_t *ret)
5025 {
5026         /*
5027          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5028          * Execution", on an exit, vmx_instruction_info holds most of the
5029          * addressing components of the operand. Only the displacement part
5030          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5031          * For how an actual address is calculated from all these components,
5032          * refer to Vol. 1, "Operand Addressing".
5033          */
5034         int  scaling = vmx_instruction_info & 3;
5035         int  addr_size = (vmx_instruction_info >> 7) & 7;
5036         bool is_reg = vmx_instruction_info & (1u << 10);
5037         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5038         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5039         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5040         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5041         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5042
5043         if (is_reg) {
5044                 kvm_queue_exception(vcpu, UD_VECTOR);
5045                 return 1;
5046         }
5047
5048         /* Addr = segment_base + offset */
5049         /* offset = base + [index * scale] + displacement */
5050         *ret = vmx_get_segment_base(vcpu, seg_reg);
5051         if (base_is_valid)
5052                 *ret += kvm_register_read(vcpu, base_reg);
5053         if (index_is_valid)
5054                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5055         *ret += exit_qualification; /* holds the displacement */
5056
5057         if (addr_size == 1) /* 32 bit */
5058                 *ret &= 0xffffffff;
5059
5060         /*
5061          * TODO: throw #GP (and return 1) in various cases that the VM*
5062          * instructions require it - e.g., offset beyond segment limit,
5063          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5064          * address, and so on. Currently these are not checked.
5065          */
5066         return 0;
5067 }
5068
5069 /*
5070  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5071  * set the success or error code of an emulated VMX instruction, as specified
5072  * by Vol 2B, VMX Instruction Reference, "Conventions".
5073  */
5074 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5075 {
5076         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5077                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5078                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5079 }
5080
5081 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5082 {
5083         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5084                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5085                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5086                         | X86_EFLAGS_CF);
5087 }
5088
5089 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5090                                         u32 vm_instruction_error)
5091 {
5092         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5093                 /*
5094                  * failValid writes the error number to the current VMCS, which
5095                  * can't be done there isn't a current VMCS.
5096                  */
5097                 nested_vmx_failInvalid(vcpu);
5098                 return;
5099         }
5100         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5101                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5102                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5103                         | X86_EFLAGS_ZF);
5104         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5105 }
5106
5107 /* Emulate the VMCLEAR instruction */
5108 static int handle_vmclear(struct kvm_vcpu *vcpu)
5109 {
5110         struct vcpu_vmx *vmx = to_vmx(vcpu);
5111         gva_t gva;
5112         gpa_t vmptr;
5113         struct vmcs12 *vmcs12;
5114         struct page *page;
5115         struct x86_exception e;
5116
5117         if (!nested_vmx_check_permission(vcpu))
5118                 return 1;
5119
5120         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5121                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5122                 return 1;
5123
5124         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5125                                 sizeof(vmptr), &e)) {
5126                 kvm_inject_page_fault(vcpu, &e);
5127                 return 1;
5128         }
5129
5130         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5131                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5132                 skip_emulated_instruction(vcpu);
5133                 return 1;
5134         }
5135
5136         if (vmptr == vmx->nested.current_vmptr) {
5137                 kunmap(vmx->nested.current_vmcs12_page);
5138                 nested_release_page(vmx->nested.current_vmcs12_page);
5139                 vmx->nested.current_vmptr = -1ull;
5140                 vmx->nested.current_vmcs12 = NULL;
5141         }
5142
5143         page = nested_get_page(vcpu, vmptr);
5144         if (page == NULL) {
5145                 /*
5146                  * For accurate processor emulation, VMCLEAR beyond available
5147                  * physical memory should do nothing at all. However, it is
5148                  * possible that a nested vmx bug, not a guest hypervisor bug,
5149                  * resulted in this case, so let's shut down before doing any
5150                  * more damage:
5151                  */
5152                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5153                 return 1;
5154         }
5155         vmcs12 = kmap(page);
5156         vmcs12->launch_state = 0;
5157         kunmap(page);
5158         nested_release_page(page);
5159
5160         nested_free_vmcs02(vmx, vmptr);
5161
5162         skip_emulated_instruction(vcpu);
5163         nested_vmx_succeed(vcpu);
5164         return 1;
5165 }
5166
5167 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5168
5169 /* Emulate the VMLAUNCH instruction */
5170 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5171 {
5172         return nested_vmx_run(vcpu, true);
5173 }
5174
5175 /* Emulate the VMRESUME instruction */
5176 static int handle_vmresume(struct kvm_vcpu *vcpu)
5177 {
5178
5179         return nested_vmx_run(vcpu, false);
5180 }
5181
5182 enum vmcs_field_type {
5183         VMCS_FIELD_TYPE_U16 = 0,
5184         VMCS_FIELD_TYPE_U64 = 1,
5185         VMCS_FIELD_TYPE_U32 = 2,
5186         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5187 };
5188
5189 static inline int vmcs_field_type(unsigned long field)
5190 {
5191         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5192                 return VMCS_FIELD_TYPE_U32;
5193         return (field >> 13) & 0x3 ;
5194 }
5195
5196 static inline int vmcs_field_readonly(unsigned long field)
5197 {
5198         return (((field >> 10) & 0x3) == 1);
5199 }
5200
5201 /*
5202  * Read a vmcs12 field. Since these can have varying lengths and we return
5203  * one type, we chose the biggest type (u64) and zero-extend the return value
5204  * to that size. Note that the caller, handle_vmread, might need to use only
5205  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5206  * 64-bit fields are to be returned).
5207  */
5208 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5209                                         unsigned long field, u64 *ret)
5210 {
5211         short offset = vmcs_field_to_offset(field);
5212         char *p;
5213
5214         if (offset < 0)
5215                 return 0;
5216
5217         p = ((char *)(get_vmcs12(vcpu))) + offset;
5218
5219         switch (vmcs_field_type(field)) {
5220         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5221                 *ret = *((natural_width *)p);
5222                 return 1;
5223         case VMCS_FIELD_TYPE_U16:
5224                 *ret = *((u16 *)p);
5225                 return 1;
5226         case VMCS_FIELD_TYPE_U32:
5227                 *ret = *((u32 *)p);
5228                 return 1;
5229         case VMCS_FIELD_TYPE_U64:
5230                 *ret = *((u64 *)p);
5231                 return 1;
5232         default:
5233                 return 0; /* can never happen. */
5234         }
5235 }
5236
5237 /*
5238  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5239  * used before) all generate the same failure when it is missing.
5240  */
5241 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5242 {
5243         struct vcpu_vmx *vmx = to_vmx(vcpu);
5244         if (vmx->nested.current_vmptr == -1ull) {
5245                 nested_vmx_failInvalid(vcpu);
5246                 skip_emulated_instruction(vcpu);
5247                 return 0;
5248         }
5249         return 1;
5250 }
5251
5252 static int handle_vmread(struct kvm_vcpu *vcpu)
5253 {
5254         unsigned long field;
5255         u64 field_value;
5256         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5257         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5258         gva_t gva = 0;
5259
5260         if (!nested_vmx_check_permission(vcpu) ||
5261             !nested_vmx_check_vmcs12(vcpu))
5262                 return 1;
5263
5264         /* Decode instruction info and find the field to read */
5265         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5266         /* Read the field, zero-extended to a u64 field_value */
5267         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5268                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5269                 skip_emulated_instruction(vcpu);
5270                 return 1;
5271         }
5272         /*
5273          * Now copy part of this value to register or memory, as requested.
5274          * Note that the number of bits actually copied is 32 or 64 depending
5275          * on the guest's mode (32 or 64 bit), not on the given field's length.
5276          */
5277         if (vmx_instruction_info & (1u << 10)) {
5278                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5279                         field_value);
5280         } else {
5281                 if (get_vmx_mem_address(vcpu, exit_qualification,
5282                                 vmx_instruction_info, &gva))
5283                         return 1;
5284                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5285                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5286                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5287         }
5288
5289         nested_vmx_succeed(vcpu);
5290         skip_emulated_instruction(vcpu);
5291         return 1;
5292 }
5293
5294
5295 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5296 {
5297         unsigned long field;
5298         gva_t gva;
5299         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5300         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5301         char *p;
5302         short offset;
5303         /* The value to write might be 32 or 64 bits, depending on L1's long
5304          * mode, and eventually we need to write that into a field of several
5305          * possible lengths. The code below first zero-extends the value to 64
5306          * bit (field_value), and then copies only the approriate number of
5307          * bits into the vmcs12 field.
5308          */
5309         u64 field_value = 0;
5310         struct x86_exception e;
5311
5312         if (!nested_vmx_check_permission(vcpu) ||
5313             !nested_vmx_check_vmcs12(vcpu))
5314                 return 1;
5315
5316         if (vmx_instruction_info & (1u << 10))
5317                 field_value = kvm_register_read(vcpu,
5318                         (((vmx_instruction_info) >> 3) & 0xf));
5319         else {
5320                 if (get_vmx_mem_address(vcpu, exit_qualification,
5321                                 vmx_instruction_info, &gva))
5322                         return 1;
5323                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5324                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5325                         kvm_inject_page_fault(vcpu, &e);
5326                         return 1;
5327                 }
5328         }
5329
5330
5331         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5332         if (vmcs_field_readonly(field)) {
5333                 nested_vmx_failValid(vcpu,
5334                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5335                 skip_emulated_instruction(vcpu);
5336                 return 1;
5337         }
5338
5339         offset = vmcs_field_to_offset(field);
5340         if (offset < 0) {
5341                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5342                 skip_emulated_instruction(vcpu);
5343                 return 1;
5344         }
5345         p = ((char *) get_vmcs12(vcpu)) + offset;
5346
5347         switch (vmcs_field_type(field)) {
5348         case VMCS_FIELD_TYPE_U16:
5349                 *(u16 *)p = field_value;
5350                 break;
5351         case VMCS_FIELD_TYPE_U32:
5352                 *(u32 *)p = field_value;
5353                 break;
5354         case VMCS_FIELD_TYPE_U64:
5355                 *(u64 *)p = field_value;
5356                 break;
5357         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5358                 *(natural_width *)p = field_value;
5359                 break;
5360         default:
5361                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5362                 skip_emulated_instruction(vcpu);
5363                 return 1;
5364         }
5365
5366         nested_vmx_succeed(vcpu);
5367         skip_emulated_instruction(vcpu);
5368         return 1;
5369 }
5370
5371 /* Emulate the VMPTRLD instruction */
5372 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5373 {
5374         struct vcpu_vmx *vmx = to_vmx(vcpu);
5375         gva_t gva;
5376         gpa_t vmptr;
5377         struct x86_exception e;
5378
5379         if (!nested_vmx_check_permission(vcpu))
5380                 return 1;
5381
5382         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5383                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5384                 return 1;
5385
5386         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5387                                 sizeof(vmptr), &e)) {
5388                 kvm_inject_page_fault(vcpu, &e);
5389                 return 1;
5390         }
5391
5392         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5393                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5394                 skip_emulated_instruction(vcpu);
5395                 return 1;
5396         }
5397
5398         if (vmx->nested.current_vmptr != vmptr) {
5399                 struct vmcs12 *new_vmcs12;
5400                 struct page *page;
5401                 page = nested_get_page(vcpu, vmptr);
5402                 if (page == NULL) {
5403                         nested_vmx_failInvalid(vcpu);
5404                         skip_emulated_instruction(vcpu);
5405                         return 1;
5406                 }
5407                 new_vmcs12 = kmap(page);
5408                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5409                         kunmap(page);
5410                         nested_release_page_clean(page);
5411                         nested_vmx_failValid(vcpu,
5412                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5413                         skip_emulated_instruction(vcpu);
5414                         return 1;
5415                 }
5416                 if (vmx->nested.current_vmptr != -1ull) {
5417                         kunmap(vmx->nested.current_vmcs12_page);
5418                         nested_release_page(vmx->nested.current_vmcs12_page);
5419                 }
5420
5421                 vmx->nested.current_vmptr = vmptr;
5422                 vmx->nested.current_vmcs12 = new_vmcs12;
5423                 vmx->nested.current_vmcs12_page = page;
5424         }
5425
5426         nested_vmx_succeed(vcpu);
5427         skip_emulated_instruction(vcpu);
5428         return 1;
5429 }
5430
5431 /* Emulate the VMPTRST instruction */
5432 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5433 {
5434         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5435         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5436         gva_t vmcs_gva;
5437         struct x86_exception e;
5438
5439         if (!nested_vmx_check_permission(vcpu))
5440                 return 1;
5441
5442         if (get_vmx_mem_address(vcpu, exit_qualification,
5443                         vmx_instruction_info, &vmcs_gva))
5444                 return 1;
5445         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5446         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5447                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5448                                  sizeof(u64), &e)) {
5449                 kvm_inject_page_fault(vcpu, &e);
5450                 return 1;
5451         }
5452         nested_vmx_succeed(vcpu);
5453         skip_emulated_instruction(vcpu);
5454         return 1;
5455 }
5456
5457 /*
5458  * The exit handlers return 1 if the exit was handled fully and guest execution
5459  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5460  * to be done to userspace and return 0.
5461  */
5462 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5463         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5464         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5465         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5466         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5467         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5468         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5469         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5470         [EXIT_REASON_CPUID]                   = handle_cpuid,
5471         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5472         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5473         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5474         [EXIT_REASON_HLT]                     = handle_halt,
5475         [EXIT_REASON_INVD]                    = handle_invd,
5476         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5477         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5478         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5479         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5480         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5481         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5482         [EXIT_REASON_VMREAD]                  = handle_vmread,
5483         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5484         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5485         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5486         [EXIT_REASON_VMON]                    = handle_vmon,
5487         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5488         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5489         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5490         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5491         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5492         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5493         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5494         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5495         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5496         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5497         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5498 };
5499
5500 static const int kvm_vmx_max_exit_handlers =
5501         ARRAY_SIZE(kvm_vmx_exit_handlers);
5502
5503 /*
5504  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5505  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5506  * disinterest in the current event (read or write a specific MSR) by using an
5507  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5508  */
5509 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5510         struct vmcs12 *vmcs12, u32 exit_reason)
5511 {
5512         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5513         gpa_t bitmap;
5514
5515         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5516                 return 1;
5517
5518         /*
5519          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5520          * for the four combinations of read/write and low/high MSR numbers.
5521          * First we need to figure out which of the four to use:
5522          */
5523         bitmap = vmcs12->msr_bitmap;
5524         if (exit_reason == EXIT_REASON_MSR_WRITE)
5525                 bitmap += 2048;
5526         if (msr_index >= 0xc0000000) {
5527                 msr_index -= 0xc0000000;
5528                 bitmap += 1024;
5529         }
5530
5531         /* Then read the msr_index'th bit from this bitmap: */
5532         if (msr_index < 1024*8) {
5533                 unsigned char b;
5534                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5535                 return 1 & (b >> (msr_index & 7));
5536         } else
5537                 return 1; /* let L1 handle the wrong parameter */
5538 }
5539
5540 /*
5541  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5542  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5543  * intercept (via guest_host_mask etc.) the current event.
5544  */
5545 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5546         struct vmcs12 *vmcs12)
5547 {
5548         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5549         int cr = exit_qualification & 15;
5550         int reg = (exit_qualification >> 8) & 15;
5551         unsigned long val = kvm_register_read(vcpu, reg);
5552
5553         switch ((exit_qualification >> 4) & 3) {
5554         case 0: /* mov to cr */
5555                 switch (cr) {
5556                 case 0:
5557                         if (vmcs12->cr0_guest_host_mask &
5558                             (val ^ vmcs12->cr0_read_shadow))
5559                                 return 1;
5560                         break;
5561                 case 3:
5562                         if ((vmcs12->cr3_target_count >= 1 &&
5563                                         vmcs12->cr3_target_value0 == val) ||
5564                                 (vmcs12->cr3_target_count >= 2 &&
5565                                         vmcs12->cr3_target_value1 == val) ||
5566                                 (vmcs12->cr3_target_count >= 3 &&
5567                                         vmcs12->cr3_target_value2 == val) ||
5568                                 (vmcs12->cr3_target_count >= 4 &&
5569                                         vmcs12->cr3_target_value3 == val))
5570                                 return 0;
5571                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5572                                 return 1;
5573                         break;
5574                 case 4:
5575                         if (vmcs12->cr4_guest_host_mask &
5576                             (vmcs12->cr4_read_shadow ^ val))
5577                                 return 1;
5578                         break;
5579                 case 8:
5580                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5581                                 return 1;
5582                         break;
5583                 }
5584                 break;
5585         case 2: /* clts */
5586                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5587                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5588                         return 1;
5589                 break;
5590         case 1: /* mov from cr */
5591                 switch (cr) {
5592                 case 3:
5593                         if (vmcs12->cpu_based_vm_exec_control &
5594                             CPU_BASED_CR3_STORE_EXITING)
5595                                 return 1;
5596                         break;
5597                 case 8:
5598                         if (vmcs12->cpu_based_vm_exec_control &
5599                             CPU_BASED_CR8_STORE_EXITING)
5600                                 return 1;
5601                         break;
5602                 }
5603                 break;
5604         case 3: /* lmsw */
5605                 /*
5606                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5607                  * cr0. Other attempted changes are ignored, with no exit.
5608                  */
5609                 if (vmcs12->cr0_guest_host_mask & 0xe &
5610                     (val ^ vmcs12->cr0_read_shadow))
5611                         return 1;
5612                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5613                     !(vmcs12->cr0_read_shadow & 0x1) &&
5614                     (val & 0x1))
5615                         return 1;
5616                 break;
5617         }
5618         return 0;
5619 }
5620
5621 /*
5622  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5623  * should handle it ourselves in L0 (and then continue L2). Only call this
5624  * when in is_guest_mode (L2).
5625  */
5626 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5627 {
5628         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5629         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5630         struct vcpu_vmx *vmx = to_vmx(vcpu);
5631         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5632
5633         if (vmx->nested.nested_run_pending)
5634                 return 0;
5635
5636         if (unlikely(vmx->fail)) {
5637                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5638                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5639                 return 1;
5640         }
5641
5642         switch (exit_reason) {
5643         case EXIT_REASON_EXCEPTION_NMI:
5644                 if (!is_exception(intr_info))
5645                         return 0;
5646                 else if (is_page_fault(intr_info))
5647                         return enable_ept;
5648                 return vmcs12->exception_bitmap &
5649                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5650         case EXIT_REASON_EXTERNAL_INTERRUPT:
5651                 return 0;
5652         case EXIT_REASON_TRIPLE_FAULT:
5653                 return 1;
5654         case EXIT_REASON_PENDING_INTERRUPT:
5655         case EXIT_REASON_NMI_WINDOW:
5656                 /*
5657                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5658                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5659                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5660                  * Same for NMI Window Exiting.
5661                  */
5662                 return 1;
5663         case EXIT_REASON_TASK_SWITCH:
5664                 return 1;
5665         case EXIT_REASON_CPUID:
5666                 return 1;
5667         case EXIT_REASON_HLT:
5668                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5669         case EXIT_REASON_INVD:
5670                 return 1;
5671         case EXIT_REASON_INVLPG:
5672                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5673         case EXIT_REASON_RDPMC:
5674                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5675         case EXIT_REASON_RDTSC:
5676                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5677         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5678         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5679         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5680         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5681         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5682                 /*
5683                  * VMX instructions trap unconditionally. This allows L1 to
5684                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5685                  */
5686                 return 1;
5687         case EXIT_REASON_CR_ACCESS:
5688                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5689         case EXIT_REASON_DR_ACCESS:
5690                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5691         case EXIT_REASON_IO_INSTRUCTION:
5692                 /* TODO: support IO bitmaps */
5693                 return 1;
5694         case EXIT_REASON_MSR_READ:
5695         case EXIT_REASON_MSR_WRITE:
5696                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5697         case EXIT_REASON_INVALID_STATE:
5698                 return 1;
5699         case EXIT_REASON_MWAIT_INSTRUCTION:
5700                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5701         case EXIT_REASON_MONITOR_INSTRUCTION:
5702                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5703         case EXIT_REASON_PAUSE_INSTRUCTION:
5704                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5705                         nested_cpu_has2(vmcs12,
5706                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5707         case EXIT_REASON_MCE_DURING_VMENTRY:
5708                 return 0;
5709         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5710                 return 1;
5711         case EXIT_REASON_APIC_ACCESS:
5712                 return nested_cpu_has2(vmcs12,
5713                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5714         case EXIT_REASON_EPT_VIOLATION:
5715         case EXIT_REASON_EPT_MISCONFIG:
5716                 return 0;
5717         case EXIT_REASON_WBINVD:
5718                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5719         case EXIT_REASON_XSETBV:
5720                 return 1;
5721         default:
5722                 return 1;
5723         }
5724 }
5725
5726 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5727 {
5728         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5729         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5730 }
5731
5732 /*
5733  * The guest has exited.  See if we can fix it or if we need userspace
5734  * assistance.
5735  */
5736 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5737 {
5738         struct vcpu_vmx *vmx = to_vmx(vcpu);
5739         u32 exit_reason = vmx->exit_reason;
5740         u32 vectoring_info = vmx->idt_vectoring_info;
5741
5742         /* If guest state is invalid, start emulating */
5743         if (vmx->emulation_required && emulate_invalid_guest_state)
5744                 return handle_invalid_guest_state(vcpu);
5745
5746         /*
5747          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5748          * we did not inject a still-pending event to L1 now because of
5749          * nested_run_pending, we need to re-enable this bit.
5750          */
5751         if (vmx->nested.nested_run_pending)
5752                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5753
5754         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5755             exit_reason == EXIT_REASON_VMRESUME))
5756                 vmx->nested.nested_run_pending = 1;
5757         else
5758                 vmx->nested.nested_run_pending = 0;
5759
5760         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5761                 nested_vmx_vmexit(vcpu);
5762                 return 1;
5763         }
5764
5765         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5766                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5767                 vcpu->run->fail_entry.hardware_entry_failure_reason
5768                         = exit_reason;
5769                 return 0;
5770         }
5771
5772         if (unlikely(vmx->fail)) {
5773                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5774                 vcpu->run->fail_entry.hardware_entry_failure_reason
5775                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5776                 return 0;
5777         }
5778
5779         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5780                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5781                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5782                         exit_reason != EXIT_REASON_TASK_SWITCH))
5783                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5784                        "(0x%x) and exit reason is 0x%x\n",
5785                        __func__, vectoring_info, exit_reason);
5786
5787         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5788             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5789                                         get_vmcs12(vcpu), vcpu)))) {
5790                 if (vmx_interrupt_allowed(vcpu)) {
5791                         vmx->soft_vnmi_blocked = 0;
5792                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5793                            vcpu->arch.nmi_pending) {
5794                         /*
5795                          * This CPU don't support us in finding the end of an
5796                          * NMI-blocked window if the guest runs with IRQs
5797                          * disabled. So we pull the trigger after 1 s of
5798                          * futile waiting, but inform the user about this.
5799                          */
5800                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5801                                "state on VCPU %d after 1 s timeout\n",
5802                                __func__, vcpu->vcpu_id);
5803                         vmx->soft_vnmi_blocked = 0;
5804                 }
5805         }
5806
5807         if (exit_reason < kvm_vmx_max_exit_handlers
5808             && kvm_vmx_exit_handlers[exit_reason])
5809                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5810         else {
5811                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5812                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5813         }
5814         return 0;
5815 }
5816
5817 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5818 {
5819         if (irr == -1 || tpr < irr) {
5820                 vmcs_write32(TPR_THRESHOLD, 0);
5821                 return;
5822         }
5823
5824         vmcs_write32(TPR_THRESHOLD, irr);
5825 }
5826
5827 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5828 {
5829         u32 exit_intr_info;
5830
5831         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5832               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5833                 return;
5834
5835         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5836         exit_intr_info = vmx->exit_intr_info;
5837
5838         /* Handle machine checks before interrupts are enabled */
5839         if (is_machine_check(exit_intr_info))
5840                 kvm_machine_check();
5841
5842         /* We need to handle NMIs before interrupts are enabled */
5843         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5844             (exit_intr_info & INTR_INFO_VALID_MASK)) {
5845                 kvm_before_handle_nmi(&vmx->vcpu);
5846                 asm("int $2");
5847                 kvm_after_handle_nmi(&vmx->vcpu);
5848         }
5849 }
5850
5851 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5852 {
5853         u32 exit_intr_info;
5854         bool unblock_nmi;
5855         u8 vector;
5856         bool idtv_info_valid;
5857
5858         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5859
5860         if (cpu_has_virtual_nmis()) {
5861                 if (vmx->nmi_known_unmasked)
5862                         return;
5863                 /*
5864                  * Can't use vmx->exit_intr_info since we're not sure what
5865                  * the exit reason is.
5866                  */
5867                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5868                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5869                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5870                 /*
5871                  * SDM 3: 27.7.1.2 (September 2008)
5872                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
5873                  * a guest IRET fault.
5874                  * SDM 3: 23.2.2 (September 2008)
5875                  * Bit 12 is undefined in any of the following cases:
5876                  *  If the VM exit sets the valid bit in the IDT-vectoring
5877                  *   information field.
5878                  *  If the VM exit is due to a double fault.
5879                  */
5880                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5881                     vector != DF_VECTOR && !idtv_info_valid)
5882                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5883                                       GUEST_INTR_STATE_NMI);
5884                 else
5885                         vmx->nmi_known_unmasked =
5886                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5887                                   & GUEST_INTR_STATE_NMI);
5888         } else if (unlikely(vmx->soft_vnmi_blocked))
5889                 vmx->vnmi_blocked_time +=
5890                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5891 }
5892
5893 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5894                                       u32 idt_vectoring_info,
5895                                       int instr_len_field,
5896                                       int error_code_field)
5897 {
5898         u8 vector;
5899         int type;
5900         bool idtv_info_valid;
5901
5902         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5903
5904         vmx->vcpu.arch.nmi_injected = false;
5905         kvm_clear_exception_queue(&vmx->vcpu);
5906         kvm_clear_interrupt_queue(&vmx->vcpu);
5907
5908         if (!idtv_info_valid)
5909                 return;
5910
5911         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
5912
5913         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5914         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
5915
5916         switch (type) {
5917         case INTR_TYPE_NMI_INTR:
5918                 vmx->vcpu.arch.nmi_injected = true;
5919                 /*
5920                  * SDM 3: 27.7.1.2 (September 2008)
5921                  * Clear bit "block by NMI" before VM entry if a NMI
5922                  * delivery faulted.
5923                  */
5924                 vmx_set_nmi_mask(&vmx->vcpu, false);
5925                 break;
5926         case INTR_TYPE_SOFT_EXCEPTION:
5927                 vmx->vcpu.arch.event_exit_inst_len =
5928                         vmcs_read32(instr_len_field);
5929                 /* fall through */
5930         case INTR_TYPE_HARD_EXCEPTION:
5931                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
5932                         u32 err = vmcs_read32(error_code_field);
5933                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
5934                 } else
5935                         kvm_queue_exception(&vmx->vcpu, vector);
5936                 break;
5937         case INTR_TYPE_SOFT_INTR:
5938                 vmx->vcpu.arch.event_exit_inst_len =
5939                         vmcs_read32(instr_len_field);
5940                 /* fall through */
5941         case INTR_TYPE_EXT_INTR:
5942                 kvm_queue_interrupt(&vmx->vcpu, vector,
5943                         type == INTR_TYPE_SOFT_INTR);
5944                 break;
5945         default:
5946                 break;
5947         }
5948 }
5949
5950 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
5951 {
5952         if (is_guest_mode(&vmx->vcpu))
5953                 return;
5954         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
5955                                   VM_EXIT_INSTRUCTION_LEN,
5956                                   IDT_VECTORING_ERROR_CODE);
5957 }
5958
5959 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
5960 {
5961         if (is_guest_mode(vcpu))
5962                 return;
5963         __vmx_complete_interrupts(to_vmx(vcpu),
5964                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5965                                   VM_ENTRY_INSTRUCTION_LEN,
5966                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
5967
5968         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
5969 }
5970
5971 #ifdef CONFIG_X86_64
5972 #define R "r"
5973 #define Q "q"
5974 #else
5975 #define R "e"
5976 #define Q "l"
5977 #endif
5978
5979 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
5980 {
5981         struct vcpu_vmx *vmx = to_vmx(vcpu);
5982
5983         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
5984                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5985                 if (vmcs12->idt_vectoring_info_field &
5986                                 VECTORING_INFO_VALID_MASK) {
5987                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
5988                                 vmcs12->idt_vectoring_info_field);
5989                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
5990                                 vmcs12->vm_exit_instruction_len);
5991                         if (vmcs12->idt_vectoring_info_field &
5992                                         VECTORING_INFO_DELIVER_CODE_MASK)
5993                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
5994                                         vmcs12->idt_vectoring_error_code);
5995                 }
5996         }
5997
5998         /* Record the guest's net vcpu time for enforced NMI injections. */
5999         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6000                 vmx->entry_time = ktime_get();
6001
6002         /* Don't enter VMX if guest state is invalid, let the exit handler
6003            start emulation until we arrive back to a valid state */
6004         if (vmx->emulation_required && emulate_invalid_guest_state)
6005                 return;
6006
6007         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6008                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6009         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6010                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6011
6012         /* When single-stepping over STI and MOV SS, we must clear the
6013          * corresponding interruptibility bits in the guest state. Otherwise
6014          * vmentry fails as it then expects bit 14 (BS) in pending debug
6015          * exceptions being set, but that's not correct for the guest debugging
6016          * case. */
6017         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6018                 vmx_set_interrupt_shadow(vcpu, 0);
6019
6020         vmx->__launched = vmx->loaded_vmcs->launched;
6021         asm(
6022                 /* Store host registers */
6023                 "push %%"R"dx; push %%"R"bp;"
6024                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6025                 "push %%"R"cx \n\t"
6026                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6027                 "je 1f \n\t"
6028                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6029                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6030                 "1: \n\t"
6031                 /* Reload cr2 if changed */
6032                 "mov %c[cr2](%0), %%"R"ax \n\t"
6033                 "mov %%cr2, %%"R"dx \n\t"
6034                 "cmp %%"R"ax, %%"R"dx \n\t"
6035                 "je 2f \n\t"
6036                 "mov %%"R"ax, %%cr2 \n\t"
6037                 "2: \n\t"
6038                 /* Check if vmlaunch of vmresume is needed */
6039                 "cmpl $0, %c[launched](%0) \n\t"
6040                 /* Load guest registers.  Don't clobber flags. */
6041                 "mov %c[rax](%0), %%"R"ax \n\t"
6042                 "mov %c[rbx](%0), %%"R"bx \n\t"
6043                 "mov %c[rdx](%0), %%"R"dx \n\t"
6044                 "mov %c[rsi](%0), %%"R"si \n\t"
6045                 "mov %c[rdi](%0), %%"R"di \n\t"
6046                 "mov %c[rbp](%0), %%"R"bp \n\t"
6047 #ifdef CONFIG_X86_64
6048                 "mov %c[r8](%0),  %%r8  \n\t"
6049                 "mov %c[r9](%0),  %%r9  \n\t"
6050                 "mov %c[r10](%0), %%r10 \n\t"
6051                 "mov %c[r11](%0), %%r11 \n\t"
6052                 "mov %c[r12](%0), %%r12 \n\t"
6053                 "mov %c[r13](%0), %%r13 \n\t"
6054                 "mov %c[r14](%0), %%r14 \n\t"
6055                 "mov %c[r15](%0), %%r15 \n\t"
6056 #endif
6057                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6058
6059                 /* Enter guest mode */
6060                 "jne .Llaunched \n\t"
6061                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6062                 "jmp .Lkvm_vmx_return \n\t"
6063                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6064                 ".Lkvm_vmx_return: "
6065                 /* Save guest registers, load host registers, keep flags */
6066                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6067                 "pop %0 \n\t"
6068                 "mov %%"R"ax, %c[rax](%0) \n\t"
6069                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6070                 "pop"Q" %c[rcx](%0) \n\t"
6071                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6072                 "mov %%"R"si, %c[rsi](%0) \n\t"
6073                 "mov %%"R"di, %c[rdi](%0) \n\t"
6074                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6075 #ifdef CONFIG_X86_64
6076                 "mov %%r8,  %c[r8](%0) \n\t"
6077                 "mov %%r9,  %c[r9](%0) \n\t"
6078                 "mov %%r10, %c[r10](%0) \n\t"
6079                 "mov %%r11, %c[r11](%0) \n\t"
6080                 "mov %%r12, %c[r12](%0) \n\t"
6081                 "mov %%r13, %c[r13](%0) \n\t"
6082                 "mov %%r14, %c[r14](%0) \n\t"
6083                 "mov %%r15, %c[r15](%0) \n\t"
6084 #endif
6085                 "mov %%cr2, %%"R"ax   \n\t"
6086                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6087
6088                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6089                 "setbe %c[fail](%0) \n\t"
6090               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6091                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6092                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6093                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6094                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6095                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6096                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6097                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6098                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6099                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6100                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6101 #ifdef CONFIG_X86_64
6102                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6103                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6104                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6105                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6106                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6107                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6108                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6109                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6110 #endif
6111                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6112                 [wordsize]"i"(sizeof(ulong))
6113               : "cc", "memory"
6114                 , R"ax", R"bx", R"di", R"si"
6115 #ifdef CONFIG_X86_64
6116                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6117 #endif
6118               );
6119
6120         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6121                                   | (1 << VCPU_EXREG_RFLAGS)
6122                                   | (1 << VCPU_EXREG_CPL)
6123                                   | (1 << VCPU_EXREG_PDPTR)
6124                                   | (1 << VCPU_EXREG_SEGMENTS)
6125                                   | (1 << VCPU_EXREG_CR3));
6126         vcpu->arch.regs_dirty = 0;
6127
6128         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6129
6130         if (is_guest_mode(vcpu)) {
6131                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6132                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6133                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6134                         vmcs12->idt_vectoring_error_code =
6135                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6136                         vmcs12->vm_exit_instruction_len =
6137                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6138                 }
6139         }
6140
6141         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6142         vmx->loaded_vmcs->launched = 1;
6143
6144         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6145         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6146
6147         vmx_complete_atomic_exit(vmx);
6148         vmx_recover_nmi_blocking(vmx);
6149         vmx_complete_interrupts(vmx);
6150 }
6151
6152 #undef R
6153 #undef Q
6154
6155 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6156 {
6157         struct vcpu_vmx *vmx = to_vmx(vcpu);
6158
6159         free_vpid(vmx);
6160         free_nested(vmx);
6161         free_loaded_vmcs(vmx->loaded_vmcs);
6162         kfree(vmx->guest_msrs);
6163         kvm_vcpu_uninit(vcpu);
6164         kmem_cache_free(kvm_vcpu_cache, vmx);
6165 }
6166
6167 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6168 {
6169         int err;
6170         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6171         int cpu;
6172
6173         if (!vmx)
6174                 return ERR_PTR(-ENOMEM);
6175
6176         allocate_vpid(vmx);
6177
6178         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6179         if (err)
6180                 goto free_vcpu;
6181
6182         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6183         err = -ENOMEM;
6184         if (!vmx->guest_msrs) {
6185                 goto uninit_vcpu;
6186         }
6187
6188         vmx->loaded_vmcs = &vmx->vmcs01;
6189         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6190         if (!vmx->loaded_vmcs->vmcs)
6191                 goto free_msrs;
6192         if (!vmm_exclusive)
6193                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6194         loaded_vmcs_init(vmx->loaded_vmcs);
6195         if (!vmm_exclusive)
6196                 kvm_cpu_vmxoff();
6197
6198         cpu = get_cpu();
6199         vmx_vcpu_load(&vmx->vcpu, cpu);
6200         vmx->vcpu.cpu = cpu;
6201         err = vmx_vcpu_setup(vmx);
6202         vmx_vcpu_put(&vmx->vcpu);
6203         put_cpu();
6204         if (err)
6205                 goto free_vmcs;
6206         if (vm_need_virtualize_apic_accesses(kvm))
6207                 err = alloc_apic_access_page(kvm);
6208                 if (err)
6209                         goto free_vmcs;
6210
6211         if (enable_ept) {
6212                 if (!kvm->arch.ept_identity_map_addr)
6213                         kvm->arch.ept_identity_map_addr =
6214                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6215                 err = -ENOMEM;
6216                 if (alloc_identity_pagetable(kvm) != 0)
6217                         goto free_vmcs;
6218                 if (!init_rmode_identity_map(kvm))
6219                         goto free_vmcs;
6220         }
6221
6222         vmx->nested.current_vmptr = -1ull;
6223         vmx->nested.current_vmcs12 = NULL;
6224
6225         return &vmx->vcpu;
6226
6227 free_vmcs:
6228         free_vmcs(vmx->loaded_vmcs->vmcs);
6229 free_msrs:
6230         kfree(vmx->guest_msrs);
6231 uninit_vcpu:
6232         kvm_vcpu_uninit(&vmx->vcpu);
6233 free_vcpu:
6234         free_vpid(vmx);
6235         kmem_cache_free(kvm_vcpu_cache, vmx);
6236         return ERR_PTR(err);
6237 }
6238
6239 static void __init vmx_check_processor_compat(void *rtn)
6240 {
6241         struct vmcs_config vmcs_conf;
6242
6243         *(int *)rtn = 0;
6244         if (setup_vmcs_config(&vmcs_conf) < 0)
6245                 *(int *)rtn = -EIO;
6246         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6247                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6248                                 smp_processor_id());
6249                 *(int *)rtn = -EIO;
6250         }
6251 }
6252
6253 static int get_ept_level(void)
6254 {
6255         return VMX_EPT_DEFAULT_GAW + 1;
6256 }
6257
6258 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6259 {
6260         u64 ret;
6261
6262         /* For VT-d and EPT combination
6263          * 1. MMIO: always map as UC
6264          * 2. EPT with VT-d:
6265          *   a. VT-d without snooping control feature: can't guarantee the
6266          *      result, try to trust guest.
6267          *   b. VT-d with snooping control feature: snooping control feature of
6268          *      VT-d engine can guarantee the cache correctness. Just set it
6269          *      to WB to keep consistent with host. So the same as item 3.
6270          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6271          *    consistent with host MTRR
6272          */
6273         if (is_mmio)
6274                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6275         else if (vcpu->kvm->arch.iommu_domain &&
6276                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6277                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6278                       VMX_EPT_MT_EPTE_SHIFT;
6279         else
6280                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6281                         | VMX_EPT_IPAT_BIT;
6282
6283         return ret;
6284 }
6285
6286 static int vmx_get_lpage_level(void)
6287 {
6288         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6289                 return PT_DIRECTORY_LEVEL;
6290         else
6291                 /* For shadow and EPT supported 1GB page */
6292                 return PT_PDPE_LEVEL;
6293 }
6294
6295 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6296 {
6297         struct kvm_cpuid_entry2 *best;
6298         struct vcpu_vmx *vmx = to_vmx(vcpu);
6299         u32 exec_control;
6300
6301         vmx->rdtscp_enabled = false;
6302         if (vmx_rdtscp_supported()) {
6303                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6304                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6305                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6306                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6307                                 vmx->rdtscp_enabled = true;
6308                         else {
6309                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6310                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6311                                                 exec_control);
6312                         }
6313                 }
6314         }
6315 }
6316
6317 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6318 {
6319         if (func == 1 && nested)
6320                 entry->ecx |= bit(X86_FEATURE_VMX);
6321 }
6322
6323 /*
6324  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6325  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6326  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6327  * guest in a way that will both be appropriate to L1's requests, and our
6328  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6329  * function also has additional necessary side-effects, like setting various
6330  * vcpu->arch fields.
6331  */
6332 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6333 {
6334         struct vcpu_vmx *vmx = to_vmx(vcpu);
6335         u32 exec_control;
6336
6337         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6338         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6339         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6340         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6341         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6342         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6343         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6344         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6345         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6346         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6347         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6348         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6349         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6350         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6351         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6352         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6353         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6354         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6355         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6356         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6357         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6358         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6359         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6360         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6361         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6362         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6363         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6364         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6365         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6366         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6367         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6368         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6369         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6370         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6371         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6372         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6373
6374         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6375         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6376                 vmcs12->vm_entry_intr_info_field);
6377         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6378                 vmcs12->vm_entry_exception_error_code);
6379         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6380                 vmcs12->vm_entry_instruction_len);
6381         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6382                 vmcs12->guest_interruptibility_info);
6383         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6384         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6385         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6386         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6387         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6388                 vmcs12->guest_pending_dbg_exceptions);
6389         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6390         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6391
6392         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6393
6394         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6395                 (vmcs_config.pin_based_exec_ctrl |
6396                  vmcs12->pin_based_vm_exec_control));
6397
6398         /*
6399          * Whether page-faults are trapped is determined by a combination of
6400          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6401          * If enable_ept, L0 doesn't care about page faults and we should
6402          * set all of these to L1's desires. However, if !enable_ept, L0 does
6403          * care about (at least some) page faults, and because it is not easy
6404          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6405          * to exit on each and every L2 page fault. This is done by setting
6406          * MASK=MATCH=0 and (see below) EB.PF=1.
6407          * Note that below we don't need special code to set EB.PF beyond the
6408          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6409          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6410          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6411          *
6412          * A problem with this approach (when !enable_ept) is that L1 may be
6413          * injected with more page faults than it asked for. This could have
6414          * caused problems, but in practice existing hypervisors don't care.
6415          * To fix this, we will need to emulate the PFEC checking (on the L1
6416          * page tables), using walk_addr(), when injecting PFs to L1.
6417          */
6418         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6419                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6420         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6421                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6422
6423         if (cpu_has_secondary_exec_ctrls()) {
6424                 u32 exec_control = vmx_secondary_exec_control(vmx);
6425                 if (!vmx->rdtscp_enabled)
6426                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6427                 /* Take the following fields only from vmcs12 */
6428                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6429                 if (nested_cpu_has(vmcs12,
6430                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6431                         exec_control |= vmcs12->secondary_vm_exec_control;
6432
6433                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6434                         /*
6435                          * Translate L1 physical address to host physical
6436                          * address for vmcs02. Keep the page pinned, so this
6437                          * physical address remains valid. We keep a reference
6438                          * to it so we can release it later.
6439                          */
6440                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6441                                 nested_release_page(vmx->nested.apic_access_page);
6442                         vmx->nested.apic_access_page =
6443                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6444                         /*
6445                          * If translation failed, no matter: This feature asks
6446                          * to exit when accessing the given address, and if it
6447                          * can never be accessed, this feature won't do
6448                          * anything anyway.
6449                          */
6450                         if (!vmx->nested.apic_access_page)
6451                                 exec_control &=
6452                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6453                         else
6454                                 vmcs_write64(APIC_ACCESS_ADDR,
6455                                   page_to_phys(vmx->nested.apic_access_page));
6456                 }
6457
6458                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6459         }
6460
6461
6462         /*
6463          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6464          * Some constant fields are set here by vmx_set_constant_host_state().
6465          * Other fields are different per CPU, and will be set later when
6466          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6467          */
6468         vmx_set_constant_host_state();
6469
6470         /*
6471          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6472          * entry, but only if the current (host) sp changed from the value
6473          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6474          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6475          * here we just force the write to happen on entry.
6476          */
6477         vmx->host_rsp = 0;
6478
6479         exec_control = vmx_exec_control(vmx); /* L0's desires */
6480         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6481         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6482         exec_control &= ~CPU_BASED_TPR_SHADOW;
6483         exec_control |= vmcs12->cpu_based_vm_exec_control;
6484         /*
6485          * Merging of IO and MSR bitmaps not currently supported.
6486          * Rather, exit every time.
6487          */
6488         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6489         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6490         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6491
6492         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6493
6494         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6495          * bitwise-or of what L1 wants to trap for L2, and what we want to
6496          * trap. Note that CR0.TS also needs updating - we do this later.
6497          */
6498         update_exception_bitmap(vcpu);
6499         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6500         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6501
6502         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6503         vmcs_write32(VM_EXIT_CONTROLS,
6504                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6505         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6506                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6507
6508         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6509                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6510         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6511                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6512
6513
6514         set_cr4_guest_host_mask(vmx);
6515
6516         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6517                 vmcs_write64(TSC_OFFSET,
6518                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6519         else
6520                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6521
6522         if (enable_vpid) {
6523                 /*
6524                  * Trivially support vpid by letting L2s share their parent
6525                  * L1's vpid. TODO: move to a more elaborate solution, giving
6526                  * each L2 its own vpid and exposing the vpid feature to L1.
6527                  */
6528                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6529                 vmx_flush_tlb(vcpu);
6530         }
6531
6532         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6533                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6534         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6535                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6536         else
6537                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6538         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6539         vmx_set_efer(vcpu, vcpu->arch.efer);
6540
6541         /*
6542          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6543          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6544          * The CR0_READ_SHADOW is what L2 should have expected to read given
6545          * the specifications by L1; It's not enough to take
6546          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6547          * have more bits than L1 expected.
6548          */
6549         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6550         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6551
6552         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6553         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6554
6555         /* shadow page tables on either EPT or shadow page tables */
6556         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6557         kvm_mmu_reset_context(vcpu);
6558
6559         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6560         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6561 }
6562
6563 /*
6564  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6565  * for running an L2 nested guest.
6566  */
6567 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6568 {
6569         struct vmcs12 *vmcs12;
6570         struct vcpu_vmx *vmx = to_vmx(vcpu);
6571         int cpu;
6572         struct loaded_vmcs *vmcs02;
6573
6574         if (!nested_vmx_check_permission(vcpu) ||
6575             !nested_vmx_check_vmcs12(vcpu))
6576                 return 1;
6577
6578         skip_emulated_instruction(vcpu);
6579         vmcs12 = get_vmcs12(vcpu);
6580
6581         /*
6582          * The nested entry process starts with enforcing various prerequisites
6583          * on vmcs12 as required by the Intel SDM, and act appropriately when
6584          * they fail: As the SDM explains, some conditions should cause the
6585          * instruction to fail, while others will cause the instruction to seem
6586          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6587          * To speed up the normal (success) code path, we should avoid checking
6588          * for misconfigurations which will anyway be caught by the processor
6589          * when using the merged vmcs02.
6590          */
6591         if (vmcs12->launch_state == launch) {
6592                 nested_vmx_failValid(vcpu,
6593                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6594                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6595                 return 1;
6596         }
6597
6598         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6599                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6600                 /*TODO: Also verify bits beyond physical address width are 0*/
6601                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6602                 return 1;
6603         }
6604
6605         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6606                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6607                 /*TODO: Also verify bits beyond physical address width are 0*/
6608                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6609                 return 1;
6610         }
6611
6612         if (vmcs12->vm_entry_msr_load_count > 0 ||
6613             vmcs12->vm_exit_msr_load_count > 0 ||
6614             vmcs12->vm_exit_msr_store_count > 0) {
6615                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6616                                     __func__);
6617                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6618                 return 1;
6619         }
6620
6621         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6622               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6623             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6624               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6625             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6626               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6627             !vmx_control_verify(vmcs12->vm_exit_controls,
6628               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6629             !vmx_control_verify(vmcs12->vm_entry_controls,
6630               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6631         {
6632                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6633                 return 1;
6634         }
6635
6636         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6637             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6638                 nested_vmx_failValid(vcpu,
6639                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6640                 return 1;
6641         }
6642
6643         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6644             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6645                 nested_vmx_entry_failure(vcpu, vmcs12,
6646                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6647                 return 1;
6648         }
6649         if (vmcs12->vmcs_link_pointer != -1ull) {
6650                 nested_vmx_entry_failure(vcpu, vmcs12,
6651                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6652                 return 1;
6653         }
6654
6655         /*
6656          * We're finally done with prerequisite checking, and can start with
6657          * the nested entry.
6658          */
6659
6660         vmcs02 = nested_get_current_vmcs02(vmx);
6661         if (!vmcs02)
6662                 return -ENOMEM;
6663
6664         enter_guest_mode(vcpu);
6665
6666         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6667
6668         cpu = get_cpu();
6669         vmx->loaded_vmcs = vmcs02;
6670         vmx_vcpu_put(vcpu);
6671         vmx_vcpu_load(vcpu, cpu);
6672         vcpu->cpu = cpu;
6673         put_cpu();
6674
6675         vmcs12->launch_state = 1;
6676
6677         prepare_vmcs02(vcpu, vmcs12);
6678
6679         /*
6680          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6681          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6682          * returned as far as L1 is concerned. It will only return (and set
6683          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6684          */
6685         return 1;
6686 }
6687
6688 /*
6689  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6690  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6691  * This function returns the new value we should put in vmcs12.guest_cr0.
6692  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6693  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6694  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6695  *     didn't trap the bit, because if L1 did, so would L0).
6696  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6697  *     been modified by L2, and L1 knows it. So just leave the old value of
6698  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6699  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6700  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6701  *     changed these bits, and therefore they need to be updated, but L0
6702  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6703  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6704  */
6705 static inline unsigned long
6706 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6707 {
6708         return
6709         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6710         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6711         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6712                         vcpu->arch.cr0_guest_owned_bits));
6713 }
6714
6715 static inline unsigned long
6716 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6717 {
6718         return
6719         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6720         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6721         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6722                         vcpu->arch.cr4_guest_owned_bits));
6723 }
6724
6725 /*
6726  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6727  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6728  * and this function updates it to reflect the changes to the guest state while
6729  * L2 was running (and perhaps made some exits which were handled directly by L0
6730  * without going back to L1), and to reflect the exit reason.
6731  * Note that we do not have to copy here all VMCS fields, just those that
6732  * could have changed by the L2 guest or the exit - i.e., the guest-state and
6733  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6734  * which already writes to vmcs12 directly.
6735  */
6736 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6737 {
6738         /* update guest state fields: */
6739         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6740         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6741
6742         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6743         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6744         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6745         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6746
6747         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6748         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6749         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6750         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6751         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6752         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6753         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6754         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6755         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6756         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6757         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6758         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6759         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6760         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6761         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6762         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6763         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6764         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6765         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6766         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6767         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6768         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6769         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6770         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6771         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6772         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6773         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6774         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6775         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6776         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6777         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6778         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6779         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6780         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6781         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6782         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6783
6784         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6785         vmcs12->guest_interruptibility_info =
6786                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6787         vmcs12->guest_pending_dbg_exceptions =
6788                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6789
6790         /* TODO: These cannot have changed unless we have MSR bitmaps and
6791          * the relevant bit asks not to trap the change */
6792         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6793         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6794                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6795         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6796         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6797         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6798
6799         /* update exit information fields: */
6800
6801         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
6802         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6803
6804         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6805         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6806         vmcs12->idt_vectoring_info_field =
6807                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6808         vmcs12->idt_vectoring_error_code =
6809                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6810         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6811         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6812
6813         /* clear vm-entry fields which are to be cleared on exit */
6814         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6815                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6816 }
6817
6818 /*
6819  * A part of what we need to when the nested L2 guest exits and we want to
6820  * run its L1 parent, is to reset L1's guest state to the host state specified
6821  * in vmcs12.
6822  * This function is to be called not only on normal nested exit, but also on
6823  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6824  * Failures During or After Loading Guest State").
6825  * This function should be called when the active VMCS is L1's (vmcs01).
6826  */
6827 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6828 {
6829         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6830                 vcpu->arch.efer = vmcs12->host_ia32_efer;
6831         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6832                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6833         else
6834                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6835         vmx_set_efer(vcpu, vcpu->arch.efer);
6836
6837         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6838         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6839         /*
6840          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6841          * actually changed, because it depends on the current state of
6842          * fpu_active (which may have changed).
6843          * Note that vmx_set_cr0 refers to efer set above.
6844          */
6845         kvm_set_cr0(vcpu, vmcs12->host_cr0);
6846         /*
6847          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6848          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6849          * but we also need to update cr0_guest_host_mask and exception_bitmap.
6850          */
6851         update_exception_bitmap(vcpu);
6852         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6853         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6854
6855         /*
6856          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6857          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6858          */
6859         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6860         kvm_set_cr4(vcpu, vmcs12->host_cr4);
6861
6862         /* shadow page tables on either EPT or shadow page tables */
6863         kvm_set_cr3(vcpu, vmcs12->host_cr3);
6864         kvm_mmu_reset_context(vcpu);
6865
6866         if (enable_vpid) {
6867                 /*
6868                  * Trivially support vpid by letting L2s share their parent
6869                  * L1's vpid. TODO: move to a more elaborate solution, giving
6870                  * each L2 its own vpid and exposing the vpid feature to L1.
6871                  */
6872                 vmx_flush_tlb(vcpu);
6873         }
6874
6875
6876         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6877         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6878         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6879         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6880         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6881         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6882         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6883         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6884         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6885         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6886         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6887         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6888         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6889         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6890         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
6891
6892         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
6893                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
6894         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
6895                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
6896                         vmcs12->host_ia32_perf_global_ctrl);
6897 }
6898
6899 /*
6900  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
6901  * and modify vmcs12 to make it see what it would expect to see there if
6902  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
6903  */
6904 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
6905 {
6906         struct vcpu_vmx *vmx = to_vmx(vcpu);
6907         int cpu;
6908         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6909
6910         leave_guest_mode(vcpu);
6911         prepare_vmcs12(vcpu, vmcs12);
6912
6913         cpu = get_cpu();
6914         vmx->loaded_vmcs = &vmx->vmcs01;
6915         vmx_vcpu_put(vcpu);
6916         vmx_vcpu_load(vcpu, cpu);
6917         vcpu->cpu = cpu;
6918         put_cpu();
6919
6920         /* if no vmcs02 cache requested, remove the one we used */
6921         if (VMCS02_POOL_SIZE == 0)
6922                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
6923
6924         load_vmcs12_host_state(vcpu, vmcs12);
6925
6926         /* Update TSC_OFFSET if TSC was changed while L2 ran */
6927         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6928
6929         /* This is needed for same reason as it was needed in prepare_vmcs02 */
6930         vmx->host_rsp = 0;
6931
6932         /* Unpin physical memory we referred to in vmcs02 */
6933         if (vmx->nested.apic_access_page) {
6934                 nested_release_page(vmx->nested.apic_access_page);
6935                 vmx->nested.apic_access_page = 0;
6936         }
6937
6938         /*
6939          * Exiting from L2 to L1, we're now back to L1 which thinks it just
6940          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
6941          * success or failure flag accordingly.
6942          */
6943         if (unlikely(vmx->fail)) {
6944                 vmx->fail = 0;
6945                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
6946         } else
6947                 nested_vmx_succeed(vcpu);
6948 }
6949
6950 /*
6951  * L1's failure to enter L2 is a subset of a normal exit, as explained in
6952  * 23.7 "VM-entry failures during or after loading guest state" (this also
6953  * lists the acceptable exit-reason and exit-qualification parameters).
6954  * It should only be called before L2 actually succeeded to run, and when
6955  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
6956  */
6957 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
6958                         struct vmcs12 *vmcs12,
6959                         u32 reason, unsigned long qualification)
6960 {
6961         load_vmcs12_host_state(vcpu, vmcs12);
6962         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
6963         vmcs12->exit_qualification = qualification;
6964         nested_vmx_succeed(vcpu);
6965 }
6966
6967 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6968                                struct x86_instruction_info *info,
6969                                enum x86_intercept_stage stage)
6970 {
6971         return X86EMUL_CONTINUE;
6972 }
6973
6974 static struct kvm_x86_ops vmx_x86_ops = {
6975         .cpu_has_kvm_support = cpu_has_kvm_support,
6976         .disabled_by_bios = vmx_disabled_by_bios,
6977         .hardware_setup = hardware_setup,
6978         .hardware_unsetup = hardware_unsetup,
6979         .check_processor_compatibility = vmx_check_processor_compat,
6980         .hardware_enable = hardware_enable,
6981         .hardware_disable = hardware_disable,
6982         .cpu_has_accelerated_tpr = report_flexpriority,
6983
6984         .vcpu_create = vmx_create_vcpu,
6985         .vcpu_free = vmx_free_vcpu,
6986         .vcpu_reset = vmx_vcpu_reset,
6987
6988         .prepare_guest_switch = vmx_save_host_state,
6989         .vcpu_load = vmx_vcpu_load,
6990         .vcpu_put = vmx_vcpu_put,
6991
6992         .set_guest_debug = set_guest_debug,
6993         .get_msr = vmx_get_msr,
6994         .set_msr = vmx_set_msr,
6995         .get_segment_base = vmx_get_segment_base,
6996         .get_segment = vmx_get_segment,
6997         .set_segment = vmx_set_segment,
6998         .get_cpl = vmx_get_cpl,
6999         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7000         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7001         .decache_cr3 = vmx_decache_cr3,
7002         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7003         .set_cr0 = vmx_set_cr0,
7004         .set_cr3 = vmx_set_cr3,
7005         .set_cr4 = vmx_set_cr4,
7006         .set_efer = vmx_set_efer,
7007         .get_idt = vmx_get_idt,
7008         .set_idt = vmx_set_idt,
7009         .get_gdt = vmx_get_gdt,
7010         .set_gdt = vmx_set_gdt,
7011         .set_dr7 = vmx_set_dr7,
7012         .cache_reg = vmx_cache_reg,
7013         .get_rflags = vmx_get_rflags,
7014         .set_rflags = vmx_set_rflags,
7015         .fpu_activate = vmx_fpu_activate,
7016         .fpu_deactivate = vmx_fpu_deactivate,
7017
7018         .tlb_flush = vmx_flush_tlb,
7019
7020         .run = vmx_vcpu_run,
7021         .handle_exit = vmx_handle_exit,
7022         .skip_emulated_instruction = skip_emulated_instruction,
7023         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7024         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7025         .patch_hypercall = vmx_patch_hypercall,
7026         .set_irq = vmx_inject_irq,
7027         .set_nmi = vmx_inject_nmi,
7028         .queue_exception = vmx_queue_exception,
7029         .cancel_injection = vmx_cancel_injection,
7030         .interrupt_allowed = vmx_interrupt_allowed,
7031         .nmi_allowed = vmx_nmi_allowed,
7032         .get_nmi_mask = vmx_get_nmi_mask,
7033         .set_nmi_mask = vmx_set_nmi_mask,
7034         .enable_nmi_window = enable_nmi_window,
7035         .enable_irq_window = enable_irq_window,
7036         .update_cr8_intercept = update_cr8_intercept,
7037
7038         .set_tss_addr = vmx_set_tss_addr,
7039         .get_tdp_level = get_ept_level,
7040         .get_mt_mask = vmx_get_mt_mask,
7041
7042         .get_exit_info = vmx_get_exit_info,
7043
7044         .get_lpage_level = vmx_get_lpage_level,
7045
7046         .cpuid_update = vmx_cpuid_update,
7047
7048         .rdtscp_supported = vmx_rdtscp_supported,
7049
7050         .set_supported_cpuid = vmx_set_supported_cpuid,
7051
7052         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7053
7054         .set_tsc_khz = vmx_set_tsc_khz,
7055         .write_tsc_offset = vmx_write_tsc_offset,
7056         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7057         .compute_tsc_offset = vmx_compute_tsc_offset,
7058         .read_l1_tsc = vmx_read_l1_tsc,
7059
7060         .set_tdp_cr3 = vmx_set_cr3,
7061
7062         .check_intercept = vmx_check_intercept,
7063 };
7064
7065 static int __init vmx_init(void)
7066 {
7067         int r, i;
7068
7069         rdmsrl_safe(MSR_EFER, &host_efer);
7070
7071         for (i = 0; i < NR_VMX_MSR; ++i)
7072                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7073
7074         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7075         if (!vmx_io_bitmap_a)
7076                 return -ENOMEM;
7077
7078         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7079         if (!vmx_io_bitmap_b) {
7080                 r = -ENOMEM;
7081                 goto out;
7082         }
7083
7084         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7085         if (!vmx_msr_bitmap_legacy) {
7086                 r = -ENOMEM;
7087                 goto out1;
7088         }
7089
7090         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7091         if (!vmx_msr_bitmap_longmode) {
7092                 r = -ENOMEM;
7093                 goto out2;
7094         }
7095
7096         /*
7097          * Allow direct access to the PC debug port (it is often used for I/O
7098          * delays, but the vmexits simply slow things down).
7099          */
7100         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7101         clear_bit(0x80, vmx_io_bitmap_a);
7102
7103         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7104
7105         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7106         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7107
7108         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7109
7110         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7111                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7112         if (r)
7113                 goto out3;
7114
7115         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7116         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7117         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7118         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7119         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7120         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7121
7122         if (enable_ept) {
7123                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7124                                 VMX_EPT_EXECUTABLE_MASK);
7125                 ept_set_mmio_spte_mask();
7126                 kvm_enable_tdp();
7127         } else
7128                 kvm_disable_tdp();
7129
7130         return 0;
7131
7132 out3:
7133         free_page((unsigned long)vmx_msr_bitmap_longmode);
7134 out2:
7135         free_page((unsigned long)vmx_msr_bitmap_legacy);
7136 out1:
7137         free_page((unsigned long)vmx_io_bitmap_b);
7138 out:
7139         free_page((unsigned long)vmx_io_bitmap_a);
7140         return r;
7141 }
7142
7143 static void __exit vmx_exit(void)
7144 {
7145         free_page((unsigned long)vmx_msr_bitmap_legacy);
7146         free_page((unsigned long)vmx_msr_bitmap_longmode);
7147         free_page((unsigned long)vmx_io_bitmap_b);
7148         free_page((unsigned long)vmx_io_bitmap_a);
7149
7150         kvm_exit();
7151 }
7152
7153 module_init(vmx_init)
7154 module_exit(vmx_exit)