arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  *
   9  * Authors:
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *   Yaniv Kamay  <yaniv@qumranet.com>
  12  *
  13  * This work is licensed under the terms of the GNU GPL, version 2.  See
  14  * the COPYING file in the top-level directory.
  15  *
  16  */
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/mm.h>
  25 #include <linux/highmem.h>
  26 #include <linux/sched.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/ftrace_event.h>
  29 #include <linux/slab.h>
  30 #include <linux/tboot.h>
  31 #include "kvm_cache_regs.h"
  32 #include "x86.h"
  33
  34 #include <asm/io.h>
  35 #include <asm/desc.h>
  36 #include <asm/vmx.h>
  37 #include <asm/virtext.h>
  38 #include <asm/mce.h>
  39
  40 #include "trace.h"
  41
  42 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  43
  44 MODULE_AUTHOR("Qumranet");
  45 MODULE_LICENSE("GPL");
  46
  47 static int __read_mostly bypass_guest_pf = 1;
  48 module_param(bypass_guest_pf, bool, S_IRUGO);
  49
  50 static int __read_mostly enable_vpid = 1;
  51 module_param_named(vpid, enable_vpid, bool, 0444);
  52
  53 static int __read_mostly flexpriority_enabled = 1;
  54 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  55
  56 static int __read_mostly enable_ept = 1;
  57 module_param_named(ept, enable_ept, bool, S_IRUGO);
  58
  59 static int __read_mostly enable_unrestricted_guest = 1;
  60 module_param_named(unrestricted_guest,
  61                         enable_unrestricted_guest, bool, S_IRUGO);
  62
  63 static int __read_mostly emulate_invalid_guest_state = 0;
  64 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  65
  66 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  67         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  68 #define KVM_GUEST_CR0_MASK                                              \
  69         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  70 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  71         (X86_CR0_WP | X86_CR0_NE)
  72 #define KVM_VM_CR0_ALWAYS_ON                                            \
  73         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  74 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  75         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  76          | X86_CR4_OSXMMEXCPT)
  77
  78 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  79 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
  80
  81 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
  82
  83 /*
  84  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
  85  * ple_gap:    upper bound on the amount of time between two successive
  86  *             executions of PAUSE in a loop. Also indicate if ple enabled.
  87  *             According to test, this time is usually small than 41 cycles.
  88  * ple_window: upper bound on the amount of time a guest is allowed to execute
  89  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
  90  *             less than 2^12 cycles
  91  * Time is measured based on a counter that runs at the same rate as the TSC,
  92  * refer SDM volume 3b section 21.6.13 & 22.1.3.
  93  */
  94 #define KVM_VMX_DEFAULT_PLE_GAP    41
  95 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
  96 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
  97 module_param(ple_gap, int, S_IRUGO);
  98
  99 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 100 module_param(ple_window, int, S_IRUGO);
 101
 102 #define NR_AUTOLOAD_MSRS 1
 103
 104 struct vmcs {
 105         u32 revision_id;
 106         u32 abort;
 107         char data[0];
 108 };
 109
 110 struct shared_msr_entry {
 111         unsigned index;
 112         u64 data;
 113         u64 mask;
 114 };
 115
 116 struct vcpu_vmx {
 117         struct kvm_vcpu       vcpu;
 118         struct list_head      local_vcpus_link;
 119         unsigned long         host_rsp;
 120         int                   launched;
 121         u8                    fail;
 122         u32                   idt_vectoring_info;
 123         struct shared_msr_entry *guest_msrs;
 124         int                   nmsrs;
 125         int                   save_nmsrs;
 126 #ifdef CONFIG_X86_64
 127         u64                   msr_host_kernel_gs_base;
 128         u64                   msr_guest_kernel_gs_base;
 129 #endif
 130         struct vmcs          *vmcs;
 131         struct msr_autoload {
 132                 unsigned nr;
 133                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 134                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 135         } msr_autoload;
 136         struct {
 137                 int           loaded;
 138                 u16           fs_sel, gs_sel, ldt_sel;
 139                 int           gs_ldt_reload_needed;
 140                 int           fs_reload_needed;
 141         } host_state;
 142         struct {
 143                 int vm86_active;
 144                 ulong save_rflags;
 145                 struct kvm_save_segment {
 146                         u16 selector;
 147                         unsigned long base;
 148                         u32 limit;
 149                         u32 ar;
 150                 } tr, es, ds, fs, gs;
 151                 struct {
 152                         bool pending;
 153                         u8 vector;
 154                         unsigned rip;
 155                 } irq;
 156         } rmode;
 157         int vpid;
 158         bool emulation_required;
 159
 160         /* Support for vnmi-less CPUs */
 161         int soft_vnmi_blocked;
 162         ktime_t entry_time;
 163         s64 vnmi_blocked_time;
 164         u32 exit_reason;
 165
 166         bool rdtscp_enabled;
 167 };
 168
 169 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 170 {
 171         return container_of(vcpu, struct vcpu_vmx, vcpu);
 172 }
 173
 174 static int init_rmode(struct kvm *kvm);
 175 static u64 construct_eptp(unsigned long root_hpa);
 176
 177 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 178 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 179 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
 180
 181 static unsigned long *vmx_io_bitmap_a;
 182 static unsigned long *vmx_io_bitmap_b;
 183 static unsigned long *vmx_msr_bitmap_legacy;
 184 static unsigned long *vmx_msr_bitmap_longmode;
 185
 186 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 187 static DEFINE_SPINLOCK(vmx_vpid_lock);
 188
 189 static struct vmcs_config {
 190         int size;
 191         int order;
 192         u32 revision_id;
 193         u32 pin_based_exec_ctrl;
 194         u32 cpu_based_exec_ctrl;
 195         u32 cpu_based_2nd_exec_ctrl;
 196         u32 vmexit_ctrl;
 197         u32 vmentry_ctrl;
 198 } vmcs_config;
 199
 200 static struct vmx_capability {
 201         u32 ept;
 202         u32 vpid;
 203 } vmx_capability;
 204
 205 #define VMX_SEGMENT_FIELD(seg)                                  \
 206         [VCPU_SREG_##seg] = {                                   \
 207                 .selector = GUEST_##seg##_SELECTOR,             \
 208                 .base = GUEST_##seg##_BASE,                     \
 209                 .limit = GUEST_##seg##_LIMIT,                   \
 210                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 211         }
 212
 213 static struct kvm_vmx_segment_field {
 214         unsigned selector;
 215         unsigned base;
 216         unsigned limit;
 217         unsigned ar_bytes;
 218 } kvm_vmx_segment_fields[] = {
 219         VMX_SEGMENT_FIELD(CS),
 220         VMX_SEGMENT_FIELD(DS),
 221         VMX_SEGMENT_FIELD(ES),
 222         VMX_SEGMENT_FIELD(FS),
 223         VMX_SEGMENT_FIELD(GS),
 224         VMX_SEGMENT_FIELD(SS),
 225         VMX_SEGMENT_FIELD(TR),
 226         VMX_SEGMENT_FIELD(LDTR),
 227 };
 228
 229 static u64 host_efer;
 230
 231 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 232
 233 /*
 234  * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
 235  * away by decrementing the array size.
 236  */
 237 static const u32 vmx_msr_index[] = {
 238 #ifdef CONFIG_X86_64
 239         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 240 #endif
 241         MSR_EFER, MSR_TSC_AUX, MSR_K6_STAR,
 242 };
 243 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 244
 245 static inline bool is_page_fault(u32 intr_info)
 246 {
 247         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 248                              INTR_INFO_VALID_MASK)) ==
 249                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 250 }
 251
 252 static inline bool is_no_device(u32 intr_info)
 253 {
 254         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 255                              INTR_INFO_VALID_MASK)) ==
 256                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 257 }
 258
 259 static inline bool is_invalid_opcode(u32 intr_info)
 260 {
 261         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 262                              INTR_INFO_VALID_MASK)) ==
 263                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 264 }
 265
 266 static inline bool is_external_interrupt(u32 intr_info)
 267 {
 268         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 269                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 270 }
 271
 272 static inline bool is_machine_check(u32 intr_info)
 273 {
 274         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 275                              INTR_INFO_VALID_MASK)) ==
 276                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 277 }
 278
 279 static inline bool cpu_has_vmx_msr_bitmap(void)
 280 {
 281         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 282 }
 283
 284 static inline bool cpu_has_vmx_tpr_shadow(void)
 285 {
 286         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 287 }
 288
 289 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 290 {
 291         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 292 }
 293
 294 static inline bool cpu_has_secondary_exec_ctrls(void)
 295 {
 296         return vmcs_config.cpu_based_exec_ctrl &
 297                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 298 }
 299
 300 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 301 {
 302         return vmcs_config.cpu_based_2nd_exec_ctrl &
 303                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 304 }
 305
 306 static inline bool cpu_has_vmx_flexpriority(void)
 307 {
 308         return cpu_has_vmx_tpr_shadow() &&
 309                 cpu_has_vmx_virtualize_apic_accesses();
 310 }
 311
 312 static inline bool cpu_has_vmx_ept_execute_only(void)
 313 {
 314         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 315 }
 316
 317 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 318 {
 319         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 320 }
 321
 322 static inline bool cpu_has_vmx_eptp_writeback(void)
 323 {
 324         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 325 }
 326
 327 static inline bool cpu_has_vmx_ept_2m_page(void)
 328 {
 329         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 330 }
 331
 332 static inline bool cpu_has_vmx_ept_1g_page(void)
 333 {
 334         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 335 }
 336
 337 static inline bool cpu_has_vmx_invept_individual_addr(void)
 338 {
 339         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 340 }
 341
 342 static inline bool cpu_has_vmx_invept_context(void)
 343 {
 344         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 345 }
 346
 347 static inline bool cpu_has_vmx_invept_global(void)
 348 {
 349         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 350 }
 351
 352 static inline bool cpu_has_vmx_ept(void)
 353 {
 354         return vmcs_config.cpu_based_2nd_exec_ctrl &
 355                 SECONDARY_EXEC_ENABLE_EPT;
 356 }
 357
 358 static inline bool cpu_has_vmx_unrestricted_guest(void)
 359 {
 360         return vmcs_config.cpu_based_2nd_exec_ctrl &
 361                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 362 }
 363
 364 static inline bool cpu_has_vmx_ple(void)
 365 {
 366         return vmcs_config.cpu_based_2nd_exec_ctrl &
 367                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 368 }
 369
 370 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 371 {
 372         return flexpriority_enabled && irqchip_in_kernel(kvm);
 373 }
 374
 375 static inline bool cpu_has_vmx_vpid(void)
 376 {
 377         return vmcs_config.cpu_based_2nd_exec_ctrl &
 378                 SECONDARY_EXEC_ENABLE_VPID;
 379 }
 380
 381 static inline bool cpu_has_vmx_rdtscp(void)
 382 {
 383         return vmcs_config.cpu_based_2nd_exec_ctrl &
 384                 SECONDARY_EXEC_RDTSCP;
 385 }
 386
 387 static inline bool cpu_has_virtual_nmis(void)
 388 {
 389         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 390 }
 391
 392 static inline bool report_flexpriority(void)
 393 {
 394         return flexpriority_enabled;
 395 }
 396
 397 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 398 {
 399         int i;
 400
 401         for (i = 0; i < vmx->nmsrs; ++i)
 402                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 403                         return i;
 404         return -1;
 405 }
 406
 407 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 408 {
 409     struct {
 410         u64 vpid : 16;
 411         u64 rsvd : 48;
 412         u64 gva;
 413     } operand = { vpid, 0, gva };
 414
 415     asm volatile (__ex(ASM_VMX_INVVPID)
 416                   /* CF==1 or ZF==1 --> rc = -1 */
 417                   "; ja 1f ; ud2 ; 1:"
 418                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 419 }
 420
 421 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 422 {
 423         struct {
 424                 u64 eptp, gpa;
 425         } operand = {eptp, gpa};
 426
 427         asm volatile (__ex(ASM_VMX_INVEPT)
 428                         /* CF==1 or ZF==1 --> rc = -1 */
 429                         "; ja 1f ; ud2 ; 1:\n"
 430                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 431 }
 432
 433 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 434 {
 435         int i;
 436
 437         i = __find_msr_index(vmx, msr);
 438         if (i >= 0)
 439                 return &vmx->guest_msrs[i];
 440         return NULL;
 441 }
 442
 443 static void vmcs_clear(struct vmcs *vmcs)
 444 {
 445         u64 phys_addr = __pa(vmcs);
 446         u8 error;
 447
 448         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 449                       : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 450                       : "cc", "memory");
 451         if (error)
 452                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 453                        vmcs, phys_addr);
 454 }
 455
 456 static void __vcpu_clear(void *arg)
 457 {
 458         struct vcpu_vmx *vmx = arg;
 459         int cpu = raw_smp_processor_id();
 460
 461         if (vmx->vcpu.cpu == cpu)
 462                 vmcs_clear(vmx->vmcs);
 463         if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
 464                 per_cpu(current_vmcs, cpu) = NULL;
 465         rdtscll(vmx->vcpu.arch.host_tsc);
 466         list_del(&vmx->local_vcpus_link);
 467         vmx->vcpu.cpu = -1;
 468         vmx->launched = 0;
 469 }
 470
 471 static void vcpu_clear(struct vcpu_vmx *vmx)
 472 {
 473         if (vmx->vcpu.cpu == -1)
 474                 return;
 475         smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
 476 }
 477
 478 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
 479 {
 480         if (vmx->vpid == 0)
 481                 return;
 482
 483         __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 484 }
 485
 486 static inline void ept_sync_global(void)
 487 {
 488         if (cpu_has_vmx_invept_global())
 489                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
 490 }
 491
 492 static inline void ept_sync_context(u64 eptp)
 493 {
 494         if (enable_ept) {
 495                 if (cpu_has_vmx_invept_context())
 496                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
 497                 else
 498                         ept_sync_global();
 499         }
 500 }
 501
 502 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
 503 {
 504         if (enable_ept) {
 505                 if (cpu_has_vmx_invept_individual_addr())
 506                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
 507                                         eptp, gpa);
 508                 else
 509                         ept_sync_context(eptp);
 510         }
 511 }
 512
 513 static unsigned long vmcs_readl(unsigned long field)
 514 {
 515         unsigned long value;
 516
 517         asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
 518                       : "=a"(value) : "d"(field) : "cc");
 519         return value;
 520 }
 521
 522 static u16 vmcs_read16(unsigned long field)
 523 {
 524         return vmcs_readl(field);
 525 }
 526
 527 static u32 vmcs_read32(unsigned long field)
 528 {
 529         return vmcs_readl(field);
 530 }
 531
 532 static u64 vmcs_read64(unsigned long field)
 533 {
 534 #ifdef CONFIG_X86_64
 535         return vmcs_readl(field);
 536 #else
 537         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
 538 #endif
 539 }
 540
 541 static noinline void vmwrite_error(unsigned long field, unsigned long value)
 542 {
 543         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
 544                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
 545         dump_stack();
 546 }
 547
 548 static void vmcs_writel(unsigned long field, unsigned long value)
 549 {
 550         u8 error;
 551
 552         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
 553                        : "=q"(error) : "a"(value), "d"(field) : "cc");
 554         if (unlikely(error))
 555                 vmwrite_error(field, value);
 556 }
 557
 558 static void vmcs_write16(unsigned long field, u16 value)
 559 {
 560         vmcs_writel(field, value);
 561 }
 562
 563 static void vmcs_write32(unsigned long field, u32 value)
 564 {
 565         vmcs_writel(field, value);
 566 }
 567
 568 static void vmcs_write64(unsigned long field, u64 value)
 569 {
 570         vmcs_writel(field, value);
 571 #ifndef CONFIG_X86_64
 572         asm volatile ("");
 573         vmcs_writel(field+1, value >> 32);
 574 #endif
 575 }
 576
 577 static void vmcs_clear_bits(unsigned long field, u32 mask)
 578 {
 579         vmcs_writel(field, vmcs_readl(field) & ~mask);
 580 }
 581
 582 static void vmcs_set_bits(unsigned long field, u32 mask)
 583 {
 584         vmcs_writel(field, vmcs_readl(field) | mask);
 585 }
 586
 587 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
 588 {
 589         u32 eb;
 590
 591         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
 592              (1u << NM_VECTOR) | (1u << DB_VECTOR);
 593         if ((vcpu->guest_debug &
 594              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
 595             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
 596                 eb |= 1u << BP_VECTOR;
 597         if (to_vmx(vcpu)->rmode.vm86_active)
 598                 eb = ~0;
 599         if (enable_ept)
 600                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
 601         if (vcpu->fpu_active)
 602                 eb &= ~(1u << NM_VECTOR);
 603         vmcs_write32(EXCEPTION_BITMAP, eb);
 604 }
 605
 606 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
 607 {
 608         unsigned i;
 609         struct msr_autoload *m = &vmx->msr_autoload;
 610
 611         for (i = 0; i < m->nr; ++i)
 612                 if (m->guest[i].index == msr)
 613                         break;
 614
 615         if (i == m->nr)
 616                 return;
 617         --m->nr;
 618         m->guest[i] = m->guest[m->nr];
 619         m->host[i] = m->host[m->nr];
 620         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 621         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 622 }
 623
 624 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
 625                                   u64 guest_val, u64 host_val)
 626 {
 627         unsigned i;
 628         struct msr_autoload *m = &vmx->msr_autoload;
 629
 630         for (i = 0; i < m->nr; ++i)
 631                 if (m->guest[i].index == msr)
 632                         break;
 633
 634         if (i == m->nr) {
 635                 ++m->nr;
 636                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
 637                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
 638         }
 639
 640         m->guest[i].index = msr;
 641         m->guest[i].value = guest_val;
 642         m->host[i].index = msr;
 643         m->host[i].value = host_val;
 644 }
 645
 646 static void reload_tss(void)
 647 {
 648         /*
 649          * VT restores TR but not its size.  Useless.
 650          */
 651         struct desc_ptr gdt;
 652         struct desc_struct *descs;
 653
 654         native_store_gdt(&gdt);
 655         descs = (void *)gdt.address;
 656         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
 657         load_TR_desc();
 658 }
 659
 660 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
 661 {
 662         u64 guest_efer;
 663         u64 ignore_bits;
 664
 665         guest_efer = vmx->vcpu.arch.efer;
 666
 667         /*
 668          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
 669          * outside long mode
 670          */
 671         ignore_bits = EFER_NX | EFER_SCE;
 672 #ifdef CONFIG_X86_64
 673         ignore_bits |= EFER_LMA | EFER_LME;
 674         /* SCE is meaningful only in long mode on Intel */
 675         if (guest_efer & EFER_LMA)
 676                 ignore_bits &= ~(u64)EFER_SCE;
 677 #endif
 678         guest_efer &= ~ignore_bits;
 679         guest_efer |= host_efer & ignore_bits;
 680         vmx->guest_msrs[efer_offset].data = guest_efer;
 681         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
 682
 683         clear_atomic_switch_msr(vmx, MSR_EFER);
 684         /* On ept, can't emulate nx, and must switch nx atomically */
 685         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
 686                 guest_efer = vmx->vcpu.arch.efer;
 687                 if (!(guest_efer & EFER_LMA))
 688                         guest_efer &= ~EFER_LME;
 689                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
 690                 return false;
 691         }
 692
 693         return true;
 694 }
 695
 696 static unsigned long segment_base(u16 selector)
 697 {
 698         struct desc_ptr gdt;
 699         struct desc_struct *d;
 700         unsigned long table_base;
 701         unsigned long v;
 702
 703         if (!(selector & ~3))
 704                 return 0;
 705
 706         native_store_gdt(&gdt);
 707         table_base = gdt.address;
 708
 709         if (selector & 4) {           /* from ldt */
 710                 u16 ldt_selector = kvm_read_ldt();
 711
 712                 if (!(ldt_selector & ~3))
 713                         return 0;
 714
 715                 table_base = segment_base(ldt_selector);
 716         }
 717         d = (struct desc_struct *)(table_base + (selector & ~7));
 718         v = get_desc_base(d);
 719 #ifdef CONFIG_X86_64
 720        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
 721                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
 722 #endif
 723         return v;
 724 }
 725
 726 static inline unsigned long kvm_read_tr_base(void)
 727 {
 728         u16 tr;
 729         asm("str %0" : "=g"(tr));
 730         return segment_base(tr);
 731 }
 732
 733 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
 734 {
 735         struct vcpu_vmx *vmx = to_vmx(vcpu);
 736         int i;
 737
 738         if (vmx->host_state.loaded)
 739                 return;
 740
 741         vmx->host_state.loaded = 1;
 742         /*
 743          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
 744          * allow segment selectors with cpl > 0 or ti == 1.
 745          */
 746         vmx->host_state.ldt_sel = kvm_read_ldt();
 747         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
 748         vmx->host_state.fs_sel = kvm_read_fs();
 749         if (!(vmx->host_state.fs_sel & 7)) {
 750                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
 751                 vmx->host_state.fs_reload_needed = 0;
 752         } else {
 753                 vmcs_write16(HOST_FS_SELECTOR, 0);
 754                 vmx->host_state.fs_reload_needed = 1;
 755         }
 756         vmx->host_state.gs_sel = kvm_read_gs();
 757         if (!(vmx->host_state.gs_sel & 7))
 758                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
 759         else {
 760                 vmcs_write16(HOST_GS_SELECTOR, 0);
 761                 vmx->host_state.gs_ldt_reload_needed = 1;
 762         }
 763
 764 #ifdef CONFIG_X86_64
 765         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
 766         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
 767 #else
 768         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
 769         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
 770 #endif
 771
 772 #ifdef CONFIG_X86_64
 773         if (is_long_mode(&vmx->vcpu)) {
 774                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 775                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 776         }
 777 #endif
 778         for (i = 0; i < vmx->save_nmsrs; ++i)
 779                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
 780                                    vmx->guest_msrs[i].data,
 781                                    vmx->guest_msrs[i].mask);
 782 }
 783
 784 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
 785 {
 786         unsigned long flags;
 787
 788         if (!vmx->host_state.loaded)
 789                 return;
 790
 791         ++vmx->vcpu.stat.host_state_reload;
 792         vmx->host_state.loaded = 0;
 793         if (vmx->host_state.fs_reload_needed)
 794                 kvm_load_fs(vmx->host_state.fs_sel);
 795         if (vmx->host_state.gs_ldt_reload_needed) {
 796                 kvm_load_ldt(vmx->host_state.ldt_sel);
 797                 /*
 798                  * If we have to reload gs, we must take care to
 799                  * preserve our gs base.
 800                  */
 801                 local_irq_save(flags);
 802                 kvm_load_gs(vmx->host_state.gs_sel);
 803 #ifdef CONFIG_X86_64
 804                 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
 805 #endif
 806                 local_irq_restore(flags);
 807         }
 808         reload_tss();
 809 #ifdef CONFIG_X86_64
 810         if (is_long_mode(&vmx->vcpu)) {
 811                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
 812                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
 813         }
 814 #endif
 815 }
 816
 817 static void vmx_load_host_state(struct vcpu_vmx *vmx)
 818 {
 819         preempt_disable();
 820         __vmx_load_host_state(vmx);
 821         preempt_enable();
 822 }
 823
 824 /*
 825  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
 826  * vcpu mutex is already taken.
 827  */
 828 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 829 {
 830         struct vcpu_vmx *vmx = to_vmx(vcpu);
 831         u64 phys_addr = __pa(vmx->vmcs);
 832         u64 tsc_this, delta, new_offset;
 833
 834         if (vcpu->cpu != cpu) {
 835                 vcpu_clear(vmx);
 836                 kvm_migrate_timers(vcpu);
 837                 set_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests);
 838                 local_irq_disable();
 839                 list_add(&vmx->local_vcpus_link,
 840                          &per_cpu(vcpus_on_cpu, cpu));
 841                 local_irq_enable();
 842         }
 843
 844         if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
 845                 u8 error;
 846
 847                 per_cpu(current_vmcs, cpu) = vmx->vmcs;
 848                 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 849                               : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
 850                               : "cc");
 851                 if (error)
 852                         printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
 853                                vmx->vmcs, phys_addr);
 854         }
 855
 856         if (vcpu->cpu != cpu) {
 857                 struct desc_ptr dt;
 858                 unsigned long sysenter_esp;
 859
 860                 vcpu->cpu = cpu;
 861                 /*
 862                  * Linux uses per-cpu TSS and GDT, so set these when switching
 863                  * processors.
 864                  */
 865                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
 866                 native_store_gdt(&dt);
 867                 vmcs_writel(HOST_GDTR_BASE, dt.address);   /* 22.2.4 */
 868
 869                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
 870                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
 871
 872                 /*
 873                  * Make sure the time stamp counter is monotonous.
 874                  */
 875                 rdtscll(tsc_this);
 876                 if (tsc_this < vcpu->arch.host_tsc) {
 877                         delta = vcpu->arch.host_tsc - tsc_this;
 878                         new_offset = vmcs_read64(TSC_OFFSET) + delta;
 879                         vmcs_write64(TSC_OFFSET, new_offset);
 880                 }
 881         }
 882 }
 883
 884 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
 885 {
 886         __vmx_load_host_state(to_vmx(vcpu));
 887 }
 888
 889 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
 890 {
 891         ulong cr0;
 892
 893         if (vcpu->fpu_active)
 894                 return;
 895         vcpu->fpu_active = 1;
 896         cr0 = vmcs_readl(GUEST_CR0);
 897         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
 898         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
 899         vmcs_writel(GUEST_CR0, cr0);
 900         update_exception_bitmap(vcpu);
 901         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
 902         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 903 }
 904
 905 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
 906
 907 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
 908 {
 909         vmx_decache_cr0_guest_bits(vcpu);
 910         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
 911         update_exception_bitmap(vcpu);
 912         vcpu->arch.cr0_guest_owned_bits = 0;
 913         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
 914         vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
 915 }
 916
 917 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
 918 {
 919         unsigned long rflags, save_rflags;
 920
 921         rflags = vmcs_readl(GUEST_RFLAGS);
 922         if (to_vmx(vcpu)->rmode.vm86_active) {
 923                 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
 924                 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
 925                 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
 926         }
 927         return rflags;
 928 }
 929
 930 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 931 {
 932         if (to_vmx(vcpu)->rmode.vm86_active) {
 933                 to_vmx(vcpu)->rmode.save_rflags = rflags;
 934                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
 935         }
 936         vmcs_writel(GUEST_RFLAGS, rflags);
 937 }
 938
 939 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 940 {
 941         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 942         int ret = 0;
 943
 944         if (interruptibility & GUEST_INTR_STATE_STI)
 945                 ret |= KVM_X86_SHADOW_INT_STI;
 946         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
 947                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
 948
 949         return ret & mask;
 950 }
 951
 952 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 953 {
 954         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
 955         u32 interruptibility = interruptibility_old;
 956
 957         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
 958
 959         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
 960                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
 961         else if (mask & KVM_X86_SHADOW_INT_STI)
 962                 interruptibility |= GUEST_INTR_STATE_STI;
 963
 964         if ((interruptibility != interruptibility_old))
 965                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
 966 }
 967
 968 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 969 {
 970         unsigned long rip;
 971
 972         rip = kvm_rip_read(vcpu);
 973         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
 974         kvm_rip_write(vcpu, rip);
 975
 976         /* skipping an emulated instruction also counts */
 977         vmx_set_interrupt_shadow(vcpu, 0);
 978 }
 979
 980 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 981                                 bool has_error_code, u32 error_code,
 982                                 bool reinject)
 983 {
 984         struct vcpu_vmx *vmx = to_vmx(vcpu);
 985         u32 intr_info = nr | INTR_INFO_VALID_MASK;
 986
 987         if (has_error_code) {
 988                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
 989                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
 990         }
 991
 992         if (vmx->rmode.vm86_active) {
 993                 vmx->rmode.irq.pending = true;
 994                 vmx->rmode.irq.vector = nr;
 995                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
 996                 if (kvm_exception_is_soft(nr))
 997                         vmx->rmode.irq.rip +=
 998                                 vmx->vcpu.arch.event_exit_inst_len;
 999                 intr_info |= INTR_TYPE_SOFT_INTR;
1000                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1001                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
1002                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
1003                 return;
1004         }
1005
1006         if (kvm_exception_is_soft(nr)) {
1007                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1008                              vmx->vcpu.arch.event_exit_inst_len);
1009                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1010         } else
1011                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1012
1013         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1014 }
1015
1016 static bool vmx_rdtscp_supported(void)
1017 {
1018         return cpu_has_vmx_rdtscp();
1019 }
1020
1021 /*
1022  * Swap MSR entry in host/guest MSR entry array.
1023  */
1024 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1025 {
1026         struct shared_msr_entry tmp;
1027
1028         tmp = vmx->guest_msrs[to];
1029         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1030         vmx->guest_msrs[from] = tmp;
1031 }
1032
1033 /*
1034  * Set up the vmcs to automatically save and restore system
1035  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1036  * mode, as fiddling with msrs is very expensive.
1037  */
1038 static void setup_msrs(struct vcpu_vmx *vmx)
1039 {
1040         int save_nmsrs, index;
1041         unsigned long *msr_bitmap;
1042
1043         vmx_load_host_state(vmx);
1044         save_nmsrs = 0;
1045 #ifdef CONFIG_X86_64
1046         if (is_long_mode(&vmx->vcpu)) {
1047                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1048                 if (index >= 0)
1049                         move_msr_up(vmx, index, save_nmsrs++);
1050                 index = __find_msr_index(vmx, MSR_LSTAR);
1051                 if (index >= 0)
1052                         move_msr_up(vmx, index, save_nmsrs++);
1053                 index = __find_msr_index(vmx, MSR_CSTAR);
1054                 if (index >= 0)
1055                         move_msr_up(vmx, index, save_nmsrs++);
1056                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1057                 if (index >= 0 && vmx->rdtscp_enabled)
1058                         move_msr_up(vmx, index, save_nmsrs++);
1059                 /*
1060                  * MSR_K6_STAR is only needed on long mode guests, and only
1061                  * if efer.sce is enabled.
1062                  */
1063                 index = __find_msr_index(vmx, MSR_K6_STAR);
1064                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1065                         move_msr_up(vmx, index, save_nmsrs++);
1066         }
1067 #endif
1068         index = __find_msr_index(vmx, MSR_EFER);
1069         if (index >= 0 && update_transition_efer(vmx, index))
1070                 move_msr_up(vmx, index, save_nmsrs++);
1071
1072         vmx->save_nmsrs = save_nmsrs;
1073
1074         if (cpu_has_vmx_msr_bitmap()) {
1075                 if (is_long_mode(&vmx->vcpu))
1076                         msr_bitmap = vmx_msr_bitmap_longmode;
1077                 else
1078                         msr_bitmap = vmx_msr_bitmap_legacy;
1079
1080                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1081         }
1082 }
1083
1084 /*
1085  * reads and returns guest's timestamp counter "register"
1086  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1087  */
1088 static u64 guest_read_tsc(void)
1089 {
1090         u64 host_tsc, tsc_offset;
1091
1092         rdtscll(host_tsc);
1093         tsc_offset = vmcs_read64(TSC_OFFSET);
1094         return host_tsc + tsc_offset;
1095 }
1096
1097 /*
1098  * writes 'guest_tsc' into guest's timestamp counter "register"
1099  * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
1100  */
1101 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
1102 {
1103         vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
1104 }
1105
1106 /*
1107  * Reads an msr value (of 'msr_index') into 'pdata'.
1108  * Returns 0 on success, non-0 otherwise.
1109  * Assumes vcpu_load() was already called.
1110  */
1111 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1112 {
1113         u64 data;
1114         struct shared_msr_entry *msr;
1115
1116         if (!pdata) {
1117                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
1118                 return -EINVAL;
1119         }
1120
1121         switch (msr_index) {
1122 #ifdef CONFIG_X86_64
1123         case MSR_FS_BASE:
1124                 data = vmcs_readl(GUEST_FS_BASE);
1125                 break;
1126         case MSR_GS_BASE:
1127                 data = vmcs_readl(GUEST_GS_BASE);
1128                 break;
1129         case MSR_KERNEL_GS_BASE:
1130                 vmx_load_host_state(to_vmx(vcpu));
1131                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
1132                 break;
1133 #endif
1134         case MSR_EFER:
1135                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1136         case MSR_IA32_TSC:
1137                 data = guest_read_tsc();
1138                 break;
1139         case MSR_IA32_SYSENTER_CS:
1140                 data = vmcs_read32(GUEST_SYSENTER_CS);
1141                 break;
1142         case MSR_IA32_SYSENTER_EIP:
1143                 data = vmcs_readl(GUEST_SYSENTER_EIP);
1144                 break;
1145         case MSR_IA32_SYSENTER_ESP:
1146                 data = vmcs_readl(GUEST_SYSENTER_ESP);
1147                 break;
1148         case MSR_TSC_AUX:
1149                 if (!to_vmx(vcpu)->rdtscp_enabled)
1150                         return 1;
1151                 /* Otherwise falls through */
1152         default:
1153                 vmx_load_host_state(to_vmx(vcpu));
1154                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
1155                 if (msr) {
1156                         vmx_load_host_state(to_vmx(vcpu));
1157                         data = msr->data;
1158                         break;
1159                 }
1160                 return kvm_get_msr_common(vcpu, msr_index, pdata);
1161         }
1162
1163         *pdata = data;
1164         return 0;
1165 }
1166
1167 /*
1168  * Writes msr value into into the appropriate "register".
1169  * Returns 0 on success, non-0 otherwise.
1170  * Assumes vcpu_load() was already called.
1171  */
1172 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1173 {
1174         struct vcpu_vmx *vmx = to_vmx(vcpu);
1175         struct shared_msr_entry *msr;
1176         u64 host_tsc;
1177         int ret = 0;
1178
1179         switch (msr_index) {
1180         case MSR_EFER:
1181                 vmx_load_host_state(vmx);
1182                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1183                 break;
1184 #ifdef CONFIG_X86_64
1185         case MSR_FS_BASE:
1186                 vmcs_writel(GUEST_FS_BASE, data);
1187                 break;
1188         case MSR_GS_BASE:
1189                 vmcs_writel(GUEST_GS_BASE, data);
1190                 break;
1191         case MSR_KERNEL_GS_BASE:
1192                 vmx_load_host_state(vmx);
1193                 vmx->msr_guest_kernel_gs_base = data;
1194                 break;
1195 #endif
1196         case MSR_IA32_SYSENTER_CS:
1197                 vmcs_write32(GUEST_SYSENTER_CS, data);
1198                 break;
1199         case MSR_IA32_SYSENTER_EIP:
1200                 vmcs_writel(GUEST_SYSENTER_EIP, data);
1201                 break;
1202         case MSR_IA32_SYSENTER_ESP:
1203                 vmcs_writel(GUEST_SYSENTER_ESP, data);
1204                 break;
1205         case MSR_IA32_TSC:
1206                 rdtscll(host_tsc);
1207                 guest_write_tsc(data, host_tsc);
1208                 break;
1209         case MSR_IA32_CR_PAT:
1210                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1211                         vmcs_write64(GUEST_IA32_PAT, data);
1212                         vcpu->arch.pat = data;
1213                         break;
1214                 }
1215                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1216                 break;
1217         case MSR_TSC_AUX:
1218                 if (!vmx->rdtscp_enabled)
1219                         return 1;
1220                 /* Check reserved bit, higher 32 bits should be zero */
1221                 if ((data >> 32) != 0)
1222                         return 1;
1223                 /* Otherwise falls through */
1224         default:
1225                 msr = find_msr_entry(vmx, msr_index);
1226                 if (msr) {
1227                         vmx_load_host_state(vmx);
1228                         msr->data = data;
1229                         break;
1230                 }
1231                 ret = kvm_set_msr_common(vcpu, msr_index, data);
1232         }
1233
1234         return ret;
1235 }
1236
1237 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1238 {
1239         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1240         switch (reg) {
1241         case VCPU_REGS_RSP:
1242                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1243                 break;
1244         case VCPU_REGS_RIP:
1245                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1246                 break;
1247         case VCPU_EXREG_PDPTR:
1248                 if (enable_ept)
1249                         ept_save_pdptrs(vcpu);
1250                 break;
1251         default:
1252                 break;
1253         }
1254 }
1255
1256 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1257 {
1258         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1259                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1260         else
1261                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1262
1263         update_exception_bitmap(vcpu);
1264 }
1265
1266 static __init int cpu_has_kvm_support(void)
1267 {
1268         return cpu_has_vmx();
1269 }
1270
1271 static __init int vmx_disabled_by_bios(void)
1272 {
1273         u64 msr;
1274
1275         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1276         if (msr & FEATURE_CONTROL_LOCKED) {
1277                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1278                         && tboot_enabled())
1279                         return 1;
1280                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1281                         && !tboot_enabled())
1282                         return 1;
1283         }
1284
1285         return 0;
1286         /* locked but not enabled */
1287 }
1288
1289 static int hardware_enable(void *garbage)
1290 {
1291         int cpu = raw_smp_processor_id();
1292         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1293         u64 old, test_bits;
1294
1295         if (read_cr4() & X86_CR4_VMXE)
1296                 return -EBUSY;
1297
1298         INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1299         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1300
1301         test_bits = FEATURE_CONTROL_LOCKED;
1302         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1303         if (tboot_enabled())
1304                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1305
1306         if ((old & test_bits) != test_bits) {
1307                 /* enable and lock */
1308                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1309         }
1310         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1311         asm volatile (ASM_VMX_VMXON_RAX
1312                       : : "a"(&phys_addr), "m"(phys_addr)
1313                       : "memory", "cc");
1314
1315         ept_sync_global();
1316
1317         return 0;
1318 }
1319
1320 static void vmclear_local_vcpus(void)
1321 {
1322         int cpu = raw_smp_processor_id();
1323         struct vcpu_vmx *vmx, *n;
1324
1325         list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1326                                  local_vcpus_link)
1327                 __vcpu_clear(vmx);
1328 }
1329
1330
1331 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1332  * tricks.
1333  */
1334 static void kvm_cpu_vmxoff(void)
1335 {
1336         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1337         write_cr4(read_cr4() & ~X86_CR4_VMXE);
1338 }
1339
1340 static void hardware_disable(void *garbage)
1341 {
1342         vmclear_local_vcpus();
1343         kvm_cpu_vmxoff();
1344 }
1345
1346 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1347                                       u32 msr, u32 *result)
1348 {
1349         u32 vmx_msr_low, vmx_msr_high;
1350         u32 ctl = ctl_min | ctl_opt;
1351
1352         rdmsr(msr, vmx_msr_low, vmx_msr_high);
1353
1354         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1355         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
1356
1357         /* Ensure minimum (required) set of control bits are supported. */
1358         if (ctl_min & ~ctl)
1359                 return -EIO;
1360
1361         *result = ctl;
1362         return 0;
1363 }
1364
1365 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1366 {
1367         u32 vmx_msr_low, vmx_msr_high;
1368         u32 min, opt, min2, opt2;
1369         u32 _pin_based_exec_control = 0;
1370         u32 _cpu_based_exec_control = 0;
1371         u32 _cpu_based_2nd_exec_control = 0;
1372         u32 _vmexit_control = 0;
1373         u32 _vmentry_control = 0;
1374
1375         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1376         opt = PIN_BASED_VIRTUAL_NMIS;
1377         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1378                                 &_pin_based_exec_control) < 0)
1379                 return -EIO;
1380
1381         min = CPU_BASED_HLT_EXITING |
1382 #ifdef CONFIG_X86_64
1383               CPU_BASED_CR8_LOAD_EXITING |
1384               CPU_BASED_CR8_STORE_EXITING |
1385 #endif
1386               CPU_BASED_CR3_LOAD_EXITING |
1387               CPU_BASED_CR3_STORE_EXITING |
1388               CPU_BASED_USE_IO_BITMAPS |
1389               CPU_BASED_MOV_DR_EXITING |
1390               CPU_BASED_USE_TSC_OFFSETING |
1391               CPU_BASED_MWAIT_EXITING |
1392               CPU_BASED_MONITOR_EXITING |
1393               CPU_BASED_INVLPG_EXITING;
1394         opt = CPU_BASED_TPR_SHADOW |
1395               CPU_BASED_USE_MSR_BITMAPS |
1396               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1397         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1398                                 &_cpu_based_exec_control) < 0)
1399                 return -EIO;
1400 #ifdef CONFIG_X86_64
1401         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1402                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1403                                            ~CPU_BASED_CR8_STORE_EXITING;
1404 #endif
1405         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1406                 min2 = 0;
1407                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1408                         SECONDARY_EXEC_WBINVD_EXITING |
1409                         SECONDARY_EXEC_ENABLE_VPID |
1410                         SECONDARY_EXEC_ENABLE_EPT |
1411                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
1412                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
1413                         SECONDARY_EXEC_RDTSCP;
1414                 if (adjust_vmx_controls(min2, opt2,
1415                                         MSR_IA32_VMX_PROCBASED_CTLS2,
1416                                         &_cpu_based_2nd_exec_control) < 0)
1417                         return -EIO;
1418         }
1419 #ifndef CONFIG_X86_64
1420         if (!(_cpu_based_2nd_exec_control &
1421                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1422                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1423 #endif
1424         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1425                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1426                    enabled */
1427                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
1428                                              CPU_BASED_CR3_STORE_EXITING |
1429                                              CPU_BASED_INVLPG_EXITING);
1430                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1431                       vmx_capability.ept, vmx_capability.vpid);
1432         }
1433
1434         min = 0;
1435 #ifdef CONFIG_X86_64
1436         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1437 #endif
1438         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1439         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1440                                 &_vmexit_control) < 0)
1441                 return -EIO;
1442
1443         min = 0;
1444         opt = VM_ENTRY_LOAD_IA32_PAT;
1445         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1446                                 &_vmentry_control) < 0)
1447                 return -EIO;
1448
1449         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1450
1451         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1452         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1453                 return -EIO;
1454
1455 #ifdef CONFIG_X86_64
1456         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1457         if (vmx_msr_high & (1u<<16))
1458                 return -EIO;
1459 #endif
1460
1461         /* Require Write-Back (WB) memory type for VMCS accesses. */
1462         if (((vmx_msr_high >> 18) & 15) != 6)
1463                 return -EIO;
1464
1465         vmcs_conf->size = vmx_msr_high & 0x1fff;
1466         vmcs_conf->order = get_order(vmcs_config.size);
1467         vmcs_conf->revision_id = vmx_msr_low;
1468
1469         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1470         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1471         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1472         vmcs_conf->vmexit_ctrl         = _vmexit_control;
1473         vmcs_conf->vmentry_ctrl        = _vmentry_control;
1474
1475         return 0;
1476 }
1477
1478 static struct vmcs *alloc_vmcs_cpu(int cpu)
1479 {
1480         int node = cpu_to_node(cpu);
1481         struct page *pages;
1482         struct vmcs *vmcs;
1483
1484         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1485         if (!pages)
1486                 return NULL;
1487         vmcs = page_address(pages);
1488         memset(vmcs, 0, vmcs_config.size);
1489         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1490         return vmcs;
1491 }
1492
1493 static struct vmcs *alloc_vmcs(void)
1494 {
1495         return alloc_vmcs_cpu(raw_smp_processor_id());
1496 }
1497
1498 static void free_vmcs(struct vmcs *vmcs)
1499 {
1500         free_pages((unsigned long)vmcs, vmcs_config.order);
1501 }
1502
1503 static void free_kvm_area(void)
1504 {
1505         int cpu;
1506
1507         for_each_possible_cpu(cpu) {
1508                 free_vmcs(per_cpu(vmxarea, cpu));
1509                 per_cpu(vmxarea, cpu) = NULL;
1510         }
1511 }
1512
1513 static __init int alloc_kvm_area(void)
1514 {
1515         int cpu;
1516
1517         for_each_possible_cpu(cpu) {
1518                 struct vmcs *vmcs;
1519
1520                 vmcs = alloc_vmcs_cpu(cpu);
1521                 if (!vmcs) {
1522                         free_kvm_area();
1523                         return -ENOMEM;
1524                 }
1525
1526                 per_cpu(vmxarea, cpu) = vmcs;
1527         }
1528         return 0;
1529 }
1530
1531 static __init int hardware_setup(void)
1532 {
1533         if (setup_vmcs_config(&vmcs_config) < 0)
1534                 return -EIO;
1535
1536         if (boot_cpu_has(X86_FEATURE_NX))
1537                 kvm_enable_efer_bits(EFER_NX);
1538
1539         if (!cpu_has_vmx_vpid())
1540                 enable_vpid = 0;
1541
1542         if (!cpu_has_vmx_ept()) {
1543                 enable_ept = 0;
1544                 enable_unrestricted_guest = 0;
1545         }
1546
1547         if (!cpu_has_vmx_unrestricted_guest())
1548                 enable_unrestricted_guest = 0;
1549
1550         if (!cpu_has_vmx_flexpriority())
1551                 flexpriority_enabled = 0;
1552
1553         if (!cpu_has_vmx_tpr_shadow())
1554                 kvm_x86_ops->update_cr8_intercept = NULL;
1555
1556         if (enable_ept && !cpu_has_vmx_ept_2m_page())
1557                 kvm_disable_largepages();
1558
1559         if (!cpu_has_vmx_ple())
1560                 ple_gap = 0;
1561
1562         return alloc_kvm_area();
1563 }
1564
1565 static __exit void hardware_unsetup(void)
1566 {
1567         free_kvm_area();
1568 }
1569
1570 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1571 {
1572         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1573
1574         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1575                 vmcs_write16(sf->selector, save->selector);
1576                 vmcs_writel(sf->base, save->base);
1577                 vmcs_write32(sf->limit, save->limit);
1578                 vmcs_write32(sf->ar_bytes, save->ar);
1579         } else {
1580                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1581                         << AR_DPL_SHIFT;
1582                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1583         }
1584 }
1585
1586 static void enter_pmode(struct kvm_vcpu *vcpu)
1587 {
1588         unsigned long flags;
1589         struct vcpu_vmx *vmx = to_vmx(vcpu);
1590
1591         vmx->emulation_required = 1;
1592         vmx->rmode.vm86_active = 0;
1593
1594         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1595         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1596         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1597
1598         flags = vmcs_readl(GUEST_RFLAGS);
1599         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1600         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1601         vmcs_writel(GUEST_RFLAGS, flags);
1602
1603         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1604                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1605
1606         update_exception_bitmap(vcpu);
1607
1608         if (emulate_invalid_guest_state)
1609                 return;
1610
1611         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1612         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1613         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1614         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1615
1616         vmcs_write16(GUEST_SS_SELECTOR, 0);
1617         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1618
1619         vmcs_write16(GUEST_CS_SELECTOR,
1620                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1621         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1622 }
1623
1624 static gva_t rmode_tss_base(struct kvm *kvm)
1625 {
1626         if (!kvm->arch.tss_addr) {
1627                 struct kvm_memslots *slots;
1628                 gfn_t base_gfn;
1629
1630                 slots = kvm_memslots(kvm);
1631                 base_gfn = kvm->memslots->memslots[0].base_gfn +
1632                                  kvm->memslots->memslots[0].npages - 3;
1633                 return base_gfn << PAGE_SHIFT;
1634         }
1635         return kvm->arch.tss_addr;
1636 }
1637
1638 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1639 {
1640         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1641
1642         save->selector = vmcs_read16(sf->selector);
1643         save->base = vmcs_readl(sf->base);
1644         save->limit = vmcs_read32(sf->limit);
1645         save->ar = vmcs_read32(sf->ar_bytes);
1646         vmcs_write16(sf->selector, save->base >> 4);
1647         vmcs_write32(sf->base, save->base & 0xfffff);
1648         vmcs_write32(sf->limit, 0xffff);
1649         vmcs_write32(sf->ar_bytes, 0xf3);
1650 }
1651
1652 static void enter_rmode(struct kvm_vcpu *vcpu)
1653 {
1654         unsigned long flags;
1655         struct vcpu_vmx *vmx = to_vmx(vcpu);
1656
1657         if (enable_unrestricted_guest)
1658                 return;
1659
1660         vmx->emulation_required = 1;
1661         vmx->rmode.vm86_active = 1;
1662
1663         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1664         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1665
1666         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1667         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1668
1669         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1670         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1671
1672         flags = vmcs_readl(GUEST_RFLAGS);
1673         vmx->rmode.save_rflags = flags;
1674
1675         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1676
1677         vmcs_writel(GUEST_RFLAGS, flags);
1678         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1679         update_exception_bitmap(vcpu);
1680
1681         if (emulate_invalid_guest_state)
1682                 goto continue_rmode;
1683
1684         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1685         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1686         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1687
1688         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1689         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1690         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1691                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1692         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1693
1694         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1695         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1696         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1697         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1698
1699 continue_rmode:
1700         kvm_mmu_reset_context(vcpu);
1701         init_rmode(vcpu->kvm);
1702 }
1703
1704 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1705 {
1706         struct vcpu_vmx *vmx = to_vmx(vcpu);
1707         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1708
1709         if (!msr)
1710                 return;
1711
1712         /*
1713          * Force kernel_gs_base reloading before EFER changes, as control
1714          * of this msr depends on is_long_mode().
1715          */
1716         vmx_load_host_state(to_vmx(vcpu));
1717         vcpu->arch.efer = efer;
1718         if (efer & EFER_LMA) {
1719                 vmcs_write32(VM_ENTRY_CONTROLS,
1720                              vmcs_read32(VM_ENTRY_CONTROLS) |
1721                              VM_ENTRY_IA32E_MODE);
1722                 msr->data = efer;
1723         } else {
1724                 vmcs_write32(VM_ENTRY_CONTROLS,
1725                              vmcs_read32(VM_ENTRY_CONTROLS) &
1726                              ~VM_ENTRY_IA32E_MODE);
1727
1728                 msr->data = efer & ~EFER_LME;
1729         }
1730         setup_msrs(vmx);
1731 }
1732
1733 #ifdef CONFIG_X86_64
1734
1735 static void enter_lmode(struct kvm_vcpu *vcpu)
1736 {
1737         u32 guest_tr_ar;
1738
1739         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1740         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1741                 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1742                        __func__);
1743                 vmcs_write32(GUEST_TR_AR_BYTES,
1744                              (guest_tr_ar & ~AR_TYPE_MASK)
1745                              | AR_TYPE_BUSY_64_TSS);
1746         }
1747         vcpu->arch.efer |= EFER_LMA;
1748         vmx_set_efer(vcpu, vcpu->arch.efer);
1749 }
1750
1751 static void exit_lmode(struct kvm_vcpu *vcpu)
1752 {
1753         vcpu->arch.efer &= ~EFER_LMA;
1754
1755         vmcs_write32(VM_ENTRY_CONTROLS,
1756                      vmcs_read32(VM_ENTRY_CONTROLS)
1757                      & ~VM_ENTRY_IA32E_MODE);
1758         vmx_set_efer(vcpu, vcpu->arch.efer);
1759 }
1760
1761 #endif
1762
1763 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1764 {
1765         vpid_sync_vcpu_all(to_vmx(vcpu));
1766         if (enable_ept)
1767                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1768 }
1769
1770 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1771 {
1772         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
1773
1774         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
1775         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
1776 }
1777
1778 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1779 {
1780         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
1781
1782         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
1783         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
1784 }
1785
1786 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1787 {
1788         if (!test_bit(VCPU_EXREG_PDPTR,
1789                       (unsigned long *)&vcpu->arch.regs_dirty))
1790                 return;
1791
1792         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1793                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1794                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1795                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1796                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1797         }
1798 }
1799
1800 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1801 {
1802         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1803                 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1804                 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1805                 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1806                 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1807         }
1808
1809         __set_bit(VCPU_EXREG_PDPTR,
1810                   (unsigned long *)&vcpu->arch.regs_avail);
1811         __set_bit(VCPU_EXREG_PDPTR,
1812                   (unsigned long *)&vcpu->arch.regs_dirty);
1813 }
1814
1815 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1816
1817 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1818                                         unsigned long cr0,
1819                                         struct kvm_vcpu *vcpu)
1820 {
1821         if (!(cr0 & X86_CR0_PG)) {
1822                 /* From paging/starting to nonpaging */
1823                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1824                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1825                              (CPU_BASED_CR3_LOAD_EXITING |
1826                               CPU_BASED_CR3_STORE_EXITING));
1827                 vcpu->arch.cr0 = cr0;
1828                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1829         } else if (!is_paging(vcpu)) {
1830                 /* From nonpaging to paging */
1831                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1832                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1833                              ~(CPU_BASED_CR3_LOAD_EXITING |
1834                                CPU_BASED_CR3_STORE_EXITING));
1835                 vcpu->arch.cr0 = cr0;
1836                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1837         }
1838
1839         if (!(cr0 & X86_CR0_WP))
1840                 *hw_cr0 &= ~X86_CR0_WP;
1841 }
1842
1843 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1844 {
1845         struct vcpu_vmx *vmx = to_vmx(vcpu);
1846         unsigned long hw_cr0;
1847
1848         if (enable_unrestricted_guest)
1849                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1850                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1851         else
1852                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1853
1854         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1855                 enter_pmode(vcpu);
1856
1857         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1858                 enter_rmode(vcpu);
1859
1860 #ifdef CONFIG_X86_64
1861         if (vcpu->arch.efer & EFER_LME) {
1862                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1863                         enter_lmode(vcpu);
1864                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1865                         exit_lmode(vcpu);
1866         }
1867 #endif
1868
1869         if (enable_ept)
1870                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1871
1872         if (!vcpu->fpu_active)
1873                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
1874
1875         vmcs_writel(CR0_READ_SHADOW, cr0);
1876         vmcs_writel(GUEST_CR0, hw_cr0);
1877         vcpu->arch.cr0 = cr0;
1878 }
1879
1880 static u64 construct_eptp(unsigned long root_hpa)
1881 {
1882         u64 eptp;
1883
1884         /* TODO write the value reading from MSR */
1885         eptp = VMX_EPT_DEFAULT_MT |
1886                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1887         eptp |= (root_hpa & PAGE_MASK);
1888
1889         return eptp;
1890 }
1891
1892 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1893 {
1894         unsigned long guest_cr3;
1895         u64 eptp;
1896
1897         guest_cr3 = cr3;
1898         if (enable_ept) {
1899                 eptp = construct_eptp(cr3);
1900                 vmcs_write64(EPT_POINTER, eptp);
1901                 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1902                         vcpu->kvm->arch.ept_identity_map_addr;
1903                 ept_load_pdptrs(vcpu);
1904         }
1905
1906         vmx_flush_tlb(vcpu);
1907         vmcs_writel(GUEST_CR3, guest_cr3);
1908 }
1909
1910 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1911 {
1912         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1913                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1914
1915         vcpu->arch.cr4 = cr4;
1916         if (enable_ept) {
1917                 if (!is_paging(vcpu)) {
1918                         hw_cr4 &= ~X86_CR4_PAE;
1919                         hw_cr4 |= X86_CR4_PSE;
1920                 } else if (!(cr4 & X86_CR4_PAE)) {
1921                         hw_cr4 &= ~X86_CR4_PAE;
1922                 }
1923         }
1924
1925         vmcs_writel(CR4_READ_SHADOW, cr4);
1926         vmcs_writel(GUEST_CR4, hw_cr4);
1927 }
1928
1929 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1930 {
1931         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1932
1933         return vmcs_readl(sf->base);
1934 }
1935
1936 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1937                             struct kvm_segment *var, int seg)
1938 {
1939         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1940         u32 ar;
1941
1942         var->base = vmcs_readl(sf->base);
1943         var->limit = vmcs_read32(sf->limit);
1944         var->selector = vmcs_read16(sf->selector);
1945         ar = vmcs_read32(sf->ar_bytes);
1946         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1947                 ar = 0;
1948         var->type = ar & 15;
1949         var->s = (ar >> 4) & 1;
1950         var->dpl = (ar >> 5) & 3;
1951         var->present = (ar >> 7) & 1;
1952         var->avl = (ar >> 12) & 1;
1953         var->l = (ar >> 13) & 1;
1954         var->db = (ar >> 14) & 1;
1955         var->g = (ar >> 15) & 1;
1956         var->unusable = (ar >> 16) & 1;
1957 }
1958
1959 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1960 {
1961         if (!is_protmode(vcpu))
1962                 return 0;
1963
1964         if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1965                 return 3;
1966
1967         return vmcs_read16(GUEST_CS_SELECTOR) & 3;
1968 }
1969
1970 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1971 {
1972         u32 ar;
1973
1974         if (var->unusable)
1975                 ar = 1 << 16;
1976         else {
1977                 ar = var->type & 15;
1978                 ar |= (var->s & 1) << 4;
1979                 ar |= (var->dpl & 3) << 5;
1980                 ar |= (var->present & 1) << 7;
1981                 ar |= (var->avl & 1) << 12;
1982                 ar |= (var->l & 1) << 13;
1983                 ar |= (var->db & 1) << 14;
1984                 ar |= (var->g & 1) << 15;
1985         }
1986         if (ar == 0) /* a 0 value means unusable */
1987                 ar = AR_UNUSABLE_MASK;
1988
1989         return ar;
1990 }
1991
1992 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1993                             struct kvm_segment *var, int seg)
1994 {
1995         struct vcpu_vmx *vmx = to_vmx(vcpu);
1996         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1997         u32 ar;
1998
1999         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
2000                 vmx->rmode.tr.selector = var->selector;
2001                 vmx->rmode.tr.base = var->base;
2002                 vmx->rmode.tr.limit = var->limit;
2003                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
2004                 return;
2005         }
2006         vmcs_writel(sf->base, var->base);
2007         vmcs_write32(sf->limit, var->limit);
2008         vmcs_write16(sf->selector, var->selector);
2009         if (vmx->rmode.vm86_active && var->s) {
2010                 /*
2011                  * Hack real-mode segments into vm86 compatibility.
2012                  */
2013                 if (var->base == 0xffff0000 && var->selector == 0xf000)
2014                         vmcs_writel(sf->base, 0xf0000);
2015                 ar = 0xf3;
2016         } else
2017                 ar = vmx_segment_access_rights(var);
2018
2019         /*
2020          *   Fix the "Accessed" bit in AR field of segment registers for older
2021          * qemu binaries.
2022          *   IA32 arch specifies that at the time of processor reset the
2023          * "Accessed" bit in the AR field of segment registers is 1. And qemu
2024          * is setting it to 0 in the usedland code. This causes invalid guest
2025          * state vmexit when "unrestricted guest" mode is turned on.
2026          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
2027          * tree. Newer qemu binaries with that qemu fix would not need this
2028          * kvm hack.
2029          */
2030         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
2031                 ar |= 0x1; /* Accessed */
2032
2033         vmcs_write32(sf->ar_bytes, ar);
2034 }
2035
2036 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2037 {
2038         u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
2039
2040         *db = (ar >> 14) & 1;
2041         *l = (ar >> 13) & 1;
2042 }
2043
2044 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2045 {
2046         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2047         dt->address = vmcs_readl(GUEST_IDTR_BASE);
2048 }
2049
2050 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2051 {
2052         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2053         vmcs_writel(GUEST_IDTR_BASE, dt->address);
2054 }
2055
2056 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2057 {
2058         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2059         dt->address = vmcs_readl(GUEST_GDTR_BASE);
2060 }
2061
2062 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
2063 {
2064         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2065         vmcs_writel(GUEST_GDTR_BASE, dt->address);
2066 }
2067
2068 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2069 {
2070         struct kvm_segment var;
2071         u32 ar;
2072
2073         vmx_get_segment(vcpu, &var, seg);
2074         ar = vmx_segment_access_rights(&var);
2075
2076         if (var.base != (var.selector << 4))
2077                 return false;
2078         if (var.limit != 0xffff)
2079                 return false;
2080         if (ar != 0xf3)
2081                 return false;
2082
2083         return true;
2084 }
2085
2086 static bool code_segment_valid(struct kvm_vcpu *vcpu)
2087 {
2088         struct kvm_segment cs;
2089         unsigned int cs_rpl;
2090
2091         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2092         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
2093
2094         if (cs.unusable)
2095                 return false;
2096         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
2097                 return false;
2098         if (!cs.s)
2099                 return false;
2100         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
2101                 if (cs.dpl > cs_rpl)
2102                         return false;
2103         } else {
2104                 if (cs.dpl != cs_rpl)
2105                         return false;
2106         }
2107         if (!cs.present)
2108                 return false;
2109
2110         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2111         return true;
2112 }
2113
2114 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2115 {
2116         struct kvm_segment ss;
2117         unsigned int ss_rpl;
2118
2119         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2120         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
2121
2122         if (ss.unusable)
2123                 return true;
2124         if (ss.type != 3 && ss.type != 7)
2125                 return false;
2126         if (!ss.s)
2127                 return false;
2128         if (ss.dpl != ss_rpl) /* DPL != RPL */
2129                 return false;
2130         if (!ss.present)
2131                 return false;
2132
2133         return true;
2134 }
2135
2136 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2137 {
2138         struct kvm_segment var;
2139         unsigned int rpl;
2140
2141         vmx_get_segment(vcpu, &var, seg);
2142         rpl = var.selector & SELECTOR_RPL_MASK;
2143
2144         if (var.unusable)
2145                 return true;
2146         if (!var.s)
2147                 return false;
2148         if (!var.present)
2149                 return false;
2150         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
2151                 if (var.dpl < rpl) /* DPL < RPL */
2152                         return false;
2153         }
2154
2155         /* TODO: Add other members to kvm_segment_field to allow checking for other access
2156          * rights flags
2157          */
2158         return true;
2159 }
2160
2161 static bool tr_valid(struct kvm_vcpu *vcpu)
2162 {
2163         struct kvm_segment tr;
2164
2165         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2166
2167         if (tr.unusable)
2168                 return false;
2169         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
2170                 return false;
2171         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
2172                 return false;
2173         if (!tr.present)
2174                 return false;
2175
2176         return true;
2177 }
2178
2179 static bool ldtr_valid(struct kvm_vcpu *vcpu)
2180 {
2181         struct kvm_segment ldtr;
2182
2183         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2184
2185         if (ldtr.unusable)
2186                 return true;
2187         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
2188                 return false;
2189         if (ldtr.type != 2)
2190                 return false;
2191         if (!ldtr.present)
2192                 return false;
2193
2194         return true;
2195 }
2196
2197 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2198 {
2199         struct kvm_segment cs, ss;
2200
2201         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2202         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2203
2204         return ((cs.selector & SELECTOR_RPL_MASK) ==
2205                  (ss.selector & SELECTOR_RPL_MASK));
2206 }
2207
2208 /*
2209  * Check if guest state is valid. Returns true if valid, false if
2210  * not.
2211  * We assume that registers are always usable
2212  */
2213 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2214 {
2215         /* real mode guest state checks */
2216         if (!is_protmode(vcpu)) {
2217                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2218                         return false;
2219                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2220                         return false;
2221                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2222                         return false;
2223                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2224                         return false;
2225                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2226                         return false;
2227                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2228                         return false;
2229         } else {
2230         /* protected mode guest state checks */
2231                 if (!cs_ss_rpl_check(vcpu))
2232                         return false;
2233                 if (!code_segment_valid(vcpu))
2234                         return false;
2235                 if (!stack_segment_valid(vcpu))
2236                         return false;
2237                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2238                         return false;
2239                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2240                         return false;
2241                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2242                         return false;
2243                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2244                         return false;
2245                 if (!tr_valid(vcpu))
2246                         return false;
2247                 if (!ldtr_valid(vcpu))
2248                         return false;
2249         }
2250         /* TODO:
2251          * - Add checks on RIP
2252          * - Add checks on RFLAGS
2253          */
2254
2255         return true;
2256 }
2257
2258 static int init_rmode_tss(struct kvm *kvm)
2259 {
2260         gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2261         u16 data = 0;
2262         int ret = 0;
2263         int r;
2264
2265         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2266         if (r < 0)
2267                 goto out;
2268         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2269         r = kvm_write_guest_page(kvm, fn++, &data,
2270                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
2271         if (r < 0)
2272                 goto out;
2273         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2274         if (r < 0)
2275                 goto out;
2276         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2277         if (r < 0)
2278                 goto out;
2279         data = ~0;
2280         r = kvm_write_guest_page(kvm, fn, &data,
2281                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2282                                  sizeof(u8));
2283         if (r < 0)
2284                 goto out;
2285
2286         ret = 1;
2287 out:
2288         return ret;
2289 }
2290
2291 static int init_rmode_identity_map(struct kvm *kvm)
2292 {
2293         int i, r, ret;
2294         pfn_t identity_map_pfn;
2295         u32 tmp;
2296
2297         if (!enable_ept)
2298                 return 1;
2299         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2300                 printk(KERN_ERR "EPT: identity-mapping pagetable "
2301                         "haven't been allocated!\n");
2302                 return 0;
2303         }
2304         if (likely(kvm->arch.ept_identity_pagetable_done))
2305                 return 1;
2306         ret = 0;
2307         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
2308         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2309         if (r < 0)
2310                 goto out;
2311         /* Set up identity-mapping pagetable for EPT in real mode */
2312         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2313                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2314                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2315                 r = kvm_write_guest_page(kvm, identity_map_pfn,
2316                                 &tmp, i * sizeof(tmp), sizeof(tmp));
2317                 if (r < 0)
2318                         goto out;
2319         }
2320         kvm->arch.ept_identity_pagetable_done = true;
2321         ret = 1;
2322 out:
2323         return ret;
2324 }
2325
2326 static void seg_setup(int seg)
2327 {
2328         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2329         unsigned int ar;
2330
2331         vmcs_write16(sf->selector, 0);
2332         vmcs_writel(sf->base, 0);
2333         vmcs_write32(sf->limit, 0xffff);
2334         if (enable_unrestricted_guest) {
2335                 ar = 0x93;
2336                 if (seg == VCPU_SREG_CS)
2337                         ar |= 0x08; /* code segment */
2338         } else
2339                 ar = 0xf3;
2340
2341         vmcs_write32(sf->ar_bytes, ar);
2342 }
2343
2344 static int alloc_apic_access_page(struct kvm *kvm)
2345 {
2346         struct kvm_userspace_memory_region kvm_userspace_mem;
2347         int r = 0;
2348
2349         mutex_lock(&kvm->slots_lock);
2350         if (kvm->arch.apic_access_page)
2351                 goto out;
2352         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2353         kvm_userspace_mem.flags = 0;
2354         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2355         kvm_userspace_mem.memory_size = PAGE_SIZE;
2356         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2357         if (r)
2358                 goto out;
2359
2360         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2361 out:
2362         mutex_unlock(&kvm->slots_lock);
2363         return r;
2364 }
2365
2366 static int alloc_identity_pagetable(struct kvm *kvm)
2367 {
2368         struct kvm_userspace_memory_region kvm_userspace_mem;
2369         int r = 0;
2370
2371         mutex_lock(&kvm->slots_lock);
2372         if (kvm->arch.ept_identity_pagetable)
2373                 goto out;
2374         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2375         kvm_userspace_mem.flags = 0;
2376         kvm_userspace_mem.guest_phys_addr =
2377                 kvm->arch.ept_identity_map_addr;
2378         kvm_userspace_mem.memory_size = PAGE_SIZE;
2379         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2380         if (r)
2381                 goto out;
2382
2383         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2384                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
2385 out:
2386         mutex_unlock(&kvm->slots_lock);
2387         return r;
2388 }
2389
2390 static void allocate_vpid(struct vcpu_vmx *vmx)
2391 {
2392         int vpid;
2393
2394         vmx->vpid = 0;
2395         if (!enable_vpid)
2396                 return;
2397         spin_lock(&vmx_vpid_lock);
2398         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2399         if (vpid < VMX_NR_VPIDS) {
2400                 vmx->vpid = vpid;
2401                 __set_bit(vpid, vmx_vpid_bitmap);
2402         }
2403         spin_unlock(&vmx_vpid_lock);
2404 }
2405
2406 static void free_vpid(struct vcpu_vmx *vmx)
2407 {
2408         if (!enable_vpid)
2409                 return;
2410         spin_lock(&vmx_vpid_lock);
2411         if (vmx->vpid != 0)
2412                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
2413         spin_unlock(&vmx_vpid_lock);
2414 }
2415
2416 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2417 {
2418         int f = sizeof(unsigned long);
2419
2420         if (!cpu_has_vmx_msr_bitmap())
2421                 return;
2422
2423         /*
2424          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2425          * have the write-low and read-high bitmap offsets the wrong way round.
2426          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2427          */
2428         if (msr <= 0x1fff) {
2429                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2430                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2431         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2432                 msr &= 0x1fff;
2433                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2434                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2435         }
2436 }
2437
2438 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2439 {
2440         if (!longmode_only)
2441                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2442         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2443 }
2444
2445 /*
2446  * Sets up the vmcs for emulated real mode.
2447  */
2448 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2449 {
2450         u32 host_sysenter_cs, msr_low, msr_high;
2451         u32 junk;
2452         u64 host_pat, tsc_this, tsc_base;
2453         unsigned long a;
2454         struct desc_ptr dt;
2455         int i;
2456         unsigned long kvm_vmx_return;
2457         u32 exec_control;
2458
2459         /* I/O */
2460         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2461         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2462
2463         if (cpu_has_vmx_msr_bitmap())
2464                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2465
2466         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2467
2468         /* Control */
2469         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2470                 vmcs_config.pin_based_exec_ctrl);
2471
2472         exec_control = vmcs_config.cpu_based_exec_ctrl;
2473         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2474                 exec_control &= ~CPU_BASED_TPR_SHADOW;
2475 #ifdef CONFIG_X86_64
2476                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2477                                 CPU_BASED_CR8_LOAD_EXITING;
2478 #endif
2479         }
2480         if (!enable_ept)
2481                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2482                                 CPU_BASED_CR3_LOAD_EXITING  |
2483                                 CPU_BASED_INVLPG_EXITING;
2484         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2485
2486         if (cpu_has_secondary_exec_ctrls()) {
2487                 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2488                 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2489                         exec_control &=
2490                                 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2491                 if (vmx->vpid == 0)
2492                         exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2493                 if (!enable_ept) {
2494                         exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2495                         enable_unrestricted_guest = 0;
2496                 }
2497                 if (!enable_unrestricted_guest)
2498                         exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2499                 if (!ple_gap)
2500                         exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
2501                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2502         }
2503
2504         if (ple_gap) {
2505                 vmcs_write32(PLE_GAP, ple_gap);
2506                 vmcs_write32(PLE_WINDOW, ple_window);
2507         }
2508
2509         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2510         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2511         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
2512
2513         vmcs_writel(HOST_CR0, read_cr0());  /* 22.2.3 */
2514         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
2515         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
2516
2517         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
2518         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2519         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2520         vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs());    /* 22.2.4 */
2521         vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs());    /* 22.2.4 */
2522         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
2523 #ifdef CONFIG_X86_64
2524         rdmsrl(MSR_FS_BASE, a);
2525         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2526         rdmsrl(MSR_GS_BASE, a);
2527         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2528 #else
2529         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2530         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2531 #endif
2532
2533         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
2534
2535         native_store_idt(&dt);
2536         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
2537
2538         asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2539         vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2540         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2541         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2542         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
2543         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2544         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
2545
2546         rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2547         vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2548         rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2549         vmcs_writel(HOST_IA32_SYSENTER_ESP, a);   /* 22.2.3 */
2550         rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2551         vmcs_writel(HOST_IA32_SYSENTER_EIP, a);   /* 22.2.3 */
2552
2553         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2554                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2555                 host_pat = msr_low | ((u64) msr_high << 32);
2556                 vmcs_write64(HOST_IA32_PAT, host_pat);
2557         }
2558         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2559                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2560                 host_pat = msr_low | ((u64) msr_high << 32);
2561                 /* Write the default value follow host pat */
2562                 vmcs_write64(GUEST_IA32_PAT, host_pat);
2563                 /* Keep arch.pat sync with GUEST_IA32_PAT */
2564                 vmx->vcpu.arch.pat = host_pat;
2565         }
2566
2567         for (i = 0; i < NR_VMX_MSR; ++i) {
2568                 u32 index = vmx_msr_index[i];
2569                 u32 data_low, data_high;
2570                 int j = vmx->nmsrs;
2571
2572                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2573                         continue;
2574                 if (wrmsr_safe(index, data_low, data_high) < 0)
2575                         continue;
2576                 vmx->guest_msrs[j].index = i;
2577                 vmx->guest_msrs[j].data = 0;
2578                 vmx->guest_msrs[j].mask = -1ull;
2579                 ++vmx->nmsrs;
2580         }
2581
2582         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2583
2584         /* 22.2.1, 20.8.1 */
2585         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2586
2587         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2588         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
2589         if (enable_ept)
2590                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
2591         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
2592
2593         tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2594         rdtscll(tsc_this);
2595         if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2596                 tsc_base = tsc_this;
2597
2598         guest_write_tsc(0, tsc_base);
2599
2600         return 0;
2601 }
2602
2603 static int init_rmode(struct kvm *kvm)
2604 {
2605         if (!init_rmode_tss(kvm))
2606                 return 0;
2607         if (!init_rmode_identity_map(kvm))
2608                 return 0;
2609         return 1;
2610 }
2611
2612 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2613 {
2614         struct vcpu_vmx *vmx = to_vmx(vcpu);
2615         u64 msr;
2616         int ret, idx;
2617
2618         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2619         idx = srcu_read_lock(&vcpu->kvm->srcu);
2620         if (!init_rmode(vmx->vcpu.kvm)) {
2621                 ret = -ENOMEM;
2622                 goto out;
2623         }
2624
2625         vmx->rmode.vm86_active = 0;
2626
2627         vmx->soft_vnmi_blocked = 0;
2628
2629         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2630         kvm_set_cr8(&vmx->vcpu, 0);
2631         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2632         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2633                 msr |= MSR_IA32_APICBASE_BSP;
2634         kvm_set_apic_base(&vmx->vcpu, msr);
2635
2636         fx_init(&vmx->vcpu);
2637
2638         seg_setup(VCPU_SREG_CS);
2639         /*
2640          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2641          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
2642          */
2643         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2644                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2645                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2646         } else {
2647                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2648                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2649         }
2650
2651         seg_setup(VCPU_SREG_DS);
2652         seg_setup(VCPU_SREG_ES);
2653         seg_setup(VCPU_SREG_FS);
2654         seg_setup(VCPU_SREG_GS);
2655         seg_setup(VCPU_SREG_SS);
2656
2657         vmcs_write16(GUEST_TR_SELECTOR, 0);
2658         vmcs_writel(GUEST_TR_BASE, 0);
2659         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2660         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2661
2662         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2663         vmcs_writel(GUEST_LDTR_BASE, 0);
2664         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2665         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2666
2667         vmcs_write32(GUEST_SYSENTER_CS, 0);
2668         vmcs_writel(GUEST_SYSENTER_ESP, 0);
2669         vmcs_writel(GUEST_SYSENTER_EIP, 0);
2670
2671         vmcs_writel(GUEST_RFLAGS, 0x02);
2672         if (kvm_vcpu_is_bsp(&vmx->vcpu))
2673                 kvm_rip_write(vcpu, 0xfff0);
2674         else
2675                 kvm_rip_write(vcpu, 0);
2676         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2677
2678         vmcs_writel(GUEST_DR7, 0x400);
2679
2680         vmcs_writel(GUEST_GDTR_BASE, 0);
2681         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2682
2683         vmcs_writel(GUEST_IDTR_BASE, 0);
2684         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2685
2686         vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2687         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2688         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2689
2690         /* Special registers */
2691         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2692
2693         setup_msrs(vmx);
2694
2695         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
2696
2697         if (cpu_has_vmx_tpr_shadow()) {
2698                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2699                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2700                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2701                                 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2702                 vmcs_write32(TPR_THRESHOLD, 0);
2703         }
2704
2705         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2706                 vmcs_write64(APIC_ACCESS_ADDR,
2707                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2708
2709         if (vmx->vpid != 0)
2710                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2711
2712         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
2713         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
2714         vmx_set_cr4(&vmx->vcpu, 0);
2715         vmx_set_efer(&vmx->vcpu, 0);
2716         vmx_fpu_activate(&vmx->vcpu);
2717         update_exception_bitmap(&vmx->vcpu);
2718
2719         vpid_sync_vcpu_all(vmx);
2720
2721         ret = 0;
2722
2723         /* HACK: Don't enable emulation on guest boot/reset */
2724         vmx->emulation_required = 0;
2725
2726 out:
2727         srcu_read_unlock(&vcpu->kvm->srcu, idx);
2728         return ret;
2729 }
2730
2731 static void enable_irq_window(struct kvm_vcpu *vcpu)
2732 {
2733         u32 cpu_based_vm_exec_control;
2734
2735         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2736         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2737         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2738 }
2739
2740 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2741 {
2742         u32 cpu_based_vm_exec_control;
2743
2744         if (!cpu_has_virtual_nmis()) {
2745                 enable_irq_window(vcpu);
2746                 return;
2747         }
2748
2749         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2750         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2751         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2752 }
2753
2754 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2755 {
2756         struct vcpu_vmx *vmx = to_vmx(vcpu);
2757         uint32_t intr;
2758         int irq = vcpu->arch.interrupt.nr;
2759
2760         trace_kvm_inj_virq(irq);
2761
2762         ++vcpu->stat.irq_injections;
2763         if (vmx->rmode.vm86_active) {
2764                 vmx->rmode.irq.pending = true;
2765                 vmx->rmode.irq.vector = irq;
2766                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2767                 if (vcpu->arch.interrupt.soft)
2768                         vmx->rmode.irq.rip +=
2769                                 vmx->vcpu.arch.event_exit_inst_len;
2770                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2771                              irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2772                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2773                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2774                 return;
2775         }
2776         intr = irq | INTR_INFO_VALID_MASK;
2777         if (vcpu->arch.interrupt.soft) {
2778                 intr |= INTR_TYPE_SOFT_INTR;
2779                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2780                              vmx->vcpu.arch.event_exit_inst_len);
2781         } else
2782                 intr |= INTR_TYPE_EXT_INTR;
2783         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2784 }
2785
2786 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2787 {
2788         struct vcpu_vmx *vmx = to_vmx(vcpu);
2789
2790         if (!cpu_has_virtual_nmis()) {
2791                 /*
2792                  * Tracking the NMI-blocked state in software is built upon
2793                  * finding the next open IRQ window. This, in turn, depends on
2794                  * well-behaving guests: They have to keep IRQs disabled at
2795                  * least as long as the NMI handler runs. Otherwise we may
2796                  * cause NMI nesting, maybe breaking the guest. But as this is
2797                  * highly unlikely, we can live with the residual risk.
2798                  */
2799                 vmx->soft_vnmi_blocked = 1;
2800                 vmx->vnmi_blocked_time = 0;
2801         }
2802
2803         ++vcpu->stat.nmi_injections;
2804         if (vmx->rmode.vm86_active) {
2805                 vmx->rmode.irq.pending = true;
2806                 vmx->rmode.irq.vector = NMI_VECTOR;
2807                 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2808                 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2809                              NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2810                              INTR_INFO_VALID_MASK);
2811                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2812                 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2813                 return;
2814         }
2815         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2816                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2817 }
2818
2819 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2820 {
2821         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2822                 return 0;
2823
2824         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2825                         (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_NMI));
2826 }
2827
2828 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
2829 {
2830         if (!cpu_has_virtual_nmis())
2831                 return to_vmx(vcpu)->soft_vnmi_blocked;
2832         else
2833                 return !!(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2834                           GUEST_INTR_STATE_NMI);
2835 }
2836
2837 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2838 {
2839         struct vcpu_vmx *vmx = to_vmx(vcpu);
2840
2841         if (!cpu_has_virtual_nmis()) {
2842                 if (vmx->soft_vnmi_blocked != masked) {
2843                         vmx->soft_vnmi_blocked = masked;
2844                         vmx->vnmi_blocked_time = 0;
2845                 }
2846         } else {
2847                 if (masked)
2848                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
2849                                       GUEST_INTR_STATE_NMI);
2850                 else
2851                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
2852                                         GUEST_INTR_STATE_NMI);
2853         }
2854 }
2855
2856 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2857 {
2858         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2859                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2860                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2861 }
2862
2863 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2864 {
2865         int ret;
2866         struct kvm_userspace_memory_region tss_mem = {
2867                 .slot = TSS_PRIVATE_MEMSLOT,
2868                 .guest_phys_addr = addr,
2869                 .memory_size = PAGE_SIZE * 3,
2870                 .flags = 0,
2871         };
2872
2873         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2874         if (ret)
2875                 return ret;
2876         kvm->arch.tss_addr = addr;
2877         return 0;
2878 }
2879
2880 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2881                                   int vec, u32 err_code)
2882 {
2883         /*
2884          * Instruction with address size override prefix opcode 0x67
2885          * Cause the #SS fault with 0 error code in VM86 mode.
2886          */
2887         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2888                 if (emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DONE)
2889                         return 1;
2890         /*
2891          * Forward all other exceptions that are valid in real mode.
2892          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2893          *        the required debugging infrastructure rework.
2894          */
2895         switch (vec) {
2896         case DB_VECTOR:
2897                 if (vcpu->guest_debug &
2898                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2899                         return 0;
2900                 kvm_queue_exception(vcpu, vec);
2901                 return 1;
2902         case BP_VECTOR:
2903                 /*
2904                  * Update instruction length as we may reinject the exception
2905                  * from user space while in guest debugging mode.
2906                  */
2907                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
2908                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
2909                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2910                         return 0;
2911                 /* fall through */
2912         case DE_VECTOR:
2913         case OF_VECTOR:
2914         case BR_VECTOR:
2915         case UD_VECTOR:
2916         case DF_VECTOR:
2917         case SS_VECTOR:
2918         case GP_VECTOR:
2919         case MF_VECTOR:
2920                 kvm_queue_exception(vcpu, vec);
2921                 return 1;
2922         }
2923         return 0;
2924 }
2925
2926 /*
2927  * Trigger machine check on the host. We assume all the MSRs are already set up
2928  * by the CPU and that we still run on the same CPU as the MCE occurred on.
2929  * We pass a fake environment to the machine check handler because we want
2930  * the guest to be always treated like user space, no matter what context
2931  * it used internally.
2932  */
2933 static void kvm_machine_check(void)
2934 {
2935 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2936         struct pt_regs regs = {
2937                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2938                 .flags = X86_EFLAGS_IF,
2939         };
2940
2941         do_machine_check(&regs, 0);
2942 #endif
2943 }
2944
2945 static int handle_machine_check(struct kvm_vcpu *vcpu)
2946 {
2947         /* already handled by vcpu_run */
2948         return 1;
2949 }
2950
2951 static int handle_exception(struct kvm_vcpu *vcpu)
2952 {
2953         struct vcpu_vmx *vmx = to_vmx(vcpu);
2954         struct kvm_run *kvm_run = vcpu->run;
2955         u32 intr_info, ex_no, error_code;
2956         unsigned long cr2, rip, dr6;
2957         u32 vect_info;
2958         enum emulation_result er;
2959
2960         vect_info = vmx->idt_vectoring_info;
2961         intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2962
2963         if (is_machine_check(intr_info))
2964                 return handle_machine_check(vcpu);
2965
2966         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2967             !is_page_fault(intr_info)) {
2968                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2969                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
2970                 vcpu->run->internal.ndata = 2;
2971                 vcpu->run->internal.data[0] = vect_info;
2972                 vcpu->run->internal.data[1] = intr_info;
2973                 return 0;
2974         }
2975
2976         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2977                 return 1;  /* already handled by vmx_vcpu_run() */
2978
2979         if (is_no_device(intr_info)) {
2980                 vmx_fpu_activate(vcpu);
2981                 return 1;
2982         }
2983
2984         if (is_invalid_opcode(intr_info)) {
2985                 er = emulate_instruction(vcpu, 0, 0, EMULTYPE_TRAP_UD);
2986                 if (er != EMULATE_DONE)
2987                         kvm_queue_exception(vcpu, UD_VECTOR);
2988                 return 1;
2989         }
2990
2991         error_code = 0;
2992         rip = kvm_rip_read(vcpu);
2993         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2994                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2995         if (is_page_fault(intr_info)) {
2996                 /* EPT won't cause page fault directly */
2997                 if (enable_ept)
2998                         BUG();
2999                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
3000                 trace_kvm_page_fault(cr2, error_code);
3001
3002                 if (kvm_event_needs_reinjection(vcpu))
3003                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
3004                 return kvm_mmu_page_fault(vcpu, cr2, error_code);
3005         }
3006
3007         if (vmx->rmode.vm86_active &&
3008             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
3009                                                                 error_code)) {
3010                 if (vcpu->arch.halt_request) {
3011                         vcpu->arch.halt_request = 0;
3012                         return kvm_emulate_halt(vcpu);
3013                 }
3014                 return 1;
3015         }
3016
3017         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
3018         switch (ex_no) {
3019         case DB_VECTOR:
3020                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
3021                 if (!(vcpu->guest_debug &
3022                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
3023                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
3024                         kvm_queue_exception(vcpu, DB_VECTOR);
3025                         return 1;
3026                 }
3027                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
3028                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
3029                 /* fall through */
3030         case BP_VECTOR:
3031                 /*
3032                  * Update instruction length as we may reinject #BP from
3033                  * user space while in guest debugging mode. Reading it for
3034                  * #DB as well causes no harm, it is not used in that case.
3035                  */
3036                 vmx->vcpu.arch.event_exit_inst_len =
3037                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3038                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
3039                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
3040                 kvm_run->debug.arch.exception = ex_no;
3041                 break;
3042         default:
3043                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
3044                 kvm_run->ex.exception = ex_no;
3045                 kvm_run->ex.error_code = error_code;
3046                 break;
3047         }
3048         return 0;
3049 }
3050
3051 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
3052 {
3053         ++vcpu->stat.irq_exits;
3054         return 1;
3055 }
3056
3057 static int handle_triple_fault(struct kvm_vcpu *vcpu)
3058 {
3059         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
3060         return 0;
3061 }
3062
3063 static int handle_io(struct kvm_vcpu *vcpu)
3064 {
3065         unsigned long exit_qualification;
3066         int size, in, string;
3067         unsigned port;
3068
3069         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3070         string = (exit_qualification & 16) != 0;
3071         in = (exit_qualification & 8) != 0;
3072
3073         ++vcpu->stat.io_exits;
3074
3075         if (string || in)
3076                 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
3077
3078         port = exit_qualification >> 16;
3079         size = (exit_qualification & 7) + 1;
3080         skip_emulated_instruction(vcpu);
3081
3082         return kvm_fast_pio_out(vcpu, size, port);
3083 }
3084
3085 static void
3086 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3087 {
3088         /*
3089          * Patch in the VMCALL instruction:
3090          */
3091         hypercall[0] = 0x0f;
3092         hypercall[1] = 0x01;
3093         hypercall[2] = 0xc1;
3094 }
3095
3096 static int handle_cr(struct kvm_vcpu *vcpu)
3097 {
3098         unsigned long exit_qualification, val;
3099         int cr;
3100         int reg;
3101
3102         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3103         cr = exit_qualification & 15;
3104         reg = (exit_qualification >> 8) & 15;
3105         switch ((exit_qualification >> 4) & 3) {
3106         case 0: /* mov to cr */
3107                 val = kvm_register_read(vcpu, reg);
3108                 trace_kvm_cr_write(cr, val);
3109                 switch (cr) {
3110                 case 0:
3111                         kvm_set_cr0(vcpu, val);
3112                         skip_emulated_instruction(vcpu);
3113                         return 1;
3114                 case 3:
3115                         kvm_set_cr3(vcpu, val);
3116                         skip_emulated_instruction(vcpu);
3117                         return 1;
3118                 case 4:
3119                         kvm_set_cr4(vcpu, val);
3120                         skip_emulated_instruction(vcpu);
3121                         return 1;
3122                 case 8: {
3123                                 u8 cr8_prev = kvm_get_cr8(vcpu);
3124                                 u8 cr8 = kvm_register_read(vcpu, reg);
3125                                 kvm_set_cr8(vcpu, cr8);
3126                                 skip_emulated_instruction(vcpu);
3127                                 if (irqchip_in_kernel(vcpu->kvm))
3128                                         return 1;
3129                                 if (cr8_prev <= cr8)
3130                                         return 1;
3131                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
3132                                 return 0;
3133                         }
3134                 };
3135                 break;
3136         case 2: /* clts */
3137                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
3138                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
3139                 skip_emulated_instruction(vcpu);
3140                 vmx_fpu_activate(vcpu);
3141                 return 1;
3142         case 1: /*mov from cr*/
3143                 switch (cr) {
3144                 case 3:
3145                         kvm_register_write(vcpu, reg, vcpu->arch.cr3);
3146                         trace_kvm_cr_read(cr, vcpu->arch.cr3);
3147                         skip_emulated_instruction(vcpu);
3148                         return 1;
3149                 case 8:
3150                         val = kvm_get_cr8(vcpu);
3151                         kvm_register_write(vcpu, reg, val);
3152                         trace_kvm_cr_read(cr, val);
3153                         skip_emulated_instruction(vcpu);
3154                         return 1;
3155                 }
3156                 break;
3157         case 3: /* lmsw */
3158                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
3159                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
3160                 kvm_lmsw(vcpu, val);
3161
3162                 skip_emulated_instruction(vcpu);
3163                 return 1;
3164         default:
3165                 break;
3166         }
3167         vcpu->run->exit_reason = 0;
3168         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
3169                (int)(exit_qualification >> 4) & 3, cr);
3170         return 0;
3171 }
3172
3173 static int handle_dr(struct kvm_vcpu *vcpu)
3174 {
3175         unsigned long exit_qualification;
3176         int dr, reg;
3177
3178         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
3179         if (!kvm_require_cpl(vcpu, 0))
3180                 return 1;
3181         dr = vmcs_readl(GUEST_DR7);
3182         if (dr & DR7_GD) {
3183                 /*
3184                  * As the vm-exit takes precedence over the debug trap, we
3185                  * need to emulate the latter, either for the host or the
3186                  * guest debugging itself.
3187                  */
3188                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
3189                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
3190                         vcpu->run->debug.arch.dr7 = dr;
3191                         vcpu->run->debug.arch.pc =
3192                                 vmcs_readl(GUEST_CS_BASE) +
3193                                 vmcs_readl(GUEST_RIP);
3194                         vcpu->run->debug.arch.exception = DB_VECTOR;
3195                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
3196                         return 0;
3197                 } else {
3198                         vcpu->arch.dr7 &= ~DR7_GD;
3199                         vcpu->arch.dr6 |= DR6_BD;
3200                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3201                         kvm_queue_exception(vcpu, DB_VECTOR);
3202                         return 1;
3203                 }
3204         }
3205
3206         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3207         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
3208         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
3209         if (exit_qualification & TYPE_MOV_FROM_DR) {
3210                 unsigned long val;
3211                 if (!kvm_get_dr(vcpu, dr, &val))
3212                         kvm_register_write(vcpu, reg, val);
3213         } else
3214                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
3215         skip_emulated_instruction(vcpu);
3216         return 1;
3217 }
3218
3219 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
3220 {
3221         vmcs_writel(GUEST_DR7, val);
3222 }
3223
3224 static int handle_cpuid(struct kvm_vcpu *vcpu)
3225 {
3226         kvm_emulate_cpuid(vcpu);
3227         return 1;
3228 }
3229
3230 static int handle_rdmsr(struct kvm_vcpu *vcpu)
3231 {
3232         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3233         u64 data;
3234
3235         if (vmx_get_msr(vcpu, ecx, &data)) {
3236                 trace_kvm_msr_read_ex(ecx);
3237                 kvm_inject_gp(vcpu, 0);
3238                 return 1;
3239         }
3240
3241         trace_kvm_msr_read(ecx, data);
3242
3243         /* FIXME: handling of bits 32:63 of rax, rdx */
3244         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3245         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3246         skip_emulated_instruction(vcpu);
3247         return 1;
3248 }
3249
3250 static int handle_wrmsr(struct kvm_vcpu *vcpu)
3251 {
3252         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3253         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3254                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3255
3256         if (vmx_set_msr(vcpu, ecx, data) != 0) {
3257                 trace_kvm_msr_write_ex(ecx, data);
3258                 kvm_inject_gp(vcpu, 0);
3259                 return 1;
3260         }
3261
3262         trace_kvm_msr_write(ecx, data);
3263         skip_emulated_instruction(vcpu);
3264         return 1;
3265 }
3266
3267 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
3268 {
3269         return 1;
3270 }
3271
3272 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
3273 {
3274         u32 cpu_based_vm_exec_control;
3275
3276         /* clear pending irq */
3277         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3278         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3279         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3280
3281         ++vcpu->stat.irq_window_exits;
3282
3283         /*
3284          * If the user space waits to inject interrupts, exit as soon as
3285          * possible
3286          */
3287         if (!irqchip_in_kernel(vcpu->kvm) &&
3288             vcpu->run->request_interrupt_window &&
3289             !kvm_cpu_has_interrupt(vcpu)) {
3290                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3291                 return 0;
3292         }
3293         return 1;
3294 }
3295
3296 static int handle_halt(struct kvm_vcpu *vcpu)
3297 {
3298         skip_emulated_instruction(vcpu);
3299         return kvm_emulate_halt(vcpu);
3300 }
3301
3302 static int handle_vmcall(struct kvm_vcpu *vcpu)
3303 {
3304         skip_emulated_instruction(vcpu);
3305         kvm_emulate_hypercall(vcpu);
3306         return 1;
3307 }
3308
3309 static int handle_vmx_insn(struct kvm_vcpu *vcpu)
3310 {
3311         kvm_queue_exception(vcpu, UD_VECTOR);
3312         return 1;
3313 }
3314
3315 static int handle_invlpg(struct kvm_vcpu *vcpu)
3316 {
3317         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3318
3319         kvm_mmu_invlpg(vcpu, exit_qualification);
3320         skip_emulated_instruction(vcpu);
3321         return 1;
3322 }
3323
3324 static int handle_wbinvd(struct kvm_vcpu *vcpu)
3325 {
3326         skip_emulated_instruction(vcpu);
3327         /* TODO: Add support for VT-d/pass-through device */
3328         return 1;
3329 }
3330
3331 static int handle_apic_access(struct kvm_vcpu *vcpu)
3332 {
3333         unsigned long exit_qualification;
3334         enum emulation_result er;
3335         unsigned long offset;
3336
3337         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3338         offset = exit_qualification & 0xffful;
3339
3340         er = emulate_instruction(vcpu, 0, 0, 0);
3341
3342         if (er !=  EMULATE_DONE) {
3343                 printk(KERN_ERR
3344                        "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3345                        offset);
3346                 return -ENOEXEC;
3347         }
3348         return 1;
3349 }
3350
3351 static int handle_task_switch(struct kvm_vcpu *vcpu)
3352 {
3353         struct vcpu_vmx *vmx = to_vmx(vcpu);
3354         unsigned long exit_qualification;
3355         bool has_error_code = false;
3356         u32 error_code = 0;
3357         u16 tss_selector;
3358         int reason, type, idt_v;
3359
3360         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3361         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3362
3363         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3364
3365         reason = (u32)exit_qualification >> 30;
3366         if (reason == TASK_SWITCH_GATE && idt_v) {
3367                 switch (type) {
3368                 case INTR_TYPE_NMI_INTR:
3369                         vcpu->arch.nmi_injected = false;
3370                         if (cpu_has_virtual_nmis())
3371                                 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3372                                               GUEST_INTR_STATE_NMI);
3373                         break;
3374                 case INTR_TYPE_EXT_INTR:
3375                 case INTR_TYPE_SOFT_INTR:
3376                         kvm_clear_interrupt_queue(vcpu);
3377                         break;
3378                 case INTR_TYPE_HARD_EXCEPTION:
3379                         if (vmx->idt_vectoring_info &
3380                             VECTORING_INFO_DELIVER_CODE_MASK) {
3381                                 has_error_code = true;
3382                                 error_code =
3383                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
3384                         }
3385                         /* fall through */
3386                 case INTR_TYPE_SOFT_EXCEPTION:
3387                         kvm_clear_exception_queue(vcpu);
3388                         break;
3389                 default:
3390                         break;
3391                 }
3392         }
3393         tss_selector = exit_qualification;
3394
3395         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3396                        type != INTR_TYPE_EXT_INTR &&
3397                        type != INTR_TYPE_NMI_INTR))
3398                 skip_emulated_instruction(vcpu);
3399
3400         if (kvm_task_switch(vcpu, tss_selector, reason,
3401                                 has_error_code, error_code) == EMULATE_FAIL) {
3402                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3403                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3404                 vcpu->run->internal.ndata = 0;
3405                 return 0;
3406         }
3407
3408         /* clear all local breakpoint enable flags */
3409         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3410
3411         /*
3412          * TODO: What about debug traps on tss switch?
3413          *       Are we supposed to inject them and update dr6?
3414          */
3415
3416         return 1;
3417 }
3418
3419 static int handle_ept_violation(struct kvm_vcpu *vcpu)
3420 {
3421         unsigned long exit_qualification;
3422         gpa_t gpa;
3423         int gla_validity;
3424
3425         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3426
3427         if (exit_qualification & (1 << 6)) {
3428                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3429                 return -EINVAL;
3430         }
3431
3432         gla_validity = (exit_qualification >> 7) & 0x3;
3433         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3434                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3435                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3436                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3437                         vmcs_readl(GUEST_LINEAR_ADDRESS));
3438                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3439                         (long unsigned int)exit_qualification);
3440                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3441                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3442                 return 0;
3443         }
3444
3445         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3446         trace_kvm_page_fault(gpa, exit_qualification);
3447         return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3448 }
3449
3450 static u64 ept_rsvd_mask(u64 spte, int level)
3451 {
3452         int i;
3453         u64 mask = 0;
3454
3455         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3456                 mask |= (1ULL << i);
3457
3458         if (level > 2)
3459                 /* bits 7:3 reserved */
3460                 mask |= 0xf8;
3461         else if (level == 2) {
3462                 if (spte & (1ULL << 7))
3463                         /* 2MB ref, bits 20:12 reserved */
3464                         mask |= 0x1ff000;
3465                 else
3466                         /* bits 6:3 reserved */
3467                         mask |= 0x78;
3468         }
3469
3470         return mask;
3471 }
3472
3473 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3474                                        int level)
3475 {
3476         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3477
3478         /* 010b (write-only) */
3479         WARN_ON((spte & 0x7) == 0x2);
3480
3481         /* 110b (write/execute) */
3482         WARN_ON((spte & 0x7) == 0x6);
3483
3484         /* 100b (execute-only) and value not supported by logical processor */
3485         if (!cpu_has_vmx_ept_execute_only())
3486                 WARN_ON((spte & 0x7) == 0x4);
3487
3488         /* not 000b */
3489         if ((spte & 0x7)) {
3490                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3491
3492                 if (rsvd_bits != 0) {
3493                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3494                                          __func__, rsvd_bits);
3495                         WARN_ON(1);
3496                 }
3497
3498                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3499                         u64 ept_mem_type = (spte & 0x38) >> 3;
3500
3501                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
3502                             ept_mem_type == 7) {
3503                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3504                                                 __func__, ept_mem_type);
3505                                 WARN_ON(1);
3506                         }
3507                 }
3508         }
3509 }
3510
3511 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
3512 {
3513         u64 sptes[4];
3514         int nr_sptes, i;
3515         gpa_t gpa;
3516
3517         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3518
3519         printk(KERN_ERR "EPT: Misconfiguration.\n");
3520         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3521
3522         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3523
3524         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3525                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3526
3527         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3528         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3529
3530         return 0;
3531 }
3532
3533 static int handle_nmi_window(struct kvm_vcpu *vcpu)
3534 {
3535         u32 cpu_based_vm_exec_control;
3536
3537         /* clear pending NMI */
3538         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3539         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3540         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3541         ++vcpu->stat.nmi_window_exits;
3542
3543         return 1;
3544 }
3545
3546 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
3547 {
3548         struct vcpu_vmx *vmx = to_vmx(vcpu);
3549         enum emulation_result err = EMULATE_DONE;
3550         int ret = 1;
3551
3552         while (!guest_state_valid(vcpu)) {
3553                 err = emulate_instruction(vcpu, 0, 0, 0);
3554
3555                 if (err == EMULATE_DO_MMIO) {
3556                         ret = 0;
3557                         goto out;
3558                 }
3559
3560                 if (err != EMULATE_DONE) {
3561                         vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3562                         vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
3563                         vcpu->run->internal.ndata = 0;
3564                         ret = 0;
3565                         goto out;
3566                 }
3567
3568                 if (signal_pending(current))
3569                         goto out;
3570                 if (need_resched())
3571                         schedule();
3572         }
3573
3574         vmx->emulation_required = 0;
3575 out:
3576         return ret;
3577 }
3578
3579 /*
3580  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
3581  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
3582  */
3583 static int handle_pause(struct kvm_vcpu *vcpu)
3584 {
3585         skip_emulated_instruction(vcpu);
3586         kvm_vcpu_on_spin(vcpu);
3587
3588         return 1;
3589 }
3590
3591 static int handle_invalid_op(struct kvm_vcpu *vcpu)
3592 {
3593         kvm_queue_exception(vcpu, UD_VECTOR);
3594         return 1;
3595 }
3596
3597 /*
3598  * The exit handlers return 1 if the exit was handled fully and guest execution
3599  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
3600  * to be done to userspace and return 0.
3601  */
3602 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3603         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
3604         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
3605         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
3606         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
3607         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
3608         [EXIT_REASON_CR_ACCESS]               = handle_cr,
3609         [EXIT_REASON_DR_ACCESS]               = handle_dr,
3610         [EXIT_REASON_CPUID]                   = handle_cpuid,
3611         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
3612         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
3613         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
3614         [EXIT_REASON_HLT]                     = handle_halt,
3615         [EXIT_REASON_INVLPG]                  = handle_invlpg,
3616         [EXIT_REASON_VMCALL]                  = handle_vmcall,
3617         [EXIT_REASON_VMCLEAR]                 = handle_vmx_insn,
3618         [EXIT_REASON_VMLAUNCH]                = handle_vmx_insn,
3619         [EXIT_REASON_VMPTRLD]                 = handle_vmx_insn,
3620         [EXIT_REASON_VMPTRST]                 = handle_vmx_insn,
3621         [EXIT_REASON_VMREAD]                  = handle_vmx_insn,
3622         [EXIT_REASON_VMRESUME]                = handle_vmx_insn,
3623         [EXIT_REASON_VMWRITE]                 = handle_vmx_insn,
3624         [EXIT_REASON_VMOFF]                   = handle_vmx_insn,
3625         [EXIT_REASON_VMON]                    = handle_vmx_insn,
3626         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
3627         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
3628         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
3629         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
3630         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
3631         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
3632         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
3633         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
3634         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
3635         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
3636 };
3637
3638 static const int kvm_vmx_max_exit_handlers =
3639         ARRAY_SIZE(kvm_vmx_exit_handlers);
3640
3641 /*
3642  * The guest has exited.  See if we can fix it or if we need userspace
3643  * assistance.
3644  */
3645 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
3646 {
3647         struct vcpu_vmx *vmx = to_vmx(vcpu);
3648         u32 exit_reason = vmx->exit_reason;
3649         u32 vectoring_info = vmx->idt_vectoring_info;
3650
3651         trace_kvm_exit(exit_reason, vcpu);
3652
3653         /* If guest state is invalid, start emulating */
3654         if (vmx->emulation_required && emulate_invalid_guest_state)
3655                 return handle_invalid_guest_state(vcpu);
3656
3657         /* Access CR3 don't cause VMExit in paging mode, so we need
3658          * to sync with guest real CR3. */
3659         if (enable_ept && is_paging(vcpu))
3660                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3661
3662         if (unlikely(vmx->fail)) {
3663                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3664                 vcpu->run->fail_entry.hardware_entry_failure_reason
3665                         = vmcs_read32(VM_INSTRUCTION_ERROR);
3666                 return 0;
3667         }
3668
3669         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3670                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3671                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
3672                         exit_reason != EXIT_REASON_TASK_SWITCH))
3673                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3674                        "(0x%x) and exit reason is 0x%x\n",
3675                        __func__, vectoring_info, exit_reason);
3676
3677         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3678                 if (vmx_interrupt_allowed(vcpu)) {
3679                         vmx->soft_vnmi_blocked = 0;
3680                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3681                            vcpu->arch.nmi_pending) {
3682                         /*
3683                          * This CPU don't support us in finding the end of an
3684                          * NMI-blocked window if the guest runs with IRQs
3685                          * disabled. So we pull the trigger after 1 s of
3686                          * futile waiting, but inform the user about this.
3687                          */
3688                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3689                                "state on VCPU %d after 1 s timeout\n",
3690                                __func__, vcpu->vcpu_id);
3691                         vmx->soft_vnmi_blocked = 0;
3692                 }
3693         }
3694
3695         if (exit_reason < kvm_vmx_max_exit_handlers
3696             && kvm_vmx_exit_handlers[exit_reason])
3697                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
3698         else {
3699                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
3700                 vcpu->run->hw.hardware_exit_reason = exit_reason;
3701         }
3702         return 0;
3703 }
3704
3705 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3706 {
3707         if (irr == -1 || tpr < irr) {
3708                 vmcs_write32(TPR_THRESHOLD, 0);
3709                 return;
3710         }
3711
3712         vmcs_write32(TPR_THRESHOLD, irr);
3713 }
3714
3715 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3716 {
3717         u32 exit_intr_info;
3718         u32 idt_vectoring_info = vmx->idt_vectoring_info;
3719         bool unblock_nmi;
3720         u8 vector;
3721         int type;
3722         bool idtv_info_valid;
3723
3724         exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3725
3726         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3727
3728         /* Handle machine checks before interrupts are enabled */
3729         if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3730             || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3731                 && is_machine_check(exit_intr_info)))
3732                 kvm_machine_check();
3733
3734         /* We need to handle NMIs before interrupts are enabled */
3735         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3736             (exit_intr_info & INTR_INFO_VALID_MASK)) {
3737                 kvm_before_handle_nmi(&vmx->vcpu);
3738                 asm("int $2");
3739                 kvm_after_handle_nmi(&vmx->vcpu);
3740         }
3741
3742         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3743
3744         if (cpu_has_virtual_nmis()) {
3745                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3746                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3747                 /*
3748                  * SDM 3: 27.7.1.2 (September 2008)
3749                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
3750                  * a guest IRET fault.
3751                  * SDM 3: 23.2.2 (September 2008)
3752                  * Bit 12 is undefined in any of the following cases:
3753                  *  If the VM exit sets the valid bit in the IDT-vectoring
3754                  *   information field.
3755                  *  If the VM exit is due to a double fault.
3756                  */
3757                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3758                     vector != DF_VECTOR && !idtv_info_valid)
3759                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3760                                       GUEST_INTR_STATE_NMI);
3761         } else if (unlikely(vmx->soft_vnmi_blocked))
3762                 vmx->vnmi_blocked_time +=
3763                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3764
3765         vmx->vcpu.arch.nmi_injected = false;
3766         kvm_clear_exception_queue(&vmx->vcpu);
3767         kvm_clear_interrupt_queue(&vmx->vcpu);
3768
3769         if (!idtv_info_valid)
3770                 return;
3771
3772         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3773         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3774
3775         switch (type) {
3776         case INTR_TYPE_NMI_INTR:
3777                 vmx->vcpu.arch.nmi_injected = true;
3778                 /*
3779                  * SDM 3: 27.7.1.2 (September 2008)
3780                  * Clear bit "block by NMI" before VM entry if a NMI
3781                  * delivery faulted.
3782                  */
3783                 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3784                                 GUEST_INTR_STATE_NMI);
3785                 break;
3786         case INTR_TYPE_SOFT_EXCEPTION:
3787                 vmx->vcpu.arch.event_exit_inst_len =
3788                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3789                 /* fall through */
3790         case INTR_TYPE_HARD_EXCEPTION:
3791                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3792                         u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3793                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
3794                 } else
3795                         kvm_queue_exception(&vmx->vcpu, vector);
3796                 break;
3797         case INTR_TYPE_SOFT_INTR:
3798                 vmx->vcpu.arch.event_exit_inst_len =
3799                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3800                 /* fall through */
3801         case INTR_TYPE_EXT_INTR:
3802                 kvm_queue_interrupt(&vmx->vcpu, vector,
3803                         type == INTR_TYPE_SOFT_INTR);
3804                 break;
3805         default:
3806                 break;
3807         }
3808 }
3809
3810 /*
3811  * Failure to inject an interrupt should give us the information
3812  * in IDT_VECTORING_INFO_FIELD.  However, if the failure occurs
3813  * when fetching the interrupt redirection bitmap in the real-mode
3814  * tss, this doesn't happen.  So we do it ourselves.
3815  */
3816 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3817 {
3818         vmx->rmode.irq.pending = 0;
3819         if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3820                 return;
3821         kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3822         if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3823                 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3824                 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3825                 return;
3826         }
3827         vmx->idt_vectoring_info =
3828                 VECTORING_INFO_VALID_MASK
3829                 | INTR_TYPE_EXT_INTR
3830                 | vmx->rmode.irq.vector;
3831 }
3832
3833 #ifdef CONFIG_X86_64
3834 #define R "r"
3835 #define Q "q"
3836 #else
3837 #define R "e"
3838 #define Q "l"
3839 #endif
3840
3841 static void vmx_vcpu_run(struct kvm_vcpu *vcpu)
3842 {
3843         struct vcpu_vmx *vmx = to_vmx(vcpu);
3844
3845         /* Record the guest's net vcpu time for enforced NMI injections. */
3846         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3847                 vmx->entry_time = ktime_get();
3848
3849         /* Don't enter VMX if guest state is invalid, let the exit handler
3850            start emulation until we arrive back to a valid state */
3851         if (vmx->emulation_required && emulate_invalid_guest_state)
3852                 return;
3853
3854         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3855                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3856         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3857                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3858
3859         /* When single-stepping over STI and MOV SS, we must clear the
3860          * corresponding interruptibility bits in the guest state. Otherwise
3861          * vmentry fails as it then expects bit 14 (BS) in pending debug
3862          * exceptions being set, but that's not correct for the guest debugging
3863          * case. */
3864         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3865                 vmx_set_interrupt_shadow(vcpu, 0);
3866
3867         /*
3868          * Loading guest fpu may have cleared host cr0.ts
3869          */
3870         vmcs_writel(HOST_CR0, read_cr0());
3871
3872         asm(
3873                 /* Store host registers */
3874                 "push %%"R"dx; push %%"R"bp;"
3875                 "push %%"R"cx \n\t"
3876                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3877                 "je 1f \n\t"
3878                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3879                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3880                 "1: \n\t"
3881                 /* Reload cr2 if changed */
3882                 "mov %c[cr2](%0), %%"R"ax \n\t"
3883                 "mov %%cr2, %%"R"dx \n\t"
3884                 "cmp %%"R"ax, %%"R"dx \n\t"
3885                 "je 2f \n\t"
3886                 "mov %%"R"ax, %%cr2 \n\t"
3887                 "2: \n\t"
3888                 /* Check if vmlaunch of vmresume is needed */
3889                 "cmpl $0, %c[launched](%0) \n\t"
3890                 /* Load guest registers.  Don't clobber flags. */
3891                 "mov %c[rax](%0), %%"R"ax \n\t"
3892                 "mov %c[rbx](%0), %%"R"bx \n\t"
3893                 "mov %c[rdx](%0), %%"R"dx \n\t"
3894                 "mov %c[rsi](%0), %%"R"si \n\t"
3895                 "mov %c[rdi](%0), %%"R"di \n\t"
3896                 "mov %c[rbp](%0), %%"R"bp \n\t"
3897 #ifdef CONFIG_X86_64
3898                 "mov %c[r8](%0),  %%r8  \n\t"
3899                 "mov %c[r9](%0),  %%r9  \n\t"
3900                 "mov %c[r10](%0), %%r10 \n\t"
3901                 "mov %c[r11](%0), %%r11 \n\t"
3902                 "mov %c[r12](%0), %%r12 \n\t"
3903                 "mov %c[r13](%0), %%r13 \n\t"
3904                 "mov %c[r14](%0), %%r14 \n\t"
3905                 "mov %c[r15](%0), %%r15 \n\t"
3906 #endif
3907                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3908
3909                 /* Enter guest mode */
3910                 "jne .Llaunched \n\t"
3911                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3912                 "jmp .Lkvm_vmx_return \n\t"
3913                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3914                 ".Lkvm_vmx_return: "
3915                 /* Save guest registers, load host registers, keep flags */
3916                 "xchg %0,     (%%"R"sp) \n\t"
3917                 "mov %%"R"ax, %c[rax](%0) \n\t"
3918                 "mov %%"R"bx, %c[rbx](%0) \n\t"
3919                 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3920                 "mov %%"R"dx, %c[rdx](%0) \n\t"
3921                 "mov %%"R"si, %c[rsi](%0) \n\t"
3922                 "mov %%"R"di, %c[rdi](%0) \n\t"
3923                 "mov %%"R"bp, %c[rbp](%0) \n\t"
3924 #ifdef CONFIG_X86_64
3925                 "mov %%r8,  %c[r8](%0) \n\t"
3926                 "mov %%r9,  %c[r9](%0) \n\t"
3927                 "mov %%r10, %c[r10](%0) \n\t"
3928                 "mov %%r11, %c[r11](%0) \n\t"
3929                 "mov %%r12, %c[r12](%0) \n\t"
3930                 "mov %%r13, %c[r13](%0) \n\t"
3931                 "mov %%r14, %c[r14](%0) \n\t"
3932                 "mov %%r15, %c[r15](%0) \n\t"
3933 #endif
3934                 "mov %%cr2, %%"R"ax   \n\t"
3935                 "mov %%"R"ax, %c[cr2](%0) \n\t"
3936
3937                 "pop  %%"R"bp; pop  %%"R"bp; pop  %%"R"dx \n\t"
3938                 "setbe %c[fail](%0) \n\t"
3939               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3940                 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3941                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3942                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3943                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3944                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3945                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3946                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3947                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3948                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3949                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3950 #ifdef CONFIG_X86_64
3951                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3952                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3953                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3954                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3955                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3956                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3957                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3958                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3959 #endif
3960                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3961               : "cc", "memory"
3962                 , R"bx", R"di", R"si"
3963 #ifdef CONFIG_X86_64
3964                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3965 #endif
3966               );
3967
3968         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3969                                   | (1 << VCPU_EXREG_PDPTR));
3970         vcpu->arch.regs_dirty = 0;
3971
3972         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3973         if (vmx->rmode.irq.pending)
3974                 fixup_rmode_irq(vmx);
3975
3976         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3977         vmx->launched = 1;
3978
3979         vmx_complete_interrupts(vmx);
3980 }
3981
3982 #undef R
3983 #undef Q
3984
3985 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3986 {
3987         struct vcpu_vmx *vmx = to_vmx(vcpu);
3988
3989         if (vmx->vmcs) {
3990                 vcpu_clear(vmx);
3991                 free_vmcs(vmx->vmcs);
3992                 vmx->vmcs = NULL;
3993         }
3994 }
3995
3996 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3997 {
3998         struct vcpu_vmx *vmx = to_vmx(vcpu);
3999
4000         free_vpid(vmx);
4001         vmx_free_vmcs(vcpu);
4002         kfree(vmx->guest_msrs);
4003         kvm_vcpu_uninit(vcpu);
4004         kmem_cache_free(kvm_vcpu_cache, vmx);
4005 }
4006
4007 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
4008 {
4009         int err;
4010         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
4011         int cpu;
4012
4013         if (!vmx)
4014                 return ERR_PTR(-ENOMEM);
4015
4016         allocate_vpid(vmx);
4017
4018         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
4019         if (err)
4020                 goto free_vcpu;
4021
4022         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
4023         if (!vmx->guest_msrs) {
4024                 err = -ENOMEM;
4025                 goto uninit_vcpu;
4026         }
4027
4028         vmx->vmcs = alloc_vmcs();
4029         if (!vmx->vmcs)
4030                 goto free_msrs;
4031
4032         vmcs_clear(vmx->vmcs);
4033
4034         cpu = get_cpu();
4035         vmx_vcpu_load(&vmx->vcpu, cpu);
4036         err = vmx_vcpu_setup(vmx);
4037         vmx_vcpu_put(&vmx->vcpu);
4038         put_cpu();
4039         if (err)
4040                 goto free_vmcs;
4041         if (vm_need_virtualize_apic_accesses(kvm))
4042                 if (alloc_apic_access_page(kvm) != 0)
4043                         goto free_vmcs;
4044
4045         if (enable_ept) {
4046                 if (!kvm->arch.ept_identity_map_addr)
4047                         kvm->arch.ept_identity_map_addr =
4048                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
4049                 if (alloc_identity_pagetable(kvm) != 0)
4050                         goto free_vmcs;
4051         }
4052
4053         return &vmx->vcpu;
4054
4055 free_vmcs:
4056         free_vmcs(vmx->vmcs);
4057 free_msrs:
4058         kfree(vmx->guest_msrs);
4059 uninit_vcpu:
4060         kvm_vcpu_uninit(&vmx->vcpu);
4061 free_vcpu:
4062         free_vpid(vmx);
4063         kmem_cache_free(kvm_vcpu_cache, vmx);
4064         return ERR_PTR(err);
4065 }
4066
4067 static void __init vmx_check_processor_compat(void *rtn)
4068 {
4069         struct vmcs_config vmcs_conf;
4070
4071         *(int *)rtn = 0;
4072         if (setup_vmcs_config(&vmcs_conf) < 0)
4073                 *(int *)rtn = -EIO;
4074         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
4075                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
4076                                 smp_processor_id());
4077                 *(int *)rtn = -EIO;
4078         }
4079 }
4080
4081 static int get_ept_level(void)
4082 {
4083         return VMX_EPT_DEFAULT_GAW + 1;
4084 }
4085
4086 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
4087 {
4088         u64 ret;
4089
4090         /* For VT-d and EPT combination
4091          * 1. MMIO: always map as UC
4092          * 2. EPT with VT-d:
4093          *   a. VT-d without snooping control feature: can't guarantee the
4094          *      result, try to trust guest.
4095          *   b. VT-d with snooping control feature: snooping control feature of
4096          *      VT-d engine can guarantee the cache correctness. Just set it
4097          *      to WB to keep consistent with host. So the same as item 3.
4098          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
4099          *    consistent with host MTRR
4100          */
4101         if (is_mmio)
4102                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
4103         else if (vcpu->kvm->arch.iommu_domain &&
4104                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
4105                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
4106                       VMX_EPT_MT_EPTE_SHIFT;
4107         else
4108                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
4109                         | VMX_EPT_IPAT_BIT;
4110
4111         return ret;
4112 }
4113
4114 #define _ER(x) { EXIT_REASON_##x, #x }
4115
4116 static const struct trace_print_flags vmx_exit_reasons_str[] = {
4117         _ER(EXCEPTION_NMI),
4118         _ER(EXTERNAL_INTERRUPT),
4119         _ER(TRIPLE_FAULT),
4120         _ER(PENDING_INTERRUPT),
4121         _ER(NMI_WINDOW),
4122         _ER(TASK_SWITCH),
4123         _ER(CPUID),
4124         _ER(HLT),
4125         _ER(INVLPG),
4126         _ER(RDPMC),
4127         _ER(RDTSC),
4128         _ER(VMCALL),
4129         _ER(VMCLEAR),
4130         _ER(VMLAUNCH),
4131         _ER(VMPTRLD),
4132         _ER(VMPTRST),
4133         _ER(VMREAD),
4134         _ER(VMRESUME),
4135         _ER(VMWRITE),
4136         _ER(VMOFF),
4137         _ER(VMON),
4138         _ER(CR_ACCESS),
4139         _ER(DR_ACCESS),
4140         _ER(IO_INSTRUCTION),
4141         _ER(MSR_READ),
4142         _ER(MSR_WRITE),
4143         _ER(MWAIT_INSTRUCTION),
4144         _ER(MONITOR_INSTRUCTION),
4145         _ER(PAUSE_INSTRUCTION),
4146         _ER(MCE_DURING_VMENTRY),
4147         _ER(TPR_BELOW_THRESHOLD),
4148         _ER(APIC_ACCESS),
4149         _ER(EPT_VIOLATION),
4150         _ER(EPT_MISCONFIG),
4151         _ER(WBINVD),
4152         { -1, NULL }
4153 };
4154
4155 #undef _ER
4156
4157 static int vmx_get_lpage_level(void)
4158 {
4159         if (enable_ept && !cpu_has_vmx_ept_1g_page())
4160                 return PT_DIRECTORY_LEVEL;
4161         else
4162                 /* For shadow and EPT supported 1GB page */
4163                 return PT_PDPE_LEVEL;
4164 }
4165
4166 static inline u32 bit(int bitno)
4167 {
4168         return 1 << (bitno & 31);
4169 }
4170
4171 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
4172 {
4173         struct kvm_cpuid_entry2 *best;
4174         struct vcpu_vmx *vmx = to_vmx(vcpu);
4175         u32 exec_control;
4176
4177         vmx->rdtscp_enabled = false;
4178         if (vmx_rdtscp_supported()) {
4179                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
4180                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
4181                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
4182                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
4183                                 vmx->rdtscp_enabled = true;
4184                         else {
4185                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
4186                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
4187                                                 exec_control);
4188                         }
4189                 }
4190         }
4191 }
4192
4193 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
4194 {
4195 }
4196
4197 static struct kvm_x86_ops vmx_x86_ops = {
4198         .cpu_has_kvm_support = cpu_has_kvm_support,
4199         .disabled_by_bios = vmx_disabled_by_bios,
4200         .hardware_setup = hardware_setup,
4201         .hardware_unsetup = hardware_unsetup,
4202         .check_processor_compatibility = vmx_check_processor_compat,
4203         .hardware_enable = hardware_enable,
4204         .hardware_disable = hardware_disable,
4205         .cpu_has_accelerated_tpr = report_flexpriority,
4206
4207         .vcpu_create = vmx_create_vcpu,
4208         .vcpu_free = vmx_free_vcpu,
4209         .vcpu_reset = vmx_vcpu_reset,
4210
4211         .prepare_guest_switch = vmx_save_host_state,
4212         .vcpu_load = vmx_vcpu_load,
4213         .vcpu_put = vmx_vcpu_put,
4214
4215         .set_guest_debug = set_guest_debug,
4216         .get_msr = vmx_get_msr,
4217         .set_msr = vmx_set_msr,
4218         .get_segment_base = vmx_get_segment_base,
4219         .get_segment = vmx_get_segment,
4220         .set_segment = vmx_set_segment,
4221         .get_cpl = vmx_get_cpl,
4222         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
4223         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
4224         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
4225         .set_cr0 = vmx_set_cr0,
4226         .set_cr3 = vmx_set_cr3,
4227         .set_cr4 = vmx_set_cr4,
4228         .set_efer = vmx_set_efer,
4229         .get_idt = vmx_get_idt,
4230         .set_idt = vmx_set_idt,
4231         .get_gdt = vmx_get_gdt,
4232         .set_gdt = vmx_set_gdt,
4233         .set_dr7 = vmx_set_dr7,
4234         .cache_reg = vmx_cache_reg,
4235         .get_rflags = vmx_get_rflags,
4236         .set_rflags = vmx_set_rflags,
4237         .fpu_activate = vmx_fpu_activate,
4238         .fpu_deactivate = vmx_fpu_deactivate,
4239
4240         .tlb_flush = vmx_flush_tlb,
4241
4242         .run = vmx_vcpu_run,
4243         .handle_exit = vmx_handle_exit,
4244         .skip_emulated_instruction = skip_emulated_instruction,
4245         .set_interrupt_shadow = vmx_set_interrupt_shadow,
4246         .get_interrupt_shadow = vmx_get_interrupt_shadow,
4247         .patch_hypercall = vmx_patch_hypercall,
4248         .set_irq = vmx_inject_irq,
4249         .set_nmi = vmx_inject_nmi,
4250         .queue_exception = vmx_queue_exception,
4251         .interrupt_allowed = vmx_interrupt_allowed,
4252         .nmi_allowed = vmx_nmi_allowed,
4253         .get_nmi_mask = vmx_get_nmi_mask,
4254         .set_nmi_mask = vmx_set_nmi_mask,
4255         .enable_nmi_window = enable_nmi_window,
4256         .enable_irq_window = enable_irq_window,
4257         .update_cr8_intercept = update_cr8_intercept,
4258
4259         .set_tss_addr = vmx_set_tss_addr,
4260         .get_tdp_level = get_ept_level,
4261         .get_mt_mask = vmx_get_mt_mask,
4262
4263         .exit_reasons_str = vmx_exit_reasons_str,
4264         .get_lpage_level = vmx_get_lpage_level,
4265
4266         .cpuid_update = vmx_cpuid_update,
4267
4268         .rdtscp_supported = vmx_rdtscp_supported,
4269
4270         .set_supported_cpuid = vmx_set_supported_cpuid,
4271 };
4272
4273 static int __init vmx_init(void)
4274 {
4275         int r, i;
4276
4277         rdmsrl_safe(MSR_EFER, &host_efer);
4278
4279         for (i = 0; i < NR_VMX_MSR; ++i)
4280                 kvm_define_shared_msr(i, vmx_msr_index[i]);
4281
4282         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
4283         if (!vmx_io_bitmap_a)
4284                 return -ENOMEM;
4285
4286         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
4287         if (!vmx_io_bitmap_b) {
4288                 r = -ENOMEM;
4289                 goto out;
4290         }
4291
4292         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
4293         if (!vmx_msr_bitmap_legacy) {
4294                 r = -ENOMEM;
4295                 goto out1;
4296         }
4297
4298         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
4299         if (!vmx_msr_bitmap_longmode) {
4300                 r = -ENOMEM;
4301                 goto out2;
4302         }
4303
4304         /*
4305          * Allow direct access to the PC debug port (it is often used for I/O
4306          * delays, but the vmexits simply slow things down).
4307          */
4308         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
4309         clear_bit(0x80, vmx_io_bitmap_a);
4310
4311         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
4312
4313         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
4314         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
4315
4316         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
4317
4318         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
4319                      __alignof__(struct vcpu_vmx), THIS_MODULE);
4320         if (r)
4321                 goto out3;
4322
4323         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
4324         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
4325         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
4326         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
4327         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
4328         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
4329
4330         if (enable_ept) {
4331                 bypass_guest_pf = 0;
4332                 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4333                         VMX_EPT_WRITABLE_MASK);
4334                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4335                                 VMX_EPT_EXECUTABLE_MASK);
4336                 kvm_enable_tdp();
4337         } else
4338                 kvm_disable_tdp();
4339
4340         if (bypass_guest_pf)
4341                 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4342
4343         return 0;
4344
4345 out3:
4346         free_page((unsigned long)vmx_msr_bitmap_longmode);
4347 out2:
4348         free_page((unsigned long)vmx_msr_bitmap_legacy);
4349 out1:
4350         free_page((unsigned long)vmx_io_bitmap_b);
4351 out:
4352         free_page((unsigned long)vmx_io_bitmap_a);
4353         return r;
4354 }
4355
4356 static void __exit vmx_exit(void)
4357 {
4358         free_page((unsigned long)vmx_msr_bitmap_legacy);
4359         free_page((unsigned long)vmx_msr_bitmap_longmode);
4360         free_page((unsigned long)vmx_io_bitmap_b);
4361         free_page((unsigned long)vmx_io_bitmap_a);
4362
4363         kvm_exit();
4364 }
4365
4366 module_init(vmx_init)
4367 module_exit(vmx_exit)