arch/x86/kvm/vmx.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * This module enables machines with Intel VT-x extensions to run virtual
   5  * machines without emulation or binary translation.
   6  *
   7  * Copyright (C) 2006 Qumranet, Inc.
   8  * Copyright 2010 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Avi Kivity   <avi@qumranet.com>
  12  *   Yaniv Kamay  <yaniv@qumranet.com>
  13  *
  14  * This work is licensed under the terms of the GNU GPL, version 2.  See
  15  * the COPYING file in the top-level directory.
  16  *
  17  */
  18
  19 #include "irq.h"
  20 #include "mmu.h"
  21
  22 #include <linux/kvm_host.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/mm.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/moduleparam.h>
  29 #include <linux/ftrace_event.h>
  30 #include <linux/slab.h>
  31 #include <linux/tboot.h>
  32 #include "kvm_cache_regs.h"
  33 #include "x86.h"
  34
  35 #include <asm/io.h>
  36 #include <asm/desc.h>
  37 #include <asm/vmx.h>
  38 #include <asm/virtext.h>
  39 #include <asm/mce.h>
  40 #include <asm/i387.h>
  41 #include <asm/xcr.h>
  42 #include <asm/perf_event.h>
  43
  44 #include "trace.h"
  45
  46 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  47 #define __ex_clear(x, reg) \
  48         ____kvm_handle_fault_on_reboot(x, "xor " reg " , " reg)
  49
  50 MODULE_AUTHOR("Qumranet");
  51 MODULE_LICENSE("GPL");
  52
  53 static int __read_mostly enable_vpid = 1;
  54 module_param_named(vpid, enable_vpid, bool, 0444);
  55
  56 static int __read_mostly flexpriority_enabled = 1;
  57 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
  58
  59 static int __read_mostly enable_ept = 1;
  60 module_param_named(ept, enable_ept, bool, S_IRUGO);
  61
  62 static int __read_mostly enable_unrestricted_guest = 1;
  63 module_param_named(unrestricted_guest,
  64                         enable_unrestricted_guest, bool, S_IRUGO);
  65
  66 static int __read_mostly emulate_invalid_guest_state = 0;
  67 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
  68
  69 static int __read_mostly vmm_exclusive = 1;
  70 module_param(vmm_exclusive, bool, S_IRUGO);
  71
  72 static int __read_mostly yield_on_hlt = 1;
  73 module_param(yield_on_hlt, bool, S_IRUGO);
  74
  75 static int __read_mostly fasteoi = 1;
  76 module_param(fasteoi, bool, S_IRUGO);
  77
  78 /*
  79  * If nested=1, nested virtualization is supported, i.e., guests may use
  80  * VMX and be a hypervisor for its own guests. If nested=0, guests may not
  81  * use VMX instructions.
  82  */
  83 static int __read_mostly nested = 0;
  84 module_param(nested, bool, S_IRUGO);
  85
  86 #define KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST                           \
  87         (X86_CR0_WP | X86_CR0_NE | X86_CR0_NW | X86_CR0_CD)
  88 #define KVM_GUEST_CR0_MASK                                              \
  89         (KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  90 #define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST                         \
  91         (X86_CR0_WP | X86_CR0_NE)
  92 #define KVM_VM_CR0_ALWAYS_ON                                            \
  93         (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | X86_CR0_PG | X86_CR0_PE)
  94 #define KVM_CR4_GUEST_OWNED_BITS                                      \
  95         (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR      \
  96          | X86_CR4_OSXMMEXCPT)
  97
  98 #define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
  99 #define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
 100
 101 #define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
 102
 103 /*
 104  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 105  * ple_gap:    upper bound on the amount of time between two successive
 106  *             executions of PAUSE in a loop. Also indicate if ple enabled.
 107  *             According to test, this time is usually smaller than 128 cycles.
 108  * ple_window: upper bound on the amount of time a guest is allowed to execute
 109  *             in a PAUSE loop. Tests indicate that most spinlocks are held for
 110  *             less than 2^12 cycles
 111  * Time is measured based on a counter that runs at the same rate as the TSC,
 112  * refer SDM volume 3b section 21.6.13 & 22.1.3.
 113  */
 114 #define KVM_VMX_DEFAULT_PLE_GAP    128
 115 #define KVM_VMX_DEFAULT_PLE_WINDOW 4096
 116 static int ple_gap = KVM_VMX_DEFAULT_PLE_GAP;
 117 module_param(ple_gap, int, S_IRUGO);
 118
 119 static int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
 120 module_param(ple_window, int, S_IRUGO);
 121
 122 #define NR_AUTOLOAD_MSRS 8
 123 #define VMCS02_POOL_SIZE 1
 124
 125 struct vmcs {
 126         u32 revision_id;
 127         u32 abort;
 128         char data[0];
 129 };
 130
 131 /*
 132  * Track a VMCS that may be loaded on a certain CPU. If it is (cpu!=-1), also
 133  * remember whether it was VMLAUNCHed, and maintain a linked list of all VMCSs
 134  * loaded on this CPU (so we can clear them if the CPU goes down).
 135  */
 136 struct loaded_vmcs {
 137         struct vmcs *vmcs;
 138         int cpu;
 139         int launched;
 140         struct list_head loaded_vmcss_on_cpu_link;
 141 };
 142
 143 struct shared_msr_entry {
 144         unsigned index;
 145         u64 data;
 146         u64 mask;
 147 };
 148
 149 /*
 150  * struct vmcs12 describes the state that our guest hypervisor (L1) keeps for a
 151  * single nested guest (L2), hence the name vmcs12. Any VMX implementation has
 152  * a VMCS structure, and vmcs12 is our emulated VMX's VMCS. This structure is
 153  * stored in guest memory specified by VMPTRLD, but is opaque to the guest,
 154  * which must access it using VMREAD/VMWRITE/VMCLEAR instructions.
 155  * More than one of these structures may exist, if L1 runs multiple L2 guests.
 156  * nested_vmx_run() will use the data here to build a vmcs02: a VMCS for the
 157  * underlying hardware which will be used to run L2.
 158  * This structure is packed to ensure that its layout is identical across
 159  * machines (necessary for live migration).
 160  * If there are changes in this struct, VMCS12_REVISION must be changed.
 161  */
 162 typedef u64 natural_width;
 163 struct __packed vmcs12 {
 164         /* According to the Intel spec, a VMCS region must start with the
 165          * following two fields. Then follow implementation-specific data.
 166          */
 167         u32 revision_id;
 168         u32 abort;
 169
 170         u32 launch_state; /* set to 0 by VMCLEAR, to 1 by VMLAUNCH */
 171         u32 padding[7]; /* room for future expansion */
 172
 173         u64 io_bitmap_a;
 174         u64 io_bitmap_b;
 175         u64 msr_bitmap;
 176         u64 vm_exit_msr_store_addr;
 177         u64 vm_exit_msr_load_addr;
 178         u64 vm_entry_msr_load_addr;
 179         u64 tsc_offset;
 180         u64 virtual_apic_page_addr;
 181         u64 apic_access_addr;
 182         u64 ept_pointer;
 183         u64 guest_physical_address;
 184         u64 vmcs_link_pointer;
 185         u64 guest_ia32_debugctl;
 186         u64 guest_ia32_pat;
 187         u64 guest_ia32_efer;
 188         u64 guest_ia32_perf_global_ctrl;
 189         u64 guest_pdptr0;
 190         u64 guest_pdptr1;
 191         u64 guest_pdptr2;
 192         u64 guest_pdptr3;
 193         u64 host_ia32_pat;
 194         u64 host_ia32_efer;
 195         u64 host_ia32_perf_global_ctrl;
 196         u64 padding64[8]; /* room for future expansion */
 197         /*
 198          * To allow migration of L1 (complete with its L2 guests) between
 199          * machines of different natural widths (32 or 64 bit), we cannot have
 200          * unsigned long fields with no explict size. We use u64 (aliased
 201          * natural_width) instead. Luckily, x86 is little-endian.
 202          */
 203         natural_width cr0_guest_host_mask;
 204         natural_width cr4_guest_host_mask;
 205         natural_width cr0_read_shadow;
 206         natural_width cr4_read_shadow;
 207         natural_width cr3_target_value0;
 208         natural_width cr3_target_value1;
 209         natural_width cr3_target_value2;
 210         natural_width cr3_target_value3;
 211         natural_width exit_qualification;
 212         natural_width guest_linear_address;
 213         natural_width guest_cr0;
 214         natural_width guest_cr3;
 215         natural_width guest_cr4;
 216         natural_width guest_es_base;
 217         natural_width guest_cs_base;
 218         natural_width guest_ss_base;
 219         natural_width guest_ds_base;
 220         natural_width guest_fs_base;
 221         natural_width guest_gs_base;
 222         natural_width guest_ldtr_base;
 223         natural_width guest_tr_base;
 224         natural_width guest_gdtr_base;
 225         natural_width guest_idtr_base;
 226         natural_width guest_dr7;
 227         natural_width guest_rsp;
 228         natural_width guest_rip;
 229         natural_width guest_rflags;
 230         natural_width guest_pending_dbg_exceptions;
 231         natural_width guest_sysenter_esp;
 232         natural_width guest_sysenter_eip;
 233         natural_width host_cr0;
 234         natural_width host_cr3;
 235         natural_width host_cr4;
 236         natural_width host_fs_base;
 237         natural_width host_gs_base;
 238         natural_width host_tr_base;
 239         natural_width host_gdtr_base;
 240         natural_width host_idtr_base;
 241         natural_width host_ia32_sysenter_esp;
 242         natural_width host_ia32_sysenter_eip;
 243         natural_width host_rsp;
 244         natural_width host_rip;
 245         natural_width paddingl[8]; /* room for future expansion */
 246         u32 pin_based_vm_exec_control;
 247         u32 cpu_based_vm_exec_control;
 248         u32 exception_bitmap;
 249         u32 page_fault_error_code_mask;
 250         u32 page_fault_error_code_match;
 251         u32 cr3_target_count;
 252         u32 vm_exit_controls;
 253         u32 vm_exit_msr_store_count;
 254         u32 vm_exit_msr_load_count;
 255         u32 vm_entry_controls;
 256         u32 vm_entry_msr_load_count;
 257         u32 vm_entry_intr_info_field;
 258         u32 vm_entry_exception_error_code;
 259         u32 vm_entry_instruction_len;
 260         u32 tpr_threshold;
 261         u32 secondary_vm_exec_control;
 262         u32 vm_instruction_error;
 263         u32 vm_exit_reason;
 264         u32 vm_exit_intr_info;
 265         u32 vm_exit_intr_error_code;
 266         u32 idt_vectoring_info_field;
 267         u32 idt_vectoring_error_code;
 268         u32 vm_exit_instruction_len;
 269         u32 vmx_instruction_info;
 270         u32 guest_es_limit;
 271         u32 guest_cs_limit;
 272         u32 guest_ss_limit;
 273         u32 guest_ds_limit;
 274         u32 guest_fs_limit;
 275         u32 guest_gs_limit;
 276         u32 guest_ldtr_limit;
 277         u32 guest_tr_limit;
 278         u32 guest_gdtr_limit;
 279         u32 guest_idtr_limit;
 280         u32 guest_es_ar_bytes;
 281         u32 guest_cs_ar_bytes;
 282         u32 guest_ss_ar_bytes;
 283         u32 guest_ds_ar_bytes;
 284         u32 guest_fs_ar_bytes;
 285         u32 guest_gs_ar_bytes;
 286         u32 guest_ldtr_ar_bytes;
 287         u32 guest_tr_ar_bytes;
 288         u32 guest_interruptibility_info;
 289         u32 guest_activity_state;
 290         u32 guest_sysenter_cs;
 291         u32 host_ia32_sysenter_cs;
 292         u32 padding32[8]; /* room for future expansion */
 293         u16 virtual_processor_id;
 294         u16 guest_es_selector;
 295         u16 guest_cs_selector;
 296         u16 guest_ss_selector;
 297         u16 guest_ds_selector;
 298         u16 guest_fs_selector;
 299         u16 guest_gs_selector;
 300         u16 guest_ldtr_selector;
 301         u16 guest_tr_selector;
 302         u16 host_es_selector;
 303         u16 host_cs_selector;
 304         u16 host_ss_selector;
 305         u16 host_ds_selector;
 306         u16 host_fs_selector;
 307         u16 host_gs_selector;
 308         u16 host_tr_selector;
 309 };
 310
 311 /*
 312  * VMCS12_REVISION is an arbitrary id that should be changed if the content or
 313  * layout of struct vmcs12 is changed. MSR_IA32_VMX_BASIC returns this id, and
 314  * VMPTRLD verifies that the VMCS region that L1 is loading contains this id.
 315  */
 316 #define VMCS12_REVISION 0x11e57ed0
 317
 318 /*
 319  * VMCS12_SIZE is the number of bytes L1 should allocate for the VMXON region
 320  * and any VMCS region. Although only sizeof(struct vmcs12) are used by the
 321  * current implementation, 4K are reserved to avoid future complications.
 322  */
 323 #define VMCS12_SIZE 0x1000
 324
 325 /* Used to remember the last vmcs02 used for some recently used vmcs12s */
 326 struct vmcs02_list {
 327         struct list_head list;
 328         gpa_t vmptr;
 329         struct loaded_vmcs vmcs02;
 330 };
 331
 332 /*
 333  * The nested_vmx structure is part of vcpu_vmx, and holds information we need
 334  * for correct emulation of VMX (i.e., nested VMX) on this vcpu.
 335  */
 336 struct nested_vmx {
 337         /* Has the level1 guest done vmxon? */
 338         bool vmxon;
 339
 340         /* The guest-physical address of the current VMCS L1 keeps for L2 */
 341         gpa_t current_vmptr;
 342         /* The host-usable pointer to the above */
 343         struct page *current_vmcs12_page;
 344         struct vmcs12 *current_vmcs12;
 345
 346         /* vmcs02_list cache of VMCSs recently used to run L2 guests */
 347         struct list_head vmcs02_pool;
 348         int vmcs02_num;
 349         u64 vmcs01_tsc_offset;
 350         /* L2 must run next, and mustn't decide to exit to L1. */
 351         bool nested_run_pending;
 352         /*
 353          * Guest pages referred to in vmcs02 with host-physical pointers, so
 354          * we must keep them pinned while L2 runs.
 355          */
 356         struct page *apic_access_page;
 357 };
 358
 359 struct vcpu_vmx {
 360         struct kvm_vcpu       vcpu;
 361         unsigned long         host_rsp;
 362         u8                    fail;
 363         u8                    cpl;
 364         bool                  nmi_known_unmasked;
 365         u32                   exit_intr_info;
 366         u32                   idt_vectoring_info;
 367         ulong                 rflags;
 368         struct shared_msr_entry *guest_msrs;
 369         int                   nmsrs;
 370         int                   save_nmsrs;
 371 #ifdef CONFIG_X86_64
 372         u64                   msr_host_kernel_gs_base;
 373         u64                   msr_guest_kernel_gs_base;
 374 #endif
 375         /*
 376          * loaded_vmcs points to the VMCS currently used in this vcpu. For a
 377          * non-nested (L1) guest, it always points to vmcs01. For a nested
 378          * guest (L2), it points to a different VMCS.
 379          */
 380         struct loaded_vmcs    vmcs01;
 381         struct loaded_vmcs   *loaded_vmcs;
 382         bool                  __launched; /* temporary, used in vmx_vcpu_run */
 383         struct msr_autoload {
 384                 unsigned nr;
 385                 struct vmx_msr_entry guest[NR_AUTOLOAD_MSRS];
 386                 struct vmx_msr_entry host[NR_AUTOLOAD_MSRS];
 387         } msr_autoload;
 388         struct {
 389                 int           loaded;
 390                 u16           fs_sel, gs_sel, ldt_sel;
 391                 int           gs_ldt_reload_needed;
 392                 int           fs_reload_needed;
 393         } host_state;
 394         struct {
 395                 int vm86_active;
 396                 ulong save_rflags;
 397                 struct kvm_save_segment {
 398                         u16 selector;
 399                         unsigned long base;
 400                         u32 limit;
 401                         u32 ar;
 402                 } tr, es, ds, fs, gs;
 403         } rmode;
 404         struct {
 405                 u32 bitmask; /* 4 bits per segment (1 bit per field) */
 406                 struct kvm_save_segment seg[8];
 407         } segment_cache;
 408         int vpid;
 409         bool emulation_required;
 410
 411         /* Support for vnmi-less CPUs */
 412         int soft_vnmi_blocked;
 413         ktime_t entry_time;
 414         s64 vnmi_blocked_time;
 415         u32 exit_reason;
 416
 417         bool rdtscp_enabled;
 418
 419         /* Support for a guest hypervisor (nested VMX) */
 420         struct nested_vmx nested;
 421 };
 422
 423 enum segment_cache_field {
 424         SEG_FIELD_SEL = 0,
 425         SEG_FIELD_BASE = 1,
 426         SEG_FIELD_LIMIT = 2,
 427         SEG_FIELD_AR = 3,
 428
 429         SEG_FIELD_NR = 4
 430 };
 431
 432 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
 433 {
 434         return container_of(vcpu, struct vcpu_vmx, vcpu);
 435 }
 436
 437 #define VMCS12_OFFSET(x) offsetof(struct vmcs12, x)
 438 #define FIELD(number, name)     [number] = VMCS12_OFFSET(name)
 439 #define FIELD64(number, name)   [number] = VMCS12_OFFSET(name), \
 440                                 [number##_HIGH] = VMCS12_OFFSET(name)+4
 441
 442 static unsigned short vmcs_field_to_offset_table[] = {
 443         FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
 444         FIELD(GUEST_ES_SELECTOR, guest_es_selector),
 445         FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
 446         FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
 447         FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
 448         FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
 449         FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
 450         FIELD(GUEST_LDTR_SELECTOR, guest_ldtr_selector),
 451         FIELD(GUEST_TR_SELECTOR, guest_tr_selector),
 452         FIELD(HOST_ES_SELECTOR, host_es_selector),
 453         FIELD(HOST_CS_SELECTOR, host_cs_selector),
 454         FIELD(HOST_SS_SELECTOR, host_ss_selector),
 455         FIELD(HOST_DS_SELECTOR, host_ds_selector),
 456         FIELD(HOST_FS_SELECTOR, host_fs_selector),
 457         FIELD(HOST_GS_SELECTOR, host_gs_selector),
 458         FIELD(HOST_TR_SELECTOR, host_tr_selector),
 459         FIELD64(IO_BITMAP_A, io_bitmap_a),
 460         FIELD64(IO_BITMAP_B, io_bitmap_b),
 461         FIELD64(MSR_BITMAP, msr_bitmap),
 462         FIELD64(VM_EXIT_MSR_STORE_ADDR, vm_exit_msr_store_addr),
 463         FIELD64(VM_EXIT_MSR_LOAD_ADDR, vm_exit_msr_load_addr),
 464         FIELD64(VM_ENTRY_MSR_LOAD_ADDR, vm_entry_msr_load_addr),
 465         FIELD64(TSC_OFFSET, tsc_offset),
 466         FIELD64(VIRTUAL_APIC_PAGE_ADDR, virtual_apic_page_addr),
 467         FIELD64(APIC_ACCESS_ADDR, apic_access_addr),
 468         FIELD64(EPT_POINTER, ept_pointer),
 469         FIELD64(GUEST_PHYSICAL_ADDRESS, guest_physical_address),
 470         FIELD64(VMCS_LINK_POINTER, vmcs_link_pointer),
 471         FIELD64(GUEST_IA32_DEBUGCTL, guest_ia32_debugctl),
 472         FIELD64(GUEST_IA32_PAT, guest_ia32_pat),
 473         FIELD64(GUEST_IA32_EFER, guest_ia32_efer),
 474         FIELD64(GUEST_IA32_PERF_GLOBAL_CTRL, guest_ia32_perf_global_ctrl),
 475         FIELD64(GUEST_PDPTR0, guest_pdptr0),
 476         FIELD64(GUEST_PDPTR1, guest_pdptr1),
 477         FIELD64(GUEST_PDPTR2, guest_pdptr2),
 478         FIELD64(GUEST_PDPTR3, guest_pdptr3),
 479         FIELD64(HOST_IA32_PAT, host_ia32_pat),
 480         FIELD64(HOST_IA32_EFER, host_ia32_efer),
 481         FIELD64(HOST_IA32_PERF_GLOBAL_CTRL, host_ia32_perf_global_ctrl),
 482         FIELD(PIN_BASED_VM_EXEC_CONTROL, pin_based_vm_exec_control),
 483         FIELD(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control),
 484         FIELD(EXCEPTION_BITMAP, exception_bitmap),
 485         FIELD(PAGE_FAULT_ERROR_CODE_MASK, page_fault_error_code_mask),
 486         FIELD(PAGE_FAULT_ERROR_CODE_MATCH, page_fault_error_code_match),
 487         FIELD(CR3_TARGET_COUNT, cr3_target_count),
 488         FIELD(VM_EXIT_CONTROLS, vm_exit_controls),
 489         FIELD(VM_EXIT_MSR_STORE_COUNT, vm_exit_msr_store_count),
 490         FIELD(VM_EXIT_MSR_LOAD_COUNT, vm_exit_msr_load_count),
 491         FIELD(VM_ENTRY_CONTROLS, vm_entry_controls),
 492         FIELD(VM_ENTRY_MSR_LOAD_COUNT, vm_entry_msr_load_count),
 493         FIELD(VM_ENTRY_INTR_INFO_FIELD, vm_entry_intr_info_field),
 494         FIELD(VM_ENTRY_EXCEPTION_ERROR_CODE, vm_entry_exception_error_code),
 495         FIELD(VM_ENTRY_INSTRUCTION_LEN, vm_entry_instruction_len),
 496         FIELD(TPR_THRESHOLD, tpr_threshold),
 497         FIELD(SECONDARY_VM_EXEC_CONTROL, secondary_vm_exec_control),
 498         FIELD(VM_INSTRUCTION_ERROR, vm_instruction_error),
 499         FIELD(VM_EXIT_REASON, vm_exit_reason),
 500         FIELD(VM_EXIT_INTR_INFO, vm_exit_intr_info),
 501         FIELD(VM_EXIT_INTR_ERROR_CODE, vm_exit_intr_error_code),
 502         FIELD(IDT_VECTORING_INFO_FIELD, idt_vectoring_info_field),
 503         FIELD(IDT_VECTORING_ERROR_CODE, idt_vectoring_error_code),
 504         FIELD(VM_EXIT_INSTRUCTION_LEN, vm_exit_instruction_len),
 505         FIELD(VMX_INSTRUCTION_INFO, vmx_instruction_info),
 506         FIELD(GUEST_ES_LIMIT, guest_es_limit),
 507         FIELD(GUEST_CS_LIMIT, guest_cs_limit),
 508         FIELD(GUEST_SS_LIMIT, guest_ss_limit),
 509         FIELD(GUEST_DS_LIMIT, guest_ds_limit),
 510         FIELD(GUEST_FS_LIMIT, guest_fs_limit),
 511         FIELD(GUEST_GS_LIMIT, guest_gs_limit),
 512         FIELD(GUEST_LDTR_LIMIT, guest_ldtr_limit),
 513         FIELD(GUEST_TR_LIMIT, guest_tr_limit),
 514         FIELD(GUEST_GDTR_LIMIT, guest_gdtr_limit),
 515         FIELD(GUEST_IDTR_LIMIT, guest_idtr_limit),
 516         FIELD(GUEST_ES_AR_BYTES, guest_es_ar_bytes),
 517         FIELD(GUEST_CS_AR_BYTES, guest_cs_ar_bytes),
 518         FIELD(GUEST_SS_AR_BYTES, guest_ss_ar_bytes),
 519         FIELD(GUEST_DS_AR_BYTES, guest_ds_ar_bytes),
 520         FIELD(GUEST_FS_AR_BYTES, guest_fs_ar_bytes),
 521         FIELD(GUEST_GS_AR_BYTES, guest_gs_ar_bytes),
 522         FIELD(GUEST_LDTR_AR_BYTES, guest_ldtr_ar_bytes),
 523         FIELD(GUEST_TR_AR_BYTES, guest_tr_ar_bytes),
 524         FIELD(GUEST_INTERRUPTIBILITY_INFO, guest_interruptibility_info),
 525         FIELD(GUEST_ACTIVITY_STATE, guest_activity_state),
 526         FIELD(GUEST_SYSENTER_CS, guest_sysenter_cs),
 527         FIELD(HOST_IA32_SYSENTER_CS, host_ia32_sysenter_cs),
 528         FIELD(CR0_GUEST_HOST_MASK, cr0_guest_host_mask),
 529         FIELD(CR4_GUEST_HOST_MASK, cr4_guest_host_mask),
 530         FIELD(CR0_READ_SHADOW, cr0_read_shadow),
 531         FIELD(CR4_READ_SHADOW, cr4_read_shadow),
 532         FIELD(CR3_TARGET_VALUE0, cr3_target_value0),
 533         FIELD(CR3_TARGET_VALUE1, cr3_target_value1),
 534         FIELD(CR3_TARGET_VALUE2, cr3_target_value2),
 535         FIELD(CR3_TARGET_VALUE3, cr3_target_value3),
 536         FIELD(EXIT_QUALIFICATION, exit_qualification),
 537         FIELD(GUEST_LINEAR_ADDRESS, guest_linear_address),
 538         FIELD(GUEST_CR0, guest_cr0),
 539         FIELD(GUEST_CR3, guest_cr3),
 540         FIELD(GUEST_CR4, guest_cr4),
 541         FIELD(GUEST_ES_BASE, guest_es_base),
 542         FIELD(GUEST_CS_BASE, guest_cs_base),
 543         FIELD(GUEST_SS_BASE, guest_ss_base),
 544         FIELD(GUEST_DS_BASE, guest_ds_base),
 545         FIELD(GUEST_FS_BASE, guest_fs_base),
 546         FIELD(GUEST_GS_BASE, guest_gs_base),
 547         FIELD(GUEST_LDTR_BASE, guest_ldtr_base),
 548         FIELD(GUEST_TR_BASE, guest_tr_base),
 549         FIELD(GUEST_GDTR_BASE, guest_gdtr_base),
 550         FIELD(GUEST_IDTR_BASE, guest_idtr_base),
 551         FIELD(GUEST_DR7, guest_dr7),
 552         FIELD(GUEST_RSP, guest_rsp),
 553         FIELD(GUEST_RIP, guest_rip),
 554         FIELD(GUEST_RFLAGS, guest_rflags),
 555         FIELD(GUEST_PENDING_DBG_EXCEPTIONS, guest_pending_dbg_exceptions),
 556         FIELD(GUEST_SYSENTER_ESP, guest_sysenter_esp),
 557         FIELD(GUEST_SYSENTER_EIP, guest_sysenter_eip),
 558         FIELD(HOST_CR0, host_cr0),
 559         FIELD(HOST_CR3, host_cr3),
 560         FIELD(HOST_CR4, host_cr4),
 561         FIELD(HOST_FS_BASE, host_fs_base),
 562         FIELD(HOST_GS_BASE, host_gs_base),
 563         FIELD(HOST_TR_BASE, host_tr_base),
 564         FIELD(HOST_GDTR_BASE, host_gdtr_base),
 565         FIELD(HOST_IDTR_BASE, host_idtr_base),
 566         FIELD(HOST_IA32_SYSENTER_ESP, host_ia32_sysenter_esp),
 567         FIELD(HOST_IA32_SYSENTER_EIP, host_ia32_sysenter_eip),
 568         FIELD(HOST_RSP, host_rsp),
 569         FIELD(HOST_RIP, host_rip),
 570 };
 571 static const int max_vmcs_field = ARRAY_SIZE(vmcs_field_to_offset_table);
 572
 573 static inline short vmcs_field_to_offset(unsigned long field)
 574 {
 575         if (field >= max_vmcs_field || vmcs_field_to_offset_table[field] == 0)
 576                 return -1;
 577         return vmcs_field_to_offset_table[field];
 578 }
 579
 580 static inline struct vmcs12 *get_vmcs12(struct kvm_vcpu *vcpu)
 581 {
 582         return to_vmx(vcpu)->nested.current_vmcs12;
 583 }
 584
 585 static struct page *nested_get_page(struct kvm_vcpu *vcpu, gpa_t addr)
 586 {
 587         struct page *page = gfn_to_page(vcpu->kvm, addr >> PAGE_SHIFT);
 588         if (is_error_page(page)) {
 589                 kvm_release_page_clean(page);
 590                 return NULL;
 591         }
 592         return page;
 593 }
 594
 595 static void nested_release_page(struct page *page)
 596 {
 597         kvm_release_page_dirty(page);
 598 }
 599
 600 static void nested_release_page_clean(struct page *page)
 601 {
 602         kvm_release_page_clean(page);
 603 }
 604
 605 static u64 construct_eptp(unsigned long root_hpa);
 606 static void kvm_cpu_vmxon(u64 addr);
 607 static void kvm_cpu_vmxoff(void);
 608 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3);
 609 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr);
 610
 611 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
 612 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
 613 /*
 614  * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
 615  * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
 616  */
 617 static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
 618 static DEFINE_PER_CPU(struct desc_ptr, host_gdt);
 619
 620 static unsigned long *vmx_io_bitmap_a;
 621 static unsigned long *vmx_io_bitmap_b;
 622 static unsigned long *vmx_msr_bitmap_legacy;
 623 static unsigned long *vmx_msr_bitmap_longmode;
 624
 625 static bool cpu_has_load_ia32_efer;
 626 static bool cpu_has_load_perf_global_ctrl;
 627
 628 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
 629 static DEFINE_SPINLOCK(vmx_vpid_lock);
 630
 631 static struct vmcs_config {
 632         int size;
 633         int order;
 634         u32 revision_id;
 635         u32 pin_based_exec_ctrl;
 636         u32 cpu_based_exec_ctrl;
 637         u32 cpu_based_2nd_exec_ctrl;
 638         u32 vmexit_ctrl;
 639         u32 vmentry_ctrl;
 640 } vmcs_config;
 641
 642 static struct vmx_capability {
 643         u32 ept;
 644         u32 vpid;
 645 } vmx_capability;
 646
 647 #define VMX_SEGMENT_FIELD(seg)                                  \
 648         [VCPU_SREG_##seg] = {                                   \
 649                 .selector = GUEST_##seg##_SELECTOR,             \
 650                 .base = GUEST_##seg##_BASE,                     \
 651                 .limit = GUEST_##seg##_LIMIT,                   \
 652                 .ar_bytes = GUEST_##seg##_AR_BYTES,             \
 653         }
 654
 655 static struct kvm_vmx_segment_field {
 656         unsigned selector;
 657         unsigned base;
 658         unsigned limit;
 659         unsigned ar_bytes;
 660 } kvm_vmx_segment_fields[] = {
 661         VMX_SEGMENT_FIELD(CS),
 662         VMX_SEGMENT_FIELD(DS),
 663         VMX_SEGMENT_FIELD(ES),
 664         VMX_SEGMENT_FIELD(FS),
 665         VMX_SEGMENT_FIELD(GS),
 666         VMX_SEGMENT_FIELD(SS),
 667         VMX_SEGMENT_FIELD(TR),
 668         VMX_SEGMENT_FIELD(LDTR),
 669 };
 670
 671 static u64 host_efer;
 672
 673 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
 674
 675 /*
 676  * Keep MSR_STAR at the end, as setup_msrs() will try to optimize it
 677  * away by decrementing the array size.
 678  */
 679 static const u32 vmx_msr_index[] = {
 680 #ifdef CONFIG_X86_64
 681         MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
 682 #endif
 683         MSR_EFER, MSR_TSC_AUX, MSR_STAR,
 684 };
 685 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
 686
 687 static inline bool is_page_fault(u32 intr_info)
 688 {
 689         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 690                              INTR_INFO_VALID_MASK)) ==
 691                 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
 692 }
 693
 694 static inline bool is_no_device(u32 intr_info)
 695 {
 696         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 697                              INTR_INFO_VALID_MASK)) ==
 698                 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
 699 }
 700
 701 static inline bool is_invalid_opcode(u32 intr_info)
 702 {
 703         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 704                              INTR_INFO_VALID_MASK)) ==
 705                 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
 706 }
 707
 708 static inline bool is_external_interrupt(u32 intr_info)
 709 {
 710         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 711                 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
 712 }
 713
 714 static inline bool is_machine_check(u32 intr_info)
 715 {
 716         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
 717                              INTR_INFO_VALID_MASK)) ==
 718                 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
 719 }
 720
 721 static inline bool cpu_has_vmx_msr_bitmap(void)
 722 {
 723         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
 724 }
 725
 726 static inline bool cpu_has_vmx_tpr_shadow(void)
 727 {
 728         return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
 729 }
 730
 731 static inline bool vm_need_tpr_shadow(struct kvm *kvm)
 732 {
 733         return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
 734 }
 735
 736 static inline bool cpu_has_secondary_exec_ctrls(void)
 737 {
 738         return vmcs_config.cpu_based_exec_ctrl &
 739                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
 740 }
 741
 742 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
 743 {
 744         return vmcs_config.cpu_based_2nd_exec_ctrl &
 745                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
 746 }
 747
 748 static inline bool cpu_has_vmx_flexpriority(void)
 749 {
 750         return cpu_has_vmx_tpr_shadow() &&
 751                 cpu_has_vmx_virtualize_apic_accesses();
 752 }
 753
 754 static inline bool cpu_has_vmx_ept_execute_only(void)
 755 {
 756         return vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT;
 757 }
 758
 759 static inline bool cpu_has_vmx_eptp_uncacheable(void)
 760 {
 761         return vmx_capability.ept & VMX_EPTP_UC_BIT;
 762 }
 763
 764 static inline bool cpu_has_vmx_eptp_writeback(void)
 765 {
 766         return vmx_capability.ept & VMX_EPTP_WB_BIT;
 767 }
 768
 769 static inline bool cpu_has_vmx_ept_2m_page(void)
 770 {
 771         return vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT;
 772 }
 773
 774 static inline bool cpu_has_vmx_ept_1g_page(void)
 775 {
 776         return vmx_capability.ept & VMX_EPT_1GB_PAGE_BIT;
 777 }
 778
 779 static inline bool cpu_has_vmx_ept_4levels(void)
 780 {
 781         return vmx_capability.ept & VMX_EPT_PAGE_WALK_4_BIT;
 782 }
 783
 784 static inline bool cpu_has_vmx_invept_individual_addr(void)
 785 {
 786         return vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT;
 787 }
 788
 789 static inline bool cpu_has_vmx_invept_context(void)
 790 {
 791         return vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT;
 792 }
 793
 794 static inline bool cpu_has_vmx_invept_global(void)
 795 {
 796         return vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT;
 797 }
 798
 799 static inline bool cpu_has_vmx_invvpid_single(void)
 800 {
 801         return vmx_capability.vpid & VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT;
 802 }
 803
 804 static inline bool cpu_has_vmx_invvpid_global(void)
 805 {
 806         return vmx_capability.vpid & VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT;
 807 }
 808
 809 static inline bool cpu_has_vmx_ept(void)
 810 {
 811         return vmcs_config.cpu_based_2nd_exec_ctrl &
 812                 SECONDARY_EXEC_ENABLE_EPT;
 813 }
 814
 815 static inline bool cpu_has_vmx_unrestricted_guest(void)
 816 {
 817         return vmcs_config.cpu_based_2nd_exec_ctrl &
 818                 SECONDARY_EXEC_UNRESTRICTED_GUEST;
 819 }
 820
 821 static inline bool cpu_has_vmx_ple(void)
 822 {
 823         return vmcs_config.cpu_based_2nd_exec_ctrl &
 824                 SECONDARY_EXEC_PAUSE_LOOP_EXITING;
 825 }
 826
 827 static inline bool vm_need_virtualize_apic_accesses(struct kvm *kvm)
 828 {
 829         return flexpriority_enabled && irqchip_in_kernel(kvm);
 830 }
 831
 832 static inline bool cpu_has_vmx_vpid(void)
 833 {
 834         return vmcs_config.cpu_based_2nd_exec_ctrl &
 835                 SECONDARY_EXEC_ENABLE_VPID;
 836 }
 837
 838 static inline bool cpu_has_vmx_rdtscp(void)
 839 {
 840         return vmcs_config.cpu_based_2nd_exec_ctrl &
 841                 SECONDARY_EXEC_RDTSCP;
 842 }
 843
 844 static inline bool cpu_has_virtual_nmis(void)
 845 {
 846         return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
 847 }
 848
 849 static inline bool cpu_has_vmx_wbinvd_exit(void)
 850 {
 851         return vmcs_config.cpu_based_2nd_exec_ctrl &
 852                 SECONDARY_EXEC_WBINVD_EXITING;
 853 }
 854
 855 static inline bool report_flexpriority(void)
 856 {
 857         return flexpriority_enabled;
 858 }
 859
 860 static inline bool nested_cpu_has(struct vmcs12 *vmcs12, u32 bit)
 861 {
 862         return vmcs12->cpu_based_vm_exec_control & bit;
 863 }
 864
 865 static inline bool nested_cpu_has2(struct vmcs12 *vmcs12, u32 bit)
 866 {
 867         return (vmcs12->cpu_based_vm_exec_control &
 868                         CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) &&
 869                 (vmcs12->secondary_vm_exec_control & bit);
 870 }
 871
 872 static inline bool nested_cpu_has_virtual_nmis(struct vmcs12 *vmcs12,
 873         struct kvm_vcpu *vcpu)
 874 {
 875         return vmcs12->pin_based_vm_exec_control & PIN_BASED_VIRTUAL_NMIS;
 876 }
 877
 878 static inline bool is_exception(u32 intr_info)
 879 {
 880         return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
 881                 == (INTR_TYPE_HARD_EXCEPTION | INTR_INFO_VALID_MASK);
 882 }
 883
 884 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu);
 885 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
 886                         struct vmcs12 *vmcs12,
 887                         u32 reason, unsigned long qualification);
 888
 889 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
 890 {
 891         int i;
 892
 893         for (i = 0; i < vmx->nmsrs; ++i)
 894                 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
 895                         return i;
 896         return -1;
 897 }
 898
 899 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
 900 {
 901     struct {
 902         u64 vpid : 16;
 903         u64 rsvd : 48;
 904         u64 gva;
 905     } operand = { vpid, 0, gva };
 906
 907     asm volatile (__ex(ASM_VMX_INVVPID)
 908                   /* CF==1 or ZF==1 --> rc = -1 */
 909                   "; ja 1f ; ud2 ; 1:"
 910                   : : "a"(&operand), "c"(ext) : "cc", "memory");
 911 }
 912
 913 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
 914 {
 915         struct {
 916                 u64 eptp, gpa;
 917         } operand = {eptp, gpa};
 918
 919         asm volatile (__ex(ASM_VMX_INVEPT)
 920                         /* CF==1 or ZF==1 --> rc = -1 */
 921                         "; ja 1f ; ud2 ; 1:\n"
 922                         : : "a" (&operand), "c" (ext) : "cc", "memory");
 923 }
 924
 925 static struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
 926 {
 927         int i;
 928
 929         i = __find_msr_index(vmx, msr);
 930         if (i >= 0)
 931                 return &vmx->guest_msrs[i];
 932         return NULL;
 933 }
 934
 935 static void vmcs_clear(struct vmcs *vmcs)
 936 {
 937         u64 phys_addr = __pa(vmcs);
 938         u8 error;
 939
 940         asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
 941                       : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 942                       : "cc", "memory");
 943         if (error)
 944                 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
 945                        vmcs, phys_addr);
 946 }
 947
 948 static inline void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
 949 {
 950         vmcs_clear(loaded_vmcs->vmcs);
 951         loaded_vmcs->cpu = -1;
 952         loaded_vmcs->launched = 0;
 953 }
 954
 955 static void vmcs_load(struct vmcs *vmcs)
 956 {
 957         u64 phys_addr = __pa(vmcs);
 958         u8 error;
 959
 960         asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
 961                         : "=qm"(error) : "a"(&phys_addr), "m"(phys_addr)
 962                         : "cc", "memory");
 963         if (error)
 964                 printk(KERN_ERR "kvm: vmptrld %p/%llx failed\n",
 965                        vmcs, phys_addr);
 966 }
 967
 968 static void __loaded_vmcs_clear(void *arg)
 969 {
 970         struct loaded_vmcs *loaded_vmcs = arg;
 971         int cpu = raw_smp_processor_id();
 972
 973         if (loaded_vmcs->cpu != cpu)
 974                 return; /* vcpu migration can race with cpu offline */
 975         if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
 976                 per_cpu(current_vmcs, cpu) = NULL;
 977         list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
 978         loaded_vmcs_init(loaded_vmcs);
 979 }
 980
 981 static void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
 982 {
 983         if (loaded_vmcs->cpu != -1)
 984                 smp_call_function_single(
 985                         loaded_vmcs->cpu, __loaded_vmcs_clear, loaded_vmcs, 1);
 986 }
 987
 988 static inline void vpid_sync_vcpu_single(struct vcpu_vmx *vmx)
 989 {
 990         if (vmx->vpid == 0)
 991                 return;
 992
 993         if (cpu_has_vmx_invvpid_single())
 994                 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
 995 }
 996
 997 static inline void vpid_sync_vcpu_global(void)
 998 {
 999         if (cpu_has_vmx_invvpid_global())
1000                 __invvpid(VMX_VPID_EXTENT_ALL_CONTEXT, 0, 0);
1001 }
1002
1003 static inline void vpid_sync_context(struct vcpu_vmx *vmx)
1004 {
1005         if (cpu_has_vmx_invvpid_single())
1006                 vpid_sync_vcpu_single(vmx);
1007         else
1008                 vpid_sync_vcpu_global();
1009 }
1010
1011 static inline void ept_sync_global(void)
1012 {
1013         if (cpu_has_vmx_invept_global())
1014                 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
1015 }
1016
1017 static inline void ept_sync_context(u64 eptp)
1018 {
1019         if (enable_ept) {
1020                 if (cpu_has_vmx_invept_context())
1021                         __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
1022                 else
1023                         ept_sync_global();
1024         }
1025 }
1026
1027 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
1028 {
1029         if (enable_ept) {
1030                 if (cpu_has_vmx_invept_individual_addr())
1031                         __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
1032                                         eptp, gpa);
1033                 else
1034                         ept_sync_context(eptp);
1035         }
1036 }
1037
1038 static __always_inline unsigned long vmcs_readl(unsigned long field)
1039 {
1040         unsigned long value;
1041
1042         asm volatile (__ex_clear(ASM_VMX_VMREAD_RDX_RAX, "%0")
1043                       : "=a"(value) : "d"(field) : "cc");
1044         return value;
1045 }
1046
1047 static __always_inline u16 vmcs_read16(unsigned long field)
1048 {
1049         return vmcs_readl(field);
1050 }
1051
1052 static __always_inline u32 vmcs_read32(unsigned long field)
1053 {
1054         return vmcs_readl(field);
1055 }
1056
1057 static __always_inline u64 vmcs_read64(unsigned long field)
1058 {
1059 #ifdef CONFIG_X86_64
1060         return vmcs_readl(field);
1061 #else
1062         return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
1063 #endif
1064 }
1065
1066 static noinline void vmwrite_error(unsigned long field, unsigned long value)
1067 {
1068         printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
1069                field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
1070         dump_stack();
1071 }
1072
1073 static void vmcs_writel(unsigned long field, unsigned long value)
1074 {
1075         u8 error;
1076
1077         asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
1078                        : "=q"(error) : "a"(value), "d"(field) : "cc");
1079         if (unlikely(error))
1080                 vmwrite_error(field, value);
1081 }
1082
1083 static void vmcs_write16(unsigned long field, u16 value)
1084 {
1085         vmcs_writel(field, value);
1086 }
1087
1088 static void vmcs_write32(unsigned long field, u32 value)
1089 {
1090         vmcs_writel(field, value);
1091 }
1092
1093 static void vmcs_write64(unsigned long field, u64 value)
1094 {
1095         vmcs_writel(field, value);
1096 #ifndef CONFIG_X86_64
1097         asm volatile ("");
1098         vmcs_writel(field+1, value >> 32);
1099 #endif
1100 }
1101
1102 static void vmcs_clear_bits(unsigned long field, u32 mask)
1103 {
1104         vmcs_writel(field, vmcs_readl(field) & ~mask);
1105 }
1106
1107 static void vmcs_set_bits(unsigned long field, u32 mask)
1108 {
1109         vmcs_writel(field, vmcs_readl(field) | mask);
1110 }
1111
1112 static void vmx_segment_cache_clear(struct vcpu_vmx *vmx)
1113 {
1114         vmx->segment_cache.bitmask = 0;
1115 }
1116
1117 static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
1118                                        unsigned field)
1119 {
1120         bool ret;
1121         u32 mask = 1 << (seg * SEG_FIELD_NR + field);
1122
1123         if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
1124                 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
1125                 vmx->segment_cache.bitmask = 0;
1126         }
1127         ret = vmx->segment_cache.bitmask & mask;
1128         vmx->segment_cache.bitmask |= mask;
1129         return ret;
1130 }
1131
1132 static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
1133 {
1134         u16 *p = &vmx->segment_cache.seg[seg].selector;
1135
1136         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
1137                 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
1138         return *p;
1139 }
1140
1141 static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
1142 {
1143         ulong *p = &vmx->segment_cache.seg[seg].base;
1144
1145         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
1146                 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
1147         return *p;
1148 }
1149
1150 static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
1151 {
1152         u32 *p = &vmx->segment_cache.seg[seg].limit;
1153
1154         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
1155                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
1156         return *p;
1157 }
1158
1159 static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
1160 {
1161         u32 *p = &vmx->segment_cache.seg[seg].ar;
1162
1163         if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
1164                 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
1165         return *p;
1166 }
1167
1168 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
1169 {
1170         u32 eb;
1171
1172         eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
1173              (1u << NM_VECTOR) | (1u << DB_VECTOR);
1174         if ((vcpu->guest_debug &
1175              (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
1176             (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
1177                 eb |= 1u << BP_VECTOR;
1178         if (to_vmx(vcpu)->rmode.vm86_active)
1179                 eb = ~0;
1180         if (enable_ept)
1181                 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
1182         if (vcpu->fpu_active)
1183                 eb &= ~(1u << NM_VECTOR);
1184
1185         /* When we are running a nested L2 guest and L1 specified for it a
1186          * certain exception bitmap, we must trap the same exceptions and pass
1187          * them to L1. When running L2, we will only handle the exceptions
1188          * specified above if L1 did not want them.
1189          */
1190         if (is_guest_mode(vcpu))
1191                 eb |= get_vmcs12(vcpu)->exception_bitmap;
1192
1193         vmcs_write32(EXCEPTION_BITMAP, eb);
1194 }
1195
1196 static void clear_atomic_switch_msr_special(unsigned long entry,
1197                 unsigned long exit)
1198 {
1199         vmcs_clear_bits(VM_ENTRY_CONTROLS, entry);
1200         vmcs_clear_bits(VM_EXIT_CONTROLS, exit);
1201 }
1202
1203 static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
1204 {
1205         unsigned i;
1206         struct msr_autoload *m = &vmx->msr_autoload;
1207
1208         switch (msr) {
1209         case MSR_EFER:
1210                 if (cpu_has_load_ia32_efer) {
1211                         clear_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1212                                         VM_EXIT_LOAD_IA32_EFER);
1213                         return;
1214                 }
1215                 break;
1216         case MSR_CORE_PERF_GLOBAL_CTRL:
1217                 if (cpu_has_load_perf_global_ctrl) {
1218                         clear_atomic_switch_msr_special(
1219                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1220                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
1221                         return;
1222                 }
1223                 break;
1224         }
1225
1226         for (i = 0; i < m->nr; ++i)
1227                 if (m->guest[i].index == msr)
1228                         break;
1229
1230         if (i == m->nr)
1231                 return;
1232         --m->nr;
1233         m->guest[i] = m->guest[m->nr];
1234         m->host[i] = m->host[m->nr];
1235         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1236         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1237 }
1238
1239 static void add_atomic_switch_msr_special(unsigned long entry,
1240                 unsigned long exit, unsigned long guest_val_vmcs,
1241                 unsigned long host_val_vmcs, u64 guest_val, u64 host_val)
1242 {
1243         vmcs_write64(guest_val_vmcs, guest_val);
1244         vmcs_write64(host_val_vmcs, host_val);
1245         vmcs_set_bits(VM_ENTRY_CONTROLS, entry);
1246         vmcs_set_bits(VM_EXIT_CONTROLS, exit);
1247 }
1248
1249 static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
1250                                   u64 guest_val, u64 host_val)
1251 {
1252         unsigned i;
1253         struct msr_autoload *m = &vmx->msr_autoload;
1254
1255         switch (msr) {
1256         case MSR_EFER:
1257                 if (cpu_has_load_ia32_efer) {
1258                         add_atomic_switch_msr_special(VM_ENTRY_LOAD_IA32_EFER,
1259                                         VM_EXIT_LOAD_IA32_EFER,
1260                                         GUEST_IA32_EFER,
1261                                         HOST_IA32_EFER,
1262                                         guest_val, host_val);
1263                         return;
1264                 }
1265                 break;
1266         case MSR_CORE_PERF_GLOBAL_CTRL:
1267                 if (cpu_has_load_perf_global_ctrl) {
1268                         add_atomic_switch_msr_special(
1269                                         VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
1270                                         VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
1271                                         GUEST_IA32_PERF_GLOBAL_CTRL,
1272                                         HOST_IA32_PERF_GLOBAL_CTRL,
1273                                         guest_val, host_val);
1274                         return;
1275                 }
1276                 break;
1277         }
1278
1279         for (i = 0; i < m->nr; ++i)
1280                 if (m->guest[i].index == msr)
1281                         break;
1282
1283         if (i == NR_AUTOLOAD_MSRS) {
1284                 printk_once(KERN_WARNING"Not enough mst switch entries. "
1285                                 "Can't add msr %x\n", msr);
1286                 return;
1287         } else if (i == m->nr) {
1288                 ++m->nr;
1289                 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->nr);
1290                 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->nr);
1291         }
1292
1293         m->guest[i].index = msr;
1294         m->guest[i].value = guest_val;
1295         m->host[i].index = msr;
1296         m->host[i].value = host_val;
1297 }
1298
1299 static void reload_tss(void)
1300 {
1301         /*
1302          * VT restores TR but not its size.  Useless.
1303          */
1304         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1305         struct desc_struct *descs;
1306
1307         descs = (void *)gdt->address;
1308         descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
1309         load_TR_desc();
1310 }
1311
1312 static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
1313 {
1314         u64 guest_efer;
1315         u64 ignore_bits;
1316
1317         guest_efer = vmx->vcpu.arch.efer;
1318
1319         /*
1320          * NX is emulated; LMA and LME handled by hardware; SCE meaninless
1321          * outside long mode
1322          */
1323         ignore_bits = EFER_NX | EFER_SCE;
1324 #ifdef CONFIG_X86_64
1325         ignore_bits |= EFER_LMA | EFER_LME;
1326         /* SCE is meaningful only in long mode on Intel */
1327         if (guest_efer & EFER_LMA)
1328                 ignore_bits &= ~(u64)EFER_SCE;
1329 #endif
1330         guest_efer &= ~ignore_bits;
1331         guest_efer |= host_efer & ignore_bits;
1332         vmx->guest_msrs[efer_offset].data = guest_efer;
1333         vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
1334
1335         clear_atomic_switch_msr(vmx, MSR_EFER);
1336         /* On ept, can't emulate nx, and must switch nx atomically */
1337         if (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX)) {
1338                 guest_efer = vmx->vcpu.arch.efer;
1339                 if (!(guest_efer & EFER_LMA))
1340                         guest_efer &= ~EFER_LME;
1341                 add_atomic_switch_msr(vmx, MSR_EFER, guest_efer, host_efer);
1342                 return false;
1343         }
1344
1345         return true;
1346 }
1347
1348 static unsigned long segment_base(u16 selector)
1349 {
1350         struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1351         struct desc_struct *d;
1352         unsigned long table_base;
1353         unsigned long v;
1354
1355         if (!(selector & ~3))
1356                 return 0;
1357
1358         table_base = gdt->address;
1359
1360         if (selector & 4) {           /* from ldt */
1361                 u16 ldt_selector = kvm_read_ldt();
1362
1363                 if (!(ldt_selector & ~3))
1364                         return 0;
1365
1366                 table_base = segment_base(ldt_selector);
1367         }
1368         d = (struct desc_struct *)(table_base + (selector & ~7));
1369         v = get_desc_base(d);
1370 #ifdef CONFIG_X86_64
1371        if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
1372                v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
1373 #endif
1374         return v;
1375 }
1376
1377 static inline unsigned long kvm_read_tr_base(void)
1378 {
1379         u16 tr;
1380         asm("str %0" : "=g"(tr));
1381         return segment_base(tr);
1382 }
1383
1384 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
1385 {
1386         struct vcpu_vmx *vmx = to_vmx(vcpu);
1387         int i;
1388
1389         if (vmx->host_state.loaded)
1390                 return;
1391
1392         vmx->host_state.loaded = 1;
1393         /*
1394          * Set host fs and gs selectors.  Unfortunately, 22.2.3 does not
1395          * allow segment selectors with cpl > 0 or ti == 1.
1396          */
1397         vmx->host_state.ldt_sel = kvm_read_ldt();
1398         vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
1399         savesegment(fs, vmx->host_state.fs_sel);
1400         if (!(vmx->host_state.fs_sel & 7)) {
1401                 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
1402                 vmx->host_state.fs_reload_needed = 0;
1403         } else {
1404                 vmcs_write16(HOST_FS_SELECTOR, 0);
1405                 vmx->host_state.fs_reload_needed = 1;
1406         }
1407         savesegment(gs, vmx->host_state.gs_sel);
1408         if (!(vmx->host_state.gs_sel & 7))
1409                 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
1410         else {
1411                 vmcs_write16(HOST_GS_SELECTOR, 0);
1412                 vmx->host_state.gs_ldt_reload_needed = 1;
1413         }
1414
1415 #ifdef CONFIG_X86_64
1416         vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
1417         vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
1418 #else
1419         vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
1420         vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
1421 #endif
1422
1423 #ifdef CONFIG_X86_64
1424         rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1425         if (is_long_mode(&vmx->vcpu))
1426                 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1427 #endif
1428         for (i = 0; i < vmx->save_nmsrs; ++i)
1429                 kvm_set_shared_msr(vmx->guest_msrs[i].index,
1430                                    vmx->guest_msrs[i].data,
1431                                    vmx->guest_msrs[i].mask);
1432 }
1433
1434 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
1435 {
1436         if (!vmx->host_state.loaded)
1437                 return;
1438
1439         ++vmx->vcpu.stat.host_state_reload;
1440         vmx->host_state.loaded = 0;
1441 #ifdef CONFIG_X86_64
1442         if (is_long_mode(&vmx->vcpu))
1443                 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1444 #endif
1445         if (vmx->host_state.gs_ldt_reload_needed) {
1446                 kvm_load_ldt(vmx->host_state.ldt_sel);
1447 #ifdef CONFIG_X86_64
1448                 load_gs_index(vmx->host_state.gs_sel);
1449 #else
1450                 loadsegment(gs, vmx->host_state.gs_sel);
1451 #endif
1452         }
1453         if (vmx->host_state.fs_reload_needed)
1454                 loadsegment(fs, vmx->host_state.fs_sel);
1455         reload_tss();
1456 #ifdef CONFIG_X86_64
1457         wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
1458 #endif
1459         if (__thread_has_fpu(current))
1460                 clts();
1461         load_gdt(&__get_cpu_var(host_gdt));
1462 }
1463
1464 static void vmx_load_host_state(struct vcpu_vmx *vmx)
1465 {
1466         preempt_disable();
1467         __vmx_load_host_state(vmx);
1468         preempt_enable();
1469 }
1470
1471 /*
1472  * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1473  * vcpu mutex is already taken.
1474  */
1475 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1476 {
1477         struct vcpu_vmx *vmx = to_vmx(vcpu);
1478         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1479
1480         if (!vmm_exclusive)
1481                 kvm_cpu_vmxon(phys_addr);
1482         else if (vmx->loaded_vmcs->cpu != cpu)
1483                 loaded_vmcs_clear(vmx->loaded_vmcs);
1484
1485         if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1486                 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1487                 vmcs_load(vmx->loaded_vmcs->vmcs);
1488         }
1489
1490         if (vmx->loaded_vmcs->cpu != cpu) {
1491                 struct desc_ptr *gdt = &__get_cpu_var(host_gdt);
1492                 unsigned long sysenter_esp;
1493
1494                 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
1495                 local_irq_disable();
1496                 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1497                          &per_cpu(loaded_vmcss_on_cpu, cpu));
1498                 local_irq_enable();
1499
1500                 /*
1501                  * Linux uses per-cpu TSS and GDT, so set these when switching
1502                  * processors.
1503                  */
1504                 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
1505                 vmcs_writel(HOST_GDTR_BASE, gdt->address);   /* 22.2.4 */
1506
1507                 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1508                 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
1509                 vmx->loaded_vmcs->cpu = cpu;
1510         }
1511 }
1512
1513 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
1514 {
1515         __vmx_load_host_state(to_vmx(vcpu));
1516         if (!vmm_exclusive) {
1517                 __loaded_vmcs_clear(to_vmx(vcpu)->loaded_vmcs);
1518                 vcpu->cpu = -1;
1519                 kvm_cpu_vmxoff();
1520         }
1521 }
1522
1523 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
1524 {
1525         ulong cr0;
1526
1527         if (vcpu->fpu_active)
1528                 return;
1529         vcpu->fpu_active = 1;
1530         cr0 = vmcs_readl(GUEST_CR0);
1531         cr0 &= ~(X86_CR0_TS | X86_CR0_MP);
1532         cr0 |= kvm_read_cr0_bits(vcpu, X86_CR0_TS | X86_CR0_MP);
1533         vmcs_writel(GUEST_CR0, cr0);
1534         update_exception_bitmap(vcpu);
1535         vcpu->arch.cr0_guest_owned_bits = X86_CR0_TS;
1536         if (is_guest_mode(vcpu))
1537                 vcpu->arch.cr0_guest_owned_bits &=
1538                         ~get_vmcs12(vcpu)->cr0_guest_host_mask;
1539         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1540 }
1541
1542 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1543
1544 /*
1545  * Return the cr0 value that a nested guest would read. This is a combination
1546  * of the real cr0 used to run the guest (guest_cr0), and the bits shadowed by
1547  * its hypervisor (cr0_read_shadow).
1548  */
1549 static inline unsigned long nested_read_cr0(struct vmcs12 *fields)
1550 {
1551         return (fields->guest_cr0 & ~fields->cr0_guest_host_mask) |
1552                 (fields->cr0_read_shadow & fields->cr0_guest_host_mask);
1553 }
1554 static inline unsigned long nested_read_cr4(struct vmcs12 *fields)
1555 {
1556         return (fields->guest_cr4 & ~fields->cr4_guest_host_mask) |
1557                 (fields->cr4_read_shadow & fields->cr4_guest_host_mask);
1558 }
1559
1560 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
1561 {
1562         /* Note that there is no vcpu->fpu_active = 0 here. The caller must
1563          * set this *before* calling this function.
1564          */
1565         vmx_decache_cr0_guest_bits(vcpu);
1566         vmcs_set_bits(GUEST_CR0, X86_CR0_TS | X86_CR0_MP);
1567         update_exception_bitmap(vcpu);
1568         vcpu->arch.cr0_guest_owned_bits = 0;
1569         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
1570         if (is_guest_mode(vcpu)) {
1571                 /*
1572                  * L1's specified read shadow might not contain the TS bit,
1573                  * so now that we turned on shadowing of this bit, we need to
1574                  * set this bit of the shadow. Like in nested_vmx_run we need
1575                  * nested_read_cr0(vmcs12), but vmcs12->guest_cr0 is not yet
1576                  * up-to-date here because we just decached cr0.TS (and we'll
1577                  * only update vmcs12->guest_cr0 on nested exit).
1578                  */
1579                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1580                 vmcs12->guest_cr0 = (vmcs12->guest_cr0 & ~X86_CR0_TS) |
1581                         (vcpu->arch.cr0 & X86_CR0_TS);
1582                 vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
1583         } else
1584                 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
1585 }
1586
1587 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
1588 {
1589         unsigned long rflags, save_rflags;
1590
1591         if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1592                 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1593                 rflags = vmcs_readl(GUEST_RFLAGS);
1594                 if (to_vmx(vcpu)->rmode.vm86_active) {
1595                         rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1596                         save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1597                         rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1598                 }
1599                 to_vmx(vcpu)->rflags = rflags;
1600         }
1601         return to_vmx(vcpu)->rflags;
1602 }
1603
1604 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1605 {
1606         __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1607         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
1608         to_vmx(vcpu)->rflags = rflags;
1609         if (to_vmx(vcpu)->rmode.vm86_active) {
1610                 to_vmx(vcpu)->rmode.save_rflags = rflags;
1611                 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1612         }
1613         vmcs_writel(GUEST_RFLAGS, rflags);
1614 }
1615
1616 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1617 {
1618         u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1619         int ret = 0;
1620
1621         if (interruptibility & GUEST_INTR_STATE_STI)
1622                 ret |= KVM_X86_SHADOW_INT_STI;
1623         if (interruptibility & GUEST_INTR_STATE_MOV_SS)
1624                 ret |= KVM_X86_SHADOW_INT_MOV_SS;
1625
1626         return ret & mask;
1627 }
1628
1629 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
1630 {
1631         u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1632         u32 interruptibility = interruptibility_old;
1633
1634         interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1635
1636         if (mask & KVM_X86_SHADOW_INT_MOV_SS)
1637                 interruptibility |= GUEST_INTR_STATE_MOV_SS;
1638         else if (mask & KVM_X86_SHADOW_INT_STI)
1639                 interruptibility |= GUEST_INTR_STATE_STI;
1640
1641         if ((interruptibility != interruptibility_old))
1642                 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1643 }
1644
1645 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1646 {
1647         unsigned long rip;
1648
1649         rip = kvm_rip_read(vcpu);
1650         rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
1651         kvm_rip_write(vcpu, rip);
1652
1653         /* skipping an emulated instruction also counts */
1654         vmx_set_interrupt_shadow(vcpu, 0);
1655 }
1656
1657 static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1658 {
1659         /* Ensure that we clear the HLT state in the VMCS.  We don't need to
1660          * explicitly skip the instruction because if the HLT state is set, then
1661          * the instruction is already executing and RIP has already been
1662          * advanced. */
1663         if (!yield_on_hlt &&
1664             vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1665                 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1666 }
1667
1668 /*
1669  * KVM wants to inject page-faults which it got to the guest. This function
1670  * checks whether in a nested guest, we need to inject them to L1 or L2.
1671  * This function assumes it is called with the exit reason in vmcs02 being
1672  * a #PF exception (this is the only case in which KVM injects a #PF when L2
1673  * is running).
1674  */
1675 static int nested_pf_handled(struct kvm_vcpu *vcpu)
1676 {
1677         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1678
1679         /* TODO: also check PFEC_MATCH/MASK, not just EB.PF. */
1680         if (!(vmcs12->exception_bitmap & (1u << PF_VECTOR)))
1681                 return 0;
1682
1683         nested_vmx_vmexit(vcpu);
1684         return 1;
1685 }
1686
1687 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
1688                                 bool has_error_code, u32 error_code,
1689                                 bool reinject)
1690 {
1691         struct vcpu_vmx *vmx = to_vmx(vcpu);
1692         u32 intr_info = nr | INTR_INFO_VALID_MASK;
1693
1694         if (nr == PF_VECTOR && is_guest_mode(vcpu) &&
1695                 nested_pf_handled(vcpu))
1696                 return;
1697
1698         if (has_error_code) {
1699                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
1700                 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1701         }
1702
1703         if (vmx->rmode.vm86_active) {
1704                 int inc_eip = 0;
1705                 if (kvm_exception_is_soft(nr))
1706                         inc_eip = vcpu->arch.event_exit_inst_len;
1707                 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
1708                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
1709                 return;
1710         }
1711
1712         if (kvm_exception_is_soft(nr)) {
1713                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1714                              vmx->vcpu.arch.event_exit_inst_len);
1715                 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1716         } else
1717                 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1718
1719         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
1720         vmx_clear_hlt(vcpu);
1721 }
1722
1723 static bool vmx_rdtscp_supported(void)
1724 {
1725         return cpu_has_vmx_rdtscp();
1726 }
1727
1728 /*
1729  * Swap MSR entry in host/guest MSR entry array.
1730  */
1731 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
1732 {
1733         struct shared_msr_entry tmp;
1734
1735         tmp = vmx->guest_msrs[to];
1736         vmx->guest_msrs[to] = vmx->guest_msrs[from];
1737         vmx->guest_msrs[from] = tmp;
1738 }
1739
1740 /*
1741  * Set up the vmcs to automatically save and restore system
1742  * msrs.  Don't touch the 64-bit msrs if the guest is in legacy
1743  * mode, as fiddling with msrs is very expensive.
1744  */
1745 static void setup_msrs(struct vcpu_vmx *vmx)
1746 {
1747         int save_nmsrs, index;
1748         unsigned long *msr_bitmap;
1749
1750         vmx_load_host_state(vmx);
1751         save_nmsrs = 0;
1752 #ifdef CONFIG_X86_64
1753         if (is_long_mode(&vmx->vcpu)) {
1754                 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1755                 if (index >= 0)
1756                         move_msr_up(vmx, index, save_nmsrs++);
1757                 index = __find_msr_index(vmx, MSR_LSTAR);
1758                 if (index >= 0)
1759                         move_msr_up(vmx, index, save_nmsrs++);
1760                 index = __find_msr_index(vmx, MSR_CSTAR);
1761                 if (index >= 0)
1762                         move_msr_up(vmx, index, save_nmsrs++);
1763                 index = __find_msr_index(vmx, MSR_TSC_AUX);
1764                 if (index >= 0 && vmx->rdtscp_enabled)
1765                         move_msr_up(vmx, index, save_nmsrs++);
1766                 /*
1767                  * MSR_STAR is only needed on long mode guests, and only
1768                  * if efer.sce is enabled.
1769                  */
1770                 index = __find_msr_index(vmx, MSR_STAR);
1771                 if ((index >= 0) && (vmx->vcpu.arch.efer & EFER_SCE))
1772                         move_msr_up(vmx, index, save_nmsrs++);
1773         }
1774 #endif
1775         index = __find_msr_index(vmx, MSR_EFER);
1776         if (index >= 0 && update_transition_efer(vmx, index))
1777                 move_msr_up(vmx, index, save_nmsrs++);
1778
1779         vmx->save_nmsrs = save_nmsrs;
1780
1781         if (cpu_has_vmx_msr_bitmap()) {
1782                 if (is_long_mode(&vmx->vcpu))
1783                         msr_bitmap = vmx_msr_bitmap_longmode;
1784                 else
1785                         msr_bitmap = vmx_msr_bitmap_legacy;
1786
1787                 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
1788         }
1789 }
1790
1791 /*
1792  * reads and returns guest's timestamp counter "register"
1793  * guest_tsc = host_tsc + tsc_offset    -- 21.3
1794  */
1795 static u64 guest_read_tsc(void)
1796 {
1797         u64 host_tsc, tsc_offset;
1798
1799         rdtscll(host_tsc);
1800         tsc_offset = vmcs_read64(TSC_OFFSET);
1801         return host_tsc + tsc_offset;
1802 }
1803
1804 /*
1805  * Like guest_read_tsc, but always returns L1's notion of the timestamp
1806  * counter, even if a nested guest (L2) is currently running.
1807  */
1808 u64 vmx_read_l1_tsc(struct kvm_vcpu *vcpu)
1809 {
1810         u64 host_tsc, tsc_offset;
1811
1812         rdtscll(host_tsc);
1813         tsc_offset = is_guest_mode(vcpu) ?
1814                 to_vmx(vcpu)->nested.vmcs01_tsc_offset :
1815                 vmcs_read64(TSC_OFFSET);
1816         return host_tsc + tsc_offset;
1817 }
1818
1819 /*
1820  * Empty call-back. Needs to be implemented when VMX enables the SET_TSC_KHZ
1821  * ioctl. In this case the call-back should update internal vmx state to make
1822  * the changes effective.
1823  */
1824 static void vmx_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz)
1825 {
1826         /* Nothing to do here */
1827 }
1828
1829 /*
1830  * writes 'offset' into guest's timestamp counter offset register
1831  */
1832 static void vmx_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1833 {
1834         if (is_guest_mode(vcpu)) {
1835                 /*
1836                  * We're here if L1 chose not to trap WRMSR to TSC. According
1837                  * to the spec, this should set L1's TSC; The offset that L1
1838                  * set for L2 remains unchanged, and still needs to be added
1839                  * to the newly set TSC to get L2's TSC.
1840                  */
1841                 struct vmcs12 *vmcs12;
1842                 to_vmx(vcpu)->nested.vmcs01_tsc_offset = offset;
1843                 /* recalculate vmcs02.TSC_OFFSET: */
1844                 vmcs12 = get_vmcs12(vcpu);
1845                 vmcs_write64(TSC_OFFSET, offset +
1846                         (nested_cpu_has(vmcs12, CPU_BASED_USE_TSC_OFFSETING) ?
1847                          vmcs12->tsc_offset : 0));
1848         } else {
1849                 vmcs_write64(TSC_OFFSET, offset);
1850         }
1851 }
1852
1853 static void vmx_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
1854 {
1855         u64 offset = vmcs_read64(TSC_OFFSET);
1856         vmcs_write64(TSC_OFFSET, offset + adjustment);
1857         if (is_guest_mode(vcpu)) {
1858                 /* Even when running L2, the adjustment needs to apply to L1 */
1859                 to_vmx(vcpu)->nested.vmcs01_tsc_offset += adjustment;
1860         }
1861 }
1862
1863 static u64 vmx_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
1864 {
1865         return target_tsc - native_read_tsc();
1866 }
1867
1868 static bool guest_cpuid_has_vmx(struct kvm_vcpu *vcpu)
1869 {
1870         struct kvm_cpuid_entry2 *best = kvm_find_cpuid_entry(vcpu, 1, 0);
1871         return best && (best->ecx & (1 << (X86_FEATURE_VMX & 31)));
1872 }
1873
1874 /*
1875  * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1876  * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1877  * all guests if the "nested" module option is off, and can also be disabled
1878  * for a single guest by disabling its VMX cpuid bit.
1879  */
1880 static inline bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
1881 {
1882         return nested && guest_cpuid_has_vmx(vcpu);
1883 }
1884
1885 /*
1886  * nested_vmx_setup_ctls_msrs() sets up variables containing the values to be
1887  * returned for the various VMX controls MSRs when nested VMX is enabled.
1888  * The same values should also be used to verify that vmcs12 control fields are
1889  * valid during nested entry from L1 to L2.
1890  * Each of these control msrs has a low and high 32-bit half: A low bit is on
1891  * if the corresponding bit in the (32-bit) control field *must* be on, and a
1892  * bit in the high half is on if the corresponding bit in the control field
1893  * may be on. See also vmx_control_verify().
1894  * TODO: allow these variables to be modified (downgraded) by module options
1895  * or other means.
1896  */
1897 static u32 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high;
1898 static u32 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high;
1899 static u32 nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high;
1900 static u32 nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high;
1901 static u32 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high;
1902 static __init void nested_vmx_setup_ctls_msrs(void)
1903 {
1904         /*
1905          * Note that as a general rule, the high half of the MSRs (bits in
1906          * the control fields which may be 1) should be initialized by the
1907          * intersection of the underlying hardware's MSR (i.e., features which
1908          * can be supported) and the list of features we want to expose -
1909          * because they are known to be properly supported in our code.
1910          * Also, usually, the low half of the MSRs (bits which must be 1) can
1911          * be set to 0, meaning that L1 may turn off any of these bits. The
1912          * reason is that if one of these bits is necessary, it will appear
1913          * in vmcs01 and prepare_vmcs02, when it bitwise-or's the control
1914          * fields of vmcs01 and vmcs02, will turn these bits off - and
1915          * nested_vmx_exit_handled() will not pass related exits to L1.
1916          * These rules have exceptions below.
1917          */
1918
1919         /* pin-based controls */
1920         /*
1921          * According to the Intel spec, if bit 55 of VMX_BASIC is off (as it is
1922          * in our case), bits 1, 2 and 4 (i.e., 0x16) must be 1 in this MSR.
1923          */
1924         nested_vmx_pinbased_ctls_low = 0x16 ;
1925         nested_vmx_pinbased_ctls_high = 0x16 |
1926                 PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING |
1927                 PIN_BASED_VIRTUAL_NMIS;
1928
1929         /* exit controls */
1930         nested_vmx_exit_ctls_low = 0;
1931         /* Note that guest use of VM_EXIT_ACK_INTR_ON_EXIT is not supported. */
1932 #ifdef CONFIG_X86_64
1933         nested_vmx_exit_ctls_high = VM_EXIT_HOST_ADDR_SPACE_SIZE;
1934 #else
1935         nested_vmx_exit_ctls_high = 0;
1936 #endif
1937
1938         /* entry controls */
1939         rdmsr(MSR_IA32_VMX_ENTRY_CTLS,
1940                 nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high);
1941         nested_vmx_entry_ctls_low = 0;
1942         nested_vmx_entry_ctls_high &=
1943                 VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_IA32E_MODE;
1944
1945         /* cpu-based controls */
1946         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS,
1947                 nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high);
1948         nested_vmx_procbased_ctls_low = 0;
1949         nested_vmx_procbased_ctls_high &=
1950                 CPU_BASED_VIRTUAL_INTR_PENDING | CPU_BASED_USE_TSC_OFFSETING |
1951                 CPU_BASED_HLT_EXITING | CPU_BASED_INVLPG_EXITING |
1952                 CPU_BASED_MWAIT_EXITING | CPU_BASED_CR3_LOAD_EXITING |
1953                 CPU_BASED_CR3_STORE_EXITING |
1954 #ifdef CONFIG_X86_64
1955                 CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING |
1956 #endif
1957                 CPU_BASED_MOV_DR_EXITING | CPU_BASED_UNCOND_IO_EXITING |
1958                 CPU_BASED_USE_IO_BITMAPS | CPU_BASED_MONITOR_EXITING |
1959                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1960         /*
1961          * We can allow some features even when not supported by the
1962          * hardware. For example, L1 can specify an MSR bitmap - and we
1963          * can use it to avoid exits to L1 - even when L0 runs L2
1964          * without MSR bitmaps.
1965          */
1966         nested_vmx_procbased_ctls_high |= CPU_BASED_USE_MSR_BITMAPS;
1967
1968         /* secondary cpu-based controls */
1969         rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2,
1970                 nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high);
1971         nested_vmx_secondary_ctls_low = 0;
1972         nested_vmx_secondary_ctls_high &=
1973                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
1974 }
1975
1976 static inline bool vmx_control_verify(u32 control, u32 low, u32 high)
1977 {
1978         /*
1979          * Bits 0 in high must be 0, and bits 1 in low must be 1.
1980          */
1981         return ((control & high) | low) == control;
1982 }
1983
1984 static inline u64 vmx_control_msr(u32 low, u32 high)
1985 {
1986         return low | ((u64)high << 32);
1987 }
1988
1989 /*
1990  * If we allow our guest to use VMX instructions (i.e., nested VMX), we should
1991  * also let it use VMX-specific MSRs.
1992  * vmx_get_vmx_msr() and vmx_set_vmx_msr() return 1 when we handled a
1993  * VMX-specific MSR, or 0 when we haven't (and the caller should handle it
1994  * like all other MSRs).
1995  */
1996 static int vmx_get_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
1997 {
1998         if (!nested_vmx_allowed(vcpu) && msr_index >= MSR_IA32_VMX_BASIC &&
1999                      msr_index <= MSR_IA32_VMX_TRUE_ENTRY_CTLS) {
2000                 /*
2001                  * According to the spec, processors which do not support VMX
2002                  * should throw a #GP(0) when VMX capability MSRs are read.
2003                  */
2004                 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
2005                 return 1;
2006         }
2007
2008         switch (msr_index) {
2009         case MSR_IA32_FEATURE_CONTROL:
2010                 *pdata = 0;
2011                 break;
2012         case MSR_IA32_VMX_BASIC:
2013                 /*
2014                  * This MSR reports some information about VMX support. We
2015                  * should return information about the VMX we emulate for the
2016                  * guest, and the VMCS structure we give it - not about the
2017                  * VMX support of the underlying hardware.
2018                  */
2019                 *pdata = VMCS12_REVISION |
2020                            ((u64)VMCS12_SIZE << VMX_BASIC_VMCS_SIZE_SHIFT) |
2021                            (VMX_BASIC_MEM_TYPE_WB << VMX_BASIC_MEM_TYPE_SHIFT);
2022                 break;
2023         case MSR_IA32_VMX_TRUE_PINBASED_CTLS:
2024         case MSR_IA32_VMX_PINBASED_CTLS:
2025                 *pdata = vmx_control_msr(nested_vmx_pinbased_ctls_low,
2026                                         nested_vmx_pinbased_ctls_high);
2027                 break;
2028         case MSR_IA32_VMX_TRUE_PROCBASED_CTLS:
2029         case MSR_IA32_VMX_PROCBASED_CTLS:
2030                 *pdata = vmx_control_msr(nested_vmx_procbased_ctls_low,
2031                                         nested_vmx_procbased_ctls_high);
2032                 break;
2033         case MSR_IA32_VMX_TRUE_EXIT_CTLS:
2034         case MSR_IA32_VMX_EXIT_CTLS:
2035                 *pdata = vmx_control_msr(nested_vmx_exit_ctls_low,
2036                                         nested_vmx_exit_ctls_high);
2037                 break;
2038         case MSR_IA32_VMX_TRUE_ENTRY_CTLS:
2039         case MSR_IA32_VMX_ENTRY_CTLS:
2040                 *pdata = vmx_control_msr(nested_vmx_entry_ctls_low,
2041                                         nested_vmx_entry_ctls_high);
2042                 break;
2043         case MSR_IA32_VMX_MISC:
2044                 *pdata = 0;
2045                 break;
2046         /*
2047          * These MSRs specify bits which the guest must keep fixed (on or off)
2048          * while L1 is in VMXON mode (in L1's root mode, or running an L2).
2049          * We picked the standard core2 setting.
2050          */
2051 #define VMXON_CR0_ALWAYSON      (X86_CR0_PE | X86_CR0_PG | X86_CR0_NE)
2052 #define VMXON_CR4_ALWAYSON      X86_CR4_VMXE
2053         case MSR_IA32_VMX_CR0_FIXED0:
2054                 *pdata = VMXON_CR0_ALWAYSON;
2055                 break;
2056         case MSR_IA32_VMX_CR0_FIXED1:
2057                 *pdata = -1ULL;
2058                 break;
2059         case MSR_IA32_VMX_CR4_FIXED0:
2060                 *pdata = VMXON_CR4_ALWAYSON;
2061                 break;
2062         case MSR_IA32_VMX_CR4_FIXED1:
2063                 *pdata = -1ULL;
2064                 break;
2065         case MSR_IA32_VMX_VMCS_ENUM:
2066                 *pdata = 0x1f;
2067                 break;
2068         case MSR_IA32_VMX_PROCBASED_CTLS2:
2069                 *pdata = vmx_control_msr(nested_vmx_secondary_ctls_low,
2070                                         nested_vmx_secondary_ctls_high);
2071                 break;
2072         case MSR_IA32_VMX_EPT_VPID_CAP:
2073                 /* Currently, no nested ept or nested vpid */
2074                 *pdata = 0;
2075                 break;
2076         default:
2077                 return 0;
2078         }
2079
2080         return 1;
2081 }
2082
2083 static int vmx_set_vmx_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2084 {
2085         if (!nested_vmx_allowed(vcpu))
2086                 return 0;
2087
2088         if (msr_index == MSR_IA32_FEATURE_CONTROL)
2089                 /* TODO: the right thing. */
2090                 return 1;
2091         /*
2092          * No need to treat VMX capability MSRs specially: If we don't handle
2093          * them, handle_wrmsr will #GP(0), which is correct (they are readonly)
2094          */
2095         return 0;
2096 }
2097
2098 /*
2099  * Reads an msr value (of 'msr_index') into 'pdata'.
2100  * Returns 0 on success, non-0 otherwise.
2101  * Assumes vcpu_load() was already called.
2102  */
2103 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
2104 {
2105         u64 data;
2106         struct shared_msr_entry *msr;
2107
2108         if (!pdata) {
2109                 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
2110                 return -EINVAL;
2111         }
2112
2113         switch (msr_index) {
2114 #ifdef CONFIG_X86_64
2115         case MSR_FS_BASE:
2116                 data = vmcs_readl(GUEST_FS_BASE);
2117                 break;
2118         case MSR_GS_BASE:
2119                 data = vmcs_readl(GUEST_GS_BASE);
2120                 break;
2121         case MSR_KERNEL_GS_BASE:
2122                 vmx_load_host_state(to_vmx(vcpu));
2123                 data = to_vmx(vcpu)->msr_guest_kernel_gs_base;
2124                 break;
2125 #endif
2126         case MSR_EFER:
2127                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2128         case MSR_IA32_TSC:
2129                 data = guest_read_tsc();
2130                 break;
2131         case MSR_IA32_SYSENTER_CS:
2132                 data = vmcs_read32(GUEST_SYSENTER_CS);
2133                 break;
2134         case MSR_IA32_SYSENTER_EIP:
2135                 data = vmcs_readl(GUEST_SYSENTER_EIP);
2136                 break;
2137         case MSR_IA32_SYSENTER_ESP:
2138                 data = vmcs_readl(GUEST_SYSENTER_ESP);
2139                 break;
2140         case MSR_TSC_AUX:
2141                 if (!to_vmx(vcpu)->rdtscp_enabled)
2142                         return 1;
2143                 /* Otherwise falls through */
2144         default:
2145                 vmx_load_host_state(to_vmx(vcpu));
2146                 if (vmx_get_vmx_msr(vcpu, msr_index, pdata))
2147                         return 0;
2148                 msr = find_msr_entry(to_vmx(vcpu), msr_index);
2149                 if (msr) {
2150                         vmx_load_host_state(to_vmx(vcpu));
2151                         data = msr->data;
2152                         break;
2153                 }
2154                 return kvm_get_msr_common(vcpu, msr_index, pdata);
2155         }
2156
2157         *pdata = data;
2158         return 0;
2159 }
2160
2161 /*
2162  * Writes msr value into into the appropriate "register".
2163  * Returns 0 on success, non-0 otherwise.
2164  * Assumes vcpu_load() was already called.
2165  */
2166 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
2167 {
2168         struct vcpu_vmx *vmx = to_vmx(vcpu);
2169         struct shared_msr_entry *msr;
2170         int ret = 0;
2171
2172         switch (msr_index) {
2173         case MSR_EFER:
2174                 vmx_load_host_state(vmx);
2175                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2176                 break;
2177 #ifdef CONFIG_X86_64
2178         case MSR_FS_BASE:
2179                 vmx_segment_cache_clear(vmx);
2180                 vmcs_writel(GUEST_FS_BASE, data);
2181                 break;
2182         case MSR_GS_BASE:
2183                 vmx_segment_cache_clear(vmx);
2184                 vmcs_writel(GUEST_GS_BASE, data);
2185                 break;
2186         case MSR_KERNEL_GS_BASE:
2187                 vmx_load_host_state(vmx);
2188                 vmx->msr_guest_kernel_gs_base = data;
2189                 break;
2190 #endif
2191         case MSR_IA32_SYSENTER_CS:
2192                 vmcs_write32(GUEST_SYSENTER_CS, data);
2193                 break;
2194         case MSR_IA32_SYSENTER_EIP:
2195                 vmcs_writel(GUEST_SYSENTER_EIP, data);
2196                 break;
2197         case MSR_IA32_SYSENTER_ESP:
2198                 vmcs_writel(GUEST_SYSENTER_ESP, data);
2199                 break;
2200         case MSR_IA32_TSC:
2201                 kvm_write_tsc(vcpu, data);
2202                 break;
2203         case MSR_IA32_CR_PAT:
2204                 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2205                         vmcs_write64(GUEST_IA32_PAT, data);
2206                         vcpu->arch.pat = data;
2207                         break;
2208                 }
2209                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2210                 break;
2211         case MSR_TSC_AUX:
2212                 if (!vmx->rdtscp_enabled)
2213                         return 1;
2214                 /* Check reserved bit, higher 32 bits should be zero */
2215                 if ((data >> 32) != 0)
2216                         return 1;
2217                 /* Otherwise falls through */
2218         default:
2219                 if (vmx_set_vmx_msr(vcpu, msr_index, data))
2220                         break;
2221                 msr = find_msr_entry(vmx, msr_index);
2222                 if (msr) {
2223                         vmx_load_host_state(vmx);
2224                         msr->data = data;
2225                         break;
2226                 }
2227                 ret = kvm_set_msr_common(vcpu, msr_index, data);
2228         }
2229
2230         return ret;
2231 }
2232
2233 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
2234 {
2235         __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
2236         switch (reg) {
2237         case VCPU_REGS_RSP:
2238                 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
2239                 break;
2240         case VCPU_REGS_RIP:
2241                 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
2242                 break;
2243         case VCPU_EXREG_PDPTR:
2244                 if (enable_ept)
2245                         ept_save_pdptrs(vcpu);
2246                 break;
2247         default:
2248                 break;
2249         }
2250 }
2251
2252 static void set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
2253 {
2254         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
2255                 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
2256         else
2257                 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2258
2259         update_exception_bitmap(vcpu);
2260 }
2261
2262 static __init int cpu_has_kvm_support(void)
2263 {
2264         return cpu_has_vmx();
2265 }
2266
2267 static __init int vmx_disabled_by_bios(void)
2268 {
2269         u64 msr;
2270
2271         rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
2272         if (msr & FEATURE_CONTROL_LOCKED) {
2273                 /* launched w/ TXT and VMX disabled */
2274                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2275                         && tboot_enabled())
2276                         return 1;
2277                 /* launched w/o TXT and VMX only enabled w/ TXT */
2278                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2279                         && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
2280                         && !tboot_enabled()) {
2281                         printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
2282                                 "activate TXT before enabling KVM\n");
2283                         return 1;
2284                 }
2285                 /* launched w/o TXT and VMX disabled */
2286                 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
2287                         && !tboot_enabled())
2288                         return 1;
2289         }
2290
2291         return 0;
2292 }
2293
2294 static void kvm_cpu_vmxon(u64 addr)
2295 {
2296         asm volatile (ASM_VMX_VMXON_RAX
2297                         : : "a"(&addr), "m"(addr)
2298                         : "memory", "cc");
2299 }
2300
2301 static int hardware_enable(void *garbage)
2302 {
2303         int cpu = raw_smp_processor_id();
2304         u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
2305         u64 old, test_bits;
2306
2307         if (read_cr4() & X86_CR4_VMXE)
2308                 return -EBUSY;
2309
2310         INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
2311         rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
2312
2313         test_bits = FEATURE_CONTROL_LOCKED;
2314         test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
2315         if (tboot_enabled())
2316                 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
2317
2318         if ((old & test_bits) != test_bits) {
2319                 /* enable and lock */
2320                 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
2321         }
2322         write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
2323
2324         if (vmm_exclusive) {
2325                 kvm_cpu_vmxon(phys_addr);
2326                 ept_sync_global();
2327         }
2328
2329         store_gdt(&__get_cpu_var(host_gdt));
2330
2331         return 0;
2332 }
2333
2334 static void vmclear_local_loaded_vmcss(void)
2335 {
2336         int cpu = raw_smp_processor_id();
2337         struct loaded_vmcs *v, *n;
2338
2339         list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
2340                                  loaded_vmcss_on_cpu_link)
2341                 __loaded_vmcs_clear(v);
2342 }
2343
2344
2345 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
2346  * tricks.
2347  */
2348 static void kvm_cpu_vmxoff(void)
2349 {
2350         asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
2351 }
2352
2353 static void hardware_disable(void *garbage)
2354 {
2355         if (vmm_exclusive) {
2356                 vmclear_local_loaded_vmcss();
2357                 kvm_cpu_vmxoff();
2358         }
2359         write_cr4(read_cr4() & ~X86_CR4_VMXE);
2360 }
2361
2362 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
2363                                       u32 msr, u32 *result)
2364 {
2365         u32 vmx_msr_low, vmx_msr_high;
2366         u32 ctl = ctl_min | ctl_opt;
2367
2368         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2369
2370         ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
2371         ctl |= vmx_msr_low;  /* bit == 1 in low word  ==> must be one  */
2372
2373         /* Ensure minimum (required) set of control bits are supported. */
2374         if (ctl_min & ~ctl)
2375                 return -EIO;
2376
2377         *result = ctl;
2378         return 0;
2379 }
2380
2381 static __init bool allow_1_setting(u32 msr, u32 ctl)
2382 {
2383         u32 vmx_msr_low, vmx_msr_high;
2384
2385         rdmsr(msr, vmx_msr_low, vmx_msr_high);
2386         return vmx_msr_high & ctl;
2387 }
2388
2389 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
2390 {
2391         u32 vmx_msr_low, vmx_msr_high;
2392         u32 min, opt, min2, opt2;
2393         u32 _pin_based_exec_control = 0;
2394         u32 _cpu_based_exec_control = 0;
2395         u32 _cpu_based_2nd_exec_control = 0;
2396         u32 _vmexit_control = 0;
2397         u32 _vmentry_control = 0;
2398
2399         min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2400         opt = PIN_BASED_VIRTUAL_NMIS;
2401         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2402                                 &_pin_based_exec_control) < 0)
2403                 return -EIO;
2404
2405         min =
2406 #ifdef CONFIG_X86_64
2407               CPU_BASED_CR8_LOAD_EXITING |
2408               CPU_BASED_CR8_STORE_EXITING |
2409 #endif
2410               CPU_BASED_CR3_LOAD_EXITING |
2411               CPU_BASED_CR3_STORE_EXITING |
2412               CPU_BASED_USE_IO_BITMAPS |
2413               CPU_BASED_MOV_DR_EXITING |
2414               CPU_BASED_USE_TSC_OFFSETING |
2415               CPU_BASED_MWAIT_EXITING |
2416               CPU_BASED_MONITOR_EXITING |
2417               CPU_BASED_INVLPG_EXITING;
2418
2419         if (yield_on_hlt)
2420                 min |= CPU_BASED_HLT_EXITING;
2421
2422         opt = CPU_BASED_TPR_SHADOW |
2423               CPU_BASED_USE_MSR_BITMAPS |
2424               CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
2425         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
2426                                 &_cpu_based_exec_control) < 0)
2427                 return -EIO;
2428 #ifdef CONFIG_X86_64
2429         if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
2430                 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
2431                                            ~CPU_BASED_CR8_STORE_EXITING;
2432 #endif
2433         if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
2434                 min2 = 0;
2435                 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
2436                         SECONDARY_EXEC_WBINVD_EXITING |
2437                         SECONDARY_EXEC_ENABLE_VPID |
2438                         SECONDARY_EXEC_ENABLE_EPT |
2439                         SECONDARY_EXEC_UNRESTRICTED_GUEST |
2440                         SECONDARY_EXEC_PAUSE_LOOP_EXITING |
2441                         SECONDARY_EXEC_RDTSCP;
2442                 if (adjust_vmx_controls(min2, opt2,
2443                                         MSR_IA32_VMX_PROCBASED_CTLS2,
2444                                         &_cpu_based_2nd_exec_control) < 0)
2445                         return -EIO;
2446         }
2447 #ifndef CONFIG_X86_64
2448         if (!(_cpu_based_2nd_exec_control &
2449                                 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
2450                 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
2451 #endif
2452         if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
2453                 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2454                    enabled */
2455                 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2456                                              CPU_BASED_CR3_STORE_EXITING |
2457                                              CPU_BASED_INVLPG_EXITING);
2458                 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
2459                       vmx_capability.ept, vmx_capability.vpid);
2460         }
2461
2462         min = 0;
2463 #ifdef CONFIG_X86_64
2464         min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2465 #endif
2466         opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
2467         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2468                                 &_vmexit_control) < 0)
2469                 return -EIO;
2470
2471         min = 0;
2472         opt = VM_ENTRY_LOAD_IA32_PAT;
2473         if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2474                                 &_vmentry_control) < 0)
2475                 return -EIO;
2476
2477         rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
2478
2479         /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2480         if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
2481                 return -EIO;
2482
2483 #ifdef CONFIG_X86_64
2484         /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2485         if (vmx_msr_high & (1u<<16))
2486                 return -EIO;
2487 #endif
2488
2489         /* Require Write-Back (WB) memory type for VMCS accesses. */
2490         if (((vmx_msr_high >> 18) & 15) != 6)
2491                 return -EIO;
2492
2493         vmcs_conf->size = vmx_msr_high & 0x1fff;
2494         vmcs_conf->order = get_order(vmcs_config.size);
2495         vmcs_conf->revision_id = vmx_msr_low;
2496
2497         vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2498         vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
2499         vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
2500         vmcs_conf->vmexit_ctrl         = _vmexit_control;
2501         vmcs_conf->vmentry_ctrl        = _vmentry_control;
2502
2503         cpu_has_load_ia32_efer =
2504                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2505                                 VM_ENTRY_LOAD_IA32_EFER)
2506                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2507                                    VM_EXIT_LOAD_IA32_EFER);
2508
2509         cpu_has_load_perf_global_ctrl =
2510                 allow_1_setting(MSR_IA32_VMX_ENTRY_CTLS,
2511                                 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
2512                 && allow_1_setting(MSR_IA32_VMX_EXIT_CTLS,
2513                                    VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
2514
2515         /*
2516          * Some cpus support VM_ENTRY_(LOAD|SAVE)_IA32_PERF_GLOBAL_CTRL
2517          * but due to arrata below it can't be used. Workaround is to use
2518          * msr load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2519          *
2520          * VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32]
2521          *
2522          * AAK155             (model 26)
2523          * AAP115             (model 30)
2524          * AAT100             (model 37)
2525          * BC86,AAY89,BD102   (model 44)
2526          * BA97               (model 46)
2527          *
2528          */
2529         if (cpu_has_load_perf_global_ctrl && boot_cpu_data.x86 == 0x6) {
2530                 switch (boot_cpu_data.x86_model) {
2531                 case 26:
2532                 case 30:
2533                 case 37:
2534                 case 44:
2535                 case 46:
2536                         cpu_has_load_perf_global_ctrl = false;
2537                         printk_once(KERN_WARNING"kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2538                                         "does not work properly. Using workaround\n");
2539                         break;
2540                 default:
2541                         break;
2542                 }
2543         }
2544
2545         return 0;
2546 }
2547
2548 static struct vmcs *alloc_vmcs_cpu(int cpu)
2549 {
2550         int node = cpu_to_node(cpu);
2551         struct page *pages;
2552         struct vmcs *vmcs;
2553
2554         pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
2555         if (!pages)
2556                 return NULL;
2557         vmcs = page_address(pages);
2558         memset(vmcs, 0, vmcs_config.size);
2559         vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
2560         return vmcs;
2561 }
2562
2563 static struct vmcs *alloc_vmcs(void)
2564 {
2565         return alloc_vmcs_cpu(raw_smp_processor_id());
2566 }
2567
2568 static void free_vmcs(struct vmcs *vmcs)
2569 {
2570         free_pages((unsigned long)vmcs, vmcs_config.order);
2571 }
2572
2573 /*
2574  * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2575  */
2576 static void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
2577 {
2578         if (!loaded_vmcs->vmcs)
2579                 return;
2580         loaded_vmcs_clear(loaded_vmcs);
2581         free_vmcs(loaded_vmcs->vmcs);
2582         loaded_vmcs->vmcs = NULL;
2583 }
2584
2585 static void free_kvm_area(void)
2586 {
2587         int cpu;
2588
2589         for_each_possible_cpu(cpu) {
2590                 free_vmcs(per_cpu(vmxarea, cpu));
2591                 per_cpu(vmxarea, cpu) = NULL;
2592         }
2593 }
2594
2595 static __init int alloc_kvm_area(void)
2596 {
2597         int cpu;
2598
2599         for_each_possible_cpu(cpu) {
2600                 struct vmcs *vmcs;
2601
2602                 vmcs = alloc_vmcs_cpu(cpu);
2603                 if (!vmcs) {
2604                         free_kvm_area();
2605                         return -ENOMEM;
2606                 }
2607
2608                 per_cpu(vmxarea, cpu) = vmcs;
2609         }
2610         return 0;
2611 }
2612
2613 static __init int hardware_setup(void)
2614 {
2615         if (setup_vmcs_config(&vmcs_config) < 0)
2616                 return -EIO;
2617
2618         if (boot_cpu_has(X86_FEATURE_NX))
2619                 kvm_enable_efer_bits(EFER_NX);
2620
2621         if (!cpu_has_vmx_vpid())
2622                 enable_vpid = 0;
2623
2624         if (!cpu_has_vmx_ept() ||
2625             !cpu_has_vmx_ept_4levels()) {
2626                 enable_ept = 0;
2627                 enable_unrestricted_guest = 0;
2628         }
2629
2630         if (!cpu_has_vmx_unrestricted_guest())
2631                 enable_unrestricted_guest = 0;
2632
2633         if (!cpu_has_vmx_flexpriority())
2634                 flexpriority_enabled = 0;
2635
2636         if (!cpu_has_vmx_tpr_shadow())
2637                 kvm_x86_ops->update_cr8_intercept = NULL;
2638
2639         if (enable_ept && !cpu_has_vmx_ept_2m_page())
2640                 kvm_disable_largepages();
2641
2642         if (!cpu_has_vmx_ple())
2643                 ple_gap = 0;
2644
2645         if (nested)
2646                 nested_vmx_setup_ctls_msrs();
2647
2648         return alloc_kvm_area();
2649 }
2650
2651 static __exit void hardware_unsetup(void)
2652 {
2653         free_kvm_area();
2654 }
2655
2656 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
2657 {
2658         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2659
2660         if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
2661                 vmcs_write16(sf->selector, save->selector);
2662                 vmcs_writel(sf->base, save->base);
2663                 vmcs_write32(sf->limit, save->limit);
2664                 vmcs_write32(sf->ar_bytes, save->ar);
2665         } else {
2666                 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
2667                         << AR_DPL_SHIFT;
2668                 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
2669         }
2670 }
2671
2672 static void enter_pmode(struct kvm_vcpu *vcpu)
2673 {
2674         unsigned long flags;
2675         struct vcpu_vmx *vmx = to_vmx(vcpu);
2676
2677         vmx->emulation_required = 1;
2678         vmx->rmode.vm86_active = 0;
2679
2680         vmx_segment_cache_clear(vmx);
2681
2682         vmcs_write16(GUEST_TR_SELECTOR, vmx->rmode.tr.selector);
2683         vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
2684         vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
2685         vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
2686
2687         flags = vmcs_readl(GUEST_RFLAGS);
2688         flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2689         flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
2690         vmcs_writel(GUEST_RFLAGS, flags);
2691
2692         vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2693                         (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
2694
2695         update_exception_bitmap(vcpu);
2696
2697         if (emulate_invalid_guest_state)
2698                 return;
2699
2700         fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
2701         fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
2702         fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
2703         fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
2704
2705         vmx_segment_cache_clear(vmx);
2706
2707         vmcs_write16(GUEST_SS_SELECTOR, 0);
2708         vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
2709
2710         vmcs_write16(GUEST_CS_SELECTOR,
2711                      vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
2712         vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
2713 }
2714
2715 static gva_t rmode_tss_base(struct kvm *kvm)
2716 {
2717         if (!kvm->arch.tss_addr) {
2718                 struct kvm_memslots *slots;
2719                 gfn_t base_gfn;
2720
2721                 slots = kvm_memslots(kvm);
2722                 base_gfn = slots->memslots[0].base_gfn +
2723                                  kvm->memslots->memslots[0].npages - 3;
2724                 return base_gfn << PAGE_SHIFT;
2725         }
2726         return kvm->arch.tss_addr;
2727 }
2728
2729 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
2730 {
2731         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2732
2733         save->selector = vmcs_read16(sf->selector);
2734         save->base = vmcs_readl(sf->base);
2735         save->limit = vmcs_read32(sf->limit);
2736         save->ar = vmcs_read32(sf->ar_bytes);
2737         vmcs_write16(sf->selector, save->base >> 4);
2738         vmcs_write32(sf->base, save->base & 0xffff0);
2739         vmcs_write32(sf->limit, 0xffff);
2740         vmcs_write32(sf->ar_bytes, 0xf3);
2741         if (save->base & 0xf)
2742                 printk_once(KERN_WARNING "kvm: segment base is not paragraph"
2743                             " aligned when entering protected mode (seg=%d)",
2744                             seg);
2745 }
2746
2747 static void enter_rmode(struct kvm_vcpu *vcpu)
2748 {
2749         unsigned long flags;
2750         struct vcpu_vmx *vmx = to_vmx(vcpu);
2751
2752         if (enable_unrestricted_guest)
2753                 return;
2754
2755         vmx->emulation_required = 1;
2756         vmx->rmode.vm86_active = 1;
2757
2758         /*
2759          * Very old userspace does not call KVM_SET_TSS_ADDR before entering
2760          * vcpu. Call it here with phys address pointing 16M below 4G.
2761          */
2762         if (!vcpu->kvm->arch.tss_addr) {
2763                 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2764                              "called before entering vcpu\n");
2765                 srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
2766                 vmx_set_tss_addr(vcpu->kvm, 0xfeffd000);
2767                 vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
2768         }
2769
2770         vmx_segment_cache_clear(vmx);
2771
2772         vmx->rmode.tr.selector = vmcs_read16(GUEST_TR_SELECTOR);
2773         vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
2774         vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
2775
2776         vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
2777         vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
2778
2779         vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
2780         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2781
2782         flags = vmcs_readl(GUEST_RFLAGS);
2783         vmx->rmode.save_rflags = flags;
2784
2785         flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
2786
2787         vmcs_writel(GUEST_RFLAGS, flags);
2788         vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
2789         update_exception_bitmap(vcpu);
2790
2791         if (emulate_invalid_guest_state)
2792                 goto continue_rmode;
2793
2794         vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
2795         vmcs_write32(GUEST_SS_LIMIT, 0xffff);
2796         vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
2797
2798         vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
2799         vmcs_write32(GUEST_CS_LIMIT, 0xffff);
2800         if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
2801                 vmcs_writel(GUEST_CS_BASE, 0xf0000);
2802         vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
2803
2804         fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
2805         fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
2806         fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
2807         fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
2808
2809 continue_rmode:
2810         kvm_mmu_reset_context(vcpu);
2811 }
2812
2813 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
2814 {
2815         struct vcpu_vmx *vmx = to_vmx(vcpu);
2816         struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2817
2818         if (!msr)
2819                 return;
2820
2821         /*
2822          * Force kernel_gs_base reloading before EFER changes, as control
2823          * of this msr depends on is_long_mode().
2824          */
2825         vmx_load_host_state(to_vmx(vcpu));
2826         vcpu->arch.efer = efer;
2827         if (efer & EFER_LMA) {
2828                 vmcs_write32(VM_ENTRY_CONTROLS,
2829                              vmcs_read32(VM_ENTRY_CONTROLS) |
2830                              VM_ENTRY_IA32E_MODE);
2831                 msr->data = efer;
2832         } else {
2833                 vmcs_write32(VM_ENTRY_CONTROLS,
2834                              vmcs_read32(VM_ENTRY_CONTROLS) &
2835                              ~VM_ENTRY_IA32E_MODE);
2836
2837                 msr->data = efer & ~EFER_LME;
2838         }
2839         setup_msrs(vmx);
2840 }
2841
2842 #ifdef CONFIG_X86_64
2843
2844 static void enter_lmode(struct kvm_vcpu *vcpu)
2845 {
2846         u32 guest_tr_ar;
2847
2848         vmx_segment_cache_clear(to_vmx(vcpu));
2849
2850         guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
2851         if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
2852                 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2853                                      __func__);
2854                 vmcs_write32(GUEST_TR_AR_BYTES,
2855                              (guest_tr_ar & ~AR_TYPE_MASK)
2856                              | AR_TYPE_BUSY_64_TSS);
2857         }
2858         vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
2859 }
2860
2861 static void exit_lmode(struct kvm_vcpu *vcpu)
2862 {
2863         vmcs_write32(VM_ENTRY_CONTROLS,
2864                      vmcs_read32(VM_ENTRY_CONTROLS)
2865                      & ~VM_ENTRY_IA32E_MODE);
2866         vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
2867 }
2868
2869 #endif
2870
2871 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
2872 {
2873         vpid_sync_context(to_vmx(vcpu));
2874         if (enable_ept) {
2875                 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2876                         return;
2877                 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
2878         }
2879 }
2880
2881 static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2882 {
2883         ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2884
2885         vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2886         vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2887 }
2888
2889 static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2890 {
2891         if (enable_ept && is_paging(vcpu))
2892                 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2893         __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2894 }
2895
2896 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
2897 {
2898         ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2899
2900         vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2901         vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
2902 }
2903
2904 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2905 {
2906         if (!test_bit(VCPU_EXREG_PDPTR,
2907                       (unsigned long *)&vcpu->arch.regs_dirty))
2908                 return;
2909
2910         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2911                 vmcs_write64(GUEST_PDPTR0, vcpu->arch.mmu.pdptrs[0]);
2912                 vmcs_write64(GUEST_PDPTR1, vcpu->arch.mmu.pdptrs[1]);
2913                 vmcs_write64(GUEST_PDPTR2, vcpu->arch.mmu.pdptrs[2]);
2914                 vmcs_write64(GUEST_PDPTR3, vcpu->arch.mmu.pdptrs[3]);
2915         }
2916 }
2917
2918 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
2919 {
2920         if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2921                 vcpu->arch.mmu.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2922                 vcpu->arch.mmu.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2923                 vcpu->arch.mmu.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2924                 vcpu->arch.mmu.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
2925         }
2926
2927         __set_bit(VCPU_EXREG_PDPTR,
2928                   (unsigned long *)&vcpu->arch.regs_avail);
2929         __set_bit(VCPU_EXREG_PDPTR,
2930                   (unsigned long *)&vcpu->arch.regs_dirty);
2931 }
2932
2933 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
2934
2935 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2936                                         unsigned long cr0,
2937                                         struct kvm_vcpu *vcpu)
2938 {
2939         if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2940                 vmx_decache_cr3(vcpu);
2941         if (!(cr0 & X86_CR0_PG)) {
2942                 /* From paging/starting to nonpaging */
2943                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2944                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
2945                              (CPU_BASED_CR3_LOAD_EXITING |
2946                               CPU_BASED_CR3_STORE_EXITING));
2947                 vcpu->arch.cr0 = cr0;
2948                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2949         } else if (!is_paging(vcpu)) {
2950                 /* From nonpaging to paging */
2951                 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
2952                              vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
2953                              ~(CPU_BASED_CR3_LOAD_EXITING |
2954                                CPU_BASED_CR3_STORE_EXITING));
2955                 vcpu->arch.cr0 = cr0;
2956                 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
2957         }
2958
2959         if (!(cr0 & X86_CR0_WP))
2960                 *hw_cr0 &= ~X86_CR0_WP;
2961 }
2962
2963 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
2964 {
2965         struct vcpu_vmx *vmx = to_vmx(vcpu);
2966         unsigned long hw_cr0;
2967
2968         if (enable_unrestricted_guest)
2969                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
2970                         | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
2971         else
2972                 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
2973
2974         if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2975                 enter_pmode(vcpu);
2976
2977         if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2978                 enter_rmode(vcpu);
2979
2980 #ifdef CONFIG_X86_64
2981         if (vcpu->arch.efer & EFER_LME) {
2982                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
2983                         enter_lmode(vcpu);
2984                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
2985                         exit_lmode(vcpu);
2986         }
2987 #endif
2988
2989         if (enable_ept)
2990                 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2991
2992         if (!vcpu->fpu_active)
2993                 hw_cr0 |= X86_CR0_TS | X86_CR0_MP;
2994
2995         vmcs_writel(CR0_READ_SHADOW, cr0);
2996         vmcs_writel(GUEST_CR0, hw_cr0);
2997         vcpu->arch.cr0 = cr0;
2998         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
2999 }
3000
3001 static u64 construct_eptp(unsigned long root_hpa)
3002 {
3003         u64 eptp;
3004
3005         /* TODO write the value reading from MSR */
3006         eptp = VMX_EPT_DEFAULT_MT |
3007                 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
3008         eptp |= (root_hpa & PAGE_MASK);
3009
3010         return eptp;
3011 }
3012
3013 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
3014 {
3015         unsigned long guest_cr3;
3016         u64 eptp;
3017
3018         guest_cr3 = cr3;
3019         if (enable_ept) {
3020                 eptp = construct_eptp(cr3);
3021                 vmcs_write64(EPT_POINTER, eptp);
3022                 guest_cr3 = is_paging(vcpu) ? kvm_read_cr3(vcpu) :
3023                         vcpu->kvm->arch.ept_identity_map_addr;
3024                 ept_load_pdptrs(vcpu);
3025         }
3026
3027         vmx_flush_tlb(vcpu);
3028         vmcs_writel(GUEST_CR3, guest_cr3);
3029 }
3030
3031 static int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
3032 {
3033         unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
3034                     KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
3035
3036         if (cr4 & X86_CR4_VMXE) {
3037                 /*
3038                  * To use VMXON (and later other VMX instructions), a guest
3039                  * must first be able to turn on cr4.VMXE (see handle_vmon()).
3040                  * So basically the check on whether to allow nested VMX
3041                  * is here.
3042                  */
3043                 if (!nested_vmx_allowed(vcpu))
3044                         return 1;
3045         } else if (to_vmx(vcpu)->nested.vmxon)
3046                 return 1;
3047
3048         vcpu->arch.cr4 = cr4;
3049         if (enable_ept) {
3050                 if (!is_paging(vcpu)) {
3051                         hw_cr4 &= ~X86_CR4_PAE;
3052                         hw_cr4 |= X86_CR4_PSE;
3053                 } else if (!(cr4 & X86_CR4_PAE)) {
3054                         hw_cr4 &= ~X86_CR4_PAE;
3055                 }
3056         }
3057
3058         vmcs_writel(CR4_READ_SHADOW, cr4);
3059         vmcs_writel(GUEST_CR4, hw_cr4);
3060         return 0;
3061 }
3062
3063 static void vmx_get_segment(struct kvm_vcpu *vcpu,
3064                             struct kvm_segment *var, int seg)
3065 {
3066         struct vcpu_vmx *vmx = to_vmx(vcpu);
3067         struct kvm_save_segment *save;
3068         u32 ar;
3069
3070         if (vmx->rmode.vm86_active
3071             && (seg == VCPU_SREG_TR || seg == VCPU_SREG_ES
3072                 || seg == VCPU_SREG_DS || seg == VCPU_SREG_FS
3073                 || seg == VCPU_SREG_GS)
3074             && !emulate_invalid_guest_state) {
3075                 switch (seg) {
3076                 case VCPU_SREG_TR: save = &vmx->rmode.tr; break;
3077                 case VCPU_SREG_ES: save = &vmx->rmode.es; break;
3078                 case VCPU_SREG_DS: save = &vmx->rmode.ds; break;
3079                 case VCPU_SREG_FS: save = &vmx->rmode.fs; break;
3080                 case VCPU_SREG_GS: save = &vmx->rmode.gs; break;
3081                 default: BUG();
3082                 }
3083                 var->selector = save->selector;
3084                 var->base = save->base;
3085                 var->limit = save->limit;
3086                 ar = save->ar;
3087                 if (seg == VCPU_SREG_TR
3088                     || var->selector == vmx_read_guest_seg_selector(vmx, seg))
3089                         goto use_saved_rmode_seg;
3090         }
3091         var->base = vmx_read_guest_seg_base(vmx, seg);
3092         var->limit = vmx_read_guest_seg_limit(vmx, seg);
3093         var->selector = vmx_read_guest_seg_selector(vmx, seg);
3094         ar = vmx_read_guest_seg_ar(vmx, seg);
3095 use_saved_rmode_seg:
3096         if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
3097                 ar = 0;
3098         var->type = ar & 15;
3099         var->s = (ar >> 4) & 1;
3100         var->dpl = (ar >> 5) & 3;
3101         var->present = (ar >> 7) & 1;
3102         var->avl = (ar >> 12) & 1;
3103         var->l = (ar >> 13) & 1;
3104         var->db = (ar >> 14) & 1;
3105         var->g = (ar >> 15) & 1;
3106         var->unusable = (ar >> 16) & 1;
3107 }
3108
3109 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
3110 {
3111         struct kvm_segment s;
3112
3113         if (to_vmx(vcpu)->rmode.vm86_active) {
3114                 vmx_get_segment(vcpu, &s, seg);
3115                 return s.base;
3116         }
3117         return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
3118 }
3119
3120 static int __vmx_get_cpl(struct kvm_vcpu *vcpu)
3121 {
3122         if (!is_protmode(vcpu))
3123                 return 0;
3124
3125         if (!is_long_mode(vcpu)
3126             && (kvm_get_rflags(vcpu) & X86_EFLAGS_VM)) /* if virtual 8086 */
3127                 return 3;
3128
3129         return vmx_read_guest_seg_selector(to_vmx(vcpu), VCPU_SREG_CS) & 3;
3130 }
3131
3132 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
3133 {
3134         if (!test_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail)) {
3135                 __set_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3136                 to_vmx(vcpu)->cpl = __vmx_get_cpl(vcpu);
3137         }
3138         return to_vmx(vcpu)->cpl;
3139 }
3140
3141
3142 static u32 vmx_segment_access_rights(struct kvm_segment *var)
3143 {
3144         u32 ar;
3145
3146         if (var->unusable)
3147                 ar = 1 << 16;
3148         else {
3149                 ar = var->type & 15;
3150                 ar |= (var->s & 1) << 4;
3151                 ar |= (var->dpl & 3) << 5;
3152                 ar |= (var->present & 1) << 7;
3153                 ar |= (var->avl & 1) << 12;
3154                 ar |= (var->l & 1) << 13;
3155                 ar |= (var->db & 1) << 14;
3156                 ar |= (var->g & 1) << 15;
3157         }
3158         if (ar == 0) /* a 0 value means unusable */
3159                 ar = AR_UNUSABLE_MASK;
3160
3161         return ar;
3162 }
3163
3164 static void vmx_set_segment(struct kvm_vcpu *vcpu,
3165                             struct kvm_segment *var, int seg)
3166 {
3167         struct vcpu_vmx *vmx = to_vmx(vcpu);
3168         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3169         u32 ar;
3170
3171         vmx_segment_cache_clear(vmx);
3172
3173         if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
3174                 vmcs_write16(sf->selector, var->selector);
3175                 vmx->rmode.tr.selector = var->selector;
3176                 vmx->rmode.tr.base = var->base;
3177                 vmx->rmode.tr.limit = var->limit;
3178                 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
3179                 return;
3180         }
3181         vmcs_writel(sf->base, var->base);
3182         vmcs_write32(sf->limit, var->limit);
3183         vmcs_write16(sf->selector, var->selector);
3184         if (vmx->rmode.vm86_active && var->s) {
3185                 /*
3186                  * Hack real-mode segments into vm86 compatibility.
3187                  */
3188                 if (var->base == 0xffff0000 && var->selector == 0xf000)
3189                         vmcs_writel(sf->base, 0xf0000);
3190                 ar = 0xf3;
3191         } else
3192                 ar = vmx_segment_access_rights(var);
3193
3194         /*
3195          *   Fix the "Accessed" bit in AR field of segment registers for older
3196          * qemu binaries.
3197          *   IA32 arch specifies that at the time of processor reset the
3198          * "Accessed" bit in the AR field of segment registers is 1. And qemu
3199          * is setting it to 0 in the usedland code. This causes invalid guest
3200          * state vmexit when "unrestricted guest" mode is turned on.
3201          *    Fix for this setup issue in cpu_reset is being pushed in the qemu
3202          * tree. Newer qemu binaries with that qemu fix would not need this
3203          * kvm hack.
3204          */
3205         if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
3206                 ar |= 0x1; /* Accessed */
3207
3208         vmcs_write32(sf->ar_bytes, ar);
3209         __clear_bit(VCPU_EXREG_CPL, (ulong *)&vcpu->arch.regs_avail);
3210 }
3211
3212 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3213 {
3214         u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
3215
3216         *db = (ar >> 14) & 1;
3217         *l = (ar >> 13) & 1;
3218 }
3219
3220 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3221 {
3222         dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
3223         dt->address = vmcs_readl(GUEST_IDTR_BASE);
3224 }
3225
3226 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3227 {
3228         vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
3229         vmcs_writel(GUEST_IDTR_BASE, dt->address);
3230 }
3231
3232 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3233 {
3234         dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
3235         dt->address = vmcs_readl(GUEST_GDTR_BASE);
3236 }
3237
3238 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
3239 {
3240         vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
3241         vmcs_writel(GUEST_GDTR_BASE, dt->address);
3242 }
3243
3244 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
3245 {
3246         struct kvm_segment var;
3247         u32 ar;
3248
3249         vmx_get_segment(vcpu, &var, seg);
3250         ar = vmx_segment_access_rights(&var);
3251
3252         if (var.base != (var.selector << 4))
3253                 return false;
3254         if (var.limit != 0xffff)
3255                 return false;
3256         if (ar != 0xf3)
3257                 return false;
3258
3259         return true;
3260 }
3261
3262 static bool code_segment_valid(struct kvm_vcpu *vcpu)
3263 {
3264         struct kvm_segment cs;
3265         unsigned int cs_rpl;
3266
3267         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3268         cs_rpl = cs.selector & SELECTOR_RPL_MASK;
3269
3270         if (cs.unusable)
3271                 return false;
3272         if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
3273                 return false;
3274         if (!cs.s)
3275                 return false;
3276         if (cs.type & AR_TYPE_WRITEABLE_MASK) {
3277                 if (cs.dpl > cs_rpl)
3278                         return false;
3279         } else {
3280                 if (cs.dpl != cs_rpl)
3281                         return false;
3282         }
3283         if (!cs.present)
3284                 return false;
3285
3286         /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
3287         return true;
3288 }
3289
3290 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
3291 {
3292         struct kvm_segment ss;
3293         unsigned int ss_rpl;
3294
3295         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3296         ss_rpl = ss.selector & SELECTOR_RPL_MASK;
3297
3298         if (ss.unusable)
3299                 return true;
3300         if (ss.type != 3 && ss.type != 7)
3301                 return false;
3302         if (!ss.s)
3303                 return false;
3304         if (ss.dpl != ss_rpl) /* DPL != RPL */
3305                 return false;
3306         if (!ss.present)
3307                 return false;
3308
3309         return true;
3310 }
3311
3312 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
3313 {
3314         struct kvm_segment var;
3315         unsigned int rpl;
3316
3317         vmx_get_segment(vcpu, &var, seg);
3318         rpl = var.selector & SELECTOR_RPL_MASK;
3319
3320         if (var.unusable)
3321                 return true;
3322         if (!var.s)
3323                 return false;
3324         if (!var.present)
3325                 return false;
3326         if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
3327                 if (var.dpl < rpl) /* DPL < RPL */
3328                         return false;
3329         }
3330
3331         /* TODO: Add other members to kvm_segment_field to allow checking for other access
3332          * rights flags
3333          */
3334         return true;
3335 }
3336
3337 static bool tr_valid(struct kvm_vcpu *vcpu)
3338 {
3339         struct kvm_segment tr;
3340
3341         vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
3342
3343         if (tr.unusable)
3344                 return false;
3345         if (tr.selector & SELECTOR_TI_MASK)     /* TI = 1 */
3346                 return false;
3347         if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
3348                 return false;
3349         if (!tr.present)
3350                 return false;
3351
3352         return true;
3353 }
3354
3355 static bool ldtr_valid(struct kvm_vcpu *vcpu)
3356 {
3357         struct kvm_segment ldtr;
3358
3359         vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
3360
3361         if (ldtr.unusable)
3362                 return true;
3363         if (ldtr.selector & SELECTOR_TI_MASK)   /* TI = 1 */
3364                 return false;
3365         if (ldtr.type != 2)
3366                 return false;
3367         if (!ldtr.present)
3368                 return false;
3369
3370         return true;
3371 }
3372
3373 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
3374 {
3375         struct kvm_segment cs, ss;
3376
3377         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
3378         vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
3379
3380         return ((cs.selector & SELECTOR_RPL_MASK) ==
3381                  (ss.selector & SELECTOR_RPL_MASK));
3382 }
3383
3384 /*
3385  * Check if guest state is valid. Returns true if valid, false if
3386  * not.
3387  * We assume that registers are always usable
3388  */
3389 static bool guest_state_valid(struct kvm_vcpu *vcpu)
3390 {
3391         /* real mode guest state checks */
3392         if (!is_protmode(vcpu)) {
3393                 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
3394                         return false;
3395                 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
3396                         return false;
3397                 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
3398                         return false;
3399                 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
3400                         return false;
3401                 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
3402                         return false;
3403                 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
3404                         return false;
3405         } else {
3406         /* protected mode guest state checks */
3407                 if (!cs_ss_rpl_check(vcpu))
3408                         return false;
3409                 if (!code_segment_valid(vcpu))
3410                         return false;
3411                 if (!stack_segment_valid(vcpu))
3412                         return false;
3413                 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3414                         return false;
3415                 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3416                         return false;
3417                 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3418                         return false;
3419                 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3420                         return false;
3421                 if (!tr_valid(vcpu))
3422                         return false;
3423                 if (!ldtr_valid(vcpu))
3424                         return false;
3425         }
3426         /* TODO:
3427          * - Add checks on RIP
3428          * - Add checks on RFLAGS
3429          */
3430
3431         return true;
3432 }
3433
3434 static int init_rmode_tss(struct kvm *kvm)
3435 {
3436         gfn_t fn;
3437         u16 data = 0;
3438         int r, idx, ret = 0;
3439
3440         idx = srcu_read_lock(&kvm->srcu);
3441         fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
3442         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3443         if (r < 0)
3444                 goto out;
3445         data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
3446         r = kvm_write_guest_page(kvm, fn++, &data,
3447                         TSS_IOPB_BASE_OFFSET, sizeof(u16));
3448         if (r < 0)
3449                 goto out;
3450         r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3451         if (r < 0)
3452                 goto out;
3453         r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3454         if (r < 0)
3455                 goto out;
3456         data = ~0;
3457         r = kvm_write_guest_page(kvm, fn, &data,
3458                                  RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3459                                  sizeof(u8));
3460         if (r < 0)
3461                 goto out;
3462
3463         ret = 1;
3464 out:
3465         srcu_read_unlock(&kvm->srcu, idx);
3466         return ret;
3467 }
3468
3469 static int init_rmode_identity_map(struct kvm *kvm)
3470 {
3471         int i, idx, r, ret;
3472         pfn_t identity_map_pfn;
3473         u32 tmp;
3474
3475         if (!enable_ept)
3476                 return 1;
3477         if (unlikely(!kvm->arch.ept_identity_pagetable)) {
3478                 printk(KERN_ERR "EPT: identity-mapping pagetable "
3479                         "haven't been allocated!\n");
3480                 return 0;
3481         }
3482         if (likely(kvm->arch.ept_identity_pagetable_done))
3483                 return 1;
3484         ret = 0;
3485         identity_map_pfn = kvm->arch.ept_identity_map_addr >> PAGE_SHIFT;
3486         idx = srcu_read_lock(&kvm->srcu);
3487         r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3488         if (r < 0)
3489                 goto out;
3490         /* Set up identity-mapping pagetable for EPT in real mode */
3491         for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3492                 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3493                         _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3494                 r = kvm_write_guest_page(kvm, identity_map_pfn,
3495                                 &tmp, i * sizeof(tmp), sizeof(tmp));
3496                 if (r < 0)
3497                         goto out;
3498         }
3499         kvm->arch.ept_identity_pagetable_done = true;
3500         ret = 1;
3501 out:
3502         srcu_read_unlock(&kvm->srcu, idx);
3503         return ret;
3504 }
3505
3506 static void seg_setup(int seg)
3507 {
3508         struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3509         unsigned int ar;
3510
3511         vmcs_write16(sf->selector, 0);
3512         vmcs_writel(sf->base, 0);
3513         vmcs_write32(sf->limit, 0xffff);
3514         if (enable_unrestricted_guest) {
3515                 ar = 0x93;
3516                 if (seg == VCPU_SREG_CS)
3517                         ar |= 0x08; /* code segment */
3518         } else
3519                 ar = 0xf3;
3520
3521         vmcs_write32(sf->ar_bytes, ar);
3522 }
3523
3524 static int alloc_apic_access_page(struct kvm *kvm)
3525 {
3526         struct kvm_userspace_memory_region kvm_userspace_mem;
3527         int r = 0;
3528
3529         mutex_lock(&kvm->slots_lock);
3530         if (kvm->arch.apic_access_page)
3531                 goto out;
3532         kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
3533         kvm_userspace_mem.flags = 0;
3534         kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
3535         kvm_userspace_mem.memory_size = PAGE_SIZE;
3536         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3537         if (r)
3538                 goto out;
3539
3540         kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
3541 out:
3542         mutex_unlock(&kvm->slots_lock);
3543         return r;
3544 }
3545
3546 static int alloc_identity_pagetable(struct kvm *kvm)
3547 {
3548         struct kvm_userspace_memory_region kvm_userspace_mem;
3549         int r = 0;
3550
3551         mutex_lock(&kvm->slots_lock);
3552         if (kvm->arch.ept_identity_pagetable)
3553                 goto out;
3554         kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
3555         kvm_userspace_mem.flags = 0;
3556         kvm_userspace_mem.guest_phys_addr =
3557                 kvm->arch.ept_identity_map_addr;
3558         kvm_userspace_mem.memory_size = PAGE_SIZE;
3559         r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
3560         if (r)
3561                 goto out;
3562
3563         kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
3564                         kvm->arch.ept_identity_map_addr >> PAGE_SHIFT);
3565 out:
3566         mutex_unlock(&kvm->slots_lock);
3567         return r;
3568 }
3569
3570 static void allocate_vpid(struct vcpu_vmx *vmx)
3571 {
3572         int vpid;
3573
3574         vmx->vpid = 0;
3575         if (!enable_vpid)
3576                 return;
3577         spin_lock(&vmx_vpid_lock);
3578         vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
3579         if (vpid < VMX_NR_VPIDS) {
3580                 vmx->vpid = vpid;
3581                 __set_bit(vpid, vmx_vpid_bitmap);
3582         }
3583         spin_unlock(&vmx_vpid_lock);
3584 }
3585
3586 static void free_vpid(struct vcpu_vmx *vmx)
3587 {
3588         if (!enable_vpid)
3589                 return;
3590         spin_lock(&vmx_vpid_lock);
3591         if (vmx->vpid != 0)
3592                 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3593         spin_unlock(&vmx_vpid_lock);
3594 }
3595
3596 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
3597 {
3598         int f = sizeof(unsigned long);
3599
3600         if (!cpu_has_vmx_msr_bitmap())
3601                 return;
3602
3603         /*
3604          * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3605          * have the write-low and read-high bitmap offsets the wrong way round.
3606          * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3607          */
3608         if (msr <= 0x1fff) {
3609                 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
3610                 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
3611         } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3612                 msr &= 0x1fff;
3613                 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
3614                 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
3615         }
3616 }
3617
3618 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
3619 {
3620         if (!longmode_only)
3621                 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
3622         __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
3623 }
3624
3625 /*
3626  * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3627  * will not change in the lifetime of the guest.
3628  * Note that host-state that does change is set elsewhere. E.g., host-state
3629  * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3630  */
3631 static void vmx_set_constant_host_state(void)
3632 {
3633         u32 low32, high32;
3634         unsigned long tmpl;
3635         struct desc_ptr dt;
3636
3637         vmcs_writel(HOST_CR0, read_cr0() | X86_CR0_TS);  /* 22.2.3 */
3638         vmcs_writel(HOST_CR4, read_cr4());  /* 22.2.3, 22.2.5 */
3639         vmcs_writel(HOST_CR3, read_cr3());  /* 22.2.3  FIXME: shadow tables */
3640
3641         vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS);  /* 22.2.4 */
3642         vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3643         vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3644         vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS);  /* 22.2.4 */
3645         vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8);  /* 22.2.4 */
3646
3647         native_store_idt(&dt);
3648         vmcs_writel(HOST_IDTR_BASE, dt.address);   /* 22.2.4 */
3649
3650         asm("mov $.Lkvm_vmx_return, %0" : "=r"(tmpl));
3651         vmcs_writel(HOST_RIP, tmpl); /* 22.2.5 */
3652
3653         rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3654         vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3655         rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3656         vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl);   /* 22.2.3 */
3657
3658         if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3659                 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3660                 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3661         }
3662 }
3663
3664 static void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
3665 {
3666         vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3667         if (enable_ept)
3668                 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
3669         if (is_guest_mode(&vmx->vcpu))
3670                 vmx->vcpu.arch.cr4_guest_owned_bits &=
3671                         ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
3672         vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3673 }
3674
3675 static u32 vmx_exec_control(struct vcpu_vmx *vmx)
3676 {
3677         u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3678         if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
3679                 exec_control &= ~CPU_BASED_TPR_SHADOW;
3680 #ifdef CONFIG_X86_64
3681                 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3682                                 CPU_BASED_CR8_LOAD_EXITING;
3683 #endif
3684         }
3685         if (!enable_ept)
3686                 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3687                                 CPU_BASED_CR3_LOAD_EXITING  |
3688                                 CPU_BASED_INVLPG_EXITING;
3689         return exec_control;
3690 }
3691
3692 static u32 vmx_secondary_exec_control(struct vcpu_vmx *vmx)
3693 {
3694         u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
3695         if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3696                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3697         if (vmx->vpid == 0)
3698                 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3699         if (!enable_ept) {
3700                 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3701                 enable_unrestricted_guest = 0;
3702         }
3703         if (!enable_unrestricted_guest)
3704                 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
3705         if (!ple_gap)
3706                 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
3707         return exec_control;
3708 }
3709
3710 static void ept_set_mmio_spte_mask(void)
3711 {
3712         /*
3713          * EPT Misconfigurations can be generated if the value of bits 2:0
3714          * of an EPT paging-structure entry is 110b (write/execute).
3715          * Also, magic bits (0xffull << 49) is set to quickly identify mmio
3716          * spte.
3717          */
3718         kvm_mmu_set_mmio_spte_mask(0xffull << 49 | 0x6ull);
3719 }
3720
3721 /*
3722  * Sets up the vmcs for emulated real mode.
3723  */
3724 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
3725 {
3726 #ifdef CONFIG_X86_64
3727         unsigned long a;
3728 #endif
3729         int i;
3730
3731         /* I/O */
3732         vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
3733         vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
3734
3735         if (cpu_has_vmx_msr_bitmap())
3736                 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
3737
3738         vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3739
3740         /* Control */
3741         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
3742                 vmcs_config.pin_based_exec_ctrl);
3743
3744         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
3745
3746         if (cpu_has_secondary_exec_ctrls()) {
3747                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
3748                                 vmx_secondary_exec_control(vmx));
3749         }
3750
3751         if (ple_gap) {
3752                 vmcs_write32(PLE_GAP, ple_gap);
3753                 vmcs_write32(PLE_WINDOW, ple_window);
3754         }
3755
3756         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3757         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
3758         vmcs_write32(CR3_TARGET_COUNT, 0);           /* 22.2.1 */
3759
3760         vmcs_write16(HOST_FS_SELECTOR, 0);            /* 22.2.4 */
3761         vmcs_write16(HOST_GS_SELECTOR, 0);            /* 22.2.4 */
3762         vmx_set_constant_host_state();
3763 #ifdef CONFIG_X86_64
3764         rdmsrl(MSR_FS_BASE, a);
3765         vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
3766         rdmsrl(MSR_GS_BASE, a);
3767         vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
3768 #else
3769         vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3770         vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
3771 #endif
3772
3773         vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3774         vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
3775         vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host));
3776         vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
3777         vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest));
3778
3779         if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
3780                 u32 msr_low, msr_high;
3781                 u64 host_pat;
3782                 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
3783                 host_pat = msr_low | ((u64) msr_high << 32);
3784                 /* Write the default value follow host pat */
3785                 vmcs_write64(GUEST_IA32_PAT, host_pat);
3786                 /* Keep arch.pat sync with GUEST_IA32_PAT */
3787                 vmx->vcpu.arch.pat = host_pat;
3788         }
3789
3790         for (i = 0; i < NR_VMX_MSR; ++i) {
3791                 u32 index = vmx_msr_index[i];
3792                 u32 data_low, data_high;
3793                 int j = vmx->nmsrs;
3794
3795                 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3796                         continue;
3797                 if (wrmsr_safe(index, data_low, data_high) < 0)
3798                         continue;
3799                 vmx->guest_msrs[j].index = i;
3800                 vmx->guest_msrs[j].data = 0;
3801                 vmx->guest_msrs[j].mask = -1ull;
3802                 ++vmx->nmsrs;
3803         }
3804
3805         vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
3806
3807         /* 22.2.1, 20.8.1 */
3808         vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
3809
3810         vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
3811         set_cr4_guest_host_mask(vmx);
3812
3813         kvm_write_tsc(&vmx->vcpu, 0);
3814
3815         return 0;
3816 }
3817
3818 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
3819 {
3820         struct vcpu_vmx *vmx = to_vmx(vcpu);
3821         u64 msr;
3822         int ret;
3823
3824         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
3825
3826         vmx->rmode.vm86_active = 0;
3827
3828         vmx->soft_vnmi_blocked = 0;
3829
3830         vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
3831         kvm_set_cr8(&vmx->vcpu, 0);
3832         msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
3833         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3834                 msr |= MSR_IA32_APICBASE_BSP;
3835         kvm_set_apic_base(&vmx->vcpu, msr);
3836
3837         ret = fx_init(&vmx->vcpu);
3838         if (ret != 0)
3839                 goto out;
3840
3841         vmx_segment_cache_clear(vmx);
3842
3843         seg_setup(VCPU_SREG_CS);
3844         /*
3845          * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
3846          * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4.  Sigh.
3847          */
3848         if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
3849                 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
3850                 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
3851         } else {
3852                 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
3853                 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
3854         }
3855
3856         seg_setup(VCPU_SREG_DS);
3857         seg_setup(VCPU_SREG_ES);
3858         seg_setup(VCPU_SREG_FS);
3859         seg_setup(VCPU_SREG_GS);
3860         seg_setup(VCPU_SREG_SS);
3861
3862         vmcs_write16(GUEST_TR_SELECTOR, 0);
3863         vmcs_writel(GUEST_TR_BASE, 0);
3864         vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3865         vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3866
3867         vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3868         vmcs_writel(GUEST_LDTR_BASE, 0);
3869         vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3870         vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3871
3872         vmcs_write32(GUEST_SYSENTER_CS, 0);
3873         vmcs_writel(GUEST_SYSENTER_ESP, 0);
3874         vmcs_writel(GUEST_SYSENTER_EIP, 0);
3875
3876         vmcs_writel(GUEST_RFLAGS, 0x02);
3877         if (kvm_vcpu_is_bsp(&vmx->vcpu))
3878                 kvm_rip_write(vcpu, 0xfff0);
3879         else
3880                 kvm_rip_write(vcpu, 0);
3881         kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
3882
3883         vmcs_writel(GUEST_DR7, 0x400);
3884
3885         vmcs_writel(GUEST_GDTR_BASE, 0);
3886         vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3887
3888         vmcs_writel(GUEST_IDTR_BASE, 0);
3889         vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3890
3891         vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
3892         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
3893         vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
3894
3895         /* Special registers */
3896         vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3897
3898         setup_msrs(vmx);
3899
3900         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);  /* 22.2.1 */
3901
3902         if (cpu_has_vmx_tpr_shadow()) {
3903                 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
3904                 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
3905                         vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
3906                                      __pa(vmx->vcpu.arch.apic->regs));
3907                 vmcs_write32(TPR_THRESHOLD, 0);
3908         }
3909
3910         if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
3911                 vmcs_write64(APIC_ACCESS_ADDR,
3912                              page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
3913
3914         if (vmx->vpid != 0)
3915                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3916
3917         vmx->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
3918         vcpu->srcu_idx = srcu_read_lock(&vcpu->kvm->srcu);
3919         vmx_set_cr0(&vmx->vcpu, kvm_read_cr0(vcpu)); /* enter rmode */
3920         srcu_read_unlock(&vcpu->kvm->srcu, vcpu->srcu_idx);
3921         vmx_set_cr4(&vmx->vcpu, 0);
3922         vmx_set_efer(&vmx->vcpu, 0);
3923         vmx_fpu_activate(&vmx->vcpu);
3924         update_exception_bitmap(&vmx->vcpu);
3925
3926         vpid_sync_context(vmx);
3927
3928         ret = 0;
3929
3930         /* HACK: Don't enable emulation on guest boot/reset */
3931         vmx->emulation_required = 0;
3932
3933 out:
3934         return ret;
3935 }
3936
3937 /*
3938  * In nested virtualization, check if L1 asked to exit on external interrupts.
3939  * For most existing hypervisors, this will always return true.
3940  */
3941 static bool nested_exit_on_intr(struct kvm_vcpu *vcpu)
3942 {
3943         return get_vmcs12(vcpu)->pin_based_vm_exec_control &
3944                 PIN_BASED_EXT_INTR_MASK;
3945 }
3946
3947 static void enable_irq_window(struct kvm_vcpu *vcpu)
3948 {
3949         u32 cpu_based_vm_exec_control;
3950         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu))
3951                 /* We can get here when nested_run_pending caused
3952                  * vmx_interrupt_allowed() to return false. In this case, do
3953                  * nothing - the interrupt will be injected later.
3954                  */
3955                 return;
3956
3957         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3958         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
3959         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3960 }
3961
3962 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3963 {
3964         u32 cpu_based_vm_exec_control;
3965
3966         if (!cpu_has_virtual_nmis()) {
3967                 enable_irq_window(vcpu);
3968                 return;
3969         }
3970
3971         if (vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
3972                 enable_irq_window(vcpu);
3973                 return;
3974         }
3975         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3976         cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
3977         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3978 }
3979
3980 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
3981 {
3982         struct vcpu_vmx *vmx = to_vmx(vcpu);
3983         uint32_t intr;
3984         int irq = vcpu->arch.interrupt.nr;
3985
3986         trace_kvm_inj_virq(irq);
3987
3988         ++vcpu->stat.irq_injections;
3989         if (vmx->rmode.vm86_active) {
3990                 int inc_eip = 0;
3991                 if (vcpu->arch.interrupt.soft)
3992                         inc_eip = vcpu->arch.event_exit_inst_len;
3993                 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
3994                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3995                 return;
3996         }
3997         intr = irq | INTR_INFO_VALID_MASK;
3998         if (vcpu->arch.interrupt.soft) {
3999                 intr |= INTR_TYPE_SOFT_INTR;
4000                 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
4001                              vmx->vcpu.arch.event_exit_inst_len);
4002         } else
4003                 intr |= INTR_TYPE_EXT_INTR;
4004         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
4005         vmx_clear_hlt(vcpu);
4006 }
4007
4008 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
4009 {
4010         struct vcpu_vmx *vmx = to_vmx(vcpu);
4011
4012         if (is_guest_mode(vcpu))
4013                 return;
4014
4015         if (!cpu_has_virtual_nmis()) {
4016                 /*
4017                  * Tracking the NMI-blocked state in software is built upon
4018                  * finding the next open IRQ window. This, in turn, depends on
4019                  * well-behaving guests: They have to keep IRQs disabled at
4020                  * least as long as the NMI handler runs. Otherwise we may
4021                  * cause NMI nesting, maybe breaking the guest. But as this is
4022                  * highly unlikely, we can live with the residual risk.
4023                  */
4024                 vmx->soft_vnmi_blocked = 1;
4025                 vmx->vnmi_blocked_time = 0;
4026         }
4027
4028         ++vcpu->stat.nmi_injections;
4029         vmx->nmi_known_unmasked = false;
4030         if (vmx->rmode.vm86_active) {
4031                 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
4032                         kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4033                 return;
4034         }
4035         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
4036                         INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
4037         vmx_clear_hlt(vcpu);
4038 }
4039
4040 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4041 {
4042         if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
4043                 return 0;
4044
4045         return  !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4046                   (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4047                    | GUEST_INTR_STATE_NMI));
4048 }
4049
4050 static bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
4051 {
4052         if (!cpu_has_virtual_nmis())
4053                 return to_vmx(vcpu)->soft_vnmi_blocked;
4054         if (to_vmx(vcpu)->nmi_known_unmasked)
4055                 return false;
4056         return vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
4057 }
4058
4059 static void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
4060 {
4061         struct vcpu_vmx *vmx = to_vmx(vcpu);
4062
4063         if (!cpu_has_virtual_nmis()) {
4064                 if (vmx->soft_vnmi_blocked != masked) {
4065                         vmx->soft_vnmi_blocked = masked;
4066                         vmx->vnmi_blocked_time = 0;
4067                 }
4068         } else {
4069                 vmx->nmi_known_unmasked = !masked;
4070                 if (masked)
4071                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4072                                       GUEST_INTR_STATE_NMI);
4073                 else
4074                         vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4075                                         GUEST_INTR_STATE_NMI);
4076         }
4077 }
4078
4079 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4080 {
4081         if (is_guest_mode(vcpu) && nested_exit_on_intr(vcpu)) {
4082                 struct vmcs12 *vmcs12;
4083                 if (to_vmx(vcpu)->nested.nested_run_pending)
4084                         return 0;
4085                 nested_vmx_vmexit(vcpu);
4086                 vmcs12 = get_vmcs12(vcpu);
4087                 vmcs12->vm_exit_reason = EXIT_REASON_EXTERNAL_INTERRUPT;
4088                 vmcs12->vm_exit_intr_info = 0;
4089                 /* fall through to normal code, but now in L1, not L2 */
4090         }
4091
4092         return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
4093                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4094                         (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
4095 }
4096
4097 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4098 {
4099         int ret;
4100         struct kvm_userspace_memory_region tss_mem = {
4101                 .slot = TSS_PRIVATE_MEMSLOT,
4102                 .guest_phys_addr = addr,
4103                 .memory_size = PAGE_SIZE * 3,
4104                 .flags = 0,
4105         };
4106
4107         ret = kvm_set_memory_region(kvm, &tss_mem, 0);
4108         if (ret)
4109                 return ret;
4110         kvm->arch.tss_addr = addr;
4111         if (!init_rmode_tss(kvm))
4112                 return  -ENOMEM;
4113
4114         return 0;
4115 }
4116
4117 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4118                                   int vec, u32 err_code)
4119 {
4120         /*
4121          * Instruction with address size override prefix opcode 0x67
4122          * Cause the #SS fault with 0 error code in VM86 mode.
4123          */
4124         if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
4125                 if (emulate_instruction(vcpu, 0) == EMULATE_DONE)
4126                         return 1;
4127         /*
4128          * Forward all other exceptions that are valid in real mode.
4129          * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4130          *        the required debugging infrastructure rework.
4131          */
4132         switch (vec) {
4133         case DB_VECTOR:
4134                 if (vcpu->guest_debug &
4135                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4136                         return 0;
4137                 kvm_queue_exception(vcpu, vec);
4138                 return 1;
4139         case BP_VECTOR:
4140                 /*
4141                  * Update instruction length as we may reinject the exception
4142                  * from user space while in guest debugging mode.
4143                  */
4144                 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4145                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4146                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
4147                         return 0;
4148                 /* fall through */
4149         case DE_VECTOR:
4150         case OF_VECTOR:
4151         case BR_VECTOR:
4152         case UD_VECTOR:
4153         case DF_VECTOR:
4154         case SS_VECTOR:
4155         case GP_VECTOR:
4156         case MF_VECTOR:
4157                 kvm_queue_exception(vcpu, vec);
4158                 return 1;
4159         }
4160         return 0;
4161 }
4162
4163 /*
4164  * Trigger machine check on the host. We assume all the MSRs are already set up
4165  * by the CPU and that we still run on the same CPU as the MCE occurred on.
4166  * We pass a fake environment to the machine check handler because we want
4167  * the guest to be always treated like user space, no matter what context
4168  * it used internally.
4169  */
4170 static void kvm_machine_check(void)
4171 {
4172 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4173         struct pt_regs regs = {
4174                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4175                 .flags = X86_EFLAGS_IF,
4176         };
4177
4178         do_machine_check(&regs, 0);
4179 #endif
4180 }
4181
4182 static int handle_machine_check(struct kvm_vcpu *vcpu)
4183 {
4184         /* already handled by vcpu_run */
4185         return 1;
4186 }
4187
4188 static int handle_exception(struct kvm_vcpu *vcpu)
4189 {
4190         struct vcpu_vmx *vmx = to_vmx(vcpu);
4191         struct kvm_run *kvm_run = vcpu->run;
4192         u32 intr_info, ex_no, error_code;
4193         unsigned long cr2, rip, dr6;
4194         u32 vect_info;
4195         enum emulation_result er;
4196
4197         vect_info = vmx->idt_vectoring_info;
4198         intr_info = vmx->exit_intr_info;
4199
4200         if (is_machine_check(intr_info))
4201                 return handle_machine_check(vcpu);
4202
4203         if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4204             !is_page_fault(intr_info)) {
4205                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4206                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
4207                 vcpu->run->internal.ndata = 2;
4208                 vcpu->run->internal.data[0] = vect_info;
4209                 vcpu->run->internal.data[1] = intr_info;
4210                 return 0;
4211         }
4212
4213         if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
4214                 return 1;  /* already handled by vmx_vcpu_run() */
4215
4216         if (is_no_device(intr_info)) {
4217                 vmx_fpu_activate(vcpu);
4218                 return 1;
4219         }
4220
4221         if (is_invalid_opcode(intr_info)) {
4222                 er = emulate_instruction(vcpu, EMULTYPE_TRAP_UD);
4223                 if (er != EMULATE_DONE)
4224                         kvm_queue_exception(vcpu, UD_VECTOR);
4225                 return 1;
4226         }
4227
4228         error_code = 0;
4229         if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
4230                 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
4231         if (is_page_fault(intr_info)) {
4232                 /* EPT won't cause page fault directly */
4233                 BUG_ON(enable_ept);
4234                 cr2 = vmcs_readl(EXIT_QUALIFICATION);
4235                 trace_kvm_page_fault(cr2, error_code);
4236
4237                 if (kvm_event_needs_reinjection(vcpu))
4238                         kvm_mmu_unprotect_page_virt(vcpu, cr2);
4239                 return kvm_mmu_page_fault(vcpu, cr2, error_code, NULL, 0);
4240         }
4241
4242         if (vmx->rmode.vm86_active &&
4243             handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
4244                                                                 error_code)) {
4245                 if (vcpu->arch.halt_request) {
4246                         vcpu->arch.halt_request = 0;
4247                         return kvm_emulate_halt(vcpu);
4248                 }
4249                 return 1;
4250         }
4251
4252         ex_no = intr_info & INTR_INFO_VECTOR_MASK;
4253         switch (ex_no) {
4254         case DB_VECTOR:
4255                 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4256                 if (!(vcpu->guest_debug &
4257                       (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
4258                         vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
4259                         kvm_queue_exception(vcpu, DB_VECTOR);
4260                         return 1;
4261                 }
4262                 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4263                 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4264                 /* fall through */
4265         case BP_VECTOR:
4266                 /*
4267                  * Update instruction length as we may reinject #BP from
4268                  * user space while in guest debugging mode. Reading it for
4269                  * #DB as well causes no harm, it is not used in that case.
4270                  */
4271                 vmx->vcpu.arch.event_exit_inst_len =
4272                         vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
4273                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
4274                 rip = kvm_rip_read(vcpu);
4275                 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4276                 kvm_run->debug.arch.exception = ex_no;
4277                 break;
4278         default:
4279                 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4280                 kvm_run->ex.exception = ex_no;
4281                 kvm_run->ex.error_code = error_code;
4282                 break;
4283         }
4284         return 0;
4285 }
4286
4287 static int handle_external_interrupt(struct kvm_vcpu *vcpu)
4288 {
4289         ++vcpu->stat.irq_exits;
4290         return 1;
4291 }
4292
4293 static int handle_triple_fault(struct kvm_vcpu *vcpu)
4294 {
4295         vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
4296         return 0;
4297 }
4298
4299 static int handle_io(struct kvm_vcpu *vcpu)
4300 {
4301         unsigned long exit_qualification;
4302         int size, in, string;
4303         unsigned port;
4304
4305         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4306         string = (exit_qualification & 16) != 0;
4307         in = (exit_qualification & 8) != 0;
4308
4309         ++vcpu->stat.io_exits;
4310
4311         if (string || in)
4312                 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4313
4314         port = exit_qualification >> 16;
4315         size = (exit_qualification & 7) + 1;
4316         skip_emulated_instruction(vcpu);
4317
4318         return kvm_fast_pio_out(vcpu, size, port);
4319 }
4320
4321 static void
4322 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4323 {
4324         /*
4325          * Patch in the VMCALL instruction:
4326          */
4327         hypercall[0] = 0x0f;
4328         hypercall[1] = 0x01;
4329         hypercall[2] = 0xc1;
4330 }
4331
4332 /* called to set cr0 as approriate for a mov-to-cr0 exit. */
4333 static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4334 {
4335         if (to_vmx(vcpu)->nested.vmxon &&
4336             ((val & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON))
4337                 return 1;
4338
4339         if (is_guest_mode(vcpu)) {
4340                 /*
4341                  * We get here when L2 changed cr0 in a way that did not change
4342                  * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
4343                  * but did change L0 shadowed bits. This can currently happen
4344                  * with the TS bit: L0 may want to leave TS on (for lazy fpu
4345                  * loading) while pretending to allow the guest to change it.
4346                  */
4347                 if (kvm_set_cr0(vcpu, (val & vcpu->arch.cr0_guest_owned_bits) |
4348                          (vcpu->arch.cr0 & ~vcpu->arch.cr0_guest_owned_bits)))
4349                         return 1;
4350                 vmcs_writel(CR0_READ_SHADOW, val);
4351                 return 0;
4352         } else
4353                 return kvm_set_cr0(vcpu, val);
4354 }
4355
4356 static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4357 {
4358         if (is_guest_mode(vcpu)) {
4359                 if (kvm_set_cr4(vcpu, (val & vcpu->arch.cr4_guest_owned_bits) |
4360                          (vcpu->arch.cr4 & ~vcpu->arch.cr4_guest_owned_bits)))
4361                         return 1;
4362                 vmcs_writel(CR4_READ_SHADOW, val);
4363                 return 0;
4364         } else
4365                 return kvm_set_cr4(vcpu, val);
4366 }
4367
4368 /* called to set cr0 as approriate for clts instruction exit. */
4369 static void handle_clts(struct kvm_vcpu *vcpu)
4370 {
4371         if (is_guest_mode(vcpu)) {
4372                 /*
4373                  * We get here when L2 did CLTS, and L1 didn't shadow CR0.TS
4374                  * but we did (!fpu_active). We need to keep GUEST_CR0.TS on,
4375                  * just pretend it's off (also in arch.cr0 for fpu_activate).
4376                  */
4377                 vmcs_writel(CR0_READ_SHADOW,
4378                         vmcs_readl(CR0_READ_SHADOW) & ~X86_CR0_TS);
4379                 vcpu->arch.cr0 &= ~X86_CR0_TS;
4380         } else
4381                 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4382 }
4383
4384 static int handle_cr(struct kvm_vcpu *vcpu)
4385 {
4386         unsigned long exit_qualification, val;
4387         int cr;
4388         int reg;
4389         int err;
4390
4391         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4392         cr = exit_qualification & 15;
4393         reg = (exit_qualification >> 8) & 15;
4394         switch ((exit_qualification >> 4) & 3) {
4395         case 0: /* mov to cr */
4396                 val = kvm_register_read(vcpu, reg);
4397                 trace_kvm_cr_write(cr, val);
4398                 switch (cr) {
4399                 case 0:
4400                         err = handle_set_cr0(vcpu, val);
4401                         kvm_complete_insn_gp(vcpu, err);
4402                         return 1;
4403                 case 3:
4404                         err = kvm_set_cr3(vcpu, val);
4405                         kvm_complete_insn_gp(vcpu, err);
4406                         return 1;
4407                 case 4:
4408                         err = handle_set_cr4(vcpu, val);
4409                         kvm_complete_insn_gp(vcpu, err);
4410                         return 1;
4411                 case 8: {
4412                                 u8 cr8_prev = kvm_get_cr8(vcpu);
4413                                 u8 cr8 = kvm_register_read(vcpu, reg);
4414                                 err = kvm_set_cr8(vcpu, cr8);
4415                                 kvm_complete_insn_gp(vcpu, err);
4416                                 if (irqchip_in_kernel(vcpu->kvm))
4417                                         return 1;
4418                                 if (cr8_prev <= cr8)
4419                                         return 1;
4420                                 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
4421                                 return 0;
4422                         }
4423                 };
4424                 break;
4425         case 2: /* clts */
4426                 handle_clts(vcpu);
4427                 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
4428                 skip_emulated_instruction(vcpu);
4429                 vmx_fpu_activate(vcpu);
4430                 return 1;
4431         case 1: /*mov from cr*/
4432                 switch (cr) {
4433                 case 3:
4434                         val = kvm_read_cr3(vcpu);
4435                         kvm_register_write(vcpu, reg, val);
4436                         trace_kvm_cr_read(cr, val);
4437                         skip_emulated_instruction(vcpu);
4438                         return 1;
4439                 case 8:
4440                         val = kvm_get_cr8(vcpu);
4441                         kvm_register_write(vcpu, reg, val);
4442                         trace_kvm_cr_read(cr, val);
4443                         skip_emulated_instruction(vcpu);
4444                         return 1;
4445                 }
4446                 break;
4447         case 3: /* lmsw */
4448                 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4449                 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
4450                 kvm_lmsw(vcpu, val);
4451
4452                 skip_emulated_instruction(vcpu);
4453                 return 1;
4454         default:
4455                 break;
4456         }
4457         vcpu->run->exit_reason = 0;
4458         pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
4459                (int)(exit_qualification >> 4) & 3, cr);
4460         return 0;
4461 }
4462
4463 static int handle_dr(struct kvm_vcpu *vcpu)
4464 {
4465         unsigned long exit_qualification;
4466         int dr, reg;
4467
4468         /* Do not handle if the CPL > 0, will trigger GP on re-entry */
4469         if (!kvm_require_cpl(vcpu, 0))
4470                 return 1;
4471         dr = vmcs_readl(GUEST_DR7);
4472         if (dr & DR7_GD) {
4473                 /*
4474                  * As the vm-exit takes precedence over the debug trap, we
4475                  * need to emulate the latter, either for the host or the
4476                  * guest debugging itself.
4477                  */
4478                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
4479                         vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
4480                         vcpu->run->debug.arch.dr7 = dr;
4481                         vcpu->run->debug.arch.pc =
4482                                 vmcs_readl(GUEST_CS_BASE) +
4483                                 vmcs_readl(GUEST_RIP);
4484                         vcpu->run->debug.arch.exception = DB_VECTOR;
4485                         vcpu->run->exit_reason = KVM_EXIT_DEBUG;
4486                         return 0;
4487                 } else {
4488                         vcpu->arch.dr7 &= ~DR7_GD;
4489                         vcpu->arch.dr6 |= DR6_BD;
4490                         vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
4491                         kvm_queue_exception(vcpu, DB_VECTOR);
4492                         return 1;
4493                 }
4494         }
4495
4496         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4497         dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4498         reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4499         if (exit_qualification & TYPE_MOV_FROM_DR) {
4500                 unsigned long val;
4501                 if (!kvm_get_dr(vcpu, dr, &val))
4502                         kvm_register_write(vcpu, reg, val);
4503         } else
4504                 kvm_set_dr(vcpu, dr, vcpu->arch.regs[reg]);
4505         skip_emulated_instruction(vcpu);
4506         return 1;
4507 }
4508
4509 static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4510 {
4511         vmcs_writel(GUEST_DR7, val);
4512 }
4513
4514 static int handle_cpuid(struct kvm_vcpu *vcpu)
4515 {
4516         kvm_emulate_cpuid(vcpu);
4517         return 1;
4518 }
4519
4520 static int handle_rdmsr(struct kvm_vcpu *vcpu)
4521 {
4522         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4523         u64 data;
4524
4525         if (vmx_get_msr(vcpu, ecx, &data)) {
4526                 trace_kvm_msr_read_ex(ecx);
4527                 kvm_inject_gp(vcpu, 0);
4528                 return 1;
4529         }
4530
4531         trace_kvm_msr_read(ecx, data);
4532
4533         /* FIXME: handling of bits 32:63 of rax, rdx */
4534         vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
4535         vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
4536         skip_emulated_instruction(vcpu);
4537         return 1;
4538 }
4539
4540 static int handle_wrmsr(struct kvm_vcpu *vcpu)
4541 {
4542         u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4543         u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4544                 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
4545
4546         if (vmx_set_msr(vcpu, ecx, data) != 0) {
4547                 trace_kvm_msr_write_ex(ecx, data);
4548                 kvm_inject_gp(vcpu, 0);
4549                 return 1;
4550         }
4551
4552         trace_kvm_msr_write(ecx, data);
4553         skip_emulated_instruction(vcpu);
4554         return 1;
4555 }
4556
4557 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
4558 {
4559         kvm_make_request(KVM_REQ_EVENT, vcpu);
4560         return 1;
4561 }
4562
4563 static int handle_interrupt_window(struct kvm_vcpu *vcpu)
4564 {
4565         u32 cpu_based_vm_exec_control;
4566
4567         /* clear pending irq */
4568         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4569         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
4570         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4571
4572         kvm_make_request(KVM_REQ_EVENT, vcpu);
4573
4574         ++vcpu->stat.irq_window_exits;
4575
4576         /*
4577          * If the user space waits to inject interrupts, exit as soon as
4578          * possible
4579          */
4580         if (!irqchip_in_kernel(vcpu->kvm) &&
4581             vcpu->run->request_interrupt_window &&
4582             !kvm_cpu_has_interrupt(vcpu)) {
4583                 vcpu->run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
4584                 return 0;
4585         }
4586         return 1;
4587 }
4588
4589 static int handle_halt(struct kvm_vcpu *vcpu)
4590 {
4591         skip_emulated_instruction(vcpu);
4592         return kvm_emulate_halt(vcpu);
4593 }
4594
4595 static int handle_vmcall(struct kvm_vcpu *vcpu)
4596 {
4597         skip_emulated_instruction(vcpu);
4598         kvm_emulate_hypercall(vcpu);
4599         return 1;
4600 }
4601
4602 static int handle_invd(struct kvm_vcpu *vcpu)
4603 {
4604         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4605 }
4606
4607 static int handle_invlpg(struct kvm_vcpu *vcpu)
4608 {
4609         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4610
4611         kvm_mmu_invlpg(vcpu, exit_qualification);
4612         skip_emulated_instruction(vcpu);
4613         return 1;
4614 }
4615
4616 static int handle_wbinvd(struct kvm_vcpu *vcpu)
4617 {
4618         skip_emulated_instruction(vcpu);
4619         kvm_emulate_wbinvd(vcpu);
4620         return 1;
4621 }
4622
4623 static int handle_xsetbv(struct kvm_vcpu *vcpu)
4624 {
4625         u64 new_bv = kvm_read_edx_eax(vcpu);
4626         u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4627
4628         if (kvm_set_xcr(vcpu, index, new_bv) == 0)
4629                 skip_emulated_instruction(vcpu);
4630         return 1;
4631 }
4632
4633 static int handle_apic_access(struct kvm_vcpu *vcpu)
4634 {
4635         if (likely(fasteoi)) {
4636                 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4637                 int access_type, offset;
4638
4639                 access_type = exit_qualification & APIC_ACCESS_TYPE;
4640                 offset = exit_qualification & APIC_ACCESS_OFFSET;
4641                 /*
4642                  * Sane guest uses MOV to write EOI, with written value
4643                  * not cared. So make a short-circuit here by avoiding
4644                  * heavy instruction emulation.
4645                  */
4646                 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4647                     (offset == APIC_EOI)) {
4648                         kvm_lapic_set_eoi(vcpu);
4649                         skip_emulated_instruction(vcpu);
4650                         return 1;
4651                 }
4652         }
4653         return emulate_instruction(vcpu, 0) == EMULATE_DONE;
4654 }
4655
4656 static int handle_task_switch(struct kvm_vcpu *vcpu)
4657 {
4658         struct vcpu_vmx *vmx = to_vmx(vcpu);
4659         unsigned long exit_qualification;
4660         bool has_error_code = false;
4661         u32 error_code = 0;
4662         u16 tss_selector;
4663         int reason, type, idt_v;
4664
4665         idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
4666         type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
4667
4668         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4669
4670         reason = (u32)exit_qualification >> 30;
4671         if (reason == TASK_SWITCH_GATE && idt_v) {
4672                 switch (type) {
4673                 case INTR_TYPE_NMI_INTR:
4674                         vcpu->arch.nmi_injected = false;
4675                         vmx_set_nmi_mask(vcpu, true);
4676                         break;
4677                 case INTR_TYPE_EXT_INTR:
4678                 case INTR_TYPE_SOFT_INTR:
4679                         kvm_clear_interrupt_queue(vcpu);
4680                         break;
4681                 case INTR_TYPE_HARD_EXCEPTION:
4682                         if (vmx->idt_vectoring_info &
4683                             VECTORING_INFO_DELIVER_CODE_MASK) {
4684                                 has_error_code = true;
4685                                 error_code =
4686                                         vmcs_read32(IDT_VECTORING_ERROR_CODE);
4687                         }
4688                         /* fall through */
4689                 case INTR_TYPE_SOFT_EXCEPTION:
4690                         kvm_clear_exception_queue(vcpu);
4691                         break;
4692                 default:
4693                         break;
4694                 }
4695         }
4696         tss_selector = exit_qualification;
4697
4698         if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4699                        type != INTR_TYPE_EXT_INTR &&
4700                        type != INTR_TYPE_NMI_INTR))
4701                 skip_emulated_instruction(vcpu);
4702
4703         if (kvm_task_switch(vcpu, tss_selector, reason,
4704                                 has_error_code, error_code) == EMULATE_FAIL) {
4705                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4706                 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4707                 vcpu->run->internal.ndata = 0;
4708                 return 0;
4709         }
4710
4711         /* clear all local breakpoint enable flags */
4712         vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
4713
4714         /*
4715          * TODO: What about debug traps on tss switch?
4716          *       Are we supposed to inject them and update dr6?
4717          */
4718
4719         return 1;
4720 }
4721
4722 static int handle_ept_violation(struct kvm_vcpu *vcpu)
4723 {
4724         unsigned long exit_qualification;
4725         gpa_t gpa;
4726         int gla_validity;
4727
4728         exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4729
4730         if (exit_qualification & (1 << 6)) {
4731                 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
4732                 return -EINVAL;
4733         }
4734
4735         gla_validity = (exit_qualification >> 7) & 0x3;
4736         if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
4737                 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
4738                 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
4739                         (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
4740                         vmcs_readl(GUEST_LINEAR_ADDRESS));
4741                 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
4742                         (long unsigned int)exit_qualification);
4743                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4744                 vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
4745                 return 0;
4746         }
4747
4748         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4749         trace_kvm_page_fault(gpa, exit_qualification);
4750         return kvm_mmu_page_fault(vcpu, gpa, exit_qualification & 0x3, NULL, 0);
4751 }
4752
4753 static u64 ept_rsvd_mask(u64 spte, int level)
4754 {
4755         int i;
4756         u64 mask = 0;
4757
4758         for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
4759                 mask |= (1ULL << i);
4760
4761         if (level > 2)
4762                 /* bits 7:3 reserved */
4763                 mask |= 0xf8;
4764         else if (level == 2) {
4765                 if (spte & (1ULL << 7))
4766                         /* 2MB ref, bits 20:12 reserved */
4767                         mask |= 0x1ff000;
4768                 else
4769                         /* bits 6:3 reserved */
4770                         mask |= 0x78;
4771         }
4772
4773         return mask;
4774 }
4775
4776 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
4777                                        int level)
4778 {
4779         printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
4780
4781         /* 010b (write-only) */
4782         WARN_ON((spte & 0x7) == 0x2);
4783
4784         /* 110b (write/execute) */
4785         WARN_ON((spte & 0x7) == 0x6);
4786
4787         /* 100b (execute-only) and value not supported by logical processor */
4788         if (!cpu_has_vmx_ept_execute_only())
4789                 WARN_ON((spte & 0x7) == 0x4);
4790
4791         /* not 000b */
4792         if ((spte & 0x7)) {
4793                 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
4794
4795                 if (rsvd_bits != 0) {
4796                         printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
4797                                          __func__, rsvd_bits);
4798                         WARN_ON(1);
4799                 }
4800
4801                 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
4802                         u64 ept_mem_type = (spte & 0x38) >> 3;
4803
4804                         if (ept_mem_type == 2 || ept_mem_type == 3 ||
4805                             ept_mem_type == 7) {
4806                                 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
4807                                                 __func__, ept_mem_type);
4808                                 WARN_ON(1);
4809                         }
4810                 }
4811         }
4812 }
4813
4814 static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
4815 {
4816         u64 sptes[4];
4817         int nr_sptes, i, ret;
4818         gpa_t gpa;
4819
4820         gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
4821
4822         ret = handle_mmio_page_fault_common(vcpu, gpa, true);
4823         if (likely(ret == 1))
4824                 return x86_emulate_instruction(vcpu, gpa, 0, NULL, 0) ==
4825                                               EMULATE_DONE;
4826         if (unlikely(!ret))
4827                 return 1;
4828
4829         /* It is the real ept misconfig */
4830         printk(KERN_ERR "EPT: Misconfiguration.\n");
4831         printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
4832
4833         nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
4834
4835         for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
4836                 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
4837
4838         vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
4839         vcpu->run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
4840
4841         return 0;
4842 }
4843
4844 static int handle_nmi_window(struct kvm_vcpu *vcpu)
4845 {
4846         u32 cpu_based_vm_exec_control;
4847
4848         /* clear pending NMI */
4849         cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4850         cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
4851         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
4852         ++vcpu->stat.nmi_window_exits;
4853         kvm_make_request(KVM_REQ_EVENT, vcpu);
4854
4855         return 1;
4856 }
4857
4858 static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
4859 {
4860         struct vcpu_vmx *vmx = to_vmx(vcpu);
4861         enum emulation_result err = EMULATE_DONE;
4862         int ret = 1;
4863         u32 cpu_exec_ctrl;
4864         bool intr_window_requested;
4865
4866         cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4867         intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
4868
4869         while (!guest_state_valid(vcpu)) {
4870                 if (intr_window_requested
4871                     && (kvm_get_rflags(&vmx->vcpu) & X86_EFLAGS_IF))
4872                         return handle_interrupt_window(&vmx->vcpu);
4873
4874                 err = emulate_instruction(vcpu, 0);
4875
4876                 if (err == EMULATE_DO_MMIO) {
4877                         ret = 0;
4878                         goto out;
4879                 }
4880
4881                 if (err != EMULATE_DONE)
4882                         return 0;
4883
4884                 if (signal_pending(current))
4885                         goto out;
4886                 if (need_resched())
4887                         schedule();
4888         }
4889
4890         vmx->emulation_required = 0;
4891 out:
4892         return ret;
4893 }
4894
4895 /*
4896  * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4897  * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4898  */
4899 static int handle_pause(struct kvm_vcpu *vcpu)
4900 {
4901         skip_emulated_instruction(vcpu);
4902         kvm_vcpu_on_spin(vcpu);
4903
4904         return 1;
4905 }
4906
4907 static int handle_invalid_op(struct kvm_vcpu *vcpu)
4908 {
4909         kvm_queue_exception(vcpu, UD_VECTOR);
4910         return 1;
4911 }
4912
4913 /*
4914  * To run an L2 guest, we need a vmcs02 based on the L1-specified vmcs12.
4915  * We could reuse a single VMCS for all the L2 guests, but we also want the
4916  * option to allocate a separate vmcs02 for each separate loaded vmcs12 - this
4917  * allows keeping them loaded on the processor, and in the future will allow
4918  * optimizations where prepare_vmcs02 doesn't need to set all the fields on
4919  * every entry if they never change.
4920  * So we keep, in vmx->nested.vmcs02_pool, a cache of size VMCS02_POOL_SIZE
4921  * (>=0) with a vmcs02 for each recently loaded vmcs12s, most recent first.
4922  *
4923  * The following functions allocate and free a vmcs02 in this pool.
4924  */
4925
4926 /* Get a VMCS from the pool to use as vmcs02 for the current vmcs12. */
4927 static struct loaded_vmcs *nested_get_current_vmcs02(struct vcpu_vmx *vmx)
4928 {
4929         struct vmcs02_list *item;
4930         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4931                 if (item->vmptr == vmx->nested.current_vmptr) {
4932                         list_move(&item->list, &vmx->nested.vmcs02_pool);
4933                         return &item->vmcs02;
4934                 }
4935
4936         if (vmx->nested.vmcs02_num >= max(VMCS02_POOL_SIZE, 1)) {
4937                 /* Recycle the least recently used VMCS. */
4938                 item = list_entry(vmx->nested.vmcs02_pool.prev,
4939                         struct vmcs02_list, list);
4940                 item->vmptr = vmx->nested.current_vmptr;
4941                 list_move(&item->list, &vmx->nested.vmcs02_pool);
4942                 return &item->vmcs02;
4943         }
4944
4945         /* Create a new VMCS */
4946         item = (struct vmcs02_list *)
4947                 kmalloc(sizeof(struct vmcs02_list), GFP_KERNEL);
4948         if (!item)
4949                 return NULL;
4950         item->vmcs02.vmcs = alloc_vmcs();
4951         if (!item->vmcs02.vmcs) {
4952                 kfree(item);
4953                 return NULL;
4954         }
4955         loaded_vmcs_init(&item->vmcs02);
4956         item->vmptr = vmx->nested.current_vmptr;
4957         list_add(&(item->list), &(vmx->nested.vmcs02_pool));
4958         vmx->nested.vmcs02_num++;
4959         return &item->vmcs02;
4960 }
4961
4962 /* Free and remove from pool a vmcs02 saved for a vmcs12 (if there is one) */
4963 static void nested_free_vmcs02(struct vcpu_vmx *vmx, gpa_t vmptr)
4964 {
4965         struct vmcs02_list *item;
4966         list_for_each_entry(item, &vmx->nested.vmcs02_pool, list)
4967                 if (item->vmptr == vmptr) {
4968                         free_loaded_vmcs(&item->vmcs02);
4969                         list_del(&item->list);
4970                         kfree(item);
4971                         vmx->nested.vmcs02_num--;
4972                         return;
4973                 }
4974 }
4975
4976 /*
4977  * Free all VMCSs saved for this vcpu, except the one pointed by
4978  * vmx->loaded_vmcs. These include the VMCSs in vmcs02_pool (except the one
4979  * currently used, if running L2), and vmcs01 when running L2.
4980  */
4981 static void nested_free_all_saved_vmcss(struct vcpu_vmx *vmx)
4982 {
4983         struct vmcs02_list *item, *n;
4984         list_for_each_entry_safe(item, n, &vmx->nested.vmcs02_pool, list) {
4985                 if (vmx->loaded_vmcs != &item->vmcs02)
4986                         free_loaded_vmcs(&item->vmcs02);
4987                 list_del(&item->list);
4988                 kfree(item);
4989         }
4990         vmx->nested.vmcs02_num = 0;
4991
4992         if (vmx->loaded_vmcs != &vmx->vmcs01)
4993                 free_loaded_vmcs(&vmx->vmcs01);
4994 }
4995
4996 /*
4997  * Emulate the VMXON instruction.
4998  * Currently, we just remember that VMX is active, and do not save or even
4999  * inspect the argument to VMXON (the so-called "VMXON pointer") because we
5000  * do not currently need to store anything in that guest-allocated memory
5001  * region. Consequently, VMCLEAR and VMPTRLD also do not verify that the their
5002  * argument is different from the VMXON pointer (which the spec says they do).
5003  */
5004 static int handle_vmon(struct kvm_vcpu *vcpu)
5005 {
5006         struct kvm_segment cs;
5007         struct vcpu_vmx *vmx = to_vmx(vcpu);
5008
5009         /* The Intel VMX Instruction Reference lists a bunch of bits that
5010          * are prerequisite to running VMXON, most notably cr4.VMXE must be
5011          * set to 1 (see vmx_set_cr4() for when we allow the guest to set this).
5012          * Otherwise, we should fail with #UD. We test these now:
5013          */
5014         if (!kvm_read_cr4_bits(vcpu, X86_CR4_VMXE) ||
5015             !kvm_read_cr0_bits(vcpu, X86_CR0_PE) ||
5016             (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
5017                 kvm_queue_exception(vcpu, UD_VECTOR);
5018                 return 1;
5019         }
5020
5021         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5022         if (is_long_mode(vcpu) && !cs.l) {
5023                 kvm_queue_exception(vcpu, UD_VECTOR);
5024                 return 1;
5025         }
5026
5027         if (vmx_get_cpl(vcpu)) {
5028                 kvm_inject_gp(vcpu, 0);
5029                 return 1;
5030         }
5031
5032         INIT_LIST_HEAD(&(vmx->nested.vmcs02_pool));
5033         vmx->nested.vmcs02_num = 0;
5034
5035         vmx->nested.vmxon = true;
5036
5037         skip_emulated_instruction(vcpu);
5038         return 1;
5039 }
5040
5041 /*
5042  * Intel's VMX Instruction Reference specifies a common set of prerequisites
5043  * for running VMX instructions (except VMXON, whose prerequisites are
5044  * slightly different). It also specifies what exception to inject otherwise.
5045  */
5046 static int nested_vmx_check_permission(struct kvm_vcpu *vcpu)
5047 {
5048         struct kvm_segment cs;
5049         struct vcpu_vmx *vmx = to_vmx(vcpu);
5050
5051         if (!vmx->nested.vmxon) {
5052                 kvm_queue_exception(vcpu, UD_VECTOR);
5053                 return 0;
5054         }
5055
5056         vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
5057         if ((vmx_get_rflags(vcpu) & X86_EFLAGS_VM) ||
5058             (is_long_mode(vcpu) && !cs.l)) {
5059                 kvm_queue_exception(vcpu, UD_VECTOR);
5060                 return 0;
5061         }
5062
5063         if (vmx_get_cpl(vcpu)) {
5064                 kvm_inject_gp(vcpu, 0);
5065                 return 0;
5066         }
5067
5068         return 1;
5069 }
5070
5071 /*
5072  * Free whatever needs to be freed from vmx->nested when L1 goes down, or
5073  * just stops using VMX.
5074  */
5075 static void free_nested(struct vcpu_vmx *vmx)
5076 {
5077         if (!vmx->nested.vmxon)
5078                 return;
5079         vmx->nested.vmxon = false;
5080         if (vmx->nested.current_vmptr != -1ull) {
5081                 kunmap(vmx->nested.current_vmcs12_page);
5082                 nested_release_page(vmx->nested.current_vmcs12_page);
5083                 vmx->nested.current_vmptr = -1ull;
5084                 vmx->nested.current_vmcs12 = NULL;
5085         }
5086         /* Unpin physical memory we referred to in current vmcs02 */
5087         if (vmx->nested.apic_access_page) {
5088                 nested_release_page(vmx->nested.apic_access_page);
5089                 vmx->nested.apic_access_page = 0;
5090         }
5091
5092         nested_free_all_saved_vmcss(vmx);
5093 }
5094
5095 /* Emulate the VMXOFF instruction */
5096 static int handle_vmoff(struct kvm_vcpu *vcpu)
5097 {
5098         if (!nested_vmx_check_permission(vcpu))
5099                 return 1;
5100         free_nested(to_vmx(vcpu));
5101         skip_emulated_instruction(vcpu);
5102         return 1;
5103 }
5104
5105 /*
5106  * Decode the memory-address operand of a vmx instruction, as recorded on an
5107  * exit caused by such an instruction (run by a guest hypervisor).
5108  * On success, returns 0. When the operand is invalid, returns 1 and throws
5109  * #UD or #GP.
5110  */
5111 static int get_vmx_mem_address(struct kvm_vcpu *vcpu,
5112                                  unsigned long exit_qualification,
5113                                  u32 vmx_instruction_info, gva_t *ret)
5114 {
5115         /*
5116          * According to Vol. 3B, "Information for VM Exits Due to Instruction
5117          * Execution", on an exit, vmx_instruction_info holds most of the
5118          * addressing components of the operand. Only the displacement part
5119          * is put in exit_qualification (see 3B, "Basic VM-Exit Information").
5120          * For how an actual address is calculated from all these components,
5121          * refer to Vol. 1, "Operand Addressing".
5122          */
5123         int  scaling = vmx_instruction_info & 3;
5124         int  addr_size = (vmx_instruction_info >> 7) & 7;
5125         bool is_reg = vmx_instruction_info & (1u << 10);
5126         int  seg_reg = (vmx_instruction_info >> 15) & 7;
5127         int  index_reg = (vmx_instruction_info >> 18) & 0xf;
5128         bool index_is_valid = !(vmx_instruction_info & (1u << 22));
5129         int  base_reg       = (vmx_instruction_info >> 23) & 0xf;
5130         bool base_is_valid  = !(vmx_instruction_info & (1u << 27));
5131
5132         if (is_reg) {
5133                 kvm_queue_exception(vcpu, UD_VECTOR);
5134                 return 1;
5135         }
5136
5137         /* Addr = segment_base + offset */
5138         /* offset = base + [index * scale] + displacement */
5139         *ret = vmx_get_segment_base(vcpu, seg_reg);
5140         if (base_is_valid)
5141                 *ret += kvm_register_read(vcpu, base_reg);
5142         if (index_is_valid)
5143                 *ret += kvm_register_read(vcpu, index_reg)<<scaling;
5144         *ret += exit_qualification; /* holds the displacement */
5145
5146         if (addr_size == 1) /* 32 bit */
5147                 *ret &= 0xffffffff;
5148
5149         /*
5150          * TODO: throw #GP (and return 1) in various cases that the VM*
5151          * instructions require it - e.g., offset beyond segment limit,
5152          * unusable or unreadable/unwritable segment, non-canonical 64-bit
5153          * address, and so on. Currently these are not checked.
5154          */
5155         return 0;
5156 }
5157
5158 /*
5159  * The following 3 functions, nested_vmx_succeed()/failValid()/failInvalid(),
5160  * set the success or error code of an emulated VMX instruction, as specified
5161  * by Vol 2B, VMX Instruction Reference, "Conventions".
5162  */
5163 static void nested_vmx_succeed(struct kvm_vcpu *vcpu)
5164 {
5165         vmx_set_rflags(vcpu, vmx_get_rflags(vcpu)
5166                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5167                             X86_EFLAGS_ZF | X86_EFLAGS_SF | X86_EFLAGS_OF));
5168 }
5169
5170 static void nested_vmx_failInvalid(struct kvm_vcpu *vcpu)
5171 {
5172         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5173                         & ~(X86_EFLAGS_PF | X86_EFLAGS_AF | X86_EFLAGS_ZF |
5174                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5175                         | X86_EFLAGS_CF);
5176 }
5177
5178 static void nested_vmx_failValid(struct kvm_vcpu *vcpu,
5179                                         u32 vm_instruction_error)
5180 {
5181         if (to_vmx(vcpu)->nested.current_vmptr == -1ull) {
5182                 /*
5183                  * failValid writes the error number to the current VMCS, which
5184                  * can't be done there isn't a current VMCS.
5185                  */
5186                 nested_vmx_failInvalid(vcpu);
5187                 return;
5188         }
5189         vmx_set_rflags(vcpu, (vmx_get_rflags(vcpu)
5190                         & ~(X86_EFLAGS_CF | X86_EFLAGS_PF | X86_EFLAGS_AF |
5191                             X86_EFLAGS_SF | X86_EFLAGS_OF))
5192                         | X86_EFLAGS_ZF);
5193         get_vmcs12(vcpu)->vm_instruction_error = vm_instruction_error;
5194 }
5195
5196 /* Emulate the VMCLEAR instruction */
5197 static int handle_vmclear(struct kvm_vcpu *vcpu)
5198 {
5199         struct vcpu_vmx *vmx = to_vmx(vcpu);
5200         gva_t gva;
5201         gpa_t vmptr;
5202         struct vmcs12 *vmcs12;
5203         struct page *page;
5204         struct x86_exception e;
5205
5206         if (!nested_vmx_check_permission(vcpu))
5207                 return 1;
5208
5209         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5210                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5211                 return 1;
5212
5213         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5214                                 sizeof(vmptr), &e)) {
5215                 kvm_inject_page_fault(vcpu, &e);
5216                 return 1;
5217         }
5218
5219         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5220                 nested_vmx_failValid(vcpu, VMXERR_VMCLEAR_INVALID_ADDRESS);
5221                 skip_emulated_instruction(vcpu);
5222                 return 1;
5223         }
5224
5225         if (vmptr == vmx->nested.current_vmptr) {
5226                 kunmap(vmx->nested.current_vmcs12_page);
5227                 nested_release_page(vmx->nested.current_vmcs12_page);
5228                 vmx->nested.current_vmptr = -1ull;
5229                 vmx->nested.current_vmcs12 = NULL;
5230         }
5231
5232         page = nested_get_page(vcpu, vmptr);
5233         if (page == NULL) {
5234                 /*
5235                  * For accurate processor emulation, VMCLEAR beyond available
5236                  * physical memory should do nothing at all. However, it is
5237                  * possible that a nested vmx bug, not a guest hypervisor bug,
5238                  * resulted in this case, so let's shut down before doing any
5239                  * more damage:
5240                  */
5241                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
5242                 return 1;
5243         }
5244         vmcs12 = kmap(page);
5245         vmcs12->launch_state = 0;
5246         kunmap(page);
5247         nested_release_page(page);
5248
5249         nested_free_vmcs02(vmx, vmptr);
5250
5251         skip_emulated_instruction(vcpu);
5252         nested_vmx_succeed(vcpu);
5253         return 1;
5254 }
5255
5256 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch);
5257
5258 /* Emulate the VMLAUNCH instruction */
5259 static int handle_vmlaunch(struct kvm_vcpu *vcpu)
5260 {
5261         return nested_vmx_run(vcpu, true);
5262 }
5263
5264 /* Emulate the VMRESUME instruction */
5265 static int handle_vmresume(struct kvm_vcpu *vcpu)
5266 {
5267
5268         return nested_vmx_run(vcpu, false);
5269 }
5270
5271 enum vmcs_field_type {
5272         VMCS_FIELD_TYPE_U16 = 0,
5273         VMCS_FIELD_TYPE_U64 = 1,
5274         VMCS_FIELD_TYPE_U32 = 2,
5275         VMCS_FIELD_TYPE_NATURAL_WIDTH = 3
5276 };
5277
5278 static inline int vmcs_field_type(unsigned long field)
5279 {
5280         if (0x1 & field)        /* the *_HIGH fields are all 32 bit */
5281                 return VMCS_FIELD_TYPE_U32;
5282         return (field >> 13) & 0x3 ;
5283 }
5284
5285 static inline int vmcs_field_readonly(unsigned long field)
5286 {
5287         return (((field >> 10) & 0x3) == 1);
5288 }
5289
5290 /*
5291  * Read a vmcs12 field. Since these can have varying lengths and we return
5292  * one type, we chose the biggest type (u64) and zero-extend the return value
5293  * to that size. Note that the caller, handle_vmread, might need to use only
5294  * some of the bits we return here (e.g., on 32-bit guests, only 32 bits of
5295  * 64-bit fields are to be returned).
5296  */
5297 static inline bool vmcs12_read_any(struct kvm_vcpu *vcpu,
5298                                         unsigned long field, u64 *ret)
5299 {
5300         short offset = vmcs_field_to_offset(field);
5301         char *p;
5302
5303         if (offset < 0)
5304                 return 0;
5305
5306         p = ((char *)(get_vmcs12(vcpu))) + offset;
5307
5308         switch (vmcs_field_type(field)) {
5309         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5310                 *ret = *((natural_width *)p);
5311                 return 1;
5312         case VMCS_FIELD_TYPE_U16:
5313                 *ret = *((u16 *)p);
5314                 return 1;
5315         case VMCS_FIELD_TYPE_U32:
5316                 *ret = *((u32 *)p);
5317                 return 1;
5318         case VMCS_FIELD_TYPE_U64:
5319                 *ret = *((u64 *)p);
5320                 return 1;
5321         default:
5322                 return 0; /* can never happen. */
5323         }
5324 }
5325
5326 /*
5327  * VMX instructions which assume a current vmcs12 (i.e., that VMPTRLD was
5328  * used before) all generate the same failure when it is missing.
5329  */
5330 static int nested_vmx_check_vmcs12(struct kvm_vcpu *vcpu)
5331 {
5332         struct vcpu_vmx *vmx = to_vmx(vcpu);
5333         if (vmx->nested.current_vmptr == -1ull) {
5334                 nested_vmx_failInvalid(vcpu);
5335                 skip_emulated_instruction(vcpu);
5336                 return 0;
5337         }
5338         return 1;
5339 }
5340
5341 static int handle_vmread(struct kvm_vcpu *vcpu)
5342 {
5343         unsigned long field;
5344         u64 field_value;
5345         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5346         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5347         gva_t gva = 0;
5348
5349         if (!nested_vmx_check_permission(vcpu) ||
5350             !nested_vmx_check_vmcs12(vcpu))
5351                 return 1;
5352
5353         /* Decode instruction info and find the field to read */
5354         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5355         /* Read the field, zero-extended to a u64 field_value */
5356         if (!vmcs12_read_any(vcpu, field, &field_value)) {
5357                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5358                 skip_emulated_instruction(vcpu);
5359                 return 1;
5360         }
5361         /*
5362          * Now copy part of this value to register or memory, as requested.
5363          * Note that the number of bits actually copied is 32 or 64 depending
5364          * on the guest's mode (32 or 64 bit), not on the given field's length.
5365          */
5366         if (vmx_instruction_info & (1u << 10)) {
5367                 kvm_register_write(vcpu, (((vmx_instruction_info) >> 3) & 0xf),
5368                         field_value);
5369         } else {
5370                 if (get_vmx_mem_address(vcpu, exit_qualification,
5371                                 vmx_instruction_info, &gva))
5372                         return 1;
5373                 /* _system ok, as nested_vmx_check_permission verified cpl=0 */
5374                 kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, gva,
5375                              &field_value, (is_long_mode(vcpu) ? 8 : 4), NULL);
5376         }
5377
5378         nested_vmx_succeed(vcpu);
5379         skip_emulated_instruction(vcpu);
5380         return 1;
5381 }
5382
5383
5384 static int handle_vmwrite(struct kvm_vcpu *vcpu)
5385 {
5386         unsigned long field;
5387         gva_t gva;
5388         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5389         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5390         char *p;
5391         short offset;
5392         /* The value to write might be 32 or 64 bits, depending on L1's long
5393          * mode, and eventually we need to write that into a field of several
5394          * possible lengths. The code below first zero-extends the value to 64
5395          * bit (field_value), and then copies only the approriate number of
5396          * bits into the vmcs12 field.
5397          */
5398         u64 field_value = 0;
5399         struct x86_exception e;
5400
5401         if (!nested_vmx_check_permission(vcpu) ||
5402             !nested_vmx_check_vmcs12(vcpu))
5403                 return 1;
5404
5405         if (vmx_instruction_info & (1u << 10))
5406                 field_value = kvm_register_read(vcpu,
5407                         (((vmx_instruction_info) >> 3) & 0xf));
5408         else {
5409                 if (get_vmx_mem_address(vcpu, exit_qualification,
5410                                 vmx_instruction_info, &gva))
5411                         return 1;
5412                 if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva,
5413                            &field_value, (is_long_mode(vcpu) ? 8 : 4), &e)) {
5414                         kvm_inject_page_fault(vcpu, &e);
5415                         return 1;
5416                 }
5417         }
5418
5419
5420         field = kvm_register_read(vcpu, (((vmx_instruction_info) >> 28) & 0xf));
5421         if (vmcs_field_readonly(field)) {
5422                 nested_vmx_failValid(vcpu,
5423                         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT);
5424                 skip_emulated_instruction(vcpu);
5425                 return 1;
5426         }
5427
5428         offset = vmcs_field_to_offset(field);
5429         if (offset < 0) {
5430                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5431                 skip_emulated_instruction(vcpu);
5432                 return 1;
5433         }
5434         p = ((char *) get_vmcs12(vcpu)) + offset;
5435
5436         switch (vmcs_field_type(field)) {
5437         case VMCS_FIELD_TYPE_U16:
5438                 *(u16 *)p = field_value;
5439                 break;
5440         case VMCS_FIELD_TYPE_U32:
5441                 *(u32 *)p = field_value;
5442                 break;
5443         case VMCS_FIELD_TYPE_U64:
5444                 *(u64 *)p = field_value;
5445                 break;
5446         case VMCS_FIELD_TYPE_NATURAL_WIDTH:
5447                 *(natural_width *)p = field_value;
5448                 break;
5449         default:
5450                 nested_vmx_failValid(vcpu, VMXERR_UNSUPPORTED_VMCS_COMPONENT);
5451                 skip_emulated_instruction(vcpu);
5452                 return 1;
5453         }
5454
5455         nested_vmx_succeed(vcpu);
5456         skip_emulated_instruction(vcpu);
5457         return 1;
5458 }
5459
5460 /* Emulate the VMPTRLD instruction */
5461 static int handle_vmptrld(struct kvm_vcpu *vcpu)
5462 {
5463         struct vcpu_vmx *vmx = to_vmx(vcpu);
5464         gva_t gva;
5465         gpa_t vmptr;
5466         struct x86_exception e;
5467
5468         if (!nested_vmx_check_permission(vcpu))
5469                 return 1;
5470
5471         if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
5472                         vmcs_read32(VMX_INSTRUCTION_INFO), &gva))
5473                 return 1;
5474
5475         if (kvm_read_guest_virt(&vcpu->arch.emulate_ctxt, gva, &vmptr,
5476                                 sizeof(vmptr), &e)) {
5477                 kvm_inject_page_fault(vcpu, &e);
5478                 return 1;
5479         }
5480
5481         if (!IS_ALIGNED(vmptr, PAGE_SIZE)) {
5482                 nested_vmx_failValid(vcpu, VMXERR_VMPTRLD_INVALID_ADDRESS);
5483                 skip_emulated_instruction(vcpu);
5484                 return 1;
5485         }
5486
5487         if (vmx->nested.current_vmptr != vmptr) {
5488                 struct vmcs12 *new_vmcs12;
5489                 struct page *page;
5490                 page = nested_get_page(vcpu, vmptr);
5491                 if (page == NULL) {
5492                         nested_vmx_failInvalid(vcpu);
5493                         skip_emulated_instruction(vcpu);
5494                         return 1;
5495                 }
5496                 new_vmcs12 = kmap(page);
5497                 if (new_vmcs12->revision_id != VMCS12_REVISION) {
5498                         kunmap(page);
5499                         nested_release_page_clean(page);
5500                         nested_vmx_failValid(vcpu,
5501                                 VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID);
5502                         skip_emulated_instruction(vcpu);
5503                         return 1;
5504                 }
5505                 if (vmx->nested.current_vmptr != -1ull) {
5506                         kunmap(vmx->nested.current_vmcs12_page);
5507                         nested_release_page(vmx->nested.current_vmcs12_page);
5508                 }
5509
5510                 vmx->nested.current_vmptr = vmptr;
5511                 vmx->nested.current_vmcs12 = new_vmcs12;
5512                 vmx->nested.current_vmcs12_page = page;
5513         }
5514
5515         nested_vmx_succeed(vcpu);
5516         skip_emulated_instruction(vcpu);
5517         return 1;
5518 }
5519
5520 /* Emulate the VMPTRST instruction */
5521 static int handle_vmptrst(struct kvm_vcpu *vcpu)
5522 {
5523         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5524         u32 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5525         gva_t vmcs_gva;
5526         struct x86_exception e;
5527
5528         if (!nested_vmx_check_permission(vcpu))
5529                 return 1;
5530
5531         if (get_vmx_mem_address(vcpu, exit_qualification,
5532                         vmx_instruction_info, &vmcs_gva))
5533                 return 1;
5534         /* ok to use *_system, as nested_vmx_check_permission verified cpl=0 */
5535         if (kvm_write_guest_virt_system(&vcpu->arch.emulate_ctxt, vmcs_gva,
5536                                  (void *)&to_vmx(vcpu)->nested.current_vmptr,
5537                                  sizeof(u64), &e)) {
5538                 kvm_inject_page_fault(vcpu, &e);
5539                 return 1;
5540         }
5541         nested_vmx_succeed(vcpu);
5542         skip_emulated_instruction(vcpu);
5543         return 1;
5544 }
5545
5546 /*
5547  * The exit handlers return 1 if the exit was handled fully and guest execution
5548  * may resume.  Otherwise they set the kvm_run parameter to indicate what needs
5549  * to be done to userspace and return 0.
5550  */
5551 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5552         [EXIT_REASON_EXCEPTION_NMI]           = handle_exception,
5553         [EXIT_REASON_EXTERNAL_INTERRUPT]      = handle_external_interrupt,
5554         [EXIT_REASON_TRIPLE_FAULT]            = handle_triple_fault,
5555         [EXIT_REASON_NMI_WINDOW]              = handle_nmi_window,
5556         [EXIT_REASON_IO_INSTRUCTION]          = handle_io,
5557         [EXIT_REASON_CR_ACCESS]               = handle_cr,
5558         [EXIT_REASON_DR_ACCESS]               = handle_dr,
5559         [EXIT_REASON_CPUID]                   = handle_cpuid,
5560         [EXIT_REASON_MSR_READ]                = handle_rdmsr,
5561         [EXIT_REASON_MSR_WRITE]               = handle_wrmsr,
5562         [EXIT_REASON_PENDING_INTERRUPT]       = handle_interrupt_window,
5563         [EXIT_REASON_HLT]                     = handle_halt,
5564         [EXIT_REASON_INVD]                    = handle_invd,
5565         [EXIT_REASON_INVLPG]                  = handle_invlpg,
5566         [EXIT_REASON_VMCALL]                  = handle_vmcall,
5567         [EXIT_REASON_VMCLEAR]                 = handle_vmclear,
5568         [EXIT_REASON_VMLAUNCH]                = handle_vmlaunch,
5569         [EXIT_REASON_VMPTRLD]                 = handle_vmptrld,
5570         [EXIT_REASON_VMPTRST]                 = handle_vmptrst,
5571         [EXIT_REASON_VMREAD]                  = handle_vmread,
5572         [EXIT_REASON_VMRESUME]                = handle_vmresume,
5573         [EXIT_REASON_VMWRITE]                 = handle_vmwrite,
5574         [EXIT_REASON_VMOFF]                   = handle_vmoff,
5575         [EXIT_REASON_VMON]                    = handle_vmon,
5576         [EXIT_REASON_TPR_BELOW_THRESHOLD]     = handle_tpr_below_threshold,
5577         [EXIT_REASON_APIC_ACCESS]             = handle_apic_access,
5578         [EXIT_REASON_WBINVD]                  = handle_wbinvd,
5579         [EXIT_REASON_XSETBV]                  = handle_xsetbv,
5580         [EXIT_REASON_TASK_SWITCH]             = handle_task_switch,
5581         [EXIT_REASON_MCE_DURING_VMENTRY]      = handle_machine_check,
5582         [EXIT_REASON_EPT_VIOLATION]           = handle_ept_violation,
5583         [EXIT_REASON_EPT_MISCONFIG]           = handle_ept_misconfig,
5584         [EXIT_REASON_PAUSE_INSTRUCTION]       = handle_pause,
5585         [EXIT_REASON_MWAIT_INSTRUCTION]       = handle_invalid_op,
5586         [EXIT_REASON_MONITOR_INSTRUCTION]     = handle_invalid_op,
5587 };
5588
5589 static const int kvm_vmx_max_exit_handlers =
5590         ARRAY_SIZE(kvm_vmx_exit_handlers);
5591
5592 /*
5593  * Return 1 if we should exit from L2 to L1 to handle an MSR access access,
5594  * rather than handle it ourselves in L0. I.e., check whether L1 expressed
5595  * disinterest in the current event (read or write a specific MSR) by using an
5596  * MSR bitmap. This may be the case even when L0 doesn't use MSR bitmaps.
5597  */
5598 static bool nested_vmx_exit_handled_msr(struct kvm_vcpu *vcpu,
5599         struct vmcs12 *vmcs12, u32 exit_reason)
5600 {
5601         u32 msr_index = vcpu->arch.regs[VCPU_REGS_RCX];
5602         gpa_t bitmap;
5603
5604         if (!nested_cpu_has(get_vmcs12(vcpu), CPU_BASED_USE_MSR_BITMAPS))
5605                 return 1;
5606
5607         /*
5608          * The MSR_BITMAP page is divided into four 1024-byte bitmaps,
5609          * for the four combinations of read/write and low/high MSR numbers.
5610          * First we need to figure out which of the four to use:
5611          */
5612         bitmap = vmcs12->msr_bitmap;
5613         if (exit_reason == EXIT_REASON_MSR_WRITE)
5614                 bitmap += 2048;
5615         if (msr_index >= 0xc0000000) {
5616                 msr_index -= 0xc0000000;
5617                 bitmap += 1024;
5618         }
5619
5620         /* Then read the msr_index'th bit from this bitmap: */
5621         if (msr_index < 1024*8) {
5622                 unsigned char b;
5623                 kvm_read_guest(vcpu->kvm, bitmap + msr_index/8, &b, 1);
5624                 return 1 & (b >> (msr_index & 7));
5625         } else
5626                 return 1; /* let L1 handle the wrong parameter */
5627 }
5628
5629 /*
5630  * Return 1 if we should exit from L2 to L1 to handle a CR access exit,
5631  * rather than handle it ourselves in L0. I.e., check if L1 wanted to
5632  * intercept (via guest_host_mask etc.) the current event.
5633  */
5634 static bool nested_vmx_exit_handled_cr(struct kvm_vcpu *vcpu,
5635         struct vmcs12 *vmcs12)
5636 {
5637         unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
5638         int cr = exit_qualification & 15;
5639         int reg = (exit_qualification >> 8) & 15;
5640         unsigned long val = kvm_register_read(vcpu, reg);
5641
5642         switch ((exit_qualification >> 4) & 3) {
5643         case 0: /* mov to cr */
5644                 switch (cr) {
5645                 case 0:
5646                         if (vmcs12->cr0_guest_host_mask &
5647                             (val ^ vmcs12->cr0_read_shadow))
5648                                 return 1;
5649                         break;
5650                 case 3:
5651                         if ((vmcs12->cr3_target_count >= 1 &&
5652                                         vmcs12->cr3_target_value0 == val) ||
5653                                 (vmcs12->cr3_target_count >= 2 &&
5654                                         vmcs12->cr3_target_value1 == val) ||
5655                                 (vmcs12->cr3_target_count >= 3 &&
5656                                         vmcs12->cr3_target_value2 == val) ||
5657                                 (vmcs12->cr3_target_count >= 4 &&
5658                                         vmcs12->cr3_target_value3 == val))
5659                                 return 0;
5660                         if (nested_cpu_has(vmcs12, CPU_BASED_CR3_LOAD_EXITING))
5661                                 return 1;
5662                         break;
5663                 case 4:
5664                         if (vmcs12->cr4_guest_host_mask &
5665                             (vmcs12->cr4_read_shadow ^ val))
5666                                 return 1;
5667                         break;
5668                 case 8:
5669                         if (nested_cpu_has(vmcs12, CPU_BASED_CR8_LOAD_EXITING))
5670                                 return 1;
5671                         break;
5672                 }
5673                 break;
5674         case 2: /* clts */
5675                 if ((vmcs12->cr0_guest_host_mask & X86_CR0_TS) &&
5676                     (vmcs12->cr0_read_shadow & X86_CR0_TS))
5677                         return 1;
5678                 break;
5679         case 1: /* mov from cr */
5680                 switch (cr) {
5681                 case 3:
5682                         if (vmcs12->cpu_based_vm_exec_control &
5683                             CPU_BASED_CR3_STORE_EXITING)
5684                                 return 1;
5685                         break;
5686                 case 8:
5687                         if (vmcs12->cpu_based_vm_exec_control &
5688                             CPU_BASED_CR8_STORE_EXITING)
5689                                 return 1;
5690                         break;
5691                 }
5692                 break;
5693         case 3: /* lmsw */
5694                 /*
5695                  * lmsw can change bits 1..3 of cr0, and only set bit 0 of
5696                  * cr0. Other attempted changes are ignored, with no exit.
5697                  */
5698                 if (vmcs12->cr0_guest_host_mask & 0xe &
5699                     (val ^ vmcs12->cr0_read_shadow))
5700                         return 1;
5701                 if ((vmcs12->cr0_guest_host_mask & 0x1) &&
5702                     !(vmcs12->cr0_read_shadow & 0x1) &&
5703                     (val & 0x1))
5704                         return 1;
5705                 break;
5706         }
5707         return 0;
5708 }
5709
5710 /*
5711  * Return 1 if we should exit from L2 to L1 to handle an exit, or 0 if we
5712  * should handle it ourselves in L0 (and then continue L2). Only call this
5713  * when in is_guest_mode (L2).
5714  */
5715 static bool nested_vmx_exit_handled(struct kvm_vcpu *vcpu)
5716 {
5717         u32 exit_reason = vmcs_read32(VM_EXIT_REASON);
5718         u32 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5719         struct vcpu_vmx *vmx = to_vmx(vcpu);
5720         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
5721
5722         if (vmx->nested.nested_run_pending)
5723                 return 0;
5724
5725         if (unlikely(vmx->fail)) {
5726                 pr_info_ratelimited("%s failed vm entry %x\n", __func__,
5727                                     vmcs_read32(VM_INSTRUCTION_ERROR));
5728                 return 1;
5729         }
5730
5731         switch (exit_reason) {
5732         case EXIT_REASON_EXCEPTION_NMI:
5733                 if (!is_exception(intr_info))
5734                         return 0;
5735                 else if (is_page_fault(intr_info))
5736                         return enable_ept;
5737                 return vmcs12->exception_bitmap &
5738                                 (1u << (intr_info & INTR_INFO_VECTOR_MASK));
5739         case EXIT_REASON_EXTERNAL_INTERRUPT:
5740                 return 0;
5741         case EXIT_REASON_TRIPLE_FAULT:
5742                 return 1;
5743         case EXIT_REASON_PENDING_INTERRUPT:
5744         case EXIT_REASON_NMI_WINDOW:
5745                 /*
5746                  * prepare_vmcs02() set the CPU_BASED_VIRTUAL_INTR_PENDING bit
5747                  * (aka Interrupt Window Exiting) only when L1 turned it on,
5748                  * so if we got a PENDING_INTERRUPT exit, this must be for L1.
5749                  * Same for NMI Window Exiting.
5750                  */
5751                 return 1;
5752         case EXIT_REASON_TASK_SWITCH:
5753                 return 1;
5754         case EXIT_REASON_CPUID:
5755                 return 1;
5756         case EXIT_REASON_HLT:
5757                 return nested_cpu_has(vmcs12, CPU_BASED_HLT_EXITING);
5758         case EXIT_REASON_INVD:
5759                 return 1;
5760         case EXIT_REASON_INVLPG:
5761                 return nested_cpu_has(vmcs12, CPU_BASED_INVLPG_EXITING);
5762         case EXIT_REASON_RDPMC:
5763                 return nested_cpu_has(vmcs12, CPU_BASED_RDPMC_EXITING);
5764         case EXIT_REASON_RDTSC:
5765                 return nested_cpu_has(vmcs12, CPU_BASED_RDTSC_EXITING);
5766         case EXIT_REASON_VMCALL: case EXIT_REASON_VMCLEAR:
5767         case EXIT_REASON_VMLAUNCH: case EXIT_REASON_VMPTRLD:
5768         case EXIT_REASON_VMPTRST: case EXIT_REASON_VMREAD:
5769         case EXIT_REASON_VMRESUME: case EXIT_REASON_VMWRITE:
5770         case EXIT_REASON_VMOFF: case EXIT_REASON_VMON:
5771                 /*
5772                  * VMX instructions trap unconditionally. This allows L1 to
5773                  * emulate them for its L2 guest, i.e., allows 3-level nesting!
5774                  */
5775                 return 1;
5776         case EXIT_REASON_CR_ACCESS:
5777                 return nested_vmx_exit_handled_cr(vcpu, vmcs12);
5778         case EXIT_REASON_DR_ACCESS:
5779                 return nested_cpu_has(vmcs12, CPU_BASED_MOV_DR_EXITING);
5780         case EXIT_REASON_IO_INSTRUCTION:
5781                 /* TODO: support IO bitmaps */
5782                 return 1;
5783         case EXIT_REASON_MSR_READ:
5784         case EXIT_REASON_MSR_WRITE:
5785                 return nested_vmx_exit_handled_msr(vcpu, vmcs12, exit_reason);
5786         case EXIT_REASON_INVALID_STATE:
5787                 return 1;
5788         case EXIT_REASON_MWAIT_INSTRUCTION:
5789                 return nested_cpu_has(vmcs12, CPU_BASED_MWAIT_EXITING);
5790         case EXIT_REASON_MONITOR_INSTRUCTION:
5791                 return nested_cpu_has(vmcs12, CPU_BASED_MONITOR_EXITING);
5792         case EXIT_REASON_PAUSE_INSTRUCTION:
5793                 return nested_cpu_has(vmcs12, CPU_BASED_PAUSE_EXITING) ||
5794                         nested_cpu_has2(vmcs12,
5795                                 SECONDARY_EXEC_PAUSE_LOOP_EXITING);
5796         case EXIT_REASON_MCE_DURING_VMENTRY:
5797                 return 0;
5798         case EXIT_REASON_TPR_BELOW_THRESHOLD:
5799                 return 1;
5800         case EXIT_REASON_APIC_ACCESS:
5801                 return nested_cpu_has2(vmcs12,
5802                         SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES);
5803         case EXIT_REASON_EPT_VIOLATION:
5804         case EXIT_REASON_EPT_MISCONFIG:
5805                 return 0;
5806         case EXIT_REASON_WBINVD:
5807                 return nested_cpu_has2(vmcs12, SECONDARY_EXEC_WBINVD_EXITING);
5808         case EXIT_REASON_XSETBV:
5809                 return 1;
5810         default:
5811                 return 1;
5812         }
5813 }
5814
5815 static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
5816 {
5817         *info1 = vmcs_readl(EXIT_QUALIFICATION);
5818         *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
5819 }
5820
5821 /*
5822  * The guest has exited.  See if we can fix it or if we need userspace
5823  * assistance.
5824  */
5825 static int vmx_handle_exit(struct kvm_vcpu *vcpu)
5826 {
5827         struct vcpu_vmx *vmx = to_vmx(vcpu);
5828         u32 exit_reason = vmx->exit_reason;
5829         u32 vectoring_info = vmx->idt_vectoring_info;
5830
5831         /* If guest state is invalid, start emulating */
5832         if (vmx->emulation_required && emulate_invalid_guest_state)
5833                 return handle_invalid_guest_state(vcpu);
5834
5835         /*
5836          * the KVM_REQ_EVENT optimization bit is only on for one entry, and if
5837          * we did not inject a still-pending event to L1 now because of
5838          * nested_run_pending, we need to re-enable this bit.
5839          */
5840         if (vmx->nested.nested_run_pending)
5841                 kvm_make_request(KVM_REQ_EVENT, vcpu);
5842
5843         if (!is_guest_mode(vcpu) && (exit_reason == EXIT_REASON_VMLAUNCH ||
5844             exit_reason == EXIT_REASON_VMRESUME))
5845                 vmx->nested.nested_run_pending = 1;
5846         else
5847                 vmx->nested.nested_run_pending = 0;
5848
5849         if (is_guest_mode(vcpu) && nested_vmx_exit_handled(vcpu)) {
5850                 nested_vmx_vmexit(vcpu);
5851                 return 1;
5852         }
5853
5854         if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5855                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5856                 vcpu->run->fail_entry.hardware_entry_failure_reason
5857                         = exit_reason;
5858                 return 0;
5859         }
5860
5861         if (unlikely(vmx->fail)) {
5862                 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5863                 vcpu->run->fail_entry.hardware_entry_failure_reason
5864                         = vmcs_read32(VM_INSTRUCTION_ERROR);
5865                 return 0;
5866         }
5867
5868         if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5869                         (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5870                         exit_reason != EXIT_REASON_EPT_VIOLATION &&
5871                         exit_reason != EXIT_REASON_TASK_SWITCH))
5872                 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
5873                        "(0x%x) and exit reason is 0x%x\n",
5874                        __func__, vectoring_info, exit_reason);
5875
5876         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked &&
5877             !(is_guest_mode(vcpu) && nested_cpu_has_virtual_nmis(
5878                                         get_vmcs12(vcpu), vcpu)))) {
5879                 if (vmx_interrupt_allowed(vcpu)) {
5880                         vmx->soft_vnmi_blocked = 0;
5881                 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
5882                            vcpu->arch.nmi_pending) {
5883                         /*
5884                          * This CPU don't support us in finding the end of an
5885                          * NMI-blocked window if the guest runs with IRQs
5886                          * disabled. So we pull the trigger after 1 s of
5887                          * futile waiting, but inform the user about this.
5888                          */
5889                         printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5890                                "state on VCPU %d after 1 s timeout\n",
5891                                __func__, vcpu->vcpu_id);
5892                         vmx->soft_vnmi_blocked = 0;
5893                 }
5894         }
5895
5896         if (exit_reason < kvm_vmx_max_exit_handlers
5897             && kvm_vmx_exit_handlers[exit_reason])
5898                 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5899         else {
5900                 vcpu->run->exit_reason = KVM_EXIT_UNKNOWN;
5901                 vcpu->run->hw.hardware_exit_reason = exit_reason;
5902         }
5903         return 0;
5904 }
5905
5906 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
5907 {
5908         if (irr == -1 || tpr < irr) {
5909                 vmcs_write32(TPR_THRESHOLD, 0);
5910                 return;
5911         }
5912
5913         vmcs_write32(TPR_THRESHOLD, irr);
5914 }
5915
5916 static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5917 {
5918         u32 exit_intr_info;
5919
5920         if (!(vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5921               || vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI))
5922                 return;
5923
5924         vmx->exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5925         exit_intr_info = vmx->exit_intr_info;
5926
5927         /* Handle machine checks before interrupts are enabled */
5928         if (is_machine_check(exit_intr_info))
5929                 kvm_machine_check();
5930
5931         /* We need to handle NMIs before interrupts are enabled */
5932         if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
5933             (exit_intr_info & INTR_INFO_VALID_MASK)) {
5934                 kvm_before_handle_nmi(&vmx->vcpu);
5935                 asm("int $2");
5936                 kvm_after_handle_nmi(&vmx->vcpu);
5937         }
5938 }
5939
5940 static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5941 {
5942         u32 exit_intr_info;
5943         bool unblock_nmi;
5944         u8 vector;
5945         bool idtv_info_valid;
5946
5947         idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5948
5949         if (cpu_has_virtual_nmis()) {
5950                 if (vmx->nmi_known_unmasked)
5951                         return;
5952                 /*
5953                  * Can't use vmx->exit_intr_info since we're not sure what
5954                  * the exit reason is.
5955                  */
5956                 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5957                 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5958                 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5959                 /*
5960                  * SDM 3: 27.7.1.2 (September 2008)
5961                  * Re-set bit "block by NMI" before VM entry if vmexit caused by
5962                  * a guest IRET fault.
5963                  * SDM 3: 23.2.2 (September 2008)
5964                  * Bit 12 is undefined in any of the following cases:
5965                  *  If the VM exit sets the valid bit in the IDT-vectoring
5966                  *   information field.
5967                  *  If the VM exit is due to a double fault.
5968                  */
5969                 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5970                     vector != DF_VECTOR && !idtv_info_valid)
5971                         vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5972                                       GUEST_INTR_STATE_NMI);
5973                 else
5974                         vmx->nmi_known_unmasked =
5975                                 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5976                                   & GUEST_INTR_STATE_NMI);
5977         } else if (unlikely(vmx->soft_vnmi_blocked))
5978                 vmx->vnmi_blocked_time +=
5979                         ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
5980 }
5981
5982 static void __vmx_complete_interrupts(struct vcpu_vmx *vmx,
5983                                       u32 idt_vectoring_info,
5984                                       int instr_len_field,
5985                                       int error_code_field)
5986 {
5987         u8 vector;
5988         int type;
5989         bool idtv_info_valid;
5990
5991         idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
5992
5993         vmx->vcpu.arch.nmi_injected = false;
5994         kvm_clear_exception_queue(&vmx->vcpu);
5995         kvm_clear_interrupt_queue(&vmx->vcpu);
5996
5997         if (!idtv_info_valid)
5998                 return;
5999
6000         kvm_make_request(KVM_REQ_EVENT, &vmx->vcpu);
6001
6002         vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
6003         type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
6004
6005         switch (type) {
6006         case INTR_TYPE_NMI_INTR:
6007                 vmx->vcpu.arch.nmi_injected = true;
6008                 /*
6009                  * SDM 3: 27.7.1.2 (September 2008)
6010                  * Clear bit "block by NMI" before VM entry if a NMI
6011                  * delivery faulted.
6012                  */
6013                 vmx_set_nmi_mask(&vmx->vcpu, false);
6014                 break;
6015         case INTR_TYPE_SOFT_EXCEPTION:
6016                 vmx->vcpu.arch.event_exit_inst_len =
6017                         vmcs_read32(instr_len_field);
6018                 /* fall through */
6019         case INTR_TYPE_HARD_EXCEPTION:
6020                 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
6021                         u32 err = vmcs_read32(error_code_field);
6022                         kvm_queue_exception_e(&vmx->vcpu, vector, err);
6023                 } else
6024                         kvm_queue_exception(&vmx->vcpu, vector);
6025                 break;
6026         case INTR_TYPE_SOFT_INTR:
6027                 vmx->vcpu.arch.event_exit_inst_len =
6028                         vmcs_read32(instr_len_field);
6029                 /* fall through */
6030         case INTR_TYPE_EXT_INTR:
6031                 kvm_queue_interrupt(&vmx->vcpu, vector,
6032                         type == INTR_TYPE_SOFT_INTR);
6033                 break;
6034         default:
6035                 break;
6036         }
6037 }
6038
6039 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
6040 {
6041         if (is_guest_mode(&vmx->vcpu))
6042                 return;
6043         __vmx_complete_interrupts(vmx, vmx->idt_vectoring_info,
6044                                   VM_EXIT_INSTRUCTION_LEN,
6045                                   IDT_VECTORING_ERROR_CODE);
6046 }
6047
6048 static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
6049 {
6050         if (is_guest_mode(vcpu))
6051                 return;
6052         __vmx_complete_interrupts(to_vmx(vcpu),
6053                                   vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
6054                                   VM_ENTRY_INSTRUCTION_LEN,
6055                                   VM_ENTRY_EXCEPTION_ERROR_CODE);
6056
6057         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
6058 }
6059
6060 static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
6061 {
6062         int i, nr_msrs;
6063         struct perf_guest_switch_msr *msrs;
6064
6065         msrs = perf_guest_get_msrs(&nr_msrs);
6066
6067         if (!msrs)
6068                 return;
6069
6070         for (i = 0; i < nr_msrs; i++)
6071                 if (msrs[i].host == msrs[i].guest)
6072                         clear_atomic_switch_msr(vmx, msrs[i].msr);
6073                 else
6074                         add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6075                                         msrs[i].host);
6076 }
6077
6078 #ifdef CONFIG_X86_64
6079 #define R "r"
6080 #define Q "q"
6081 #else
6082 #define R "e"
6083 #define Q "l"
6084 #endif
6085
6086 static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
6087 {
6088         struct vcpu_vmx *vmx = to_vmx(vcpu);
6089
6090         if (is_guest_mode(vcpu) && !vmx->nested.nested_run_pending) {
6091                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6092                 if (vmcs12->idt_vectoring_info_field &
6093                                 VECTORING_INFO_VALID_MASK) {
6094                         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6095                                 vmcs12->idt_vectoring_info_field);
6096                         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6097                                 vmcs12->vm_exit_instruction_len);
6098                         if (vmcs12->idt_vectoring_info_field &
6099                                         VECTORING_INFO_DELIVER_CODE_MASK)
6100                                 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6101                                         vmcs12->idt_vectoring_error_code);
6102                 }
6103         }
6104
6105         /* Record the guest's net vcpu time for enforced NMI injections. */
6106         if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
6107                 vmx->entry_time = ktime_get();
6108
6109         /* Don't enter VMX if guest state is invalid, let the exit handler
6110            start emulation until we arrive back to a valid state */
6111         if (vmx->emulation_required && emulate_invalid_guest_state)
6112                 return;
6113
6114         if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6115                 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6116         if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6117                 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
6118
6119         /* When single-stepping over STI and MOV SS, we must clear the
6120          * corresponding interruptibility bits in the guest state. Otherwise
6121          * vmentry fails as it then expects bit 14 (BS) in pending debug
6122          * exceptions being set, but that's not correct for the guest debugging
6123          * case. */
6124         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6125                 vmx_set_interrupt_shadow(vcpu, 0);
6126
6127         atomic_switch_perf_msrs(vmx);
6128
6129         vmx->__launched = vmx->loaded_vmcs->launched;
6130         asm(
6131                 /* Store host registers */
6132                 "push %%"R"dx; push %%"R"bp;"
6133                 "push %%"R"cx \n\t" /* placeholder for guest rcx */
6134                 "push %%"R"cx \n\t"
6135                 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
6136                 "je 1f \n\t"
6137                 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
6138                 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
6139                 "1: \n\t"
6140                 /* Reload cr2 if changed */
6141                 "mov %c[cr2](%0), %%"R"ax \n\t"
6142                 "mov %%cr2, %%"R"dx \n\t"
6143                 "cmp %%"R"ax, %%"R"dx \n\t"
6144                 "je 2f \n\t"
6145                 "mov %%"R"ax, %%cr2 \n\t"
6146                 "2: \n\t"
6147                 /* Check if vmlaunch of vmresume is needed */
6148                 "cmpl $0, %c[launched](%0) \n\t"
6149                 /* Load guest registers.  Don't clobber flags. */
6150                 "mov %c[rax](%0), %%"R"ax \n\t"
6151                 "mov %c[rbx](%0), %%"R"bx \n\t"
6152                 "mov %c[rdx](%0), %%"R"dx \n\t"
6153                 "mov %c[rsi](%0), %%"R"si \n\t"
6154                 "mov %c[rdi](%0), %%"R"di \n\t"
6155                 "mov %c[rbp](%0), %%"R"bp \n\t"
6156 #ifdef CONFIG_X86_64
6157                 "mov %c[r8](%0),  %%r8  \n\t"
6158                 "mov %c[r9](%0),  %%r9  \n\t"
6159                 "mov %c[r10](%0), %%r10 \n\t"
6160                 "mov %c[r11](%0), %%r11 \n\t"
6161                 "mov %c[r12](%0), %%r12 \n\t"
6162                 "mov %c[r13](%0), %%r13 \n\t"
6163                 "mov %c[r14](%0), %%r14 \n\t"
6164                 "mov %c[r15](%0), %%r15 \n\t"
6165 #endif
6166                 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
6167
6168                 /* Enter guest mode */
6169                 "jne .Llaunched \n\t"
6170                 __ex(ASM_VMX_VMLAUNCH) "\n\t"
6171                 "jmp .Lkvm_vmx_return \n\t"
6172                 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
6173                 ".Lkvm_vmx_return: "
6174                 /* Save guest registers, load host registers, keep flags */
6175                 "mov %0, %c[wordsize](%%"R"sp) \n\t"
6176                 "pop %0 \n\t"
6177                 "mov %%"R"ax, %c[rax](%0) \n\t"
6178                 "mov %%"R"bx, %c[rbx](%0) \n\t"
6179                 "pop"Q" %c[rcx](%0) \n\t"
6180                 "mov %%"R"dx, %c[rdx](%0) \n\t"
6181                 "mov %%"R"si, %c[rsi](%0) \n\t"
6182                 "mov %%"R"di, %c[rdi](%0) \n\t"
6183                 "mov %%"R"bp, %c[rbp](%0) \n\t"
6184 #ifdef CONFIG_X86_64
6185                 "mov %%r8,  %c[r8](%0) \n\t"
6186                 "mov %%r9,  %c[r9](%0) \n\t"
6187                 "mov %%r10, %c[r10](%0) \n\t"
6188                 "mov %%r11, %c[r11](%0) \n\t"
6189                 "mov %%r12, %c[r12](%0) \n\t"
6190                 "mov %%r13, %c[r13](%0) \n\t"
6191                 "mov %%r14, %c[r14](%0) \n\t"
6192                 "mov %%r15, %c[r15](%0) \n\t"
6193 #endif
6194                 "mov %%cr2, %%"R"ax   \n\t"
6195                 "mov %%"R"ax, %c[cr2](%0) \n\t"
6196
6197                 "pop  %%"R"bp; pop  %%"R"dx \n\t"
6198                 "setbe %c[fail](%0) \n\t"
6199               : : "c"(vmx), "d"((unsigned long)HOST_RSP),
6200                 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6201                 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6202                 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6203                 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6204                 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6205                 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6206                 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6207                 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6208                 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6209                 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6210 #ifdef CONFIG_X86_64
6211                 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6212                 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6213                 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6214                 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6215                 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6216                 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6217                 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6218                 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6219 #endif
6220                 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6221                 [wordsize]"i"(sizeof(ulong))
6222               : "cc", "memory"
6223                 , R"ax", R"bx", R"di", R"si"
6224 #ifdef CONFIG_X86_64
6225                 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6226 #endif
6227               );
6228
6229         vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6230                                   | (1 << VCPU_EXREG_RFLAGS)
6231                                   | (1 << VCPU_EXREG_CPL)
6232                                   | (1 << VCPU_EXREG_PDPTR)
6233                                   | (1 << VCPU_EXREG_SEGMENTS)
6234                                   | (1 << VCPU_EXREG_CR3));
6235         vcpu->arch.regs_dirty = 0;
6236
6237         vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
6238
6239         if (is_guest_mode(vcpu)) {
6240                 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6241                 vmcs12->idt_vectoring_info_field = vmx->idt_vectoring_info;
6242                 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
6243                         vmcs12->idt_vectoring_error_code =
6244                                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6245                         vmcs12->vm_exit_instruction_len =
6246                                 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6247                 }
6248         }
6249
6250         asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
6251         vmx->loaded_vmcs->launched = 1;
6252
6253         vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
6254         trace_kvm_exit(vmx->exit_reason, vcpu, KVM_ISA_VMX);
6255
6256         vmx_complete_atomic_exit(vmx);
6257         vmx_recover_nmi_blocking(vmx);
6258         vmx_complete_interrupts(vmx);
6259 }
6260
6261 #undef R
6262 #undef Q
6263
6264 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
6265 {
6266         struct vcpu_vmx *vmx = to_vmx(vcpu);
6267
6268         free_vpid(vmx);
6269         free_nested(vmx);
6270         free_loaded_vmcs(vmx->loaded_vmcs);
6271         kfree(vmx->guest_msrs);
6272         kvm_vcpu_uninit(vcpu);
6273         kmem_cache_free(kvm_vcpu_cache, vmx);
6274 }
6275
6276 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6277 {
6278         int err;
6279         struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6280         int cpu;
6281
6282         if (!vmx)
6283                 return ERR_PTR(-ENOMEM);
6284
6285         allocate_vpid(vmx);
6286
6287         err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6288         if (err)
6289                 goto free_vcpu;
6290
6291         vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6292         err = -ENOMEM;
6293         if (!vmx->guest_msrs) {
6294                 goto uninit_vcpu;
6295         }
6296
6297         vmx->loaded_vmcs = &vmx->vmcs01;
6298         vmx->loaded_vmcs->vmcs = alloc_vmcs();
6299         if (!vmx->loaded_vmcs->vmcs)
6300                 goto free_msrs;
6301         if (!vmm_exclusive)
6302                 kvm_cpu_vmxon(__pa(per_cpu(vmxarea, raw_smp_processor_id())));
6303         loaded_vmcs_init(vmx->loaded_vmcs);
6304         if (!vmm_exclusive)
6305                 kvm_cpu_vmxoff();
6306
6307         cpu = get_cpu();
6308         vmx_vcpu_load(&vmx->vcpu, cpu);
6309         vmx->vcpu.cpu = cpu;
6310         err = vmx_vcpu_setup(vmx);
6311         vmx_vcpu_put(&vmx->vcpu);
6312         put_cpu();
6313         if (err)
6314                 goto free_vmcs;
6315         if (vm_need_virtualize_apic_accesses(kvm))
6316                 err = alloc_apic_access_page(kvm);
6317                 if (err)
6318                         goto free_vmcs;
6319
6320         if (enable_ept) {
6321                 if (!kvm->arch.ept_identity_map_addr)
6322                         kvm->arch.ept_identity_map_addr =
6323                                 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
6324                 err = -ENOMEM;
6325                 if (alloc_identity_pagetable(kvm) != 0)
6326                         goto free_vmcs;
6327                 if (!init_rmode_identity_map(kvm))
6328                         goto free_vmcs;
6329         }
6330
6331         vmx->nested.current_vmptr = -1ull;
6332         vmx->nested.current_vmcs12 = NULL;
6333
6334         return &vmx->vcpu;
6335
6336 free_vmcs:
6337         free_vmcs(vmx->loaded_vmcs->vmcs);
6338 free_msrs:
6339         kfree(vmx->guest_msrs);
6340 uninit_vcpu:
6341         kvm_vcpu_uninit(&vmx->vcpu);
6342 free_vcpu:
6343         free_vpid(vmx);
6344         kmem_cache_free(kvm_vcpu_cache, vmx);
6345         return ERR_PTR(err);
6346 }
6347
6348 static void __init vmx_check_processor_compat(void *rtn)
6349 {
6350         struct vmcs_config vmcs_conf;
6351
6352         *(int *)rtn = 0;
6353         if (setup_vmcs_config(&vmcs_conf) < 0)
6354                 *(int *)rtn = -EIO;
6355         if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6356                 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6357                                 smp_processor_id());
6358                 *(int *)rtn = -EIO;
6359         }
6360 }
6361
6362 static int get_ept_level(void)
6363 {
6364         return VMX_EPT_DEFAULT_GAW + 1;
6365 }
6366
6367 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
6368 {
6369         u64 ret;
6370
6371         /* For VT-d and EPT combination
6372          * 1. MMIO: always map as UC
6373          * 2. EPT with VT-d:
6374          *   a. VT-d without snooping control feature: can't guarantee the
6375          *      result, try to trust guest.
6376          *   b. VT-d with snooping control feature: snooping control feature of
6377          *      VT-d engine can guarantee the cache correctness. Just set it
6378          *      to WB to keep consistent with host. So the same as item 3.
6379          * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6380          *    consistent with host MTRR
6381          */
6382         if (is_mmio)
6383                 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
6384         else if (vcpu->kvm->arch.iommu_domain &&
6385                 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
6386                 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
6387                       VMX_EPT_MT_EPTE_SHIFT;
6388         else
6389                 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
6390                         | VMX_EPT_IPAT_BIT;
6391
6392         return ret;
6393 }
6394
6395 static int vmx_get_lpage_level(void)
6396 {
6397         if (enable_ept && !cpu_has_vmx_ept_1g_page())
6398                 return PT_DIRECTORY_LEVEL;
6399         else
6400                 /* For shadow and EPT supported 1GB page */
6401                 return PT_PDPE_LEVEL;
6402 }
6403
6404 static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6405 {
6406         struct kvm_cpuid_entry2 *best;
6407         struct vcpu_vmx *vmx = to_vmx(vcpu);
6408         u32 exec_control;
6409
6410         vmx->rdtscp_enabled = false;
6411         if (vmx_rdtscp_supported()) {
6412                 exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
6413                 if (exec_control & SECONDARY_EXEC_RDTSCP) {
6414                         best = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
6415                         if (best && (best->edx & bit(X86_FEATURE_RDTSCP)))
6416                                 vmx->rdtscp_enabled = true;
6417                         else {
6418                                 exec_control &= ~SECONDARY_EXEC_RDTSCP;
6419                                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6420                                                 exec_control);
6421                         }
6422                 }
6423         }
6424 }
6425
6426 static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6427 {
6428         if (func == 1 && nested)
6429                 entry->ecx |= bit(X86_FEATURE_VMX);
6430 }
6431
6432 /*
6433  * prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
6434  * L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
6435  * with L0's requirements for its guest (a.k.a. vmsc01), so we can run the L2
6436  * guest in a way that will both be appropriate to L1's requests, and our
6437  * needs. In addition to modifying the active vmcs (which is vmcs02), this
6438  * function also has additional necessary side-effects, like setting various
6439  * vcpu->arch fields.
6440  */
6441 static void prepare_vmcs02(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6442 {
6443         struct vcpu_vmx *vmx = to_vmx(vcpu);
6444         u32 exec_control;
6445
6446         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->guest_es_selector);
6447         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->guest_cs_selector);
6448         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->guest_ss_selector);
6449         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->guest_ds_selector);
6450         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->guest_fs_selector);
6451         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->guest_gs_selector);
6452         vmcs_write16(GUEST_LDTR_SELECTOR, vmcs12->guest_ldtr_selector);
6453         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->guest_tr_selector);
6454         vmcs_write32(GUEST_ES_LIMIT, vmcs12->guest_es_limit);
6455         vmcs_write32(GUEST_CS_LIMIT, vmcs12->guest_cs_limit);
6456         vmcs_write32(GUEST_SS_LIMIT, vmcs12->guest_ss_limit);
6457         vmcs_write32(GUEST_DS_LIMIT, vmcs12->guest_ds_limit);
6458         vmcs_write32(GUEST_FS_LIMIT, vmcs12->guest_fs_limit);
6459         vmcs_write32(GUEST_GS_LIMIT, vmcs12->guest_gs_limit);
6460         vmcs_write32(GUEST_LDTR_LIMIT, vmcs12->guest_ldtr_limit);
6461         vmcs_write32(GUEST_TR_LIMIT, vmcs12->guest_tr_limit);
6462         vmcs_write32(GUEST_GDTR_LIMIT, vmcs12->guest_gdtr_limit);
6463         vmcs_write32(GUEST_IDTR_LIMIT, vmcs12->guest_idtr_limit);
6464         vmcs_write32(GUEST_ES_AR_BYTES, vmcs12->guest_es_ar_bytes);
6465         vmcs_write32(GUEST_CS_AR_BYTES, vmcs12->guest_cs_ar_bytes);
6466         vmcs_write32(GUEST_SS_AR_BYTES, vmcs12->guest_ss_ar_bytes);
6467         vmcs_write32(GUEST_DS_AR_BYTES, vmcs12->guest_ds_ar_bytes);
6468         vmcs_write32(GUEST_FS_AR_BYTES, vmcs12->guest_fs_ar_bytes);
6469         vmcs_write32(GUEST_GS_AR_BYTES, vmcs12->guest_gs_ar_bytes);
6470         vmcs_write32(GUEST_LDTR_AR_BYTES, vmcs12->guest_ldtr_ar_bytes);
6471         vmcs_write32(GUEST_TR_AR_BYTES, vmcs12->guest_tr_ar_bytes);
6472         vmcs_writel(GUEST_ES_BASE, vmcs12->guest_es_base);
6473         vmcs_writel(GUEST_CS_BASE, vmcs12->guest_cs_base);
6474         vmcs_writel(GUEST_SS_BASE, vmcs12->guest_ss_base);
6475         vmcs_writel(GUEST_DS_BASE, vmcs12->guest_ds_base);
6476         vmcs_writel(GUEST_FS_BASE, vmcs12->guest_fs_base);
6477         vmcs_writel(GUEST_GS_BASE, vmcs12->guest_gs_base);
6478         vmcs_writel(GUEST_LDTR_BASE, vmcs12->guest_ldtr_base);
6479         vmcs_writel(GUEST_TR_BASE, vmcs12->guest_tr_base);
6480         vmcs_writel(GUEST_GDTR_BASE, vmcs12->guest_gdtr_base);
6481         vmcs_writel(GUEST_IDTR_BASE, vmcs12->guest_idtr_base);
6482
6483         vmcs_write64(GUEST_IA32_DEBUGCTL, vmcs12->guest_ia32_debugctl);
6484         vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
6485                 vmcs12->vm_entry_intr_info_field);
6486         vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE,
6487                 vmcs12->vm_entry_exception_error_code);
6488         vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
6489                 vmcs12->vm_entry_instruction_len);
6490         vmcs_write32(GUEST_INTERRUPTIBILITY_INFO,
6491                 vmcs12->guest_interruptibility_info);
6492         vmcs_write32(GUEST_ACTIVITY_STATE, vmcs12->guest_activity_state);
6493         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->guest_sysenter_cs);
6494         vmcs_writel(GUEST_DR7, vmcs12->guest_dr7);
6495         vmcs_writel(GUEST_RFLAGS, vmcs12->guest_rflags);
6496         vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS,
6497                 vmcs12->guest_pending_dbg_exceptions);
6498         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->guest_sysenter_esp);
6499         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->guest_sysenter_eip);
6500
6501         vmcs_write64(VMCS_LINK_POINTER, -1ull);
6502
6503         vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
6504                 (vmcs_config.pin_based_exec_ctrl |
6505                  vmcs12->pin_based_vm_exec_control));
6506
6507         /*
6508          * Whether page-faults are trapped is determined by a combination of
6509          * 3 settings: PFEC_MASK, PFEC_MATCH and EXCEPTION_BITMAP.PF.
6510          * If enable_ept, L0 doesn't care about page faults and we should
6511          * set all of these to L1's desires. However, if !enable_ept, L0 does
6512          * care about (at least some) page faults, and because it is not easy
6513          * (if at all possible?) to merge L0 and L1's desires, we simply ask
6514          * to exit on each and every L2 page fault. This is done by setting
6515          * MASK=MATCH=0 and (see below) EB.PF=1.
6516          * Note that below we don't need special code to set EB.PF beyond the
6517          * "or"ing of the EB of vmcs01 and vmcs12, because when enable_ept,
6518          * vmcs01's EB.PF is 0 so the "or" will take vmcs12's value, and when
6519          * !enable_ept, EB.PF is 1, so the "or" will always be 1.
6520          *
6521          * A problem with this approach (when !enable_ept) is that L1 may be
6522          * injected with more page faults than it asked for. This could have
6523          * caused problems, but in practice existing hypervisors don't care.
6524          * To fix this, we will need to emulate the PFEC checking (on the L1
6525          * page tables), using walk_addr(), when injecting PFs to L1.
6526          */
6527         vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK,
6528                 enable_ept ? vmcs12->page_fault_error_code_mask : 0);
6529         vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH,
6530                 enable_ept ? vmcs12->page_fault_error_code_match : 0);
6531
6532         if (cpu_has_secondary_exec_ctrls()) {
6533                 u32 exec_control = vmx_secondary_exec_control(vmx);
6534                 if (!vmx->rdtscp_enabled)
6535                         exec_control &= ~SECONDARY_EXEC_RDTSCP;
6536                 /* Take the following fields only from vmcs12 */
6537                 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6538                 if (nested_cpu_has(vmcs12,
6539                                 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS))
6540                         exec_control |= vmcs12->secondary_vm_exec_control;
6541
6542                 if (exec_control & SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) {
6543                         /*
6544                          * Translate L1 physical address to host physical
6545                          * address for vmcs02. Keep the page pinned, so this
6546                          * physical address remains valid. We keep a reference
6547                          * to it so we can release it later.
6548                          */
6549                         if (vmx->nested.apic_access_page) /* shouldn't happen */
6550                                 nested_release_page(vmx->nested.apic_access_page);
6551                         vmx->nested.apic_access_page =
6552                                 nested_get_page(vcpu, vmcs12->apic_access_addr);
6553                         /*
6554                          * If translation failed, no matter: This feature asks
6555                          * to exit when accessing the given address, and if it
6556                          * can never be accessed, this feature won't do
6557                          * anything anyway.
6558                          */
6559                         if (!vmx->nested.apic_access_page)
6560                                 exec_control &=
6561                                   ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
6562                         else
6563                                 vmcs_write64(APIC_ACCESS_ADDR,
6564                                   page_to_phys(vmx->nested.apic_access_page));
6565                 }
6566
6567                 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
6568         }
6569
6570
6571         /*
6572          * Set host-state according to L0's settings (vmcs12 is irrelevant here)
6573          * Some constant fields are set here by vmx_set_constant_host_state().
6574          * Other fields are different per CPU, and will be set later when
6575          * vmx_vcpu_load() is called, and when vmx_save_host_state() is called.
6576          */
6577         vmx_set_constant_host_state();
6578
6579         /*
6580          * HOST_RSP is normally set correctly in vmx_vcpu_run() just before
6581          * entry, but only if the current (host) sp changed from the value
6582          * we wrote last (vmx->host_rsp). This cache is no longer relevant
6583          * if we switch vmcs, and rather than hold a separate cache per vmcs,
6584          * here we just force the write to happen on entry.
6585          */
6586         vmx->host_rsp = 0;
6587
6588         exec_control = vmx_exec_control(vmx); /* L0's desires */
6589         exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
6590         exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
6591         exec_control &= ~CPU_BASED_TPR_SHADOW;
6592         exec_control |= vmcs12->cpu_based_vm_exec_control;
6593         /*
6594          * Merging of IO and MSR bitmaps not currently supported.
6595          * Rather, exit every time.
6596          */
6597         exec_control &= ~CPU_BASED_USE_MSR_BITMAPS;
6598         exec_control &= ~CPU_BASED_USE_IO_BITMAPS;
6599         exec_control |= CPU_BASED_UNCOND_IO_EXITING;
6600
6601         vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
6602
6603         /* EXCEPTION_BITMAP and CR0_GUEST_HOST_MASK should basically be the
6604          * bitwise-or of what L1 wants to trap for L2, and what we want to
6605          * trap. Note that CR0.TS also needs updating - we do this later.
6606          */
6607         update_exception_bitmap(vcpu);
6608         vcpu->arch.cr0_guest_owned_bits &= ~vmcs12->cr0_guest_host_mask;
6609         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6610
6611         /* Note: IA32_MODE, LOAD_IA32_EFER are modified by vmx_set_efer below */
6612         vmcs_write32(VM_EXIT_CONTROLS,
6613                 vmcs12->vm_exit_controls | vmcs_config.vmexit_ctrl);
6614         vmcs_write32(VM_ENTRY_CONTROLS, vmcs12->vm_entry_controls |
6615                 (vmcs_config.vmentry_ctrl & ~VM_ENTRY_IA32E_MODE));
6616
6617         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_PAT)
6618                 vmcs_write64(GUEST_IA32_PAT, vmcs12->guest_ia32_pat);
6619         else if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
6620                 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
6621
6622
6623         set_cr4_guest_host_mask(vmx);
6624
6625         if (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING)
6626                 vmcs_write64(TSC_OFFSET,
6627                         vmx->nested.vmcs01_tsc_offset + vmcs12->tsc_offset);
6628         else
6629                 vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
6630
6631         if (enable_vpid) {
6632                 /*
6633                  * Trivially support vpid by letting L2s share their parent
6634                  * L1's vpid. TODO: move to a more elaborate solution, giving
6635                  * each L2 its own vpid and exposing the vpid feature to L1.
6636                  */
6637                 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
6638                 vmx_flush_tlb(vcpu);
6639         }
6640
6641         if (vmcs12->vm_entry_controls & VM_ENTRY_LOAD_IA32_EFER)
6642                 vcpu->arch.efer = vmcs12->guest_ia32_efer;
6643         if (vmcs12->vm_entry_controls & VM_ENTRY_IA32E_MODE)
6644                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6645         else
6646                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6647         /* Note: modifies VM_ENTRY/EXIT_CONTROLS and GUEST/HOST_IA32_EFER */
6648         vmx_set_efer(vcpu, vcpu->arch.efer);
6649
6650         /*
6651          * This sets GUEST_CR0 to vmcs12->guest_cr0, with possibly a modified
6652          * TS bit (for lazy fpu) and bits which we consider mandatory enabled.
6653          * The CR0_READ_SHADOW is what L2 should have expected to read given
6654          * the specifications by L1; It's not enough to take
6655          * vmcs12->cr0_read_shadow because on our cr0_guest_host_mask we we
6656          * have more bits than L1 expected.
6657          */
6658         vmx_set_cr0(vcpu, vmcs12->guest_cr0);
6659         vmcs_writel(CR0_READ_SHADOW, nested_read_cr0(vmcs12));
6660
6661         vmx_set_cr4(vcpu, vmcs12->guest_cr4);
6662         vmcs_writel(CR4_READ_SHADOW, nested_read_cr4(vmcs12));
6663
6664         /* shadow page tables on either EPT or shadow page tables */
6665         kvm_set_cr3(vcpu, vmcs12->guest_cr3);
6666         kvm_mmu_reset_context(vcpu);
6667
6668         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->guest_rsp);
6669         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->guest_rip);
6670 }
6671
6672 /*
6673  * nested_vmx_run() handles a nested entry, i.e., a VMLAUNCH or VMRESUME on L1
6674  * for running an L2 nested guest.
6675  */
6676 static int nested_vmx_run(struct kvm_vcpu *vcpu, bool launch)
6677 {
6678         struct vmcs12 *vmcs12;
6679         struct vcpu_vmx *vmx = to_vmx(vcpu);
6680         int cpu;
6681         struct loaded_vmcs *vmcs02;
6682
6683         if (!nested_vmx_check_permission(vcpu) ||
6684             !nested_vmx_check_vmcs12(vcpu))
6685                 return 1;
6686
6687         skip_emulated_instruction(vcpu);
6688         vmcs12 = get_vmcs12(vcpu);
6689
6690         /*
6691          * The nested entry process starts with enforcing various prerequisites
6692          * on vmcs12 as required by the Intel SDM, and act appropriately when
6693          * they fail: As the SDM explains, some conditions should cause the
6694          * instruction to fail, while others will cause the instruction to seem
6695          * to succeed, but return an EXIT_REASON_INVALID_STATE.
6696          * To speed up the normal (success) code path, we should avoid checking
6697          * for misconfigurations which will anyway be caught by the processor
6698          * when using the merged vmcs02.
6699          */
6700         if (vmcs12->launch_state == launch) {
6701                 nested_vmx_failValid(vcpu,
6702                         launch ? VMXERR_VMLAUNCH_NONCLEAR_VMCS
6703                                : VMXERR_VMRESUME_NONLAUNCHED_VMCS);
6704                 return 1;
6705         }
6706
6707         if ((vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_MSR_BITMAPS) &&
6708                         !IS_ALIGNED(vmcs12->msr_bitmap, PAGE_SIZE)) {
6709                 /*TODO: Also verify bits beyond physical address width are 0*/
6710                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6711                 return 1;
6712         }
6713
6714         if (nested_cpu_has2(vmcs12, SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES) &&
6715                         !IS_ALIGNED(vmcs12->apic_access_addr, PAGE_SIZE)) {
6716                 /*TODO: Also verify bits beyond physical address width are 0*/
6717                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6718                 return 1;
6719         }
6720
6721         if (vmcs12->vm_entry_msr_load_count > 0 ||
6722             vmcs12->vm_exit_msr_load_count > 0 ||
6723             vmcs12->vm_exit_msr_store_count > 0) {
6724                 pr_warn_ratelimited("%s: VMCS MSR_{LOAD,STORE} unsupported\n",
6725                                     __func__);
6726                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6727                 return 1;
6728         }
6729
6730         if (!vmx_control_verify(vmcs12->cpu_based_vm_exec_control,
6731               nested_vmx_procbased_ctls_low, nested_vmx_procbased_ctls_high) ||
6732             !vmx_control_verify(vmcs12->secondary_vm_exec_control,
6733               nested_vmx_secondary_ctls_low, nested_vmx_secondary_ctls_high) ||
6734             !vmx_control_verify(vmcs12->pin_based_vm_exec_control,
6735               nested_vmx_pinbased_ctls_low, nested_vmx_pinbased_ctls_high) ||
6736             !vmx_control_verify(vmcs12->vm_exit_controls,
6737               nested_vmx_exit_ctls_low, nested_vmx_exit_ctls_high) ||
6738             !vmx_control_verify(vmcs12->vm_entry_controls,
6739               nested_vmx_entry_ctls_low, nested_vmx_entry_ctls_high))
6740         {
6741                 nested_vmx_failValid(vcpu, VMXERR_ENTRY_INVALID_CONTROL_FIELD);
6742                 return 1;
6743         }
6744
6745         if (((vmcs12->host_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6746             ((vmcs12->host_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6747                 nested_vmx_failValid(vcpu,
6748                         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD);
6749                 return 1;
6750         }
6751
6752         if (((vmcs12->guest_cr0 & VMXON_CR0_ALWAYSON) != VMXON_CR0_ALWAYSON) ||
6753             ((vmcs12->guest_cr4 & VMXON_CR4_ALWAYSON) != VMXON_CR4_ALWAYSON)) {
6754                 nested_vmx_entry_failure(vcpu, vmcs12,
6755                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_DEFAULT);
6756                 return 1;
6757         }
6758         if (vmcs12->vmcs_link_pointer != -1ull) {
6759                 nested_vmx_entry_failure(vcpu, vmcs12,
6760                         EXIT_REASON_INVALID_STATE, ENTRY_FAIL_VMCS_LINK_PTR);
6761                 return 1;
6762         }
6763
6764         /*
6765          * We're finally done with prerequisite checking, and can start with
6766          * the nested entry.
6767          */
6768
6769         vmcs02 = nested_get_current_vmcs02(vmx);
6770         if (!vmcs02)
6771                 return -ENOMEM;
6772
6773         enter_guest_mode(vcpu);
6774
6775         vmx->nested.vmcs01_tsc_offset = vmcs_read64(TSC_OFFSET);
6776
6777         cpu = get_cpu();
6778         vmx->loaded_vmcs = vmcs02;
6779         vmx_vcpu_put(vcpu);
6780         vmx_vcpu_load(vcpu, cpu);
6781         vcpu->cpu = cpu;
6782         put_cpu();
6783
6784         vmcs12->launch_state = 1;
6785
6786         prepare_vmcs02(vcpu, vmcs12);
6787
6788         /*
6789          * Note no nested_vmx_succeed or nested_vmx_fail here. At this point
6790          * we are no longer running L1, and VMLAUNCH/VMRESUME has not yet
6791          * returned as far as L1 is concerned. It will only return (and set
6792          * the success flag) when L2 exits (see nested_vmx_vmexit()).
6793          */
6794         return 1;
6795 }
6796
6797 /*
6798  * On a nested exit from L2 to L1, vmcs12.guest_cr0 might not be up-to-date
6799  * because L2 may have changed some cr0 bits directly (CRO_GUEST_HOST_MASK).
6800  * This function returns the new value we should put in vmcs12.guest_cr0.
6801  * It's not enough to just return the vmcs02 GUEST_CR0. Rather,
6802  *  1. Bits that neither L0 nor L1 trapped, were set directly by L2 and are now
6803  *     available in vmcs02 GUEST_CR0. (Note: It's enough to check that L0
6804  *     didn't trap the bit, because if L1 did, so would L0).
6805  *  2. Bits that L1 asked to trap (and therefore L0 also did) could not have
6806  *     been modified by L2, and L1 knows it. So just leave the old value of
6807  *     the bit from vmcs12.guest_cr0. Note that the bit from vmcs02 GUEST_CR0
6808  *     isn't relevant, because if L0 traps this bit it can set it to anything.
6809  *  3. Bits that L1 didn't trap, but L0 did. L1 believes the guest could have
6810  *     changed these bits, and therefore they need to be updated, but L0
6811  *     didn't necessarily allow them to be changed in GUEST_CR0 - and rather
6812  *     put them in vmcs02 CR0_READ_SHADOW. So take these bits from there.
6813  */
6814 static inline unsigned long
6815 vmcs12_guest_cr0(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6816 {
6817         return
6818         /*1*/   (vmcs_readl(GUEST_CR0) & vcpu->arch.cr0_guest_owned_bits) |
6819         /*2*/   (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask) |
6820         /*3*/   (vmcs_readl(CR0_READ_SHADOW) & ~(vmcs12->cr0_guest_host_mask |
6821                         vcpu->arch.cr0_guest_owned_bits));
6822 }
6823
6824 static inline unsigned long
6825 vmcs12_guest_cr4(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6826 {
6827         return
6828         /*1*/   (vmcs_readl(GUEST_CR4) & vcpu->arch.cr4_guest_owned_bits) |
6829         /*2*/   (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask) |
6830         /*3*/   (vmcs_readl(CR4_READ_SHADOW) & ~(vmcs12->cr4_guest_host_mask |
6831                         vcpu->arch.cr4_guest_owned_bits));
6832 }
6833
6834 /*
6835  * prepare_vmcs12 is part of what we need to do when the nested L2 guest exits
6836  * and we want to prepare to run its L1 parent. L1 keeps a vmcs for L2 (vmcs12),
6837  * and this function updates it to reflect the changes to the guest state while
6838  * L2 was running (and perhaps made some exits which were handled directly by L0
6839  * without going back to L1), and to reflect the exit reason.
6840  * Note that we do not have to copy here all VMCS fields, just those that
6841  * could have changed by the L2 guest or the exit - i.e., the guest-state and
6842  * exit-information fields only. Other fields are modified by L1 with VMWRITE,
6843  * which already writes to vmcs12 directly.
6844  */
6845 void prepare_vmcs12(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6846 {
6847         /* update guest state fields: */
6848         vmcs12->guest_cr0 = vmcs12_guest_cr0(vcpu, vmcs12);
6849         vmcs12->guest_cr4 = vmcs12_guest_cr4(vcpu, vmcs12);
6850
6851         kvm_get_dr(vcpu, 7, (unsigned long *)&vmcs12->guest_dr7);
6852         vmcs12->guest_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
6853         vmcs12->guest_rip = kvm_register_read(vcpu, VCPU_REGS_RIP);
6854         vmcs12->guest_rflags = vmcs_readl(GUEST_RFLAGS);
6855
6856         vmcs12->guest_es_selector = vmcs_read16(GUEST_ES_SELECTOR);
6857         vmcs12->guest_cs_selector = vmcs_read16(GUEST_CS_SELECTOR);
6858         vmcs12->guest_ss_selector = vmcs_read16(GUEST_SS_SELECTOR);
6859         vmcs12->guest_ds_selector = vmcs_read16(GUEST_DS_SELECTOR);
6860         vmcs12->guest_fs_selector = vmcs_read16(GUEST_FS_SELECTOR);
6861         vmcs12->guest_gs_selector = vmcs_read16(GUEST_GS_SELECTOR);
6862         vmcs12->guest_ldtr_selector = vmcs_read16(GUEST_LDTR_SELECTOR);
6863         vmcs12->guest_tr_selector = vmcs_read16(GUEST_TR_SELECTOR);
6864         vmcs12->guest_es_limit = vmcs_read32(GUEST_ES_LIMIT);
6865         vmcs12->guest_cs_limit = vmcs_read32(GUEST_CS_LIMIT);
6866         vmcs12->guest_ss_limit = vmcs_read32(GUEST_SS_LIMIT);
6867         vmcs12->guest_ds_limit = vmcs_read32(GUEST_DS_LIMIT);
6868         vmcs12->guest_fs_limit = vmcs_read32(GUEST_FS_LIMIT);
6869         vmcs12->guest_gs_limit = vmcs_read32(GUEST_GS_LIMIT);
6870         vmcs12->guest_ldtr_limit = vmcs_read32(GUEST_LDTR_LIMIT);
6871         vmcs12->guest_tr_limit = vmcs_read32(GUEST_TR_LIMIT);
6872         vmcs12->guest_gdtr_limit = vmcs_read32(GUEST_GDTR_LIMIT);
6873         vmcs12->guest_idtr_limit = vmcs_read32(GUEST_IDTR_LIMIT);
6874         vmcs12->guest_es_ar_bytes = vmcs_read32(GUEST_ES_AR_BYTES);
6875         vmcs12->guest_cs_ar_bytes = vmcs_read32(GUEST_CS_AR_BYTES);
6876         vmcs12->guest_ss_ar_bytes = vmcs_read32(GUEST_SS_AR_BYTES);
6877         vmcs12->guest_ds_ar_bytes = vmcs_read32(GUEST_DS_AR_BYTES);
6878         vmcs12->guest_fs_ar_bytes = vmcs_read32(GUEST_FS_AR_BYTES);
6879         vmcs12->guest_gs_ar_bytes = vmcs_read32(GUEST_GS_AR_BYTES);
6880         vmcs12->guest_ldtr_ar_bytes = vmcs_read32(GUEST_LDTR_AR_BYTES);
6881         vmcs12->guest_tr_ar_bytes = vmcs_read32(GUEST_TR_AR_BYTES);
6882         vmcs12->guest_es_base = vmcs_readl(GUEST_ES_BASE);
6883         vmcs12->guest_cs_base = vmcs_readl(GUEST_CS_BASE);
6884         vmcs12->guest_ss_base = vmcs_readl(GUEST_SS_BASE);
6885         vmcs12->guest_ds_base = vmcs_readl(GUEST_DS_BASE);
6886         vmcs12->guest_fs_base = vmcs_readl(GUEST_FS_BASE);
6887         vmcs12->guest_gs_base = vmcs_readl(GUEST_GS_BASE);
6888         vmcs12->guest_ldtr_base = vmcs_readl(GUEST_LDTR_BASE);
6889         vmcs12->guest_tr_base = vmcs_readl(GUEST_TR_BASE);
6890         vmcs12->guest_gdtr_base = vmcs_readl(GUEST_GDTR_BASE);
6891         vmcs12->guest_idtr_base = vmcs_readl(GUEST_IDTR_BASE);
6892
6893         vmcs12->guest_activity_state = vmcs_read32(GUEST_ACTIVITY_STATE);
6894         vmcs12->guest_interruptibility_info =
6895                 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
6896         vmcs12->guest_pending_dbg_exceptions =
6897                 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS);
6898
6899         /* TODO: These cannot have changed unless we have MSR bitmaps and
6900          * the relevant bit asks not to trap the change */
6901         vmcs12->guest_ia32_debugctl = vmcs_read64(GUEST_IA32_DEBUGCTL);
6902         if (vmcs12->vm_entry_controls & VM_EXIT_SAVE_IA32_PAT)
6903                 vmcs12->guest_ia32_pat = vmcs_read64(GUEST_IA32_PAT);
6904         vmcs12->guest_sysenter_cs = vmcs_read32(GUEST_SYSENTER_CS);
6905         vmcs12->guest_sysenter_esp = vmcs_readl(GUEST_SYSENTER_ESP);
6906         vmcs12->guest_sysenter_eip = vmcs_readl(GUEST_SYSENTER_EIP);
6907
6908         /* update exit information fields: */
6909
6910         vmcs12->vm_exit_reason  = vmcs_read32(VM_EXIT_REASON);
6911         vmcs12->exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6912
6913         vmcs12->vm_exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
6914         vmcs12->vm_exit_intr_error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
6915         vmcs12->idt_vectoring_info_field =
6916                 vmcs_read32(IDT_VECTORING_INFO_FIELD);
6917         vmcs12->idt_vectoring_error_code =
6918                 vmcs_read32(IDT_VECTORING_ERROR_CODE);
6919         vmcs12->vm_exit_instruction_len = vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6920         vmcs12->vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
6921
6922         /* clear vm-entry fields which are to be cleared on exit */
6923         if (!(vmcs12->vm_exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6924                 vmcs12->vm_entry_intr_info_field &= ~INTR_INFO_VALID_MASK;
6925 }
6926
6927 /*
6928  * A part of what we need to when the nested L2 guest exits and we want to
6929  * run its L1 parent, is to reset L1's guest state to the host state specified
6930  * in vmcs12.
6931  * This function is to be called not only on normal nested exit, but also on
6932  * a nested entry failure, as explained in Intel's spec, 3B.23.7 ("VM-Entry
6933  * Failures During or After Loading Guest State").
6934  * This function should be called when the active VMCS is L1's (vmcs01).
6935  */
6936 void load_vmcs12_host_state(struct kvm_vcpu *vcpu, struct vmcs12 *vmcs12)
6937 {
6938         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_EFER)
6939                 vcpu->arch.efer = vmcs12->host_ia32_efer;
6940         if (vmcs12->vm_exit_controls & VM_EXIT_HOST_ADDR_SPACE_SIZE)
6941                 vcpu->arch.efer |= (EFER_LMA | EFER_LME);
6942         else
6943                 vcpu->arch.efer &= ~(EFER_LMA | EFER_LME);
6944         vmx_set_efer(vcpu, vcpu->arch.efer);
6945
6946         kvm_register_write(vcpu, VCPU_REGS_RSP, vmcs12->host_rsp);
6947         kvm_register_write(vcpu, VCPU_REGS_RIP, vmcs12->host_rip);
6948         /*
6949          * Note that calling vmx_set_cr0 is important, even if cr0 hasn't
6950          * actually changed, because it depends on the current state of
6951          * fpu_active (which may have changed).
6952          * Note that vmx_set_cr0 refers to efer set above.
6953          */
6954         kvm_set_cr0(vcpu, vmcs12->host_cr0);
6955         /*
6956          * If we did fpu_activate()/fpu_deactivate() during L2's run, we need
6957          * to apply the same changes to L1's vmcs. We just set cr0 correctly,
6958          * but we also need to update cr0_guest_host_mask and exception_bitmap.
6959          */
6960         update_exception_bitmap(vcpu);
6961         vcpu->arch.cr0_guest_owned_bits = (vcpu->fpu_active ? X86_CR0_TS : 0);
6962         vmcs_writel(CR0_GUEST_HOST_MASK, ~vcpu->arch.cr0_guest_owned_bits);
6963
6964         /*
6965          * Note that CR4_GUEST_HOST_MASK is already set in the original vmcs01
6966          * (KVM doesn't change it)- no reason to call set_cr4_guest_host_mask();
6967          */
6968         vcpu->arch.cr4_guest_owned_bits = ~vmcs_readl(CR4_GUEST_HOST_MASK);
6969         kvm_set_cr4(vcpu, vmcs12->host_cr4);
6970
6971         /* shadow page tables on either EPT or shadow page tables */
6972         kvm_set_cr3(vcpu, vmcs12->host_cr3);
6973         kvm_mmu_reset_context(vcpu);
6974
6975         if (enable_vpid) {
6976                 /*
6977                  * Trivially support vpid by letting L2s share their parent
6978                  * L1's vpid. TODO: move to a more elaborate solution, giving
6979                  * each L2 its own vpid and exposing the vpid feature to L1.
6980                  */
6981                 vmx_flush_tlb(vcpu);
6982         }
6983
6984
6985         vmcs_write32(GUEST_SYSENTER_CS, vmcs12->host_ia32_sysenter_cs);
6986         vmcs_writel(GUEST_SYSENTER_ESP, vmcs12->host_ia32_sysenter_esp);
6987         vmcs_writel(GUEST_SYSENTER_EIP, vmcs12->host_ia32_sysenter_eip);
6988         vmcs_writel(GUEST_IDTR_BASE, vmcs12->host_idtr_base);
6989         vmcs_writel(GUEST_GDTR_BASE, vmcs12->host_gdtr_base);
6990         vmcs_writel(GUEST_TR_BASE, vmcs12->host_tr_base);
6991         vmcs_writel(GUEST_GS_BASE, vmcs12->host_gs_base);
6992         vmcs_writel(GUEST_FS_BASE, vmcs12->host_fs_base);
6993         vmcs_write16(GUEST_ES_SELECTOR, vmcs12->host_es_selector);
6994         vmcs_write16(GUEST_CS_SELECTOR, vmcs12->host_cs_selector);
6995         vmcs_write16(GUEST_SS_SELECTOR, vmcs12->host_ss_selector);
6996         vmcs_write16(GUEST_DS_SELECTOR, vmcs12->host_ds_selector);
6997         vmcs_write16(GUEST_FS_SELECTOR, vmcs12->host_fs_selector);
6998         vmcs_write16(GUEST_GS_SELECTOR, vmcs12->host_gs_selector);
6999         vmcs_write16(GUEST_TR_SELECTOR, vmcs12->host_tr_selector);
7000
7001         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PAT)
7002                 vmcs_write64(GUEST_IA32_PAT, vmcs12->host_ia32_pat);
7003         if (vmcs12->vm_exit_controls & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
7004                 vmcs_write64(GUEST_IA32_PERF_GLOBAL_CTRL,
7005                         vmcs12->host_ia32_perf_global_ctrl);
7006 }
7007
7008 /*
7009  * Emulate an exit from nested guest (L2) to L1, i.e., prepare to run L1
7010  * and modify vmcs12 to make it see what it would expect to see there if
7011  * L2 was its real guest. Must only be called when in L2 (is_guest_mode())
7012  */
7013 static void nested_vmx_vmexit(struct kvm_vcpu *vcpu)
7014 {
7015         struct vcpu_vmx *vmx = to_vmx(vcpu);
7016         int cpu;
7017         struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
7018
7019         leave_guest_mode(vcpu);
7020         prepare_vmcs12(vcpu, vmcs12);
7021
7022         cpu = get_cpu();
7023         vmx->loaded_vmcs = &vmx->vmcs01;
7024         vmx_vcpu_put(vcpu);
7025         vmx_vcpu_load(vcpu, cpu);
7026         vcpu->cpu = cpu;
7027         put_cpu();
7028
7029         /* if no vmcs02 cache requested, remove the one we used */
7030         if (VMCS02_POOL_SIZE == 0)
7031                 nested_free_vmcs02(vmx, vmx->nested.current_vmptr);
7032
7033         load_vmcs12_host_state(vcpu, vmcs12);
7034
7035         /* Update TSC_OFFSET if TSC was changed while L2 ran */
7036         vmcs_write64(TSC_OFFSET, vmx->nested.vmcs01_tsc_offset);
7037
7038         /* This is needed for same reason as it was needed in prepare_vmcs02 */
7039         vmx->host_rsp = 0;
7040
7041         /* Unpin physical memory we referred to in vmcs02 */
7042         if (vmx->nested.apic_access_page) {
7043                 nested_release_page(vmx->nested.apic_access_page);
7044                 vmx->nested.apic_access_page = 0;
7045         }
7046
7047         /*
7048          * Exiting from L2 to L1, we're now back to L1 which thinks it just
7049          * finished a VMLAUNCH or VMRESUME instruction, so we need to set the
7050          * success or failure flag accordingly.
7051          */
7052         if (unlikely(vmx->fail)) {
7053                 vmx->fail = 0;
7054                 nested_vmx_failValid(vcpu, vmcs_read32(VM_INSTRUCTION_ERROR));
7055         } else
7056                 nested_vmx_succeed(vcpu);
7057 }
7058
7059 /*
7060  * L1's failure to enter L2 is a subset of a normal exit, as explained in
7061  * 23.7 "VM-entry failures during or after loading guest state" (this also
7062  * lists the acceptable exit-reason and exit-qualification parameters).
7063  * It should only be called before L2 actually succeeded to run, and when
7064  * vmcs01 is current (it doesn't leave_guest_mode() or switch vmcss).
7065  */
7066 static void nested_vmx_entry_failure(struct kvm_vcpu *vcpu,
7067                         struct vmcs12 *vmcs12,
7068                         u32 reason, unsigned long qualification)
7069 {
7070         load_vmcs12_host_state(vcpu, vmcs12);
7071         vmcs12->vm_exit_reason = reason | VMX_EXIT_REASONS_FAILED_VMENTRY;
7072         vmcs12->exit_qualification = qualification;
7073         nested_vmx_succeed(vcpu);
7074 }
7075
7076 static int vmx_check_intercept(struct kvm_vcpu *vcpu,
7077                                struct x86_instruction_info *info,
7078                                enum x86_intercept_stage stage)
7079 {
7080         return X86EMUL_CONTINUE;
7081 }
7082
7083 static struct kvm_x86_ops vmx_x86_ops = {
7084         .cpu_has_kvm_support = cpu_has_kvm_support,
7085         .disabled_by_bios = vmx_disabled_by_bios,
7086         .hardware_setup = hardware_setup,
7087         .hardware_unsetup = hardware_unsetup,
7088         .check_processor_compatibility = vmx_check_processor_compat,
7089         .hardware_enable = hardware_enable,
7090         .hardware_disable = hardware_disable,
7091         .cpu_has_accelerated_tpr = report_flexpriority,
7092
7093         .vcpu_create = vmx_create_vcpu,
7094         .vcpu_free = vmx_free_vcpu,
7095         .vcpu_reset = vmx_vcpu_reset,
7096
7097         .prepare_guest_switch = vmx_save_host_state,
7098         .vcpu_load = vmx_vcpu_load,
7099         .vcpu_put = vmx_vcpu_put,
7100
7101         .set_guest_debug = set_guest_debug,
7102         .get_msr = vmx_get_msr,
7103         .set_msr = vmx_set_msr,
7104         .get_segment_base = vmx_get_segment_base,
7105         .get_segment = vmx_get_segment,
7106         .set_segment = vmx_set_segment,
7107         .get_cpl = vmx_get_cpl,
7108         .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
7109         .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
7110         .decache_cr3 = vmx_decache_cr3,
7111         .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
7112         .set_cr0 = vmx_set_cr0,
7113         .set_cr3 = vmx_set_cr3,
7114         .set_cr4 = vmx_set_cr4,
7115         .set_efer = vmx_set_efer,
7116         .get_idt = vmx_get_idt,
7117         .set_idt = vmx_set_idt,
7118         .get_gdt = vmx_get_gdt,
7119         .set_gdt = vmx_set_gdt,
7120         .set_dr7 = vmx_set_dr7,
7121         .cache_reg = vmx_cache_reg,
7122         .get_rflags = vmx_get_rflags,
7123         .set_rflags = vmx_set_rflags,
7124         .fpu_activate = vmx_fpu_activate,
7125         .fpu_deactivate = vmx_fpu_deactivate,
7126
7127         .tlb_flush = vmx_flush_tlb,
7128
7129         .run = vmx_vcpu_run,
7130         .handle_exit = vmx_handle_exit,
7131         .skip_emulated_instruction = skip_emulated_instruction,
7132         .set_interrupt_shadow = vmx_set_interrupt_shadow,
7133         .get_interrupt_shadow = vmx_get_interrupt_shadow,
7134         .patch_hypercall = vmx_patch_hypercall,
7135         .set_irq = vmx_inject_irq,
7136         .set_nmi = vmx_inject_nmi,
7137         .queue_exception = vmx_queue_exception,
7138         .cancel_injection = vmx_cancel_injection,
7139         .interrupt_allowed = vmx_interrupt_allowed,
7140         .nmi_allowed = vmx_nmi_allowed,
7141         .get_nmi_mask = vmx_get_nmi_mask,
7142         .set_nmi_mask = vmx_set_nmi_mask,
7143         .enable_nmi_window = enable_nmi_window,
7144         .enable_irq_window = enable_irq_window,
7145         .update_cr8_intercept = update_cr8_intercept,
7146
7147         .set_tss_addr = vmx_set_tss_addr,
7148         .get_tdp_level = get_ept_level,
7149         .get_mt_mask = vmx_get_mt_mask,
7150
7151         .get_exit_info = vmx_get_exit_info,
7152
7153         .get_lpage_level = vmx_get_lpage_level,
7154
7155         .cpuid_update = vmx_cpuid_update,
7156
7157         .rdtscp_supported = vmx_rdtscp_supported,
7158
7159         .set_supported_cpuid = vmx_set_supported_cpuid,
7160
7161         .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
7162
7163         .set_tsc_khz = vmx_set_tsc_khz,
7164         .write_tsc_offset = vmx_write_tsc_offset,
7165         .adjust_tsc_offset = vmx_adjust_tsc_offset,
7166         .compute_tsc_offset = vmx_compute_tsc_offset,
7167         .read_l1_tsc = vmx_read_l1_tsc,
7168
7169         .set_tdp_cr3 = vmx_set_cr3,
7170
7171         .check_intercept = vmx_check_intercept,
7172 };
7173
7174 static int __init vmx_init(void)
7175 {
7176         int r, i;
7177
7178         rdmsrl_safe(MSR_EFER, &host_efer);
7179
7180         for (i = 0; i < NR_VMX_MSR; ++i)
7181                 kvm_define_shared_msr(i, vmx_msr_index[i]);
7182
7183         vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
7184         if (!vmx_io_bitmap_a)
7185                 return -ENOMEM;
7186
7187         vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
7188         if (!vmx_io_bitmap_b) {
7189                 r = -ENOMEM;
7190                 goto out;
7191         }
7192
7193         vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
7194         if (!vmx_msr_bitmap_legacy) {
7195                 r = -ENOMEM;
7196                 goto out1;
7197         }
7198
7199         vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
7200         if (!vmx_msr_bitmap_longmode) {
7201                 r = -ENOMEM;
7202                 goto out2;
7203         }
7204
7205         /*
7206          * Allow direct access to the PC debug port (it is often used for I/O
7207          * delays, but the vmexits simply slow things down).
7208          */
7209         memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
7210         clear_bit(0x80, vmx_io_bitmap_a);
7211
7212         memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
7213
7214         memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
7215         memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
7216
7217         set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7218
7219         r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
7220                      __alignof__(struct vcpu_vmx), THIS_MODULE);
7221         if (r)
7222                 goto out3;
7223
7224         vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
7225         vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
7226         vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
7227         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
7228         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
7229         vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
7230
7231         if (enable_ept) {
7232                 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
7233                                 VMX_EPT_EXECUTABLE_MASK);
7234                 ept_set_mmio_spte_mask();
7235                 kvm_enable_tdp();
7236         } else
7237                 kvm_disable_tdp();
7238
7239         return 0;
7240
7241 out3:
7242         free_page((unsigned long)vmx_msr_bitmap_longmode);
7243 out2:
7244         free_page((unsigned long)vmx_msr_bitmap_legacy);
7245 out1:
7246         free_page((unsigned long)vmx_io_bitmap_b);
7247 out:
7248         free_page((unsigned long)vmx_io_bitmap_a);
7249         return r;
7250 }
7251
7252 static void __exit vmx_exit(void)
7253 {
7254         free_page((unsigned long)vmx_msr_bitmap_legacy);
7255         free_page((unsigned long)vmx_msr_bitmap_longmode);
7256         free_page((unsigned long)vmx_io_bitmap_b);
7257         free_page((unsigned long)vmx_io_bitmap_a);
7258
7259         kvm_exit();
7260 }
7261
7262 module_init(vmx_init)
7263 module_exit(vmx_exit)