arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "kvm_svm.h"
  19 #include "irq.h"
  20 #include "mmu.h"
  21 #include "kvm_cache_regs.h"
  22 #include "x86.h"
  23
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/vmalloc.h>
  27 #include <linux/highmem.h>
  28 #include <linux/sched.h>
  29
  30 #include <asm/desc.h>
  31
  32 #include <asm/virtext.h>
  33
  34 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  35
  36 MODULE_AUTHOR("Qumranet");
  37 MODULE_LICENSE("GPL");
  38
  39 #define IOPM_ALLOC_ORDER 2
  40 #define MSRPM_ALLOC_ORDER 1
  41
  42 #define SEG_TYPE_LDT 2
  43 #define SEG_TYPE_BUSY_TSS16 3
  44
  45 #define SVM_FEATURE_NPT  (1 << 0)
  46 #define SVM_FEATURE_LBRV (1 << 1)
  47 #define SVM_FEATURE_SVML (1 << 2)
  48
  49 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  50
  51 /* Turn on to get debugging output*/
  52 /* #define NESTED_DEBUG */
  53
  54 #ifdef NESTED_DEBUG
  55 #define nsvm_printk(fmt, args...) printk(KERN_INFO fmt, ## args)
  56 #else
  57 #define nsvm_printk(fmt, args...) do {} while(0)
  58 #endif
  59
  60 /* enable NPT for AMD64 and X86 with PAE */
  61 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  62 static bool npt_enabled = true;
  63 #else
  64 static bool npt_enabled = false;
  65 #endif
  66 static int npt = 1;
  67
  68 module_param(npt, int, S_IRUGO);
  69
  70 static int nested = 0;
  71 module_param(nested, int, S_IRUGO);
  72
  73 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  74
  75 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override);
  76 static int nested_svm_vmexit(struct vcpu_svm *svm);
  77 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
  78                              void *arg2, void *opaque);
  79 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
  80                                       bool has_error_code, u32 error_code);
  81
  82 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  83 {
  84         return container_of(vcpu, struct vcpu_svm, vcpu);
  85 }
  86
  87 static inline bool is_nested(struct vcpu_svm *svm)
  88 {
  89         return svm->nested_vmcb;
  90 }
  91
  92 static unsigned long iopm_base;
  93
  94 struct kvm_ldttss_desc {
  95         u16 limit0;
  96         u16 base0;
  97         unsigned base1 : 8, type : 5, dpl : 2, p : 1;
  98         unsigned limit1 : 4, zero0 : 3, g : 1, base2 : 8;
  99         u32 base3;
 100         u32 zero1;
 101 } __attribute__((packed));
 102
 103 struct svm_cpu_data {
 104         int cpu;
 105
 106         u64 asid_generation;
 107         u32 max_asid;
 108         u32 next_asid;
 109         struct kvm_ldttss_desc *tss_desc;
 110
 111         struct page *save_area;
 112 };
 113
 114 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 115 static uint32_t svm_features;
 116
 117 struct svm_init_data {
 118         int cpu;
 119         int r;
 120 };
 121
 122 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 123
 124 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 125 #define MSRS_RANGE_SIZE 2048
 126 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 127
 128 #define MAX_INST_SIZE 15
 129
 130 static inline u32 svm_has(u32 feat)
 131 {
 132         return svm_features & feat;
 133 }
 134
 135 static inline void clgi(void)
 136 {
 137         asm volatile (__ex(SVM_CLGI));
 138 }
 139
 140 static inline void stgi(void)
 141 {
 142         asm volatile (__ex(SVM_STGI));
 143 }
 144
 145 static inline void invlpga(unsigned long addr, u32 asid)
 146 {
 147         asm volatile (__ex(SVM_INVLPGA) :: "a"(addr), "c"(asid));
 148 }
 149
 150 static inline unsigned long kvm_read_cr2(void)
 151 {
 152         unsigned long cr2;
 153
 154         asm volatile ("mov %%cr2, %0" : "=r" (cr2));
 155         return cr2;
 156 }
 157
 158 static inline void kvm_write_cr2(unsigned long val)
 159 {
 160         asm volatile ("mov %0, %%cr2" :: "r" (val));
 161 }
 162
 163 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 164 {
 165         to_svm(vcpu)->asid_generation--;
 166 }
 167
 168 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 169 {
 170         force_new_asid(vcpu);
 171 }
 172
 173 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 174 {
 175         if (!npt_enabled && !(efer & EFER_LMA))
 176                 efer &= ~EFER_LME;
 177
 178         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 179         vcpu->arch.shadow_efer = efer;
 180 }
 181
 182 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 183                                 bool has_error_code, u32 error_code)
 184 {
 185         struct vcpu_svm *svm = to_svm(vcpu);
 186
 187         /* If we are within a nested VM we'd better #VMEXIT and let the
 188            guest handle the exception */
 189         if (nested_svm_check_exception(svm, nr, has_error_code, error_code))
 190                 return;
 191
 192         svm->vmcb->control.event_inj = nr
 193                 | SVM_EVTINJ_VALID
 194                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 195                 | SVM_EVTINJ_TYPE_EXEPT;
 196         svm->vmcb->control.event_inj_err = error_code;
 197 }
 198
 199 static int is_external_interrupt(u32 info)
 200 {
 201         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 202         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 203 }
 204
 205 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 206 {
 207         struct vcpu_svm *svm = to_svm(vcpu);
 208         u32 ret = 0;
 209
 210         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 211                 ret |= X86_SHADOW_INT_STI | X86_SHADOW_INT_MOV_SS;
 212         return ret & mask;
 213 }
 214
 215 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 216 {
 217         struct vcpu_svm *svm = to_svm(vcpu);
 218
 219         if (mask == 0)
 220                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 221         else
 222                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 223
 224 }
 225
 226 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 227 {
 228         struct vcpu_svm *svm = to_svm(vcpu);
 229
 230         if (!svm->next_rip) {
 231                 if (emulate_instruction(vcpu, vcpu->run, 0, 0, EMULTYPE_SKIP) !=
 232                                 EMULATE_DONE)
 233                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 234                 return;
 235         }
 236         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 237                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 238                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 239
 240         kvm_rip_write(vcpu, svm->next_rip);
 241         svm_set_interrupt_shadow(vcpu, 0);
 242 }
 243
 244 static int has_svm(void)
 245 {
 246         const char *msg;
 247
 248         if (!cpu_has_svm(&msg)) {
 249                 printk(KERN_INFO "has_svm: %s\n", msg);
 250                 return 0;
 251         }
 252
 253         return 1;
 254 }
 255
 256 static void svm_hardware_disable(void *garbage)
 257 {
 258         cpu_svm_disable();
 259 }
 260
 261 static void svm_hardware_enable(void *garbage)
 262 {
 263
 264         struct svm_cpu_data *svm_data;
 265         uint64_t efer;
 266         struct desc_ptr gdt_descr;
 267         struct desc_struct *gdt;
 268         int me = raw_smp_processor_id();
 269
 270         if (!has_svm()) {
 271                 printk(KERN_ERR "svm_cpu_init: err EOPNOTSUPP on %d\n", me);
 272                 return;
 273         }
 274         svm_data = per_cpu(svm_data, me);
 275
 276         if (!svm_data) {
 277                 printk(KERN_ERR "svm_cpu_init: svm_data is NULL on %d\n",
 278                        me);
 279                 return;
 280         }
 281
 282         svm_data->asid_generation = 1;
 283         svm_data->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 284         svm_data->next_asid = svm_data->max_asid + 1;
 285
 286         asm volatile ("sgdt %0" : "=m"(gdt_descr));
 287         gdt = (struct desc_struct *)gdt_descr.address;
 288         svm_data->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 289
 290         rdmsrl(MSR_EFER, efer);
 291         wrmsrl(MSR_EFER, efer | EFER_SVME);
 292
 293         wrmsrl(MSR_VM_HSAVE_PA,
 294                page_to_pfn(svm_data->save_area) << PAGE_SHIFT);
 295 }
 296
 297 static void svm_cpu_uninit(int cpu)
 298 {
 299         struct svm_cpu_data *svm_data
 300                 = per_cpu(svm_data, raw_smp_processor_id());
 301
 302         if (!svm_data)
 303                 return;
 304
 305         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 306         __free_page(svm_data->save_area);
 307         kfree(svm_data);
 308 }
 309
 310 static int svm_cpu_init(int cpu)
 311 {
 312         struct svm_cpu_data *svm_data;
 313         int r;
 314
 315         svm_data = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 316         if (!svm_data)
 317                 return -ENOMEM;
 318         svm_data->cpu = cpu;
 319         svm_data->save_area = alloc_page(GFP_KERNEL);
 320         r = -ENOMEM;
 321         if (!svm_data->save_area)
 322                 goto err_1;
 323
 324         per_cpu(svm_data, cpu) = svm_data;
 325
 326         return 0;
 327
 328 err_1:
 329         kfree(svm_data);
 330         return r;
 331
 332 }
 333
 334 static void set_msr_interception(u32 *msrpm, unsigned msr,
 335                                  int read, int write)
 336 {
 337         int i;
 338
 339         for (i = 0; i < NUM_MSR_MAPS; i++) {
 340                 if (msr >= msrpm_ranges[i] &&
 341                     msr < msrpm_ranges[i] + MSRS_IN_RANGE) {
 342                         u32 msr_offset = (i * MSRS_IN_RANGE + msr -
 343                                           msrpm_ranges[i]) * 2;
 344
 345                         u32 *base = msrpm + (msr_offset / 32);
 346                         u32 msr_shift = msr_offset % 32;
 347                         u32 mask = ((write) ? 0 : 2) | ((read) ? 0 : 1);
 348                         *base = (*base & ~(0x3 << msr_shift)) |
 349                                 (mask << msr_shift);
 350                         return;
 351                 }
 352         }
 353         BUG();
 354 }
 355
 356 static void svm_vcpu_init_msrpm(u32 *msrpm)
 357 {
 358         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 359
 360 #ifdef CONFIG_X86_64
 361         set_msr_interception(msrpm, MSR_GS_BASE, 1, 1);
 362         set_msr_interception(msrpm, MSR_FS_BASE, 1, 1);
 363         set_msr_interception(msrpm, MSR_KERNEL_GS_BASE, 1, 1);
 364         set_msr_interception(msrpm, MSR_LSTAR, 1, 1);
 365         set_msr_interception(msrpm, MSR_CSTAR, 1, 1);
 366         set_msr_interception(msrpm, MSR_SYSCALL_MASK, 1, 1);
 367 #endif
 368         set_msr_interception(msrpm, MSR_K6_STAR, 1, 1);
 369         set_msr_interception(msrpm, MSR_IA32_SYSENTER_CS, 1, 1);
 370         set_msr_interception(msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
 371         set_msr_interception(msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
 372 }
 373
 374 static void svm_enable_lbrv(struct vcpu_svm *svm)
 375 {
 376         u32 *msrpm = svm->msrpm;
 377
 378         svm->vmcb->control.lbr_ctl = 1;
 379         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 380         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 381         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 382         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 383 }
 384
 385 static void svm_disable_lbrv(struct vcpu_svm *svm)
 386 {
 387         u32 *msrpm = svm->msrpm;
 388
 389         svm->vmcb->control.lbr_ctl = 0;
 390         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 391         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 392         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 393         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 394 }
 395
 396 static __init int svm_hardware_setup(void)
 397 {
 398         int cpu;
 399         struct page *iopm_pages;
 400         void *iopm_va;
 401         int r;
 402
 403         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 404
 405         if (!iopm_pages)
 406                 return -ENOMEM;
 407
 408         iopm_va = page_address(iopm_pages);
 409         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 410         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 411
 412         if (boot_cpu_has(X86_FEATURE_NX))
 413                 kvm_enable_efer_bits(EFER_NX);
 414
 415         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 416                 kvm_enable_efer_bits(EFER_FFXSR);
 417
 418         if (nested) {
 419                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 420                 kvm_enable_efer_bits(EFER_SVME);
 421         }
 422
 423         for_each_online_cpu(cpu) {
 424                 r = svm_cpu_init(cpu);
 425                 if (r)
 426                         goto err;
 427         }
 428
 429         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 430
 431         if (!svm_has(SVM_FEATURE_NPT))
 432                 npt_enabled = false;
 433
 434         if (npt_enabled && !npt) {
 435                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 436                 npt_enabled = false;
 437         }
 438
 439         if (npt_enabled) {
 440                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 441                 kvm_enable_tdp();
 442         } else
 443                 kvm_disable_tdp();
 444
 445         return 0;
 446
 447 err:
 448         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 449         iopm_base = 0;
 450         return r;
 451 }
 452
 453 static __exit void svm_hardware_unsetup(void)
 454 {
 455         int cpu;
 456
 457         for_each_online_cpu(cpu)
 458                 svm_cpu_uninit(cpu);
 459
 460         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 461         iopm_base = 0;
 462 }
 463
 464 static void init_seg(struct vmcb_seg *seg)
 465 {
 466         seg->selector = 0;
 467         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 468                 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 469         seg->limit = 0xffff;
 470         seg->base = 0;
 471 }
 472
 473 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 474 {
 475         seg->selector = 0;
 476         seg->attrib = SVM_SELECTOR_P_MASK | type;
 477         seg->limit = 0xffff;
 478         seg->base = 0;
 479 }
 480
 481 static void init_vmcb(struct vcpu_svm *svm)
 482 {
 483         struct vmcb_control_area *control = &svm->vmcb->control;
 484         struct vmcb_save_area *save = &svm->vmcb->save;
 485
 486         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 487                                         INTERCEPT_CR3_MASK |
 488                                         INTERCEPT_CR4_MASK;
 489
 490         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 491                                         INTERCEPT_CR3_MASK |
 492                                         INTERCEPT_CR4_MASK |
 493                                         INTERCEPT_CR8_MASK;
 494
 495         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 496                                         INTERCEPT_DR1_MASK |
 497                                         INTERCEPT_DR2_MASK |
 498                                         INTERCEPT_DR3_MASK;
 499
 500         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 501                                         INTERCEPT_DR1_MASK |
 502                                         INTERCEPT_DR2_MASK |
 503                                         INTERCEPT_DR3_MASK |
 504                                         INTERCEPT_DR5_MASK |
 505                                         INTERCEPT_DR7_MASK;
 506
 507         control->intercept_exceptions = (1 << PF_VECTOR) |
 508                                         (1 << UD_VECTOR) |
 509                                         (1 << MC_VECTOR);
 510
 511
 512         control->intercept =    (1ULL << INTERCEPT_INTR) |
 513                                 (1ULL << INTERCEPT_NMI) |
 514                                 (1ULL << INTERCEPT_SMI) |
 515                                 (1ULL << INTERCEPT_CPUID) |
 516                                 (1ULL << INTERCEPT_INVD) |
 517                                 (1ULL << INTERCEPT_HLT) |
 518                                 (1ULL << INTERCEPT_INVLPG) |
 519                                 (1ULL << INTERCEPT_INVLPGA) |
 520                                 (1ULL << INTERCEPT_IOIO_PROT) |
 521                                 (1ULL << INTERCEPT_MSR_PROT) |
 522                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 523                                 (1ULL << INTERCEPT_SHUTDOWN) |
 524                                 (1ULL << INTERCEPT_VMRUN) |
 525                                 (1ULL << INTERCEPT_VMMCALL) |
 526                                 (1ULL << INTERCEPT_VMLOAD) |
 527                                 (1ULL << INTERCEPT_VMSAVE) |
 528                                 (1ULL << INTERCEPT_STGI) |
 529                                 (1ULL << INTERCEPT_CLGI) |
 530                                 (1ULL << INTERCEPT_SKINIT) |
 531                                 (1ULL << INTERCEPT_WBINVD) |
 532                                 (1ULL << INTERCEPT_MONITOR) |
 533                                 (1ULL << INTERCEPT_MWAIT);
 534
 535         control->iopm_base_pa = iopm_base;
 536         control->msrpm_base_pa = __pa(svm->msrpm);
 537         control->tsc_offset = 0;
 538         control->int_ctl = V_INTR_MASKING_MASK;
 539
 540         init_seg(&save->es);
 541         init_seg(&save->ss);
 542         init_seg(&save->ds);
 543         init_seg(&save->fs);
 544         init_seg(&save->gs);
 545
 546         save->cs.selector = 0xf000;
 547         /* Executable/Readable Code Segment */
 548         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 549                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 550         save->cs.limit = 0xffff;
 551         /*
 552          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 553          * be consistent with it.
 554          *
 555          * Replace when we have real mode working for vmx.
 556          */
 557         save->cs.base = 0xf0000;
 558
 559         save->gdtr.limit = 0xffff;
 560         save->idtr.limit = 0xffff;
 561
 562         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 563         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 564
 565         save->efer = EFER_SVME;
 566         save->dr6 = 0xffff0ff0;
 567         save->dr7 = 0x400;
 568         save->rflags = 2;
 569         save->rip = 0x0000fff0;
 570         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 571
 572         /*
 573          * cr0 val on cpu init should be 0x60000010, we enable cpu
 574          * cache by default. the orderly way is to enable cache in bios.
 575          */
 576         save->cr0 = 0x00000010 | X86_CR0_PG | X86_CR0_WP;
 577         save->cr4 = X86_CR4_PAE;
 578         /* rdx = ?? */
 579
 580         if (npt_enabled) {
 581                 /* Setup VMCB for Nested Paging */
 582                 control->nested_ctl = 1;
 583                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 584                                         (1ULL << INTERCEPT_INVLPG));
 585                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 586                 control->intercept_cr_read &= ~(INTERCEPT_CR0_MASK|
 587                                                 INTERCEPT_CR3_MASK);
 588                 control->intercept_cr_write &= ~(INTERCEPT_CR0_MASK|
 589                                                  INTERCEPT_CR3_MASK);
 590                 save->g_pat = 0x0007040600070406ULL;
 591                 /* enable caching because the QEMU Bios doesn't enable it */
 592                 save->cr0 = X86_CR0_ET;
 593                 save->cr3 = 0;
 594                 save->cr4 = 0;
 595         }
 596         force_new_asid(&svm->vcpu);
 597
 598         svm->nested_vmcb = 0;
 599         svm->vcpu.arch.hflags = HF_GIF_MASK;
 600 }
 601
 602 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 603 {
 604         struct vcpu_svm *svm = to_svm(vcpu);
 605
 606         init_vmcb(svm);
 607
 608         if (vcpu->vcpu_id != 0) {
 609                 kvm_rip_write(vcpu, 0);
 610                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 611                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 612         }
 613         vcpu->arch.regs_avail = ~0;
 614         vcpu->arch.regs_dirty = ~0;
 615
 616         return 0;
 617 }
 618
 619 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 620 {
 621         struct vcpu_svm *svm;
 622         struct page *page;
 623         struct page *msrpm_pages;
 624         struct page *hsave_page;
 625         struct page *nested_msrpm_pages;
 626         int err;
 627
 628         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 629         if (!svm) {
 630                 err = -ENOMEM;
 631                 goto out;
 632         }
 633
 634         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 635         if (err)
 636                 goto free_svm;
 637
 638         page = alloc_page(GFP_KERNEL);
 639         if (!page) {
 640                 err = -ENOMEM;
 641                 goto uninit;
 642         }
 643
 644         err = -ENOMEM;
 645         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 646         if (!msrpm_pages)
 647                 goto uninit;
 648
 649         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 650         if (!nested_msrpm_pages)
 651                 goto uninit;
 652
 653         svm->msrpm = page_address(msrpm_pages);
 654         svm_vcpu_init_msrpm(svm->msrpm);
 655
 656         hsave_page = alloc_page(GFP_KERNEL);
 657         if (!hsave_page)
 658                 goto uninit;
 659         svm->hsave = page_address(hsave_page);
 660
 661         svm->nested_msrpm = page_address(nested_msrpm_pages);
 662
 663         svm->vmcb = page_address(page);
 664         clear_page(svm->vmcb);
 665         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 666         svm->asid_generation = 0;
 667         init_vmcb(svm);
 668
 669         fx_init(&svm->vcpu);
 670         svm->vcpu.fpu_active = 1;
 671         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 672         if (svm->vcpu.vcpu_id == 0)
 673                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 674
 675         return &svm->vcpu;
 676
 677 uninit:
 678         kvm_vcpu_uninit(&svm->vcpu);
 679 free_svm:
 680         kmem_cache_free(kvm_vcpu_cache, svm);
 681 out:
 682         return ERR_PTR(err);
 683 }
 684
 685 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 686 {
 687         struct vcpu_svm *svm = to_svm(vcpu);
 688
 689         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 690         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 691         __free_page(virt_to_page(svm->hsave));
 692         __free_pages(virt_to_page(svm->nested_msrpm), MSRPM_ALLOC_ORDER);
 693         kvm_vcpu_uninit(vcpu);
 694         kmem_cache_free(kvm_vcpu_cache, svm);
 695 }
 696
 697 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 698 {
 699         struct vcpu_svm *svm = to_svm(vcpu);
 700         int i;
 701
 702         if (unlikely(cpu != vcpu->cpu)) {
 703                 u64 tsc_this, delta;
 704
 705                 /*
 706                  * Make sure that the guest sees a monotonically
 707                  * increasing TSC.
 708                  */
 709                 rdtscll(tsc_this);
 710                 delta = vcpu->arch.host_tsc - tsc_this;
 711                 svm->vmcb->control.tsc_offset += delta;
 712                 vcpu->cpu = cpu;
 713                 kvm_migrate_timers(vcpu);
 714                 svm->asid_generation = 0;
 715         }
 716
 717         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 718                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 719 }
 720
 721 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 722 {
 723         struct vcpu_svm *svm = to_svm(vcpu);
 724         int i;
 725
 726         ++vcpu->stat.host_state_reload;
 727         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 728                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 729
 730         rdtscll(vcpu->arch.host_tsc);
 731 }
 732
 733 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 734 {
 735         return to_svm(vcpu)->vmcb->save.rflags;
 736 }
 737
 738 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 739 {
 740         to_svm(vcpu)->vmcb->save.rflags = rflags;
 741 }
 742
 743 static void svm_set_vintr(struct vcpu_svm *svm)
 744 {
 745         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 746 }
 747
 748 static void svm_clear_vintr(struct vcpu_svm *svm)
 749 {
 750         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 751 }
 752
 753 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 754 {
 755         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 756
 757         switch (seg) {
 758         case VCPU_SREG_CS: return &save->cs;
 759         case VCPU_SREG_DS: return &save->ds;
 760         case VCPU_SREG_ES: return &save->es;
 761         case VCPU_SREG_FS: return &save->fs;
 762         case VCPU_SREG_GS: return &save->gs;
 763         case VCPU_SREG_SS: return &save->ss;
 764         case VCPU_SREG_TR: return &save->tr;
 765         case VCPU_SREG_LDTR: return &save->ldtr;
 766         }
 767         BUG();
 768         return NULL;
 769 }
 770
 771 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 772 {
 773         struct vmcb_seg *s = svm_seg(vcpu, seg);
 774
 775         return s->base;
 776 }
 777
 778 static void svm_get_segment(struct kvm_vcpu *vcpu,
 779                             struct kvm_segment *var, int seg)
 780 {
 781         struct vmcb_seg *s = svm_seg(vcpu, seg);
 782
 783         var->base = s->base;
 784         var->limit = s->limit;
 785         var->selector = s->selector;
 786         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
 787         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
 788         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
 789         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
 790         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
 791         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
 792         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
 793         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
 794
 795         /* AMD's VMCB does not have an explicit unusable field, so emulate it
 796          * for cross vendor migration purposes by "not present"
 797          */
 798         var->unusable = !var->present || (var->type == 0);
 799
 800         switch (seg) {
 801         case VCPU_SREG_CS:
 802                 /*
 803                  * SVM always stores 0 for the 'G' bit in the CS selector in
 804                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
 805                  * Intel's VMENTRY has a check on the 'G' bit.
 806                  */
 807                 var->g = s->limit > 0xfffff;
 808                 break;
 809         case VCPU_SREG_TR:
 810                 /*
 811                  * Work around a bug where the busy flag in the tr selector
 812                  * isn't exposed
 813                  */
 814                 var->type |= 0x2;
 815                 break;
 816         case VCPU_SREG_DS:
 817         case VCPU_SREG_ES:
 818         case VCPU_SREG_FS:
 819         case VCPU_SREG_GS:
 820                 /*
 821                  * The accessed bit must always be set in the segment
 822                  * descriptor cache, although it can be cleared in the
 823                  * descriptor, the cached bit always remains at 1. Since
 824                  * Intel has a check on this, set it here to support
 825                  * cross-vendor migration.
 826                  */
 827                 if (!var->unusable)
 828                         var->type |= 0x1;
 829                 break;
 830         case VCPU_SREG_SS:
 831                 /* On AMD CPUs sometimes the DB bit in the segment
 832                  * descriptor is left as 1, although the whole segment has
 833                  * been made unusable. Clear it here to pass an Intel VMX
 834                  * entry check when cross vendor migrating.
 835                  */
 836                 if (var->unusable)
 837                         var->db = 0;
 838                 break;
 839         }
 840 }
 841
 842 static int svm_get_cpl(struct kvm_vcpu *vcpu)
 843 {
 844         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 845
 846         return save->cpl;
 847 }
 848
 849 static void svm_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 850 {
 851         struct vcpu_svm *svm = to_svm(vcpu);
 852
 853         dt->limit = svm->vmcb->save.idtr.limit;
 854         dt->base = svm->vmcb->save.idtr.base;
 855 }
 856
 857 static void svm_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 858 {
 859         struct vcpu_svm *svm = to_svm(vcpu);
 860
 861         svm->vmcb->save.idtr.limit = dt->limit;
 862         svm->vmcb->save.idtr.base = dt->base ;
 863 }
 864
 865 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 866 {
 867         struct vcpu_svm *svm = to_svm(vcpu);
 868
 869         dt->limit = svm->vmcb->save.gdtr.limit;
 870         dt->base = svm->vmcb->save.gdtr.base;
 871 }
 872
 873 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
 874 {
 875         struct vcpu_svm *svm = to_svm(vcpu);
 876
 877         svm->vmcb->save.gdtr.limit = dt->limit;
 878         svm->vmcb->save.gdtr.base = dt->base ;
 879 }
 880
 881 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
 882 {
 883 }
 884
 885 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
 886 {
 887         struct vcpu_svm *svm = to_svm(vcpu);
 888
 889 #ifdef CONFIG_X86_64
 890         if (vcpu->arch.shadow_efer & EFER_LME) {
 891                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
 892                         vcpu->arch.shadow_efer |= EFER_LMA;
 893                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
 894                 }
 895
 896                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
 897                         vcpu->arch.shadow_efer &= ~EFER_LMA;
 898                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
 899                 }
 900         }
 901 #endif
 902         if (npt_enabled)
 903                 goto set;
 904
 905         if ((vcpu->arch.cr0 & X86_CR0_TS) && !(cr0 & X86_CR0_TS)) {
 906                 svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
 907                 vcpu->fpu_active = 1;
 908         }
 909
 910         vcpu->arch.cr0 = cr0;
 911         cr0 |= X86_CR0_PG | X86_CR0_WP;
 912         if (!vcpu->fpu_active) {
 913                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
 914                 cr0 |= X86_CR0_TS;
 915         }
 916 set:
 917         /*
 918          * re-enable caching here because the QEMU bios
 919          * does not do it - this results in some delay at
 920          * reboot
 921          */
 922         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
 923         svm->vmcb->save.cr0 = cr0;
 924 }
 925
 926 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
 927 {
 928         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
 929         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
 930
 931         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
 932                 force_new_asid(vcpu);
 933
 934         vcpu->arch.cr4 = cr4;
 935         if (!npt_enabled)
 936                 cr4 |= X86_CR4_PAE;
 937         cr4 |= host_cr4_mce;
 938         to_svm(vcpu)->vmcb->save.cr4 = cr4;
 939 }
 940
 941 static void svm_set_segment(struct kvm_vcpu *vcpu,
 942                             struct kvm_segment *var, int seg)
 943 {
 944         struct vcpu_svm *svm = to_svm(vcpu);
 945         struct vmcb_seg *s = svm_seg(vcpu, seg);
 946
 947         s->base = var->base;
 948         s->limit = var->limit;
 949         s->selector = var->selector;
 950         if (var->unusable)
 951                 s->attrib = 0;
 952         else {
 953                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
 954                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
 955                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
 956                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
 957                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
 958                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
 959                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
 960                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
 961         }
 962         if (seg == VCPU_SREG_CS)
 963                 svm->vmcb->save.cpl
 964                         = (svm->vmcb->save.cs.attrib
 965                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
 966
 967 }
 968
 969 static void update_db_intercept(struct kvm_vcpu *vcpu)
 970 {
 971         struct vcpu_svm *svm = to_svm(vcpu);
 972
 973         svm->vmcb->control.intercept_exceptions &=
 974                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
 975
 976         if (vcpu->arch.singlestep)
 977                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
 978
 979         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
 980                 if (vcpu->guest_debug &
 981                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
 982                         svm->vmcb->control.intercept_exceptions |=
 983                                 1 << DB_VECTOR;
 984                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
 985                         svm->vmcb->control.intercept_exceptions |=
 986                                 1 << BP_VECTOR;
 987         } else
 988                 vcpu->guest_debug = 0;
 989 }
 990
 991 static int svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
 992 {
 993         int old_debug = vcpu->guest_debug;
 994         struct vcpu_svm *svm = to_svm(vcpu);
 995
 996         vcpu->guest_debug = dbg->control;
 997
 998         update_db_intercept(vcpu);
 999
1000         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1001                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1002         else
1003                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1004
1005         if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1006                 svm->vmcb->save.rflags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1007         else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1008                 svm->vmcb->save.rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1009
1010         return 0;
1011 }
1012
1013 static void load_host_msrs(struct kvm_vcpu *vcpu)
1014 {
1015 #ifdef CONFIG_X86_64
1016         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1017 #endif
1018 }
1019
1020 static void save_host_msrs(struct kvm_vcpu *vcpu)
1021 {
1022 #ifdef CONFIG_X86_64
1023         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1024 #endif
1025 }
1026
1027 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *svm_data)
1028 {
1029         if (svm_data->next_asid > svm_data->max_asid) {
1030                 ++svm_data->asid_generation;
1031                 svm_data->next_asid = 1;
1032                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1033         }
1034
1035         svm->asid_generation = svm_data->asid_generation;
1036         svm->vmcb->control.asid = svm_data->next_asid++;
1037 }
1038
1039 static unsigned long svm_get_dr(struct kvm_vcpu *vcpu, int dr)
1040 {
1041         struct vcpu_svm *svm = to_svm(vcpu);
1042         unsigned long val;
1043
1044         switch (dr) {
1045         case 0 ... 3:
1046                 val = vcpu->arch.db[dr];
1047                 break;
1048         case 6:
1049                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1050                         val = vcpu->arch.dr6;
1051                 else
1052                         val = svm->vmcb->save.dr6;
1053                 break;
1054         case 7:
1055                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1056                         val = vcpu->arch.dr7;
1057                 else
1058                         val = svm->vmcb->save.dr7;
1059                 break;
1060         default:
1061                 val = 0;
1062         }
1063
1064         KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
1065         return val;
1066 }
1067
1068 static void svm_set_dr(struct kvm_vcpu *vcpu, int dr, unsigned long value,
1069                        int *exception)
1070 {
1071         struct vcpu_svm *svm = to_svm(vcpu);
1072
1073         KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)value, handler);
1074
1075         *exception = 0;
1076
1077         switch (dr) {
1078         case 0 ... 3:
1079                 vcpu->arch.db[dr] = value;
1080                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
1081                         vcpu->arch.eff_db[dr] = value;
1082                 return;
1083         case 4 ... 5:
1084                 if (vcpu->arch.cr4 & X86_CR4_DE)
1085                         *exception = UD_VECTOR;
1086                 return;
1087         case 6:
1088                 if (value & 0xffffffff00000000ULL) {
1089                         *exception = GP_VECTOR;
1090                         return;
1091                 }
1092                 vcpu->arch.dr6 = (value & DR6_VOLATILE) | DR6_FIXED_1;
1093                 return;
1094         case 7:
1095                 if (value & 0xffffffff00000000ULL) {
1096                         *exception = GP_VECTOR;
1097                         return;
1098                 }
1099                 vcpu->arch.dr7 = (value & DR7_VOLATILE) | DR7_FIXED_1;
1100                 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
1101                         svm->vmcb->save.dr7 = vcpu->arch.dr7;
1102                         vcpu->arch.switch_db_regs = (value & DR7_BP_EN_MASK);
1103                 }
1104                 return;
1105         default:
1106                 /* FIXME: Possible case? */
1107                 printk(KERN_DEBUG "%s: unexpected dr %u\n",
1108                        __func__, dr);
1109                 *exception = UD_VECTOR;
1110                 return;
1111         }
1112 }
1113
1114 static int pf_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1115 {
1116         u64 fault_address;
1117         u32 error_code;
1118
1119         fault_address  = svm->vmcb->control.exit_info_2;
1120         error_code = svm->vmcb->control.exit_info_1;
1121
1122         if (!npt_enabled)
1123                 KVMTRACE_3D(PAGE_FAULT, &svm->vcpu, error_code,
1124                             (u32)fault_address, (u32)(fault_address >> 32),
1125                             handler);
1126         else
1127                 KVMTRACE_3D(TDP_FAULT, &svm->vcpu, error_code,
1128                             (u32)fault_address, (u32)(fault_address >> 32),
1129                             handler);
1130         /*
1131          * FIXME: Tis shouldn't be necessary here, but there is a flush
1132          * missing in the MMU code. Until we find this bug, flush the
1133          * complete TLB here on an NPF
1134          */
1135         if (npt_enabled)
1136                 svm_flush_tlb(&svm->vcpu);
1137         else {
1138                 if (kvm_event_needs_reinjection(&svm->vcpu))
1139                         kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1140         }
1141         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1142 }
1143
1144 static int db_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1145 {
1146         if (!(svm->vcpu.guest_debug &
1147               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1148                 !svm->vcpu.arch.singlestep) {
1149                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1150                 return 1;
1151         }
1152
1153         if (svm->vcpu.arch.singlestep) {
1154                 svm->vcpu.arch.singlestep = false;
1155                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1156                         svm->vmcb->save.rflags &=
1157                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1158                 update_db_intercept(&svm->vcpu);
1159         }
1160
1161         if (svm->vcpu.guest_debug &
1162             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)){
1163                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1164                 kvm_run->debug.arch.pc =
1165                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1166                 kvm_run->debug.arch.exception = DB_VECTOR;
1167                 return 0;
1168         }
1169
1170         return 1;
1171 }
1172
1173 static int bp_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1174 {
1175         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1176         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1177         kvm_run->debug.arch.exception = BP_VECTOR;
1178         return 0;
1179 }
1180
1181 static int ud_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1182 {
1183         int er;
1184
1185         er = emulate_instruction(&svm->vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
1186         if (er != EMULATE_DONE)
1187                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1188         return 1;
1189 }
1190
1191 static int nm_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1192 {
1193         svm->vmcb->control.intercept_exceptions &= ~(1 << NM_VECTOR);
1194         if (!(svm->vcpu.arch.cr0 & X86_CR0_TS))
1195                 svm->vmcb->save.cr0 &= ~X86_CR0_TS;
1196         svm->vcpu.fpu_active = 1;
1197
1198         return 1;
1199 }
1200
1201 static int mc_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1202 {
1203         /*
1204          * On an #MC intercept the MCE handler is not called automatically in
1205          * the host. So do it by hand here.
1206          */
1207         asm volatile (
1208                 "int $0x12\n");
1209         /* not sure if we ever come back to this point */
1210
1211         return 1;
1212 }
1213
1214 static int shutdown_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1215 {
1216         /*
1217          * VMCB is undefined after a SHUTDOWN intercept
1218          * so reinitialize it.
1219          */
1220         clear_page(svm->vmcb);
1221         init_vmcb(svm);
1222
1223         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1224         return 0;
1225 }
1226
1227 static int io_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1228 {
1229         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1230         int size, in, string;
1231         unsigned port;
1232
1233         ++svm->vcpu.stat.io_exits;
1234
1235         svm->next_rip = svm->vmcb->control.exit_info_2;
1236
1237         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1238
1239         if (string) {
1240                 if (emulate_instruction(&svm->vcpu,
1241                                         kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
1242                         return 0;
1243                 return 1;
1244         }
1245
1246         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1247         port = io_info >> 16;
1248         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1249
1250         skip_emulated_instruction(&svm->vcpu);
1251         return kvm_emulate_pio(&svm->vcpu, kvm_run, in, size, port);
1252 }
1253
1254 static int nmi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1255 {
1256         KVMTRACE_0D(NMI, &svm->vcpu, handler);
1257         return 1;
1258 }
1259
1260 static int intr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1261 {
1262         ++svm->vcpu.stat.irq_exits;
1263         KVMTRACE_0D(INTR, &svm->vcpu, handler);
1264         return 1;
1265 }
1266
1267 static int nop_on_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1268 {
1269         return 1;
1270 }
1271
1272 static int halt_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1273 {
1274         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1275         skip_emulated_instruction(&svm->vcpu);
1276         return kvm_emulate_halt(&svm->vcpu);
1277 }
1278
1279 static int vmmcall_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1280 {
1281         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1282         skip_emulated_instruction(&svm->vcpu);
1283         kvm_emulate_hypercall(&svm->vcpu);
1284         return 1;
1285 }
1286
1287 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1288 {
1289         if (!(svm->vcpu.arch.shadow_efer & EFER_SVME)
1290             || !is_paging(&svm->vcpu)) {
1291                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1292                 return 1;
1293         }
1294
1295         if (svm->vmcb->save.cpl) {
1296                 kvm_inject_gp(&svm->vcpu, 0);
1297                 return 1;
1298         }
1299
1300        return 0;
1301 }
1302
1303 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1304                                       bool has_error_code, u32 error_code)
1305 {
1306         if (is_nested(svm)) {
1307                 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1308                 svm->vmcb->control.exit_code_hi = 0;
1309                 svm->vmcb->control.exit_info_1 = error_code;
1310                 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1311                 if (nested_svm_exit_handled(svm, false)) {
1312                         nsvm_printk("VMexit -> EXCP 0x%x\n", nr);
1313
1314                         nested_svm_vmexit(svm);
1315                         return 1;
1316                 }
1317         }
1318
1319         return 0;
1320 }
1321
1322 static inline int nested_svm_intr(struct vcpu_svm *svm)
1323 {
1324         if (is_nested(svm)) {
1325                 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1326                         return 0;
1327
1328                 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1329                         return 0;
1330
1331                 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1332
1333                 if (nested_svm_exit_handled(svm, false)) {
1334                         nsvm_printk("VMexit -> INTR\n");
1335                         nested_svm_vmexit(svm);
1336                         return 1;
1337                 }
1338         }
1339
1340         return 0;
1341 }
1342
1343 static struct page *nested_svm_get_page(struct vcpu_svm *svm, u64 gpa)
1344 {
1345         struct page *page;
1346
1347         down_read(&current->mm->mmap_sem);
1348         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1349         up_read(&current->mm->mmap_sem);
1350
1351         if (is_error_page(page)) {
1352                 printk(KERN_INFO "%s: could not find page at 0x%llx\n",
1353                        __func__, gpa);
1354                 kvm_release_page_clean(page);
1355                 kvm_inject_gp(&svm->vcpu, 0);
1356                 return NULL;
1357         }
1358         return page;
1359 }
1360
1361 static int nested_svm_do(struct vcpu_svm *svm,
1362                          u64 arg1_gpa, u64 arg2_gpa, void *opaque,
1363                          int (*handler)(struct vcpu_svm *svm,
1364                                         void *arg1,
1365                                         void *arg2,
1366                                         void *opaque))
1367 {
1368         struct page *arg1_page;
1369         struct page *arg2_page = NULL;
1370         void *arg1;
1371         void *arg2 = NULL;
1372         int retval;
1373
1374         arg1_page = nested_svm_get_page(svm, arg1_gpa);
1375         if(arg1_page == NULL)
1376                 return 1;
1377
1378         if (arg2_gpa) {
1379                 arg2_page = nested_svm_get_page(svm, arg2_gpa);
1380                 if(arg2_page == NULL) {
1381                         kvm_release_page_clean(arg1_page);
1382                         return 1;
1383                 }
1384         }
1385
1386         arg1 = kmap_atomic(arg1_page, KM_USER0);
1387         if (arg2_gpa)
1388                 arg2 = kmap_atomic(arg2_page, KM_USER1);
1389
1390         retval = handler(svm, arg1, arg2, opaque);
1391
1392         kunmap_atomic(arg1, KM_USER0);
1393         if (arg2_gpa)
1394                 kunmap_atomic(arg2, KM_USER1);
1395
1396         kvm_release_page_dirty(arg1_page);
1397         if (arg2_gpa)
1398                 kvm_release_page_dirty(arg2_page);
1399
1400         return retval;
1401 }
1402
1403 static int nested_svm_exit_handled_real(struct vcpu_svm *svm,
1404                                         void *arg1,
1405                                         void *arg2,
1406                                         void *opaque)
1407 {
1408         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1409         bool kvm_overrides = *(bool *)opaque;
1410         u32 exit_code = svm->vmcb->control.exit_code;
1411
1412         if (kvm_overrides) {
1413                 switch (exit_code) {
1414                 case SVM_EXIT_INTR:
1415                 case SVM_EXIT_NMI:
1416                         return 0;
1417                 /* For now we are always handling NPFs when using them */
1418                 case SVM_EXIT_NPF:
1419                         if (npt_enabled)
1420                                 return 0;
1421                         break;
1422                 /* When we're shadowing, trap PFs */
1423                 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1424                         if (!npt_enabled)
1425                                 return 0;
1426                         break;
1427                 default:
1428                         break;
1429                 }
1430         }
1431
1432         switch (exit_code) {
1433         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1434                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1435                 if (nested_vmcb->control.intercept_cr_read & cr_bits)
1436                         return 1;
1437                 break;
1438         }
1439         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1440                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1441                 if (nested_vmcb->control.intercept_cr_write & cr_bits)
1442                         return 1;
1443                 break;
1444         }
1445         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1446                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1447                 if (nested_vmcb->control.intercept_dr_read & dr_bits)
1448                         return 1;
1449                 break;
1450         }
1451         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1452                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1453                 if (nested_vmcb->control.intercept_dr_write & dr_bits)
1454                         return 1;
1455                 break;
1456         }
1457         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1458                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1459                 if (nested_vmcb->control.intercept_exceptions & excp_bits)
1460                         return 1;
1461                 break;
1462         }
1463         default: {
1464                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1465                 nsvm_printk("exit code: 0x%x\n", exit_code);
1466                 if (nested_vmcb->control.intercept & exit_bits)
1467                         return 1;
1468         }
1469         }
1470
1471         return 0;
1472 }
1473
1474 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm,
1475                                        void *arg1, void *arg2,
1476                                        void *opaque)
1477 {
1478         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1479         u8 *msrpm = (u8 *)arg2;
1480         u32 t0, t1;
1481         u32 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1482         u32 param = svm->vmcb->control.exit_info_1 & 1;
1483
1484         if (!(nested_vmcb->control.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1485                 return 0;
1486
1487         switch(msr) {
1488         case 0 ... 0x1fff:
1489                 t0 = (msr * 2) % 8;
1490                 t1 = msr / 8;
1491                 break;
1492         case 0xc0000000 ... 0xc0001fff:
1493                 t0 = (8192 + msr - 0xc0000000) * 2;
1494                 t1 = (t0 / 8);
1495                 t0 %= 8;
1496                 break;
1497         case 0xc0010000 ... 0xc0011fff:
1498                 t0 = (16384 + msr - 0xc0010000) * 2;
1499                 t1 = (t0 / 8);
1500                 t0 %= 8;
1501                 break;
1502         default:
1503                 return 1;
1504                 break;
1505         }
1506         if (msrpm[t1] & ((1 << param) << t0))
1507                 return 1;
1508
1509         return 0;
1510 }
1511
1512 static int nested_svm_exit_handled(struct vcpu_svm *svm, bool kvm_override)
1513 {
1514         bool k = kvm_override;
1515
1516         switch (svm->vmcb->control.exit_code) {
1517         case SVM_EXIT_MSR:
1518                 return nested_svm_do(svm, svm->nested_vmcb,
1519                                      svm->nested_vmcb_msrpm, NULL,
1520                                      nested_svm_exit_handled_msr);
1521         default: break;
1522         }
1523
1524         return nested_svm_do(svm, svm->nested_vmcb, 0, &k,
1525                              nested_svm_exit_handled_real);
1526 }
1527
1528 static int nested_svm_vmexit_real(struct vcpu_svm *svm, void *arg1,
1529                                   void *arg2, void *opaque)
1530 {
1531         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1532         struct vmcb *hsave = svm->hsave;
1533         u64 nested_save[] = { nested_vmcb->save.cr0,
1534                               nested_vmcb->save.cr3,
1535                               nested_vmcb->save.cr4,
1536                               nested_vmcb->save.efer,
1537                               nested_vmcb->control.intercept_cr_read,
1538                               nested_vmcb->control.intercept_cr_write,
1539                               nested_vmcb->control.intercept_dr_read,
1540                               nested_vmcb->control.intercept_dr_write,
1541                               nested_vmcb->control.intercept_exceptions,
1542                               nested_vmcb->control.intercept,
1543                               nested_vmcb->control.msrpm_base_pa,
1544                               nested_vmcb->control.iopm_base_pa,
1545                               nested_vmcb->control.tsc_offset };
1546
1547         /* Give the current vmcb to the guest */
1548         memcpy(nested_vmcb, svm->vmcb, sizeof(struct vmcb));
1549         nested_vmcb->save.cr0 = nested_save[0];
1550         if (!npt_enabled)
1551                 nested_vmcb->save.cr3 = nested_save[1];
1552         nested_vmcb->save.cr4 = nested_save[2];
1553         nested_vmcb->save.efer = nested_save[3];
1554         nested_vmcb->control.intercept_cr_read = nested_save[4];
1555         nested_vmcb->control.intercept_cr_write = nested_save[5];
1556         nested_vmcb->control.intercept_dr_read = nested_save[6];
1557         nested_vmcb->control.intercept_dr_write = nested_save[7];
1558         nested_vmcb->control.intercept_exceptions = nested_save[8];
1559         nested_vmcb->control.intercept = nested_save[9];
1560         nested_vmcb->control.msrpm_base_pa = nested_save[10];
1561         nested_vmcb->control.iopm_base_pa = nested_save[11];
1562         nested_vmcb->control.tsc_offset = nested_save[12];
1563
1564         /* We always set V_INTR_MASKING and remember the old value in hflags */
1565         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1566                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1567
1568         if ((nested_vmcb->control.int_ctl & V_IRQ_MASK) &&
1569             (nested_vmcb->control.int_vector)) {
1570                 nsvm_printk("WARNING: IRQ 0x%x still enabled on #VMEXIT\n",
1571                                 nested_vmcb->control.int_vector);
1572         }
1573
1574         /* Restore the original control entries */
1575         svm->vmcb->control = hsave->control;
1576
1577         /* Kill any pending exceptions */
1578         if (svm->vcpu.arch.exception.pending == true)
1579                 nsvm_printk("WARNING: Pending Exception\n");
1580         svm->vcpu.arch.exception.pending = false;
1581
1582         /* Restore selected save entries */
1583         svm->vmcb->save.es = hsave->save.es;
1584         svm->vmcb->save.cs = hsave->save.cs;
1585         svm->vmcb->save.ss = hsave->save.ss;
1586         svm->vmcb->save.ds = hsave->save.ds;
1587         svm->vmcb->save.gdtr = hsave->save.gdtr;
1588         svm->vmcb->save.idtr = hsave->save.idtr;
1589         svm->vmcb->save.rflags = hsave->save.rflags;
1590         svm_set_efer(&svm->vcpu, hsave->save.efer);
1591         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1592         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1593         if (npt_enabled) {
1594                 svm->vmcb->save.cr3 = hsave->save.cr3;
1595                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1596         } else {
1597                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1598         }
1599         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1600         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1601         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1602         svm->vmcb->save.dr7 = 0;
1603         svm->vmcb->save.cpl = 0;
1604         svm->vmcb->control.exit_int_info = 0;
1605
1606         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1607         /* Exit nested SVM mode */
1608         svm->nested_vmcb = 0;
1609
1610         return 0;
1611 }
1612
1613 static int nested_svm_vmexit(struct vcpu_svm *svm)
1614 {
1615         nsvm_printk("VMexit\n");
1616         if (nested_svm_do(svm, svm->nested_vmcb, 0,
1617                           NULL, nested_svm_vmexit_real))
1618                 return 1;
1619
1620         kvm_mmu_reset_context(&svm->vcpu);
1621         kvm_mmu_load(&svm->vcpu);
1622
1623         return 0;
1624 }
1625
1626 static int nested_svm_vmrun_msrpm(struct vcpu_svm *svm, void *arg1,
1627                                   void *arg2, void *opaque)
1628 {
1629         int i;
1630         u32 *nested_msrpm = (u32*)arg1;
1631         for (i=0; i< PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER) / 4; i++)
1632                 svm->nested_msrpm[i] = svm->msrpm[i] | nested_msrpm[i];
1633         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested_msrpm);
1634
1635         return 0;
1636 }
1637
1638 static int nested_svm_vmrun(struct vcpu_svm *svm, void *arg1,
1639                             void *arg2, void *opaque)
1640 {
1641         struct vmcb *nested_vmcb = (struct vmcb *)arg1;
1642         struct vmcb *hsave = svm->hsave;
1643
1644         /* nested_vmcb is our indicator if nested SVM is activated */
1645         svm->nested_vmcb = svm->vmcb->save.rax;
1646
1647         /* Clear internal status */
1648         svm->vcpu.arch.exception.pending = false;
1649
1650         /* Save the old vmcb, so we don't need to pick what we save, but
1651            can restore everything when a VMEXIT occurs */
1652         memcpy(hsave, svm->vmcb, sizeof(struct vmcb));
1653         /* We need to remember the original CR3 in the SPT case */
1654         if (!npt_enabled)
1655                 hsave->save.cr3 = svm->vcpu.arch.cr3;
1656         hsave->save.cr4 = svm->vcpu.arch.cr4;
1657         hsave->save.rip = svm->next_rip;
1658
1659         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1660                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1661         else
1662                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1663
1664         /* Load the nested guest state */
1665         svm->vmcb->save.es = nested_vmcb->save.es;
1666         svm->vmcb->save.cs = nested_vmcb->save.cs;
1667         svm->vmcb->save.ss = nested_vmcb->save.ss;
1668         svm->vmcb->save.ds = nested_vmcb->save.ds;
1669         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1670         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1671         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1672         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1673         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1674         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1675         if (npt_enabled) {
1676                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1677                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1678         } else {
1679                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1680                 kvm_mmu_reset_context(&svm->vcpu);
1681         }
1682         svm->vmcb->save.cr2 = nested_vmcb->save.cr2;
1683         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
1684         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
1685         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
1686         /* In case we don't even reach vcpu_run, the fields are not updated */
1687         svm->vmcb->save.rax = nested_vmcb->save.rax;
1688         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
1689         svm->vmcb->save.rip = nested_vmcb->save.rip;
1690         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
1691         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
1692         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
1693
1694         /* We don't want a nested guest to be more powerful than the guest,
1695            so all intercepts are ORed */
1696         svm->vmcb->control.intercept_cr_read |=
1697                 nested_vmcb->control.intercept_cr_read;
1698         svm->vmcb->control.intercept_cr_write |=
1699                 nested_vmcb->control.intercept_cr_write;
1700         svm->vmcb->control.intercept_dr_read |=
1701                 nested_vmcb->control.intercept_dr_read;
1702         svm->vmcb->control.intercept_dr_write |=
1703                 nested_vmcb->control.intercept_dr_write;
1704         svm->vmcb->control.intercept_exceptions |=
1705                 nested_vmcb->control.intercept_exceptions;
1706
1707         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
1708
1709         svm->nested_vmcb_msrpm = nested_vmcb->control.msrpm_base_pa;
1710
1711         force_new_asid(&svm->vcpu);
1712         svm->vmcb->control.exit_int_info = nested_vmcb->control.exit_int_info;
1713         svm->vmcb->control.exit_int_info_err = nested_vmcb->control.exit_int_info_err;
1714         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
1715         if (nested_vmcb->control.int_ctl & V_IRQ_MASK) {
1716                 nsvm_printk("nSVM Injecting Interrupt: 0x%x\n",
1717                                 nested_vmcb->control.int_ctl);
1718         }
1719         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
1720                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
1721         else
1722                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
1723
1724         nsvm_printk("nSVM exit_int_info: 0x%x | int_state: 0x%x\n",
1725                         nested_vmcb->control.exit_int_info,
1726                         nested_vmcb->control.int_state);
1727
1728         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
1729         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
1730         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
1731         if (nested_vmcb->control.event_inj & SVM_EVTINJ_VALID)
1732                 nsvm_printk("Injecting Event: 0x%x\n",
1733                                 nested_vmcb->control.event_inj);
1734         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
1735         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
1736
1737         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1738
1739         return 0;
1740 }
1741
1742 static int nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
1743 {
1744         to_vmcb->save.fs = from_vmcb->save.fs;
1745         to_vmcb->save.gs = from_vmcb->save.gs;
1746         to_vmcb->save.tr = from_vmcb->save.tr;
1747         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
1748         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
1749         to_vmcb->save.star = from_vmcb->save.star;
1750         to_vmcb->save.lstar = from_vmcb->save.lstar;
1751         to_vmcb->save.cstar = from_vmcb->save.cstar;
1752         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
1753         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
1754         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
1755         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
1756
1757         return 1;
1758 }
1759
1760 static int nested_svm_vmload(struct vcpu_svm *svm, void *nested_vmcb,
1761                              void *arg2, void *opaque)
1762 {
1763         return nested_svm_vmloadsave((struct vmcb *)nested_vmcb, svm->vmcb);
1764 }
1765
1766 static int nested_svm_vmsave(struct vcpu_svm *svm, void *nested_vmcb,
1767                              void *arg2, void *opaque)
1768 {
1769         return nested_svm_vmloadsave(svm->vmcb, (struct vmcb *)nested_vmcb);
1770 }
1771
1772 static int vmload_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1773 {
1774         if (nested_svm_check_permissions(svm))
1775                 return 1;
1776
1777         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1778         skip_emulated_instruction(&svm->vcpu);
1779
1780         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmload);
1781
1782         return 1;
1783 }
1784
1785 static int vmsave_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1786 {
1787         if (nested_svm_check_permissions(svm))
1788                 return 1;
1789
1790         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1791         skip_emulated_instruction(&svm->vcpu);
1792
1793         nested_svm_do(svm, svm->vmcb->save.rax, 0, NULL, nested_svm_vmsave);
1794
1795         return 1;
1796 }
1797
1798 static int vmrun_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1799 {
1800         nsvm_printk("VMrun\n");
1801         if (nested_svm_check_permissions(svm))
1802                 return 1;
1803
1804         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1805         skip_emulated_instruction(&svm->vcpu);
1806
1807         if (nested_svm_do(svm, svm->vmcb->save.rax, 0,
1808                           NULL, nested_svm_vmrun))
1809                 return 1;
1810
1811         if (nested_svm_do(svm, svm->nested_vmcb_msrpm, 0,
1812                       NULL, nested_svm_vmrun_msrpm))
1813                 return 1;
1814
1815         return 1;
1816 }
1817
1818 static int stgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1819 {
1820         if (nested_svm_check_permissions(svm))
1821                 return 1;
1822
1823         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1824         skip_emulated_instruction(&svm->vcpu);
1825
1826         svm->vcpu.arch.hflags |= HF_GIF_MASK;
1827
1828         return 1;
1829 }
1830
1831 static int clgi_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1832 {
1833         if (nested_svm_check_permissions(svm))
1834                 return 1;
1835
1836         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1837         skip_emulated_instruction(&svm->vcpu);
1838
1839         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
1840
1841         /* After a CLGI no interrupts should come */
1842         svm_clear_vintr(svm);
1843         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
1844
1845         return 1;
1846 }
1847
1848 static int invalid_op_interception(struct vcpu_svm *svm,
1849                                    struct kvm_run *kvm_run)
1850 {
1851         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1852         return 1;
1853 }
1854
1855 static int task_switch_interception(struct vcpu_svm *svm,
1856                                     struct kvm_run *kvm_run)
1857 {
1858         u16 tss_selector;
1859         int reason;
1860         int int_type = svm->vmcb->control.exit_int_info &
1861                 SVM_EXITINTINFO_TYPE_MASK;
1862         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
1863         uint32_t type =
1864                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
1865         uint32_t idt_v =
1866                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
1867
1868         tss_selector = (u16)svm->vmcb->control.exit_info_1;
1869
1870         if (svm->vmcb->control.exit_info_2 &
1871             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
1872                 reason = TASK_SWITCH_IRET;
1873         else if (svm->vmcb->control.exit_info_2 &
1874                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
1875                 reason = TASK_SWITCH_JMP;
1876         else if (idt_v)
1877                 reason = TASK_SWITCH_GATE;
1878         else
1879                 reason = TASK_SWITCH_CALL;
1880
1881         if (reason == TASK_SWITCH_GATE) {
1882                 switch (type) {
1883                 case SVM_EXITINTINFO_TYPE_NMI:
1884                         svm->vcpu.arch.nmi_injected = false;
1885                         break;
1886                 case SVM_EXITINTINFO_TYPE_EXEPT:
1887                         kvm_clear_exception_queue(&svm->vcpu);
1888                         break;
1889                 case SVM_EXITINTINFO_TYPE_INTR:
1890                         kvm_clear_interrupt_queue(&svm->vcpu);
1891                         break;
1892                 default:
1893                         break;
1894                 }
1895         }
1896
1897         if (reason != TASK_SWITCH_GATE ||
1898             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
1899             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
1900              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
1901                 skip_emulated_instruction(&svm->vcpu);
1902
1903         return kvm_task_switch(&svm->vcpu, tss_selector, reason);
1904 }
1905
1906 static int cpuid_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1907 {
1908         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
1909         kvm_emulate_cpuid(&svm->vcpu);
1910         return 1;
1911 }
1912
1913 static int iret_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1914 {
1915         ++svm->vcpu.stat.nmi_window_exits;
1916         svm->vmcb->control.intercept &= ~(1UL << INTERCEPT_IRET);
1917         svm->vcpu.arch.hflags |= HF_IRET_MASK;
1918         return 1;
1919 }
1920
1921 static int invlpg_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1922 {
1923         if (emulate_instruction(&svm->vcpu, kvm_run, 0, 0, 0) != EMULATE_DONE)
1924                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1925         return 1;
1926 }
1927
1928 static int emulate_on_interception(struct vcpu_svm *svm,
1929                                    struct kvm_run *kvm_run)
1930 {
1931         if (emulate_instruction(&svm->vcpu, NULL, 0, 0, 0) != EMULATE_DONE)
1932                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
1933         return 1;
1934 }
1935
1936 static int cr8_write_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
1937 {
1938         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
1939         /* instruction emulation calls kvm_set_cr8() */
1940         emulate_instruction(&svm->vcpu, NULL, 0, 0, 0);
1941         if (irqchip_in_kernel(svm->vcpu.kvm)) {
1942                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
1943                 return 1;
1944         }
1945         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
1946                 return 1;
1947         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
1948         return 0;
1949 }
1950
1951 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
1952 {
1953         struct vcpu_svm *svm = to_svm(vcpu);
1954
1955         switch (ecx) {
1956         case MSR_IA32_TIME_STAMP_COUNTER: {
1957                 u64 tsc;
1958
1959                 rdtscll(tsc);
1960                 *data = svm->vmcb->control.tsc_offset + tsc;
1961                 break;
1962         }
1963         case MSR_K6_STAR:
1964                 *data = svm->vmcb->save.star;
1965                 break;
1966 #ifdef CONFIG_X86_64
1967         case MSR_LSTAR:
1968                 *data = svm->vmcb->save.lstar;
1969                 break;
1970         case MSR_CSTAR:
1971                 *data = svm->vmcb->save.cstar;
1972                 break;
1973         case MSR_KERNEL_GS_BASE:
1974                 *data = svm->vmcb->save.kernel_gs_base;
1975                 break;
1976         case MSR_SYSCALL_MASK:
1977                 *data = svm->vmcb->save.sfmask;
1978                 break;
1979 #endif
1980         case MSR_IA32_SYSENTER_CS:
1981                 *data = svm->vmcb->save.sysenter_cs;
1982                 break;
1983         case MSR_IA32_SYSENTER_EIP:
1984                 *data = svm->vmcb->save.sysenter_eip;
1985                 break;
1986         case MSR_IA32_SYSENTER_ESP:
1987                 *data = svm->vmcb->save.sysenter_esp;
1988                 break;
1989         /* Nobody will change the following 5 values in the VMCB so
1990            we can safely return them on rdmsr. They will always be 0
1991            until LBRV is implemented. */
1992         case MSR_IA32_DEBUGCTLMSR:
1993                 *data = svm->vmcb->save.dbgctl;
1994                 break;
1995         case MSR_IA32_LASTBRANCHFROMIP:
1996                 *data = svm->vmcb->save.br_from;
1997                 break;
1998         case MSR_IA32_LASTBRANCHTOIP:
1999                 *data = svm->vmcb->save.br_to;
2000                 break;
2001         case MSR_IA32_LASTINTFROMIP:
2002                 *data = svm->vmcb->save.last_excp_from;
2003                 break;
2004         case MSR_IA32_LASTINTTOIP:
2005                 *data = svm->vmcb->save.last_excp_to;
2006                 break;
2007         case MSR_VM_HSAVE_PA:
2008                 *data = svm->hsave_msr;
2009                 break;
2010         case MSR_VM_CR:
2011                 *data = 0;
2012                 break;
2013         case MSR_IA32_UCODE_REV:
2014                 *data = 0x01000065;
2015                 break;
2016         default:
2017                 return kvm_get_msr_common(vcpu, ecx, data);
2018         }
2019         return 0;
2020 }
2021
2022 static int rdmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2023 {
2024         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2025         u64 data;
2026
2027         if (svm_get_msr(&svm->vcpu, ecx, &data))
2028                 kvm_inject_gp(&svm->vcpu, 0);
2029         else {
2030                 KVMTRACE_3D(MSR_READ, &svm->vcpu, ecx, (u32)data,
2031                             (u32)(data >> 32), handler);
2032
2033                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2034                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2035                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2036                 skip_emulated_instruction(&svm->vcpu);
2037         }
2038         return 1;
2039 }
2040
2041 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2042 {
2043         struct vcpu_svm *svm = to_svm(vcpu);
2044
2045         switch (ecx) {
2046         case MSR_IA32_TIME_STAMP_COUNTER: {
2047                 u64 tsc;
2048
2049                 rdtscll(tsc);
2050                 svm->vmcb->control.tsc_offset = data - tsc;
2051                 break;
2052         }
2053         case MSR_K6_STAR:
2054                 svm->vmcb->save.star = data;
2055                 break;
2056 #ifdef CONFIG_X86_64
2057         case MSR_LSTAR:
2058                 svm->vmcb->save.lstar = data;
2059                 break;
2060         case MSR_CSTAR:
2061                 svm->vmcb->save.cstar = data;
2062                 break;
2063         case MSR_KERNEL_GS_BASE:
2064                 svm->vmcb->save.kernel_gs_base = data;
2065                 break;
2066         case MSR_SYSCALL_MASK:
2067                 svm->vmcb->save.sfmask = data;
2068                 break;
2069 #endif
2070         case MSR_IA32_SYSENTER_CS:
2071                 svm->vmcb->save.sysenter_cs = data;
2072                 break;
2073         case MSR_IA32_SYSENTER_EIP:
2074                 svm->vmcb->save.sysenter_eip = data;
2075                 break;
2076         case MSR_IA32_SYSENTER_ESP:
2077                 svm->vmcb->save.sysenter_esp = data;
2078                 break;
2079         case MSR_IA32_DEBUGCTLMSR:
2080                 if (!svm_has(SVM_FEATURE_LBRV)) {
2081                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2082                                         __func__, data);
2083                         break;
2084                 }
2085                 if (data & DEBUGCTL_RESERVED_BITS)
2086                         return 1;
2087
2088                 svm->vmcb->save.dbgctl = data;
2089                 if (data & (1ULL<<0))
2090                         svm_enable_lbrv(svm);
2091                 else
2092                         svm_disable_lbrv(svm);
2093                 break;
2094         case MSR_K7_EVNTSEL0:
2095         case MSR_K7_EVNTSEL1:
2096         case MSR_K7_EVNTSEL2:
2097         case MSR_K7_EVNTSEL3:
2098         case MSR_K7_PERFCTR0:
2099         case MSR_K7_PERFCTR1:
2100         case MSR_K7_PERFCTR2:
2101         case MSR_K7_PERFCTR3:
2102                 /*
2103                  * Just discard all writes to the performance counters; this
2104                  * should keep both older linux and windows 64-bit guests
2105                  * happy
2106                  */
2107                 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: 0x%x data 0x%llx\n", ecx, data);
2108
2109                 break;
2110         case MSR_VM_HSAVE_PA:
2111                 svm->hsave_msr = data;
2112                 break;
2113         default:
2114                 return kvm_set_msr_common(vcpu, ecx, data);
2115         }
2116         return 0;
2117 }
2118
2119 static int wrmsr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2120 {
2121         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2122         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2123                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2124
2125         KVMTRACE_3D(MSR_WRITE, &svm->vcpu, ecx, (u32)data, (u32)(data >> 32),
2126                     handler);
2127
2128         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2129         if (svm_set_msr(&svm->vcpu, ecx, data))
2130                 kvm_inject_gp(&svm->vcpu, 0);
2131         else
2132                 skip_emulated_instruction(&svm->vcpu);
2133         return 1;
2134 }
2135
2136 static int msr_interception(struct vcpu_svm *svm, struct kvm_run *kvm_run)
2137 {
2138         if (svm->vmcb->control.exit_info_1)
2139                 return wrmsr_interception(svm, kvm_run);
2140         else
2141                 return rdmsr_interception(svm, kvm_run);
2142 }
2143
2144 static int interrupt_window_interception(struct vcpu_svm *svm,
2145                                    struct kvm_run *kvm_run)
2146 {
2147         KVMTRACE_0D(PEND_INTR, &svm->vcpu, handler);
2148
2149         svm_clear_vintr(svm);
2150         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2151         /*
2152          * If the user space waits to inject interrupts, exit as soon as
2153          * possible
2154          */
2155         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2156             kvm_run->request_interrupt_window &&
2157             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2158                 ++svm->vcpu.stat.irq_window_exits;
2159                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2160                 return 0;
2161         }
2162
2163         return 1;
2164 }
2165
2166 static int (*svm_exit_handlers[])(struct vcpu_svm *svm,
2167                                       struct kvm_run *kvm_run) = {
2168         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2169         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2170         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2171         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2172         /* for now: */
2173         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2174         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2175         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2176         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2177         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2178         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2179         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2180         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2181         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2182         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2183         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2184         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2185         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2186         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2187         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2188         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2189         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2190         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2191         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2192         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2193         [SVM_EXIT_INTR]                         = intr_interception,
2194         [SVM_EXIT_NMI]                          = nmi_interception,
2195         [SVM_EXIT_SMI]                          = nop_on_interception,
2196         [SVM_EXIT_INIT]                         = nop_on_interception,
2197         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2198         /* [SVM_EXIT_CR0_SEL_WRITE]             = emulate_on_interception, */
2199         [SVM_EXIT_CPUID]                        = cpuid_interception,
2200         [SVM_EXIT_IRET]                         = iret_interception,
2201         [SVM_EXIT_INVD]                         = emulate_on_interception,
2202         [SVM_EXIT_HLT]                          = halt_interception,
2203         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2204         [SVM_EXIT_INVLPGA]                      = invalid_op_interception,
2205         [SVM_EXIT_IOIO]                         = io_interception,
2206         [SVM_EXIT_MSR]                          = msr_interception,
2207         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2208         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2209         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2210         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2211         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2212         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2213         [SVM_EXIT_STGI]                         = stgi_interception,
2214         [SVM_EXIT_CLGI]                         = clgi_interception,
2215         [SVM_EXIT_SKINIT]                       = invalid_op_interception,
2216         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2217         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2218         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2219         [SVM_EXIT_NPF]                          = pf_interception,
2220 };
2221
2222 static int handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
2223 {
2224         struct vcpu_svm *svm = to_svm(vcpu);
2225         u32 exit_code = svm->vmcb->control.exit_code;
2226
2227         KVMTRACE_3D(VMEXIT, vcpu, exit_code, (u32)svm->vmcb->save.rip,
2228                     (u32)((u64)svm->vmcb->save.rip >> 32), entryexit);
2229
2230         if (is_nested(svm)) {
2231                 nsvm_printk("nested handle_exit: 0x%x | 0x%lx | 0x%lx | 0x%lx\n",
2232                             exit_code, svm->vmcb->control.exit_info_1,
2233                             svm->vmcb->control.exit_info_2, svm->vmcb->save.rip);
2234                 if (nested_svm_exit_handled(svm, true)) {
2235                         nested_svm_vmexit(svm);
2236                         nsvm_printk("-> #VMEXIT\n");
2237                         return 1;
2238                 }
2239         }
2240
2241         if (npt_enabled) {
2242                 int mmu_reload = 0;
2243                 if ((vcpu->arch.cr0 ^ svm->vmcb->save.cr0) & X86_CR0_PG) {
2244                         svm_set_cr0(vcpu, svm->vmcb->save.cr0);
2245                         mmu_reload = 1;
2246                 }
2247                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2248                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2249                 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
2250                         if (!load_pdptrs(vcpu, vcpu->arch.cr3)) {
2251                                 kvm_inject_gp(vcpu, 0);
2252                                 return 1;
2253                         }
2254                 }
2255                 if (mmu_reload) {
2256                         kvm_mmu_reset_context(vcpu);
2257                         kvm_mmu_load(vcpu);
2258                 }
2259         }
2260
2261
2262         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2263                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2264                 kvm_run->fail_entry.hardware_entry_failure_reason
2265                         = svm->vmcb->control.exit_code;
2266                 return 0;
2267         }
2268
2269         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2270             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2271             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2272                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2273                        "exit_code 0x%x\n",
2274                        __func__, svm->vmcb->control.exit_int_info,
2275                        exit_code);
2276
2277         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2278             || !svm_exit_handlers[exit_code]) {
2279                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2280                 kvm_run->hw.hardware_exit_reason = exit_code;
2281                 return 0;
2282         }
2283
2284         return svm_exit_handlers[exit_code](svm, kvm_run);
2285 }
2286
2287 static void reload_tss(struct kvm_vcpu *vcpu)
2288 {
2289         int cpu = raw_smp_processor_id();
2290
2291         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2292         svm_data->tss_desc->type = 9; /* available 32/64-bit TSS */
2293         load_TR_desc();
2294 }
2295
2296 static void pre_svm_run(struct vcpu_svm *svm)
2297 {
2298         int cpu = raw_smp_processor_id();
2299
2300         struct svm_cpu_data *svm_data = per_cpu(svm_data, cpu);
2301
2302         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2303         /* FIXME: handle wraparound of asid_generation */
2304         if (svm->asid_generation != svm_data->asid_generation)
2305                 new_asid(svm, svm_data);
2306 }
2307
2308 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2309 {
2310         struct vcpu_svm *svm = to_svm(vcpu);
2311
2312         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2313         vcpu->arch.hflags |= HF_NMI_MASK;
2314         svm->vmcb->control.intercept |= (1UL << INTERCEPT_IRET);
2315         ++vcpu->stat.nmi_injections;
2316 }
2317
2318 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2319 {
2320         struct vmcb_control_area *control;
2321
2322         KVMTRACE_1D(INJ_VIRQ, &svm->vcpu, (u32)irq, handler);
2323
2324         ++svm->vcpu.stat.irq_injections;
2325         control = &svm->vmcb->control;
2326         control->int_vector = irq;
2327         control->int_ctl &= ~V_INTR_PRIO_MASK;
2328         control->int_ctl |= V_IRQ_MASK |
2329                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2330 }
2331
2332 static void svm_queue_irq(struct kvm_vcpu *vcpu, unsigned nr)
2333 {
2334         struct vcpu_svm *svm = to_svm(vcpu);
2335
2336         svm->vmcb->control.event_inj = nr |
2337                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2338 }
2339
2340 static void svm_set_irq(struct kvm_vcpu *vcpu)
2341 {
2342         struct vcpu_svm *svm = to_svm(vcpu);
2343
2344         nested_svm_intr(svm);
2345
2346         svm_queue_irq(vcpu, vcpu->arch.interrupt.nr);
2347 }
2348
2349 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2350 {
2351         struct vcpu_svm *svm = to_svm(vcpu);
2352
2353         if (irr == -1)
2354                 return;
2355
2356         if (tpr >= irr)
2357                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2358 }
2359
2360 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2361 {
2362         struct vcpu_svm *svm = to_svm(vcpu);
2363         struct vmcb *vmcb = svm->vmcb;
2364         return !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2365                 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2366 }
2367
2368 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2369 {
2370         struct vcpu_svm *svm = to_svm(vcpu);
2371         struct vmcb *vmcb = svm->vmcb;
2372         return (vmcb->save.rflags & X86_EFLAGS_IF) &&
2373                 !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2374                 (svm->vcpu.arch.hflags & HF_GIF_MASK);
2375 }
2376
2377 static void enable_irq_window(struct kvm_vcpu *vcpu)
2378 {
2379         svm_set_vintr(to_svm(vcpu));
2380         svm_inject_irq(to_svm(vcpu), 0x0);
2381 }
2382
2383 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2384 {
2385         struct vcpu_svm *svm = to_svm(vcpu);
2386
2387         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2388             == HF_NMI_MASK)
2389                 return; /* IRET will cause a vm exit */
2390
2391         /* Something prevents NMI from been injected. Single step over
2392            possible problem (IRET or exception injection or interrupt
2393            shadow) */
2394         vcpu->arch.singlestep = true;
2395         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2396         update_db_intercept(vcpu);
2397 }
2398
2399 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2400 {
2401         return 0;
2402 }
2403
2404 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2405 {
2406         force_new_asid(vcpu);
2407 }
2408
2409 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2410 {
2411 }
2412
2413 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2414 {
2415         struct vcpu_svm *svm = to_svm(vcpu);
2416
2417         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2418                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2419                 kvm_set_cr8(vcpu, cr8);
2420         }
2421 }
2422
2423 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2424 {
2425         struct vcpu_svm *svm = to_svm(vcpu);
2426         u64 cr8;
2427
2428         cr8 = kvm_get_cr8(vcpu);
2429         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2430         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2431 }
2432
2433 static void svm_complete_interrupts(struct vcpu_svm *svm)
2434 {
2435         u8 vector;
2436         int type;
2437         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2438
2439         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2440                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2441
2442         svm->vcpu.arch.nmi_injected = false;
2443         kvm_clear_exception_queue(&svm->vcpu);
2444         kvm_clear_interrupt_queue(&svm->vcpu);
2445
2446         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2447                 return;
2448
2449         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2450         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2451
2452         switch (type) {
2453         case SVM_EXITINTINFO_TYPE_NMI:
2454                 svm->vcpu.arch.nmi_injected = true;
2455                 break;
2456         case SVM_EXITINTINFO_TYPE_EXEPT:
2457                 /* In case of software exception do not reinject an exception
2458                    vector, but re-execute and instruction instead */
2459                 if (kvm_exception_is_soft(vector))
2460                         break;
2461                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2462                         u32 err = svm->vmcb->control.exit_int_info_err;
2463                         kvm_queue_exception_e(&svm->vcpu, vector, err);
2464
2465                 } else
2466                         kvm_queue_exception(&svm->vcpu, vector);
2467                 break;
2468         case SVM_EXITINTINFO_TYPE_INTR:
2469                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2470                 break;
2471         default:
2472                 break;
2473         }
2474 }
2475
2476 #ifdef CONFIG_X86_64
2477 #define R "r"
2478 #else
2479 #define R "e"
2480 #endif
2481
2482 static void svm_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2483 {
2484         struct vcpu_svm *svm = to_svm(vcpu);
2485         u16 fs_selector;
2486         u16 gs_selector;
2487         u16 ldt_selector;
2488
2489         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2490         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2491         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2492
2493         pre_svm_run(svm);
2494
2495         sync_lapic_to_cr8(vcpu);
2496
2497         save_host_msrs(vcpu);
2498         fs_selector = kvm_read_fs();
2499         gs_selector = kvm_read_gs();
2500         ldt_selector = kvm_read_ldt();
2501         svm->host_cr2 = kvm_read_cr2();
2502         if (!is_nested(svm))
2503                 svm->vmcb->save.cr2 = vcpu->arch.cr2;
2504         /* required for live migration with NPT */
2505         if (npt_enabled)
2506                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2507
2508         clgi();
2509
2510         local_irq_enable();
2511
2512         asm volatile (
2513                 "push %%"R"bp; \n\t"
2514                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2515                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
2516                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
2517                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
2518                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
2519                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
2520 #ifdef CONFIG_X86_64
2521                 "mov %c[r8](%[svm]),  %%r8  \n\t"
2522                 "mov %c[r9](%[svm]),  %%r9  \n\t"
2523                 "mov %c[r10](%[svm]), %%r10 \n\t"
2524                 "mov %c[r11](%[svm]), %%r11 \n\t"
2525                 "mov %c[r12](%[svm]), %%r12 \n\t"
2526                 "mov %c[r13](%[svm]), %%r13 \n\t"
2527                 "mov %c[r14](%[svm]), %%r14 \n\t"
2528                 "mov %c[r15](%[svm]), %%r15 \n\t"
2529 #endif
2530
2531                 /* Enter guest mode */
2532                 "push %%"R"ax \n\t"
2533                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
2534                 __ex(SVM_VMLOAD) "\n\t"
2535                 __ex(SVM_VMRUN) "\n\t"
2536                 __ex(SVM_VMSAVE) "\n\t"
2537                 "pop %%"R"ax \n\t"
2538
2539                 /* Save guest registers, load host registers */
2540                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
2541                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
2542                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
2543                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
2544                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
2545                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
2546 #ifdef CONFIG_X86_64
2547                 "mov %%r8,  %c[r8](%[svm]) \n\t"
2548                 "mov %%r9,  %c[r9](%[svm]) \n\t"
2549                 "mov %%r10, %c[r10](%[svm]) \n\t"
2550                 "mov %%r11, %c[r11](%[svm]) \n\t"
2551                 "mov %%r12, %c[r12](%[svm]) \n\t"
2552                 "mov %%r13, %c[r13](%[svm]) \n\t"
2553                 "mov %%r14, %c[r14](%[svm]) \n\t"
2554                 "mov %%r15, %c[r15](%[svm]) \n\t"
2555 #endif
2556                 "pop %%"R"bp"
2557                 :
2558                 : [svm]"a"(svm),
2559                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
2560                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
2561                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
2562                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
2563                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
2564                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
2565                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
2566 #ifdef CONFIG_X86_64
2567                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
2568                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
2569                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
2570                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
2571                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
2572                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
2573                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
2574                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
2575 #endif
2576                 : "cc", "memory"
2577                 , R"bx", R"cx", R"dx", R"si", R"di"
2578 #ifdef CONFIG_X86_64
2579                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
2580 #endif
2581                 );
2582
2583         vcpu->arch.cr2 = svm->vmcb->save.cr2;
2584         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
2585         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
2586         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
2587
2588         kvm_write_cr2(svm->host_cr2);
2589
2590         kvm_load_fs(fs_selector);
2591         kvm_load_gs(gs_selector);
2592         kvm_load_ldt(ldt_selector);
2593         load_host_msrs(vcpu);
2594
2595         reload_tss(vcpu);
2596
2597         local_irq_disable();
2598
2599         stgi();
2600
2601         sync_cr8_to_lapic(vcpu);
2602
2603         svm->next_rip = 0;
2604
2605         svm_complete_interrupts(svm);
2606 }
2607
2608 #undef R
2609
2610 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
2611 {
2612         struct vcpu_svm *svm = to_svm(vcpu);
2613
2614         if (npt_enabled) {
2615                 svm->vmcb->control.nested_cr3 = root;
2616                 force_new_asid(vcpu);
2617                 return;
2618         }
2619
2620         svm->vmcb->save.cr3 = root;
2621         force_new_asid(vcpu);
2622
2623         if (vcpu->fpu_active) {
2624                 svm->vmcb->control.intercept_exceptions |= (1 << NM_VECTOR);
2625                 svm->vmcb->save.cr0 |= X86_CR0_TS;
2626                 vcpu->fpu_active = 0;
2627         }
2628 }
2629
2630 static int is_disabled(void)
2631 {
2632         u64 vm_cr;
2633
2634         rdmsrl(MSR_VM_CR, vm_cr);
2635         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
2636                 return 1;
2637
2638         return 0;
2639 }
2640
2641 static void
2642 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2643 {
2644         /*
2645          * Patch in the VMMCALL instruction:
2646          */
2647         hypercall[0] = 0x0f;
2648         hypercall[1] = 0x01;
2649         hypercall[2] = 0xd9;
2650 }
2651
2652 static void svm_check_processor_compat(void *rtn)
2653 {
2654         *(int *)rtn = 0;
2655 }
2656
2657 static bool svm_cpu_has_accelerated_tpr(void)
2658 {
2659         return false;
2660 }
2661
2662 static int get_npt_level(void)
2663 {
2664 #ifdef CONFIG_X86_64
2665         return PT64_ROOT_LEVEL;
2666 #else
2667         return PT32E_ROOT_LEVEL;
2668 #endif
2669 }
2670
2671 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
2672 {
2673         return 0;
2674 }
2675
2676 static struct kvm_x86_ops svm_x86_ops = {
2677         .cpu_has_kvm_support = has_svm,
2678         .disabled_by_bios = is_disabled,
2679         .hardware_setup = svm_hardware_setup,
2680         .hardware_unsetup = svm_hardware_unsetup,
2681         .check_processor_compatibility = svm_check_processor_compat,
2682         .hardware_enable = svm_hardware_enable,
2683         .hardware_disable = svm_hardware_disable,
2684         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
2685
2686         .vcpu_create = svm_create_vcpu,
2687         .vcpu_free = svm_free_vcpu,
2688         .vcpu_reset = svm_vcpu_reset,
2689
2690         .prepare_guest_switch = svm_prepare_guest_switch,
2691         .vcpu_load = svm_vcpu_load,
2692         .vcpu_put = svm_vcpu_put,
2693
2694         .set_guest_debug = svm_guest_debug,
2695         .get_msr = svm_get_msr,
2696         .set_msr = svm_set_msr,
2697         .get_segment_base = svm_get_segment_base,
2698         .get_segment = svm_get_segment,
2699         .set_segment = svm_set_segment,
2700         .get_cpl = svm_get_cpl,
2701         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
2702         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
2703         .set_cr0 = svm_set_cr0,
2704         .set_cr3 = svm_set_cr3,
2705         .set_cr4 = svm_set_cr4,
2706         .set_efer = svm_set_efer,
2707         .get_idt = svm_get_idt,
2708         .set_idt = svm_set_idt,
2709         .get_gdt = svm_get_gdt,
2710         .set_gdt = svm_set_gdt,
2711         .get_dr = svm_get_dr,
2712         .set_dr = svm_set_dr,
2713         .get_rflags = svm_get_rflags,
2714         .set_rflags = svm_set_rflags,
2715
2716         .tlb_flush = svm_flush_tlb,
2717
2718         .run = svm_vcpu_run,
2719         .handle_exit = handle_exit,
2720         .skip_emulated_instruction = skip_emulated_instruction,
2721         .set_interrupt_shadow = svm_set_interrupt_shadow,
2722         .get_interrupt_shadow = svm_get_interrupt_shadow,
2723         .patch_hypercall = svm_patch_hypercall,
2724         .set_irq = svm_set_irq,
2725         .set_nmi = svm_inject_nmi,
2726         .queue_exception = svm_queue_exception,
2727         .interrupt_allowed = svm_interrupt_allowed,
2728         .nmi_allowed = svm_nmi_allowed,
2729         .enable_nmi_window = enable_nmi_window,
2730         .enable_irq_window = enable_irq_window,
2731         .update_cr8_intercept = update_cr8_intercept,
2732
2733         .set_tss_addr = svm_set_tss_addr,
2734         .get_tdp_level = get_npt_level,
2735         .get_mt_mask = svm_get_mt_mask,
2736 };
2737
2738 static int __init svm_init(void)
2739 {
2740         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
2741                               THIS_MODULE);
2742 }
2743
2744 static void __exit svm_exit(void)
2745 {
2746         kvm_exit();
2747 }
2748
2749 module_init(svm_init)
2750 module_exit(svm_exit)