arch/x86/kvm/svm.c

   1 /*
   2  * Kernel-based Virtual Machine driver for Linux
   3  *
   4  * AMD SVM support
   5  *
   6  * Copyright (C) 2006 Qumranet, Inc.
   7  *
   8  * Authors:
   9  *   Yaniv Kamay  <yaniv@qumranet.com>
  10  *   Avi Kivity   <avi@qumranet.com>
  11  *
  12  * This work is licensed under the terms of the GNU GPL, version 2.  See
  13  * the COPYING file in the top-level directory.
  14  *
  15  */
  16 #include <linux/kvm_host.h>
  17
  18 #include "irq.h"
  19 #include "mmu.h"
  20 #include "kvm_cache_regs.h"
  21 #include "x86.h"
  22
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/highmem.h>
  27 #include <linux/sched.h>
  28 #include <linux/ftrace_event.h>
  29 #include <linux/slab.h>
  30
  31 #include <asm/desc.h>
  32
  33 #include <asm/virtext.h>
  34 #include "trace.h"
  35
  36 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  37
  38 MODULE_AUTHOR("Qumranet");
  39 MODULE_LICENSE("GPL");
  40
  41 #define IOPM_ALLOC_ORDER 2
  42 #define MSRPM_ALLOC_ORDER 1
  43
  44 #define SEG_TYPE_LDT 2
  45 #define SEG_TYPE_BUSY_TSS16 3
  46
  47 #define SVM_FEATURE_NPT            (1 <<  0)
  48 #define SVM_FEATURE_LBRV           (1 <<  1)
  49 #define SVM_FEATURE_SVML           (1 <<  2)
  50 #define SVM_FEATURE_NRIP           (1 <<  3)
  51 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  52
  53 #define NESTED_EXIT_HOST        0       /* Exit handled on host level */
  54 #define NESTED_EXIT_DONE        1       /* Exit caused nested vmexit  */
  55 #define NESTED_EXIT_CONTINUE    2       /* Further checks needed      */
  56
  57 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  58
  59 static const u32 host_save_user_msrs[] = {
  60 #ifdef CONFIG_X86_64
  61         MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  62         MSR_FS_BASE,
  63 #endif
  64         MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  65 };
  66
  67 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  68
  69 struct kvm_vcpu;
  70
  71 struct nested_state {
  72         struct vmcb *hsave;
  73         u64 hsave_msr;
  74         u64 vm_cr_msr;
  75         u64 vmcb;
  76
  77         /* These are the merged vectors */
  78         u32 *msrpm;
  79
  80         /* gpa pointers to the real vectors */
  81         u64 vmcb_msrpm;
  82         u64 vmcb_iopm;
  83
  84         /* A VMEXIT is required but not yet emulated */
  85         bool exit_required;
  86
  87         /* cache for intercepts of the guest */
  88         u16 intercept_cr_read;
  89         u16 intercept_cr_write;
  90         u16 intercept_dr_read;
  91         u16 intercept_dr_write;
  92         u32 intercept_exceptions;
  93         u64 intercept;
  94
  95 };
  96
  97 #define MSRPM_OFFSETS   16
  98 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  99
 100 struct vcpu_svm {
 101         struct kvm_vcpu vcpu;
 102         struct vmcb *vmcb;
 103         unsigned long vmcb_pa;
 104         struct svm_cpu_data *svm_data;
 105         uint64_t asid_generation;
 106         uint64_t sysenter_esp;
 107         uint64_t sysenter_eip;
 108
 109         u64 next_rip;
 110
 111         u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
 112         u64 host_gs_base;
 113
 114         u32 *msrpm;
 115
 116         struct nested_state nested;
 117
 118         bool nmi_singlestep;
 119
 120         unsigned int3_injected;
 121         unsigned long int3_rip;
 122 };
 123
 124 #define MSR_INVALID                     0xffffffffU
 125
 126 static struct svm_direct_access_msrs {
 127         u32 index;   /* Index of the MSR */
 128         bool always; /* True if intercept is always on */
 129 } direct_access_msrs[] = {
 130         { .index = MSR_K6_STAR,                         .always = true  },
 131         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
 132 #ifdef CONFIG_X86_64
 133         { .index = MSR_GS_BASE,                         .always = true  },
 134         { .index = MSR_FS_BASE,                         .always = true  },
 135         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 136         { .index = MSR_LSTAR,                           .always = true  },
 137         { .index = MSR_CSTAR,                           .always = true  },
 138         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 139 #endif
 140         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 141         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 142         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 143         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 144         { .index = MSR_INVALID,                         .always = false },
 145 };
 146
 147 /* enable NPT for AMD64 and X86 with PAE */
 148 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 149 static bool npt_enabled = true;
 150 #else
 151 static bool npt_enabled;
 152 #endif
 153 static int npt = 1;
 154
 155 module_param(npt, int, S_IRUGO);
 156
 157 static int nested = 1;
 158 module_param(nested, int, S_IRUGO);
 159
 160 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
 161 static void svm_complete_interrupts(struct vcpu_svm *svm);
 162
 163 static int nested_svm_exit_handled(struct vcpu_svm *svm);
 164 static int nested_svm_intercept(struct vcpu_svm *svm);
 165 static int nested_svm_vmexit(struct vcpu_svm *svm);
 166 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
 167                                       bool has_error_code, u32 error_code);
 168
 169 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
 170 {
 171         return container_of(vcpu, struct vcpu_svm, vcpu);
 172 }
 173
 174 static inline bool is_nested(struct vcpu_svm *svm)
 175 {
 176         return svm->nested.vmcb;
 177 }
 178
 179 static inline void enable_gif(struct vcpu_svm *svm)
 180 {
 181         svm->vcpu.arch.hflags |= HF_GIF_MASK;
 182 }
 183
 184 static inline void disable_gif(struct vcpu_svm *svm)
 185 {
 186         svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
 187 }
 188
 189 static inline bool gif_set(struct vcpu_svm *svm)
 190 {
 191         return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
 192 }
 193
 194 static unsigned long iopm_base;
 195
 196 struct kvm_ldttss_desc {
 197         u16 limit0;
 198         u16 base0;
 199         unsigned base1:8, type:5, dpl:2, p:1;
 200         unsigned limit1:4, zero0:3, g:1, base2:8;
 201         u32 base3;
 202         u32 zero1;
 203 } __attribute__((packed));
 204
 205 struct svm_cpu_data {
 206         int cpu;
 207
 208         u64 asid_generation;
 209         u32 max_asid;
 210         u32 next_asid;
 211         struct kvm_ldttss_desc *tss_desc;
 212
 213         struct page *save_area;
 214 };
 215
 216 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 217 static uint32_t svm_features;
 218
 219 struct svm_init_data {
 220         int cpu;
 221         int r;
 222 };
 223
 224 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 225
 226 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 227 #define MSRS_RANGE_SIZE 2048
 228 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 229
 230 static u32 svm_msrpm_offset(u32 msr)
 231 {
 232         u32 offset;
 233         int i;
 234
 235         for (i = 0; i < NUM_MSR_MAPS; i++) {
 236                 if (msr < msrpm_ranges[i] ||
 237                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 238                         continue;
 239
 240                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 241                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 242
 243                 /* Now we have the u8 offset - but need the u32 offset */
 244                 return offset / 4;
 245         }
 246
 247         /* MSR not in any range */
 248         return MSR_INVALID;
 249 }
 250
 251 #define MAX_INST_SIZE 15
 252
 253 static inline u32 svm_has(u32 feat)
 254 {
 255         return svm_features & feat;
 256 }
 257
 258 static inline void clgi(void)
 259 {
 260         asm volatile (__ex(SVM_CLGI));
 261 }
 262
 263 static inline void stgi(void)
 264 {
 265         asm volatile (__ex(SVM_STGI));
 266 }
 267
 268 static inline void invlpga(unsigned long addr, u32 asid)
 269 {
 270         asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
 271 }
 272
 273 static inline void force_new_asid(struct kvm_vcpu *vcpu)
 274 {
 275         to_svm(vcpu)->asid_generation--;
 276 }
 277
 278 static inline void flush_guest_tlb(struct kvm_vcpu *vcpu)
 279 {
 280         force_new_asid(vcpu);
 281 }
 282
 283 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 284 {
 285         if (!npt_enabled && !(efer & EFER_LMA))
 286                 efer &= ~EFER_LME;
 287
 288         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 289         vcpu->arch.efer = efer;
 290 }
 291
 292 static int is_external_interrupt(u32 info)
 293 {
 294         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 295         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 296 }
 297
 298 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 299 {
 300         struct vcpu_svm *svm = to_svm(vcpu);
 301         u32 ret = 0;
 302
 303         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 304                 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 305         return ret & mask;
 306 }
 307
 308 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 309 {
 310         struct vcpu_svm *svm = to_svm(vcpu);
 311
 312         if (mask == 0)
 313                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 314         else
 315                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 316
 317 }
 318
 319 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
 320 {
 321         struct vcpu_svm *svm = to_svm(vcpu);
 322
 323         if (svm->vmcb->control.next_rip != 0)
 324                 svm->next_rip = svm->vmcb->control.next_rip;
 325
 326         if (!svm->next_rip) {
 327                 if (emulate_instruction(vcpu, 0, 0, EMULTYPE_SKIP) !=
 328                                 EMULATE_DONE)
 329                         printk(KERN_DEBUG "%s: NOP\n", __func__);
 330                 return;
 331         }
 332         if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
 333                 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
 334                        __func__, kvm_rip_read(vcpu), svm->next_rip);
 335
 336         kvm_rip_write(vcpu, svm->next_rip);
 337         svm_set_interrupt_shadow(vcpu, 0);
 338 }
 339
 340 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
 341                                 bool has_error_code, u32 error_code,
 342                                 bool reinject)
 343 {
 344         struct vcpu_svm *svm = to_svm(vcpu);
 345
 346         /*
 347          * If we are within a nested VM we'd better #VMEXIT and let the guest
 348          * handle the exception
 349          */
 350         if (!reinject &&
 351             nested_svm_check_exception(svm, nr, has_error_code, error_code))
 352                 return;
 353
 354         if (nr == BP_VECTOR && !svm_has(SVM_FEATURE_NRIP)) {
 355                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 356
 357                 /*
 358                  * For guest debugging where we have to reinject #BP if some
 359                  * INT3 is guest-owned:
 360                  * Emulate nRIP by moving RIP forward. Will fail if injection
 361                  * raises a fault that is not intercepted. Still better than
 362                  * failing in all cases.
 363                  */
 364                 skip_emulated_instruction(&svm->vcpu);
 365                 rip = kvm_rip_read(&svm->vcpu);
 366                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 367                 svm->int3_injected = rip - old_rip;
 368         }
 369
 370         svm->vmcb->control.event_inj = nr
 371                 | SVM_EVTINJ_VALID
 372                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 373                 | SVM_EVTINJ_TYPE_EXEPT;
 374         svm->vmcb->control.event_inj_err = error_code;
 375 }
 376
 377 static int has_svm(void)
 378 {
 379         const char *msg;
 380
 381         if (!cpu_has_svm(&msg)) {
 382                 printk(KERN_INFO "has_svm: %s\n", msg);
 383                 return 0;
 384         }
 385
 386         return 1;
 387 }
 388
 389 static void svm_hardware_disable(void *garbage)
 390 {
 391         cpu_svm_disable();
 392 }
 393
 394 static int svm_hardware_enable(void *garbage)
 395 {
 396
 397         struct svm_cpu_data *sd;
 398         uint64_t efer;
 399         struct desc_ptr gdt_descr;
 400         struct desc_struct *gdt;
 401         int me = raw_smp_processor_id();
 402
 403         rdmsrl(MSR_EFER, efer);
 404         if (efer & EFER_SVME)
 405                 return -EBUSY;
 406
 407         if (!has_svm()) {
 408                 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
 409                        me);
 410                 return -EINVAL;
 411         }
 412         sd = per_cpu(svm_data, me);
 413
 414         if (!sd) {
 415                 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
 416                        me);
 417                 return -EINVAL;
 418         }
 419
 420         sd->asid_generation = 1;
 421         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 422         sd->next_asid = sd->max_asid + 1;
 423
 424         native_store_gdt(&gdt_descr);
 425         gdt = (struct desc_struct *)gdt_descr.address;
 426         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 427
 428         wrmsrl(MSR_EFER, efer | EFER_SVME);
 429
 430         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 431
 432         return 0;
 433 }
 434
 435 static void svm_cpu_uninit(int cpu)
 436 {
 437         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 438
 439         if (!sd)
 440                 return;
 441
 442         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 443         __free_page(sd->save_area);
 444         kfree(sd);
 445 }
 446
 447 static int svm_cpu_init(int cpu)
 448 {
 449         struct svm_cpu_data *sd;
 450         int r;
 451
 452         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 453         if (!sd)
 454                 return -ENOMEM;
 455         sd->cpu = cpu;
 456         sd->save_area = alloc_page(GFP_KERNEL);
 457         r = -ENOMEM;
 458         if (!sd->save_area)
 459                 goto err_1;
 460
 461         per_cpu(svm_data, cpu) = sd;
 462
 463         return 0;
 464
 465 err_1:
 466         kfree(sd);
 467         return r;
 468
 469 }
 470
 471 static bool valid_msr_intercept(u32 index)
 472 {
 473         int i;
 474
 475         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 476                 if (direct_access_msrs[i].index == index)
 477                         return true;
 478
 479         return false;
 480 }
 481
 482 static void set_msr_interception(u32 *msrpm, unsigned msr,
 483                                  int read, int write)
 484 {
 485         u8 bit_read, bit_write;
 486         unsigned long tmp;
 487         u32 offset;
 488
 489         /*
 490          * If this warning triggers extend the direct_access_msrs list at the
 491          * beginning of the file
 492          */
 493         WARN_ON(!valid_msr_intercept(msr));
 494
 495         offset    = svm_msrpm_offset(msr);
 496         bit_read  = 2 * (msr & 0x0f);
 497         bit_write = 2 * (msr & 0x0f) + 1;
 498         tmp       = msrpm[offset];
 499
 500         BUG_ON(offset == MSR_INVALID);
 501
 502         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 503         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 504
 505         msrpm[offset] = tmp;
 506 }
 507
 508 static void svm_vcpu_init_msrpm(u32 *msrpm)
 509 {
 510         int i;
 511
 512         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 513
 514         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 515                 if (!direct_access_msrs[i].always)
 516                         continue;
 517
 518                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 519         }
 520 }
 521
 522 static void add_msr_offset(u32 offset)
 523 {
 524         int i;
 525
 526         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 527
 528                 /* Offset already in list? */
 529                 if (msrpm_offsets[i] == offset)
 530                         return;
 531
 532                 /* Slot used by another offset? */
 533                 if (msrpm_offsets[i] != MSR_INVALID)
 534                         continue;
 535
 536                 /* Add offset to list */
 537                 msrpm_offsets[i] = offset;
 538
 539                 return;
 540         }
 541
 542         /*
 543          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 544          * increase MSRPM_OFFSETS in this case.
 545          */
 546         BUG();
 547 }
 548
 549 static void init_msrpm_offsets(void)
 550 {
 551         int i;
 552
 553         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 554
 555         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 556                 u32 offset;
 557
 558                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 559                 BUG_ON(offset == MSR_INVALID);
 560
 561                 add_msr_offset(offset);
 562         }
 563 }
 564
 565 static void svm_enable_lbrv(struct vcpu_svm *svm)
 566 {
 567         u32 *msrpm = svm->msrpm;
 568
 569         svm->vmcb->control.lbr_ctl = 1;
 570         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 571         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 572         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 573         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 574 }
 575
 576 static void svm_disable_lbrv(struct vcpu_svm *svm)
 577 {
 578         u32 *msrpm = svm->msrpm;
 579
 580         svm->vmcb->control.lbr_ctl = 0;
 581         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 582         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 583         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 584         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 585 }
 586
 587 static __init int svm_hardware_setup(void)
 588 {
 589         int cpu;
 590         struct page *iopm_pages;
 591         void *iopm_va;
 592         int r;
 593
 594         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 595
 596         if (!iopm_pages)
 597                 return -ENOMEM;
 598
 599         iopm_va = page_address(iopm_pages);
 600         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 601         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 602
 603         init_msrpm_offsets();
 604
 605         if (boot_cpu_has(X86_FEATURE_NX))
 606                 kvm_enable_efer_bits(EFER_NX);
 607
 608         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 609                 kvm_enable_efer_bits(EFER_FFXSR);
 610
 611         if (nested) {
 612                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 613                 kvm_enable_efer_bits(EFER_SVME);
 614         }
 615
 616         for_each_possible_cpu(cpu) {
 617                 r = svm_cpu_init(cpu);
 618                 if (r)
 619                         goto err;
 620         }
 621
 622         svm_features = cpuid_edx(SVM_CPUID_FUNC);
 623
 624         if (!svm_has(SVM_FEATURE_NPT))
 625                 npt_enabled = false;
 626
 627         if (npt_enabled && !npt) {
 628                 printk(KERN_INFO "kvm: Nested Paging disabled\n");
 629                 npt_enabled = false;
 630         }
 631
 632         if (npt_enabled) {
 633                 printk(KERN_INFO "kvm: Nested Paging enabled\n");
 634                 kvm_enable_tdp();
 635         } else
 636                 kvm_disable_tdp();
 637
 638         return 0;
 639
 640 err:
 641         __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
 642         iopm_base = 0;
 643         return r;
 644 }
 645
 646 static __exit void svm_hardware_unsetup(void)
 647 {
 648         int cpu;
 649
 650         for_each_possible_cpu(cpu)
 651                 svm_cpu_uninit(cpu);
 652
 653         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 654         iopm_base = 0;
 655 }
 656
 657 static void init_seg(struct vmcb_seg *seg)
 658 {
 659         seg->selector = 0;
 660         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 661                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 662         seg->limit = 0xffff;
 663         seg->base = 0;
 664 }
 665
 666 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 667 {
 668         seg->selector = 0;
 669         seg->attrib = SVM_SELECTOR_P_MASK | type;
 670         seg->limit = 0xffff;
 671         seg->base = 0;
 672 }
 673
 674 static void init_vmcb(struct vcpu_svm *svm)
 675 {
 676         struct vmcb_control_area *control = &svm->vmcb->control;
 677         struct vmcb_save_area *save = &svm->vmcb->save;
 678
 679         svm->vcpu.fpu_active = 1;
 680
 681         control->intercept_cr_read =    INTERCEPT_CR0_MASK |
 682                                         INTERCEPT_CR3_MASK |
 683                                         INTERCEPT_CR4_MASK;
 684
 685         control->intercept_cr_write =   INTERCEPT_CR0_MASK |
 686                                         INTERCEPT_CR3_MASK |
 687                                         INTERCEPT_CR4_MASK |
 688                                         INTERCEPT_CR8_MASK;
 689
 690         control->intercept_dr_read =    INTERCEPT_DR0_MASK |
 691                                         INTERCEPT_DR1_MASK |
 692                                         INTERCEPT_DR2_MASK |
 693                                         INTERCEPT_DR3_MASK |
 694                                         INTERCEPT_DR4_MASK |
 695                                         INTERCEPT_DR5_MASK |
 696                                         INTERCEPT_DR6_MASK |
 697                                         INTERCEPT_DR7_MASK;
 698
 699         control->intercept_dr_write =   INTERCEPT_DR0_MASK |
 700                                         INTERCEPT_DR1_MASK |
 701                                         INTERCEPT_DR2_MASK |
 702                                         INTERCEPT_DR3_MASK |
 703                                         INTERCEPT_DR4_MASK |
 704                                         INTERCEPT_DR5_MASK |
 705                                         INTERCEPT_DR6_MASK |
 706                                         INTERCEPT_DR7_MASK;
 707
 708         control->intercept_exceptions = (1 << PF_VECTOR) |
 709                                         (1 << UD_VECTOR) |
 710                                         (1 << MC_VECTOR);
 711
 712
 713         control->intercept =    (1ULL << INTERCEPT_INTR) |
 714                                 (1ULL << INTERCEPT_NMI) |
 715                                 (1ULL << INTERCEPT_SMI) |
 716                                 (1ULL << INTERCEPT_SELECTIVE_CR0) |
 717                                 (1ULL << INTERCEPT_CPUID) |
 718                                 (1ULL << INTERCEPT_INVD) |
 719                                 (1ULL << INTERCEPT_HLT) |
 720                                 (1ULL << INTERCEPT_INVLPG) |
 721                                 (1ULL << INTERCEPT_INVLPGA) |
 722                                 (1ULL << INTERCEPT_IOIO_PROT) |
 723                                 (1ULL << INTERCEPT_MSR_PROT) |
 724                                 (1ULL << INTERCEPT_TASK_SWITCH) |
 725                                 (1ULL << INTERCEPT_SHUTDOWN) |
 726                                 (1ULL << INTERCEPT_VMRUN) |
 727                                 (1ULL << INTERCEPT_VMMCALL) |
 728                                 (1ULL << INTERCEPT_VMLOAD) |
 729                                 (1ULL << INTERCEPT_VMSAVE) |
 730                                 (1ULL << INTERCEPT_STGI) |
 731                                 (1ULL << INTERCEPT_CLGI) |
 732                                 (1ULL << INTERCEPT_SKINIT) |
 733                                 (1ULL << INTERCEPT_WBINVD) |
 734                                 (1ULL << INTERCEPT_MONITOR) |
 735                                 (1ULL << INTERCEPT_MWAIT);
 736
 737         control->iopm_base_pa = iopm_base;
 738         control->msrpm_base_pa = __pa(svm->msrpm);
 739         control->tsc_offset = 0;
 740         control->int_ctl = V_INTR_MASKING_MASK;
 741
 742         init_seg(&save->es);
 743         init_seg(&save->ss);
 744         init_seg(&save->ds);
 745         init_seg(&save->fs);
 746         init_seg(&save->gs);
 747
 748         save->cs.selector = 0xf000;
 749         /* Executable/Readable Code Segment */
 750         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
 751                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
 752         save->cs.limit = 0xffff;
 753         /*
 754          * cs.base should really be 0xffff0000, but vmx can't handle that, so
 755          * be consistent with it.
 756          *
 757          * Replace when we have real mode working for vmx.
 758          */
 759         save->cs.base = 0xf0000;
 760
 761         save->gdtr.limit = 0xffff;
 762         save->idtr.limit = 0xffff;
 763
 764         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
 765         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
 766
 767         save->efer = EFER_SVME;
 768         save->dr6 = 0xffff0ff0;
 769         save->dr7 = 0x400;
 770         save->rflags = 2;
 771         save->rip = 0x0000fff0;
 772         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
 773
 774         /*
 775          * This is the guest-visible cr0 value.
 776          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
 777          */
 778         svm->vcpu.arch.cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
 779         kvm_set_cr0(&svm->vcpu, svm->vcpu.arch.cr0);
 780
 781         save->cr4 = X86_CR4_PAE;
 782         /* rdx = ?? */
 783
 784         if (npt_enabled) {
 785                 /* Setup VMCB for Nested Paging */
 786                 control->nested_ctl = 1;
 787                 control->intercept &= ~((1ULL << INTERCEPT_TASK_SWITCH) |
 788                                         (1ULL << INTERCEPT_INVLPG));
 789                 control->intercept_exceptions &= ~(1 << PF_VECTOR);
 790                 control->intercept_cr_read &= ~INTERCEPT_CR3_MASK;
 791                 control->intercept_cr_write &= ~INTERCEPT_CR3_MASK;
 792                 save->g_pat = 0x0007040600070406ULL;
 793                 save->cr3 = 0;
 794                 save->cr4 = 0;
 795         }
 796         force_new_asid(&svm->vcpu);
 797
 798         svm->nested.vmcb = 0;
 799         svm->vcpu.arch.hflags = 0;
 800
 801         if (svm_has(SVM_FEATURE_PAUSE_FILTER)) {
 802                 control->pause_filter_count = 3000;
 803                 control->intercept |= (1ULL << INTERCEPT_PAUSE);
 804         }
 805
 806         enable_gif(svm);
 807 }
 808
 809 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
 810 {
 811         struct vcpu_svm *svm = to_svm(vcpu);
 812
 813         init_vmcb(svm);
 814
 815         if (!kvm_vcpu_is_bsp(vcpu)) {
 816                 kvm_rip_write(vcpu, 0);
 817                 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
 818                 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
 819         }
 820         vcpu->arch.regs_avail = ~0;
 821         vcpu->arch.regs_dirty = ~0;
 822
 823         return 0;
 824 }
 825
 826 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
 827 {
 828         struct vcpu_svm *svm;
 829         struct page *page;
 830         struct page *msrpm_pages;
 831         struct page *hsave_page;
 832         struct page *nested_msrpm_pages;
 833         int err;
 834
 835         svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
 836         if (!svm) {
 837                 err = -ENOMEM;
 838                 goto out;
 839         }
 840
 841         err = kvm_vcpu_init(&svm->vcpu, kvm, id);
 842         if (err)
 843                 goto free_svm;
 844
 845         err = -ENOMEM;
 846         page = alloc_page(GFP_KERNEL);
 847         if (!page)
 848                 goto uninit;
 849
 850         msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 851         if (!msrpm_pages)
 852                 goto free_page1;
 853
 854         nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
 855         if (!nested_msrpm_pages)
 856                 goto free_page2;
 857
 858         hsave_page = alloc_page(GFP_KERNEL);
 859         if (!hsave_page)
 860                 goto free_page3;
 861
 862         svm->nested.hsave = page_address(hsave_page);
 863
 864         svm->msrpm = page_address(msrpm_pages);
 865         svm_vcpu_init_msrpm(svm->msrpm);
 866
 867         svm->nested.msrpm = page_address(nested_msrpm_pages);
 868         svm_vcpu_init_msrpm(svm->nested.msrpm);
 869
 870         svm->vmcb = page_address(page);
 871         clear_page(svm->vmcb);
 872         svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
 873         svm->asid_generation = 0;
 874         init_vmcb(svm);
 875
 876         fx_init(&svm->vcpu);
 877         svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
 878         if (kvm_vcpu_is_bsp(&svm->vcpu))
 879                 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
 880
 881         return &svm->vcpu;
 882
 883 free_page3:
 884         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
 885 free_page2:
 886         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
 887 free_page1:
 888         __free_page(page);
 889 uninit:
 890         kvm_vcpu_uninit(&svm->vcpu);
 891 free_svm:
 892         kmem_cache_free(kvm_vcpu_cache, svm);
 893 out:
 894         return ERR_PTR(err);
 895 }
 896
 897 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
 898 {
 899         struct vcpu_svm *svm = to_svm(vcpu);
 900
 901         __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
 902         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
 903         __free_page(virt_to_page(svm->nested.hsave));
 904         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
 905         kvm_vcpu_uninit(vcpu);
 906         kmem_cache_free(kvm_vcpu_cache, svm);
 907 }
 908
 909 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
 910 {
 911         struct vcpu_svm *svm = to_svm(vcpu);
 912         int i;
 913
 914         if (unlikely(cpu != vcpu->cpu)) {
 915                 u64 delta;
 916
 917                 if (check_tsc_unstable()) {
 918                         /*
 919                          * Make sure that the guest sees a monotonically
 920                          * increasing TSC.
 921                          */
 922                         delta = vcpu->arch.host_tsc - native_read_tsc();
 923                         svm->vmcb->control.tsc_offset += delta;
 924                         if (is_nested(svm))
 925                                 svm->nested.hsave->control.tsc_offset += delta;
 926                 }
 927                 vcpu->cpu = cpu;
 928                 kvm_migrate_timers(vcpu);
 929                 svm->asid_generation = 0;
 930         }
 931
 932         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 933                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 934 }
 935
 936 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
 937 {
 938         struct vcpu_svm *svm = to_svm(vcpu);
 939         int i;
 940
 941         ++vcpu->stat.host_state_reload;
 942         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
 943                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
 944
 945         vcpu->arch.host_tsc = native_read_tsc();
 946 }
 947
 948 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
 949 {
 950         return to_svm(vcpu)->vmcb->save.rflags;
 951 }
 952
 953 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
 954 {
 955         to_svm(vcpu)->vmcb->save.rflags = rflags;
 956 }
 957
 958 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
 959 {
 960         switch (reg) {
 961         case VCPU_EXREG_PDPTR:
 962                 BUG_ON(!npt_enabled);
 963                 load_pdptrs(vcpu, vcpu->arch.cr3);
 964                 break;
 965         default:
 966                 BUG();
 967         }
 968 }
 969
 970 static void svm_set_vintr(struct vcpu_svm *svm)
 971 {
 972         svm->vmcb->control.intercept |= 1ULL << INTERCEPT_VINTR;
 973 }
 974
 975 static void svm_clear_vintr(struct vcpu_svm *svm)
 976 {
 977         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VINTR);
 978 }
 979
 980 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
 981 {
 982         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
 983
 984         switch (seg) {
 985         case VCPU_SREG_CS: return &save->cs;
 986         case VCPU_SREG_DS: return &save->ds;
 987         case VCPU_SREG_ES: return &save->es;
 988         case VCPU_SREG_FS: return &save->fs;
 989         case VCPU_SREG_GS: return &save->gs;
 990         case VCPU_SREG_SS: return &save->ss;
 991         case VCPU_SREG_TR: return &save->tr;
 992         case VCPU_SREG_LDTR: return &save->ldtr;
 993         }
 994         BUG();
 995         return NULL;
 996 }
 997
 998 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
 999 {
1000         struct vmcb_seg *s = svm_seg(vcpu, seg);
1001
1002         return s->base;
1003 }
1004
1005 static void svm_get_segment(struct kvm_vcpu *vcpu,
1006                             struct kvm_segment *var, int seg)
1007 {
1008         struct vmcb_seg *s = svm_seg(vcpu, seg);
1009
1010         var->base = s->base;
1011         var->limit = s->limit;
1012         var->selector = s->selector;
1013         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1014         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1015         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1016         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1017         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1018         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1019         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1020         var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1021
1022         /*
1023          * AMD's VMCB does not have an explicit unusable field, so emulate it
1024          * for cross vendor migration purposes by "not present"
1025          */
1026         var->unusable = !var->present || (var->type == 0);
1027
1028         switch (seg) {
1029         case VCPU_SREG_CS:
1030                 /*
1031                  * SVM always stores 0 for the 'G' bit in the CS selector in
1032                  * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1033                  * Intel's VMENTRY has a check on the 'G' bit.
1034                  */
1035                 var->g = s->limit > 0xfffff;
1036                 break;
1037         case VCPU_SREG_TR:
1038                 /*
1039                  * Work around a bug where the busy flag in the tr selector
1040                  * isn't exposed
1041                  */
1042                 var->type |= 0x2;
1043                 break;
1044         case VCPU_SREG_DS:
1045         case VCPU_SREG_ES:
1046         case VCPU_SREG_FS:
1047         case VCPU_SREG_GS:
1048                 /*
1049                  * The accessed bit must always be set in the segment
1050                  * descriptor cache, although it can be cleared in the
1051                  * descriptor, the cached bit always remains at 1. Since
1052                  * Intel has a check on this, set it here to support
1053                  * cross-vendor migration.
1054                  */
1055                 if (!var->unusable)
1056                         var->type |= 0x1;
1057                 break;
1058         case VCPU_SREG_SS:
1059                 /*
1060                  * On AMD CPUs sometimes the DB bit in the segment
1061                  * descriptor is left as 1, although the whole segment has
1062                  * been made unusable. Clear it here to pass an Intel VMX
1063                  * entry check when cross vendor migrating.
1064                  */
1065                 if (var->unusable)
1066                         var->db = 0;
1067                 break;
1068         }
1069 }
1070
1071 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1072 {
1073         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1074
1075         return save->cpl;
1076 }
1077
1078 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1079 {
1080         struct vcpu_svm *svm = to_svm(vcpu);
1081
1082         dt->size = svm->vmcb->save.idtr.limit;
1083         dt->address = svm->vmcb->save.idtr.base;
1084 }
1085
1086 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1087 {
1088         struct vcpu_svm *svm = to_svm(vcpu);
1089
1090         svm->vmcb->save.idtr.limit = dt->size;
1091         svm->vmcb->save.idtr.base = dt->address ;
1092 }
1093
1094 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1095 {
1096         struct vcpu_svm *svm = to_svm(vcpu);
1097
1098         dt->size = svm->vmcb->save.gdtr.limit;
1099         dt->address = svm->vmcb->save.gdtr.base;
1100 }
1101
1102 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1103 {
1104         struct vcpu_svm *svm = to_svm(vcpu);
1105
1106         svm->vmcb->save.gdtr.limit = dt->size;
1107         svm->vmcb->save.gdtr.base = dt->address ;
1108 }
1109
1110 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1111 {
1112 }
1113
1114 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1115 {
1116 }
1117
1118 static void update_cr0_intercept(struct vcpu_svm *svm)
1119 {
1120         struct vmcb *vmcb = svm->vmcb;
1121         ulong gcr0 = svm->vcpu.arch.cr0;
1122         u64 *hcr0 = &svm->vmcb->save.cr0;
1123
1124         if (!svm->vcpu.fpu_active)
1125                 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1126         else
1127                 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1128                         | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1129
1130
1131         if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1132                 vmcb->control.intercept_cr_read &= ~INTERCEPT_CR0_MASK;
1133                 vmcb->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1134                 if (is_nested(svm)) {
1135                         struct vmcb *hsave = svm->nested.hsave;
1136
1137                         hsave->control.intercept_cr_read  &= ~INTERCEPT_CR0_MASK;
1138                         hsave->control.intercept_cr_write &= ~INTERCEPT_CR0_MASK;
1139                         vmcb->control.intercept_cr_read  |= svm->nested.intercept_cr_read;
1140                         vmcb->control.intercept_cr_write |= svm->nested.intercept_cr_write;
1141                 }
1142         } else {
1143                 svm->vmcb->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1144                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1145                 if (is_nested(svm)) {
1146                         struct vmcb *hsave = svm->nested.hsave;
1147
1148                         hsave->control.intercept_cr_read |= INTERCEPT_CR0_MASK;
1149                         hsave->control.intercept_cr_write |= INTERCEPT_CR0_MASK;
1150                 }
1151         }
1152 }
1153
1154 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1155 {
1156         struct vcpu_svm *svm = to_svm(vcpu);
1157
1158         if (is_nested(svm)) {
1159                 /*
1160                  * We are here because we run in nested mode, the host kvm
1161                  * intercepts cr0 writes but the l1 hypervisor does not.
1162                  * But the L1 hypervisor may intercept selective cr0 writes.
1163                  * This needs to be checked here.
1164                  */
1165                 unsigned long old, new;
1166
1167                 /* Remove bits that would trigger a real cr0 write intercept */
1168                 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1169                 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1170
1171                 if (old == new) {
1172                         /* cr0 write with ts and mp unchanged */
1173                         svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1174                         if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE)
1175                                 return;
1176                 }
1177         }
1178
1179 #ifdef CONFIG_X86_64
1180         if (vcpu->arch.efer & EFER_LME) {
1181                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1182                         vcpu->arch.efer |= EFER_LMA;
1183                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1184                 }
1185
1186                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1187                         vcpu->arch.efer &= ~EFER_LMA;
1188                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1189                 }
1190         }
1191 #endif
1192         vcpu->arch.cr0 = cr0;
1193
1194         if (!npt_enabled)
1195                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1196
1197         if (!vcpu->fpu_active)
1198                 cr0 |= X86_CR0_TS;
1199         /*
1200          * re-enable caching here because the QEMU bios
1201          * does not do it - this results in some delay at
1202          * reboot
1203          */
1204         cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1205         svm->vmcb->save.cr0 = cr0;
1206         update_cr0_intercept(svm);
1207 }
1208
1209 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1210 {
1211         unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1212         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1213
1214         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1215                 force_new_asid(vcpu);
1216
1217         vcpu->arch.cr4 = cr4;
1218         if (!npt_enabled)
1219                 cr4 |= X86_CR4_PAE;
1220         cr4 |= host_cr4_mce;
1221         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1222 }
1223
1224 static void svm_set_segment(struct kvm_vcpu *vcpu,
1225                             struct kvm_segment *var, int seg)
1226 {
1227         struct vcpu_svm *svm = to_svm(vcpu);
1228         struct vmcb_seg *s = svm_seg(vcpu, seg);
1229
1230         s->base = var->base;
1231         s->limit = var->limit;
1232         s->selector = var->selector;
1233         if (var->unusable)
1234                 s->attrib = 0;
1235         else {
1236                 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1237                 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1238                 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1239                 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1240                 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1241                 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1242                 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1243                 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1244         }
1245         if (seg == VCPU_SREG_CS)
1246                 svm->vmcb->save.cpl
1247                         = (svm->vmcb->save.cs.attrib
1248                            >> SVM_SELECTOR_DPL_SHIFT) & 3;
1249
1250 }
1251
1252 static void update_db_intercept(struct kvm_vcpu *vcpu)
1253 {
1254         struct vcpu_svm *svm = to_svm(vcpu);
1255
1256         svm->vmcb->control.intercept_exceptions &=
1257                 ~((1 << DB_VECTOR) | (1 << BP_VECTOR));
1258
1259         if (svm->nmi_singlestep)
1260                 svm->vmcb->control.intercept_exceptions |= (1 << DB_VECTOR);
1261
1262         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1263                 if (vcpu->guest_debug &
1264                     (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1265                         svm->vmcb->control.intercept_exceptions |=
1266                                 1 << DB_VECTOR;
1267                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1268                         svm->vmcb->control.intercept_exceptions |=
1269                                 1 << BP_VECTOR;
1270         } else
1271                 vcpu->guest_debug = 0;
1272 }
1273
1274 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1275 {
1276         struct vcpu_svm *svm = to_svm(vcpu);
1277
1278         if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1279                 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1280         else
1281                 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1282
1283         update_db_intercept(vcpu);
1284 }
1285
1286 static void load_host_msrs(struct kvm_vcpu *vcpu)
1287 {
1288 #ifdef CONFIG_X86_64
1289         wrmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1290 #endif
1291 }
1292
1293 static void save_host_msrs(struct kvm_vcpu *vcpu)
1294 {
1295 #ifdef CONFIG_X86_64
1296         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base);
1297 #endif
1298 }
1299
1300 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1301 {
1302         if (sd->next_asid > sd->max_asid) {
1303                 ++sd->asid_generation;
1304                 sd->next_asid = 1;
1305                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1306         }
1307
1308         svm->asid_generation = sd->asid_generation;
1309         svm->vmcb->control.asid = sd->next_asid++;
1310 }
1311
1312 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1313 {
1314         struct vcpu_svm *svm = to_svm(vcpu);
1315
1316         svm->vmcb->save.dr7 = value;
1317 }
1318
1319 static int pf_interception(struct vcpu_svm *svm)
1320 {
1321         u64 fault_address;
1322         u32 error_code;
1323
1324         fault_address  = svm->vmcb->control.exit_info_2;
1325         error_code = svm->vmcb->control.exit_info_1;
1326
1327         trace_kvm_page_fault(fault_address, error_code);
1328         if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1329                 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1330         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code);
1331 }
1332
1333 static int db_interception(struct vcpu_svm *svm)
1334 {
1335         struct kvm_run *kvm_run = svm->vcpu.run;
1336
1337         if (!(svm->vcpu.guest_debug &
1338               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1339                 !svm->nmi_singlestep) {
1340                 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1341                 return 1;
1342         }
1343
1344         if (svm->nmi_singlestep) {
1345                 svm->nmi_singlestep = false;
1346                 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1347                         svm->vmcb->save.rflags &=
1348                                 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1349                 update_db_intercept(&svm->vcpu);
1350         }
1351
1352         if (svm->vcpu.guest_debug &
1353             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1354                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1355                 kvm_run->debug.arch.pc =
1356                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1357                 kvm_run->debug.arch.exception = DB_VECTOR;
1358                 return 0;
1359         }
1360
1361         return 1;
1362 }
1363
1364 static int bp_interception(struct vcpu_svm *svm)
1365 {
1366         struct kvm_run *kvm_run = svm->vcpu.run;
1367
1368         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1369         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1370         kvm_run->debug.arch.exception = BP_VECTOR;
1371         return 0;
1372 }
1373
1374 static int ud_interception(struct vcpu_svm *svm)
1375 {
1376         int er;
1377
1378         er = emulate_instruction(&svm->vcpu, 0, 0, EMULTYPE_TRAP_UD);
1379         if (er != EMULATE_DONE)
1380                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1381         return 1;
1382 }
1383
1384 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1385 {
1386         struct vcpu_svm *svm = to_svm(vcpu);
1387         u32 excp;
1388
1389         if (is_nested(svm)) {
1390                 u32 h_excp, n_excp;
1391
1392                 h_excp  = svm->nested.hsave->control.intercept_exceptions;
1393                 n_excp  = svm->nested.intercept_exceptions;
1394                 h_excp &= ~(1 << NM_VECTOR);
1395                 excp    = h_excp | n_excp;
1396         } else {
1397                 excp  = svm->vmcb->control.intercept_exceptions;
1398                 excp &= ~(1 << NM_VECTOR);
1399         }
1400
1401         svm->vmcb->control.intercept_exceptions = excp;
1402
1403         svm->vcpu.fpu_active = 1;
1404         update_cr0_intercept(svm);
1405 }
1406
1407 static int nm_interception(struct vcpu_svm *svm)
1408 {
1409         svm_fpu_activate(&svm->vcpu);
1410         return 1;
1411 }
1412
1413 static int mc_interception(struct vcpu_svm *svm)
1414 {
1415         /*
1416          * On an #MC intercept the MCE handler is not called automatically in
1417          * the host. So do it by hand here.
1418          */
1419         asm volatile (
1420                 "int $0x12\n");
1421         /* not sure if we ever come back to this point */
1422
1423         return 1;
1424 }
1425
1426 static int shutdown_interception(struct vcpu_svm *svm)
1427 {
1428         struct kvm_run *kvm_run = svm->vcpu.run;
1429
1430         /*
1431          * VMCB is undefined after a SHUTDOWN intercept
1432          * so reinitialize it.
1433          */
1434         clear_page(svm->vmcb);
1435         init_vmcb(svm);
1436
1437         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1438         return 0;
1439 }
1440
1441 static int io_interception(struct vcpu_svm *svm)
1442 {
1443         struct kvm_vcpu *vcpu = &svm->vcpu;
1444         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1445         int size, in, string;
1446         unsigned port;
1447
1448         ++svm->vcpu.stat.io_exits;
1449         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1450         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1451         if (string || in)
1452                 return !(emulate_instruction(vcpu, 0, 0, 0) == EMULATE_DO_MMIO);
1453
1454         port = io_info >> 16;
1455         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1456         svm->next_rip = svm->vmcb->control.exit_info_2;
1457         skip_emulated_instruction(&svm->vcpu);
1458
1459         return kvm_fast_pio_out(vcpu, size, port);
1460 }
1461
1462 static int nmi_interception(struct vcpu_svm *svm)
1463 {
1464         return 1;
1465 }
1466
1467 static int intr_interception(struct vcpu_svm *svm)
1468 {
1469         ++svm->vcpu.stat.irq_exits;
1470         return 1;
1471 }
1472
1473 static int nop_on_interception(struct vcpu_svm *svm)
1474 {
1475         return 1;
1476 }
1477
1478 static int halt_interception(struct vcpu_svm *svm)
1479 {
1480         svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1481         skip_emulated_instruction(&svm->vcpu);
1482         return kvm_emulate_halt(&svm->vcpu);
1483 }
1484
1485 static int vmmcall_interception(struct vcpu_svm *svm)
1486 {
1487         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1488         skip_emulated_instruction(&svm->vcpu);
1489         kvm_emulate_hypercall(&svm->vcpu);
1490         return 1;
1491 }
1492
1493 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1494 {
1495         if (!(svm->vcpu.arch.efer & EFER_SVME)
1496             || !is_paging(&svm->vcpu)) {
1497                 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1498                 return 1;
1499         }
1500
1501         if (svm->vmcb->save.cpl) {
1502                 kvm_inject_gp(&svm->vcpu, 0);
1503                 return 1;
1504         }
1505
1506        return 0;
1507 }
1508
1509 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1510                                       bool has_error_code, u32 error_code)
1511 {
1512         int vmexit;
1513
1514         if (!is_nested(svm))
1515                 return 0;
1516
1517         svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1518         svm->vmcb->control.exit_code_hi = 0;
1519         svm->vmcb->control.exit_info_1 = error_code;
1520         svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1521
1522         vmexit = nested_svm_intercept(svm);
1523         if (vmexit == NESTED_EXIT_DONE)
1524                 svm->nested.exit_required = true;
1525
1526         return vmexit;
1527 }
1528
1529 /* This function returns true if it is save to enable the irq window */
1530 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1531 {
1532         if (!is_nested(svm))
1533                 return true;
1534
1535         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1536                 return true;
1537
1538         if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1539                 return false;
1540
1541         svm->vmcb->control.exit_code   = SVM_EXIT_INTR;
1542         svm->vmcb->control.exit_info_1 = 0;
1543         svm->vmcb->control.exit_info_2 = 0;
1544
1545         if (svm->nested.intercept & 1ULL) {
1546                 /*
1547                  * The #vmexit can't be emulated here directly because this
1548                  * code path runs with irqs and preemtion disabled. A
1549                  * #vmexit emulation might sleep. Only signal request for
1550                  * the #vmexit here.
1551                  */
1552                 svm->nested.exit_required = true;
1553                 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1554                 return false;
1555         }
1556
1557         return true;
1558 }
1559
1560 /* This function returns true if it is save to enable the nmi window */
1561 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1562 {
1563         if (!is_nested(svm))
1564                 return true;
1565
1566         if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1567                 return true;
1568
1569         svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1570         svm->nested.exit_required = true;
1571
1572         return false;
1573 }
1574
1575 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1576 {
1577         struct page *page;
1578
1579         might_sleep();
1580
1581         page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1582         if (is_error_page(page))
1583                 goto error;
1584
1585         *_page = page;
1586
1587         return kmap(page);
1588
1589 error:
1590         kvm_release_page_clean(page);
1591         kvm_inject_gp(&svm->vcpu, 0);
1592
1593         return NULL;
1594 }
1595
1596 static void nested_svm_unmap(struct page *page)
1597 {
1598         kunmap(page);
1599         kvm_release_page_dirty(page);
1600 }
1601
1602 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1603 {
1604         unsigned port;
1605         u8 val, bit;
1606         u64 gpa;
1607
1608         if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1609                 return NESTED_EXIT_HOST;
1610
1611         port = svm->vmcb->control.exit_info_1 >> 16;
1612         gpa  = svm->nested.vmcb_iopm + (port / 8);
1613         bit  = port % 8;
1614         val  = 0;
1615
1616         if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1617                 val &= (1 << bit);
1618
1619         return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1620 }
1621
1622 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1623 {
1624         u32 offset, msr, value;
1625         int write, mask;
1626
1627         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1628                 return NESTED_EXIT_HOST;
1629
1630         msr    = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1631         offset = svm_msrpm_offset(msr);
1632         write  = svm->vmcb->control.exit_info_1 & 1;
1633         mask   = 1 << ((2 * (msr & 0xf)) + write);
1634
1635         if (offset == MSR_INVALID)
1636                 return NESTED_EXIT_DONE;
1637
1638         /* Offset is in 32 bit units but need in 8 bit units */
1639         offset *= 4;
1640
1641         if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1642                 return NESTED_EXIT_DONE;
1643
1644         return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1645 }
1646
1647 static int nested_svm_exit_special(struct vcpu_svm *svm)
1648 {
1649         u32 exit_code = svm->vmcb->control.exit_code;
1650
1651         switch (exit_code) {
1652         case SVM_EXIT_INTR:
1653         case SVM_EXIT_NMI:
1654         case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1655                 return NESTED_EXIT_HOST;
1656         case SVM_EXIT_NPF:
1657                 /* For now we are always handling NPFs when using them */
1658                 if (npt_enabled)
1659                         return NESTED_EXIT_HOST;
1660                 break;
1661         case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1662                 /* When we're shadowing, trap PFs */
1663                 if (!npt_enabled)
1664                         return NESTED_EXIT_HOST;
1665                 break;
1666         case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1667                 nm_interception(svm);
1668                 break;
1669         default:
1670                 break;
1671         }
1672
1673         return NESTED_EXIT_CONTINUE;
1674 }
1675
1676 /*
1677  * If this function returns true, this #vmexit was already handled
1678  */
1679 static int nested_svm_intercept(struct vcpu_svm *svm)
1680 {
1681         u32 exit_code = svm->vmcb->control.exit_code;
1682         int vmexit = NESTED_EXIT_HOST;
1683
1684         switch (exit_code) {
1685         case SVM_EXIT_MSR:
1686                 vmexit = nested_svm_exit_handled_msr(svm);
1687                 break;
1688         case SVM_EXIT_IOIO:
1689                 vmexit = nested_svm_intercept_ioio(svm);
1690                 break;
1691         case SVM_EXIT_READ_CR0 ... SVM_EXIT_READ_CR8: {
1692                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_READ_CR0);
1693                 if (svm->nested.intercept_cr_read & cr_bits)
1694                         vmexit = NESTED_EXIT_DONE;
1695                 break;
1696         }
1697         case SVM_EXIT_WRITE_CR0 ... SVM_EXIT_WRITE_CR8: {
1698                 u32 cr_bits = 1 << (exit_code - SVM_EXIT_WRITE_CR0);
1699                 if (svm->nested.intercept_cr_write & cr_bits)
1700                         vmexit = NESTED_EXIT_DONE;
1701                 break;
1702         }
1703         case SVM_EXIT_READ_DR0 ... SVM_EXIT_READ_DR7: {
1704                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_READ_DR0);
1705                 if (svm->nested.intercept_dr_read & dr_bits)
1706                         vmexit = NESTED_EXIT_DONE;
1707                 break;
1708         }
1709         case SVM_EXIT_WRITE_DR0 ... SVM_EXIT_WRITE_DR7: {
1710                 u32 dr_bits = 1 << (exit_code - SVM_EXIT_WRITE_DR0);
1711                 if (svm->nested.intercept_dr_write & dr_bits)
1712                         vmexit = NESTED_EXIT_DONE;
1713                 break;
1714         }
1715         case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
1716                 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
1717                 if (svm->nested.intercept_exceptions & excp_bits)
1718                         vmexit = NESTED_EXIT_DONE;
1719                 break;
1720         }
1721         case SVM_EXIT_ERR: {
1722                 vmexit = NESTED_EXIT_DONE;
1723                 break;
1724         }
1725         default: {
1726                 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
1727                 if (svm->nested.intercept & exit_bits)
1728                         vmexit = NESTED_EXIT_DONE;
1729         }
1730         }
1731
1732         return vmexit;
1733 }
1734
1735 static int nested_svm_exit_handled(struct vcpu_svm *svm)
1736 {
1737         int vmexit;
1738
1739         vmexit = nested_svm_intercept(svm);
1740
1741         if (vmexit == NESTED_EXIT_DONE)
1742                 nested_svm_vmexit(svm);
1743
1744         return vmexit;
1745 }
1746
1747 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
1748 {
1749         struct vmcb_control_area *dst  = &dst_vmcb->control;
1750         struct vmcb_control_area *from = &from_vmcb->control;
1751
1752         dst->intercept_cr_read    = from->intercept_cr_read;
1753         dst->intercept_cr_write   = from->intercept_cr_write;
1754         dst->intercept_dr_read    = from->intercept_dr_read;
1755         dst->intercept_dr_write   = from->intercept_dr_write;
1756         dst->intercept_exceptions = from->intercept_exceptions;
1757         dst->intercept            = from->intercept;
1758         dst->iopm_base_pa         = from->iopm_base_pa;
1759         dst->msrpm_base_pa        = from->msrpm_base_pa;
1760         dst->tsc_offset           = from->tsc_offset;
1761         dst->asid                 = from->asid;
1762         dst->tlb_ctl              = from->tlb_ctl;
1763         dst->int_ctl              = from->int_ctl;
1764         dst->int_vector           = from->int_vector;
1765         dst->int_state            = from->int_state;
1766         dst->exit_code            = from->exit_code;
1767         dst->exit_code_hi         = from->exit_code_hi;
1768         dst->exit_info_1          = from->exit_info_1;
1769         dst->exit_info_2          = from->exit_info_2;
1770         dst->exit_int_info        = from->exit_int_info;
1771         dst->exit_int_info_err    = from->exit_int_info_err;
1772         dst->nested_ctl           = from->nested_ctl;
1773         dst->event_inj            = from->event_inj;
1774         dst->event_inj_err        = from->event_inj_err;
1775         dst->nested_cr3           = from->nested_cr3;
1776         dst->lbr_ctl              = from->lbr_ctl;
1777 }
1778
1779 static int nested_svm_vmexit(struct vcpu_svm *svm)
1780 {
1781         struct vmcb *nested_vmcb;
1782         struct vmcb *hsave = svm->nested.hsave;
1783         struct vmcb *vmcb = svm->vmcb;
1784         struct page *page;
1785
1786         trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
1787                                        vmcb->control.exit_info_1,
1788                                        vmcb->control.exit_info_2,
1789                                        vmcb->control.exit_int_info,
1790                                        vmcb->control.exit_int_info_err);
1791
1792         nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
1793         if (!nested_vmcb)
1794                 return 1;
1795
1796         /* Exit nested SVM mode */
1797         svm->nested.vmcb = 0;
1798
1799         /* Give the current vmcb to the guest */
1800         disable_gif(svm);
1801
1802         nested_vmcb->save.es     = vmcb->save.es;
1803         nested_vmcb->save.cs     = vmcb->save.cs;
1804         nested_vmcb->save.ss     = vmcb->save.ss;
1805         nested_vmcb->save.ds     = vmcb->save.ds;
1806         nested_vmcb->save.gdtr   = vmcb->save.gdtr;
1807         nested_vmcb->save.idtr   = vmcb->save.idtr;
1808         nested_vmcb->save.cr0    = kvm_read_cr0(&svm->vcpu);
1809         nested_vmcb->save.cr3    = svm->vcpu.arch.cr3;
1810         nested_vmcb->save.cr2    = vmcb->save.cr2;
1811         nested_vmcb->save.cr4    = svm->vcpu.arch.cr4;
1812         nested_vmcb->save.rflags = vmcb->save.rflags;
1813         nested_vmcb->save.rip    = vmcb->save.rip;
1814         nested_vmcb->save.rsp    = vmcb->save.rsp;
1815         nested_vmcb->save.rax    = vmcb->save.rax;
1816         nested_vmcb->save.dr7    = vmcb->save.dr7;
1817         nested_vmcb->save.dr6    = vmcb->save.dr6;
1818         nested_vmcb->save.cpl    = vmcb->save.cpl;
1819
1820         nested_vmcb->control.int_ctl           = vmcb->control.int_ctl;
1821         nested_vmcb->control.int_vector        = vmcb->control.int_vector;
1822         nested_vmcb->control.int_state         = vmcb->control.int_state;
1823         nested_vmcb->control.exit_code         = vmcb->control.exit_code;
1824         nested_vmcb->control.exit_code_hi      = vmcb->control.exit_code_hi;
1825         nested_vmcb->control.exit_info_1       = vmcb->control.exit_info_1;
1826         nested_vmcb->control.exit_info_2       = vmcb->control.exit_info_2;
1827         nested_vmcb->control.exit_int_info     = vmcb->control.exit_int_info;
1828         nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
1829
1830         /*
1831          * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
1832          * to make sure that we do not lose injected events. So check event_inj
1833          * here and copy it to exit_int_info if it is valid.
1834          * Exit_int_info and event_inj can't be both valid because the case
1835          * below only happens on a VMRUN instruction intercept which has
1836          * no valid exit_int_info set.
1837          */
1838         if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
1839                 struct vmcb_control_area *nc = &nested_vmcb->control;
1840
1841                 nc->exit_int_info     = vmcb->control.event_inj;
1842                 nc->exit_int_info_err = vmcb->control.event_inj_err;
1843         }
1844
1845         nested_vmcb->control.tlb_ctl           = 0;
1846         nested_vmcb->control.event_inj         = 0;
1847         nested_vmcb->control.event_inj_err     = 0;
1848
1849         /* We always set V_INTR_MASKING and remember the old value in hflags */
1850         if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1851                 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
1852
1853         /* Restore the original control entries */
1854         copy_vmcb_control_area(vmcb, hsave);
1855
1856         kvm_clear_exception_queue(&svm->vcpu);
1857         kvm_clear_interrupt_queue(&svm->vcpu);
1858
1859         /* Restore selected save entries */
1860         svm->vmcb->save.es = hsave->save.es;
1861         svm->vmcb->save.cs = hsave->save.cs;
1862         svm->vmcb->save.ss = hsave->save.ss;
1863         svm->vmcb->save.ds = hsave->save.ds;
1864         svm->vmcb->save.gdtr = hsave->save.gdtr;
1865         svm->vmcb->save.idtr = hsave->save.idtr;
1866         svm->vmcb->save.rflags = hsave->save.rflags;
1867         svm_set_efer(&svm->vcpu, hsave->save.efer);
1868         svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
1869         svm_set_cr4(&svm->vcpu, hsave->save.cr4);
1870         if (npt_enabled) {
1871                 svm->vmcb->save.cr3 = hsave->save.cr3;
1872                 svm->vcpu.arch.cr3 = hsave->save.cr3;
1873         } else {
1874                 kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
1875         }
1876         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
1877         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
1878         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
1879         svm->vmcb->save.dr7 = 0;
1880         svm->vmcb->save.cpl = 0;
1881         svm->vmcb->control.exit_int_info = 0;
1882
1883         nested_svm_unmap(page);
1884
1885         kvm_mmu_reset_context(&svm->vcpu);
1886         kvm_mmu_load(&svm->vcpu);
1887
1888         return 0;
1889 }
1890
1891 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
1892 {
1893         /*
1894          * This function merges the msr permission bitmaps of kvm and the
1895          * nested vmcb. It is omptimized in that it only merges the parts where
1896          * the kvm msr permission bitmap may contain zero bits
1897          */
1898         int i;
1899
1900         if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1901                 return true;
1902
1903         for (i = 0; i < MSRPM_OFFSETS; i++) {
1904                 u32 value, p;
1905                 u64 offset;
1906
1907                 if (msrpm_offsets[i] == 0xffffffff)
1908                         break;
1909
1910                 p      = msrpm_offsets[i];
1911                 offset = svm->nested.vmcb_msrpm + (p * 4);
1912
1913                 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
1914                         return false;
1915
1916                 svm->nested.msrpm[p] = svm->msrpm[p] | value;
1917         }
1918
1919         svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
1920
1921         return true;
1922 }
1923
1924 static bool nested_svm_vmrun(struct vcpu_svm *svm)
1925 {
1926         struct vmcb *nested_vmcb;
1927         struct vmcb *hsave = svm->nested.hsave;
1928         struct vmcb *vmcb = svm->vmcb;
1929         struct page *page;
1930         u64 vmcb_gpa;
1931
1932         vmcb_gpa = svm->vmcb->save.rax;
1933
1934         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
1935         if (!nested_vmcb)
1936                 return false;
1937
1938         trace_kvm_nested_vmrun(svm->vmcb->save.rip - 3, vmcb_gpa,
1939                                nested_vmcb->save.rip,
1940                                nested_vmcb->control.int_ctl,
1941                                nested_vmcb->control.event_inj,
1942                                nested_vmcb->control.nested_ctl);
1943
1944         trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr_read,
1945                                     nested_vmcb->control.intercept_cr_write,
1946                                     nested_vmcb->control.intercept_exceptions,
1947                                     nested_vmcb->control.intercept);
1948
1949         /* Clear internal status */
1950         kvm_clear_exception_queue(&svm->vcpu);
1951         kvm_clear_interrupt_queue(&svm->vcpu);
1952
1953         /*
1954          * Save the old vmcb, so we don't need to pick what we save, but can
1955          * restore everything when a VMEXIT occurs
1956          */
1957         hsave->save.es     = vmcb->save.es;
1958         hsave->save.cs     = vmcb->save.cs;
1959         hsave->save.ss     = vmcb->save.ss;
1960         hsave->save.ds     = vmcb->save.ds;
1961         hsave->save.gdtr   = vmcb->save.gdtr;
1962         hsave->save.idtr   = vmcb->save.idtr;
1963         hsave->save.efer   = svm->vcpu.arch.efer;
1964         hsave->save.cr0    = kvm_read_cr0(&svm->vcpu);
1965         hsave->save.cr4    = svm->vcpu.arch.cr4;
1966         hsave->save.rflags = vmcb->save.rflags;
1967         hsave->save.rip    = svm->next_rip;
1968         hsave->save.rsp    = vmcb->save.rsp;
1969         hsave->save.rax    = vmcb->save.rax;
1970         if (npt_enabled)
1971                 hsave->save.cr3    = vmcb->save.cr3;
1972         else
1973                 hsave->save.cr3    = svm->vcpu.arch.cr3;
1974
1975         copy_vmcb_control_area(hsave, vmcb);
1976
1977         if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
1978                 svm->vcpu.arch.hflags |= HF_HIF_MASK;
1979         else
1980                 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
1981
1982         /* Load the nested guest state */
1983         svm->vmcb->save.es = nested_vmcb->save.es;
1984         svm->vmcb->save.cs = nested_vmcb->save.cs;
1985         svm->vmcb->save.ss = nested_vmcb->save.ss;
1986         svm->vmcb->save.ds = nested_vmcb->save.ds;
1987         svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
1988         svm->vmcb->save.idtr = nested_vmcb->save.idtr;
1989         svm->vmcb->save.rflags = nested_vmcb->save.rflags;
1990         svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
1991         svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
1992         svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
1993         if (npt_enabled) {
1994                 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
1995                 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
1996         } else
1997                 kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
1998
1999         /* Guest paging mode is active - reset mmu */
2000         kvm_mmu_reset_context(&svm->vcpu);
2001
2002         svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2003         kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2004         kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2005         kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2006
2007         /* In case we don't even reach vcpu_run, the fields are not updated */
2008         svm->vmcb->save.rax = nested_vmcb->save.rax;
2009         svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2010         svm->vmcb->save.rip = nested_vmcb->save.rip;
2011         svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2012         svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2013         svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2014
2015         svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2016         svm->nested.vmcb_iopm  = nested_vmcb->control.iopm_base_pa  & ~0x0fffULL;
2017
2018         /* cache intercepts */
2019         svm->nested.intercept_cr_read    = nested_vmcb->control.intercept_cr_read;
2020         svm->nested.intercept_cr_write   = nested_vmcb->control.intercept_cr_write;
2021         svm->nested.intercept_dr_read    = nested_vmcb->control.intercept_dr_read;
2022         svm->nested.intercept_dr_write   = nested_vmcb->control.intercept_dr_write;
2023         svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2024         svm->nested.intercept            = nested_vmcb->control.intercept;
2025
2026         force_new_asid(&svm->vcpu);
2027         svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2028         if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2029                 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2030         else
2031                 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2032
2033         if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2034                 /* We only want the cr8 intercept bits of the guest */
2035                 svm->vmcb->control.intercept_cr_read &= ~INTERCEPT_CR8_MASK;
2036                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2037         }
2038
2039         /* We don't want to see VMMCALLs from a nested guest */
2040         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_VMMCALL);
2041
2042         /*
2043          * We don't want a nested guest to be more powerful than the guest, so
2044          * all intercepts are ORed
2045          */
2046         svm->vmcb->control.intercept_cr_read |=
2047                 nested_vmcb->control.intercept_cr_read;
2048         svm->vmcb->control.intercept_cr_write |=
2049                 nested_vmcb->control.intercept_cr_write;
2050         svm->vmcb->control.intercept_dr_read |=
2051                 nested_vmcb->control.intercept_dr_read;
2052         svm->vmcb->control.intercept_dr_write |=
2053                 nested_vmcb->control.intercept_dr_write;
2054         svm->vmcb->control.intercept_exceptions |=
2055                 nested_vmcb->control.intercept_exceptions;
2056
2057         svm->vmcb->control.intercept |= nested_vmcb->control.intercept;
2058
2059         svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2060         svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2061         svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2062         svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2063         svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2064         svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2065
2066         nested_svm_unmap(page);
2067
2068         /* nested_vmcb is our indicator if nested SVM is activated */
2069         svm->nested.vmcb = vmcb_gpa;
2070
2071         enable_gif(svm);
2072
2073         return true;
2074 }
2075
2076 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2077 {
2078         to_vmcb->save.fs = from_vmcb->save.fs;
2079         to_vmcb->save.gs = from_vmcb->save.gs;
2080         to_vmcb->save.tr = from_vmcb->save.tr;
2081         to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2082         to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2083         to_vmcb->save.star = from_vmcb->save.star;
2084         to_vmcb->save.lstar = from_vmcb->save.lstar;
2085         to_vmcb->save.cstar = from_vmcb->save.cstar;
2086         to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2087         to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2088         to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2089         to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2090 }
2091
2092 static int vmload_interception(struct vcpu_svm *svm)
2093 {
2094         struct vmcb *nested_vmcb;
2095         struct page *page;
2096
2097         if (nested_svm_check_permissions(svm))
2098                 return 1;
2099
2100         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2101         skip_emulated_instruction(&svm->vcpu);
2102
2103         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2104         if (!nested_vmcb)
2105                 return 1;
2106
2107         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2108         nested_svm_unmap(page);
2109
2110         return 1;
2111 }
2112
2113 static int vmsave_interception(struct vcpu_svm *svm)
2114 {
2115         struct vmcb *nested_vmcb;
2116         struct page *page;
2117
2118         if (nested_svm_check_permissions(svm))
2119                 return 1;
2120
2121         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2122         skip_emulated_instruction(&svm->vcpu);
2123
2124         nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2125         if (!nested_vmcb)
2126                 return 1;
2127
2128         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2129         nested_svm_unmap(page);
2130
2131         return 1;
2132 }
2133
2134 static int vmrun_interception(struct vcpu_svm *svm)
2135 {
2136         if (nested_svm_check_permissions(svm))
2137                 return 1;
2138
2139         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2140         skip_emulated_instruction(&svm->vcpu);
2141
2142         if (!nested_svm_vmrun(svm))
2143                 return 1;
2144
2145         if (!nested_svm_vmrun_msrpm(svm))
2146                 goto failed;
2147
2148         return 1;
2149
2150 failed:
2151
2152         svm->vmcb->control.exit_code    = SVM_EXIT_ERR;
2153         svm->vmcb->control.exit_code_hi = 0;
2154         svm->vmcb->control.exit_info_1  = 0;
2155         svm->vmcb->control.exit_info_2  = 0;
2156
2157         nested_svm_vmexit(svm);
2158
2159         return 1;
2160 }
2161
2162 static int stgi_interception(struct vcpu_svm *svm)
2163 {
2164         if (nested_svm_check_permissions(svm))
2165                 return 1;
2166
2167         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2168         skip_emulated_instruction(&svm->vcpu);
2169
2170         enable_gif(svm);
2171
2172         return 1;
2173 }
2174
2175 static int clgi_interception(struct vcpu_svm *svm)
2176 {
2177         if (nested_svm_check_permissions(svm))
2178                 return 1;
2179
2180         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2181         skip_emulated_instruction(&svm->vcpu);
2182
2183         disable_gif(svm);
2184
2185         /* After a CLGI no interrupts should come */
2186         svm_clear_vintr(svm);
2187         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2188
2189         return 1;
2190 }
2191
2192 static int invlpga_interception(struct vcpu_svm *svm)
2193 {
2194         struct kvm_vcpu *vcpu = &svm->vcpu;
2195
2196         trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2197                           vcpu->arch.regs[VCPU_REGS_RAX]);
2198
2199         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2200         kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2201
2202         svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2203         skip_emulated_instruction(&svm->vcpu);
2204         return 1;
2205 }
2206
2207 static int skinit_interception(struct vcpu_svm *svm)
2208 {
2209         trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2210
2211         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2212         return 1;
2213 }
2214
2215 static int invalid_op_interception(struct vcpu_svm *svm)
2216 {
2217         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2218         return 1;
2219 }
2220
2221 static int task_switch_interception(struct vcpu_svm *svm)
2222 {
2223         u16 tss_selector;
2224         int reason;
2225         int int_type = svm->vmcb->control.exit_int_info &
2226                 SVM_EXITINTINFO_TYPE_MASK;
2227         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2228         uint32_t type =
2229                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2230         uint32_t idt_v =
2231                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2232         bool has_error_code = false;
2233         u32 error_code = 0;
2234
2235         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2236
2237         if (svm->vmcb->control.exit_info_2 &
2238             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2239                 reason = TASK_SWITCH_IRET;
2240         else if (svm->vmcb->control.exit_info_2 &
2241                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2242                 reason = TASK_SWITCH_JMP;
2243         else if (idt_v)
2244                 reason = TASK_SWITCH_GATE;
2245         else
2246                 reason = TASK_SWITCH_CALL;
2247
2248         if (reason == TASK_SWITCH_GATE) {
2249                 switch (type) {
2250                 case SVM_EXITINTINFO_TYPE_NMI:
2251                         svm->vcpu.arch.nmi_injected = false;
2252                         break;
2253                 case SVM_EXITINTINFO_TYPE_EXEPT:
2254                         if (svm->vmcb->control.exit_info_2 &
2255                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2256                                 has_error_code = true;
2257                                 error_code =
2258                                         (u32)svm->vmcb->control.exit_info_2;
2259                         }
2260                         kvm_clear_exception_queue(&svm->vcpu);
2261                         break;
2262                 case SVM_EXITINTINFO_TYPE_INTR:
2263                         kvm_clear_interrupt_queue(&svm->vcpu);
2264                         break;
2265                 default:
2266                         break;
2267                 }
2268         }
2269
2270         if (reason != TASK_SWITCH_GATE ||
2271             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2272             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2273              (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2274                 skip_emulated_instruction(&svm->vcpu);
2275
2276         if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2277                                 has_error_code, error_code) == EMULATE_FAIL) {
2278                 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2279                 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2280                 svm->vcpu.run->internal.ndata = 0;
2281                 return 0;
2282         }
2283         return 1;
2284 }
2285
2286 static int cpuid_interception(struct vcpu_svm *svm)
2287 {
2288         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2289         kvm_emulate_cpuid(&svm->vcpu);
2290         return 1;
2291 }
2292
2293 static int iret_interception(struct vcpu_svm *svm)
2294 {
2295         ++svm->vcpu.stat.nmi_window_exits;
2296         svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2297         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2298         return 1;
2299 }
2300
2301 static int invlpg_interception(struct vcpu_svm *svm)
2302 {
2303         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2304                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2305         return 1;
2306 }
2307
2308 static int emulate_on_interception(struct vcpu_svm *svm)
2309 {
2310         if (emulate_instruction(&svm->vcpu, 0, 0, 0) != EMULATE_DONE)
2311                 pr_unimpl(&svm->vcpu, "%s: failed\n", __func__);
2312         return 1;
2313 }
2314
2315 static int cr8_write_interception(struct vcpu_svm *svm)
2316 {
2317         struct kvm_run *kvm_run = svm->vcpu.run;
2318
2319         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2320         /* instruction emulation calls kvm_set_cr8() */
2321         emulate_instruction(&svm->vcpu, 0, 0, 0);
2322         if (irqchip_in_kernel(svm->vcpu.kvm)) {
2323                 svm->vmcb->control.intercept_cr_write &= ~INTERCEPT_CR8_MASK;
2324                 return 1;
2325         }
2326         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2327                 return 1;
2328         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2329         return 0;
2330 }
2331
2332 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2333 {
2334         struct vcpu_svm *svm = to_svm(vcpu);
2335
2336         switch (ecx) {
2337         case MSR_IA32_TSC: {
2338                 u64 tsc_offset;
2339
2340                 if (is_nested(svm))
2341                         tsc_offset = svm->nested.hsave->control.tsc_offset;
2342                 else
2343                         tsc_offset = svm->vmcb->control.tsc_offset;
2344
2345                 *data = tsc_offset + native_read_tsc();
2346                 break;
2347         }
2348         case MSR_K6_STAR:
2349                 *data = svm->vmcb->save.star;
2350                 break;
2351 #ifdef CONFIG_X86_64
2352         case MSR_LSTAR:
2353                 *data = svm->vmcb->save.lstar;
2354                 break;
2355         case MSR_CSTAR:
2356                 *data = svm->vmcb->save.cstar;
2357                 break;
2358         case MSR_KERNEL_GS_BASE:
2359                 *data = svm->vmcb->save.kernel_gs_base;
2360                 break;
2361         case MSR_SYSCALL_MASK:
2362                 *data = svm->vmcb->save.sfmask;
2363                 break;
2364 #endif
2365         case MSR_IA32_SYSENTER_CS:
2366                 *data = svm->vmcb->save.sysenter_cs;
2367                 break;
2368         case MSR_IA32_SYSENTER_EIP:
2369                 *data = svm->sysenter_eip;
2370                 break;
2371         case MSR_IA32_SYSENTER_ESP:
2372                 *data = svm->sysenter_esp;
2373                 break;
2374         /*
2375          * Nobody will change the following 5 values in the VMCB so we can
2376          * safely return them on rdmsr. They will always be 0 until LBRV is
2377          * implemented.
2378          */
2379         case MSR_IA32_DEBUGCTLMSR:
2380                 *data = svm->vmcb->save.dbgctl;
2381                 break;
2382         case MSR_IA32_LASTBRANCHFROMIP:
2383                 *data = svm->vmcb->save.br_from;
2384                 break;
2385         case MSR_IA32_LASTBRANCHTOIP:
2386                 *data = svm->vmcb->save.br_to;
2387                 break;
2388         case MSR_IA32_LASTINTFROMIP:
2389                 *data = svm->vmcb->save.last_excp_from;
2390                 break;
2391         case MSR_IA32_LASTINTTOIP:
2392                 *data = svm->vmcb->save.last_excp_to;
2393                 break;
2394         case MSR_VM_HSAVE_PA:
2395                 *data = svm->nested.hsave_msr;
2396                 break;
2397         case MSR_VM_CR:
2398                 *data = svm->nested.vm_cr_msr;
2399                 break;
2400         case MSR_IA32_UCODE_REV:
2401                 *data = 0x01000065;
2402                 break;
2403         default:
2404                 return kvm_get_msr_common(vcpu, ecx, data);
2405         }
2406         return 0;
2407 }
2408
2409 static int rdmsr_interception(struct vcpu_svm *svm)
2410 {
2411         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2412         u64 data;
2413
2414         if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2415                 trace_kvm_msr_read_ex(ecx);
2416                 kvm_inject_gp(&svm->vcpu, 0);
2417         } else {
2418                 trace_kvm_msr_read(ecx, data);
2419
2420                 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2421                 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2422                 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2423                 skip_emulated_instruction(&svm->vcpu);
2424         }
2425         return 1;
2426 }
2427
2428 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2429 {
2430         struct vcpu_svm *svm = to_svm(vcpu);
2431         int svm_dis, chg_mask;
2432
2433         if (data & ~SVM_VM_CR_VALID_MASK)
2434                 return 1;
2435
2436         chg_mask = SVM_VM_CR_VALID_MASK;
2437
2438         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2439                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2440
2441         svm->nested.vm_cr_msr &= ~chg_mask;
2442         svm->nested.vm_cr_msr |= (data & chg_mask);
2443
2444         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2445
2446         /* check for svm_disable while efer.svme is set */
2447         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2448                 return 1;
2449
2450         return 0;
2451 }
2452
2453 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2454 {
2455         struct vcpu_svm *svm = to_svm(vcpu);
2456
2457         switch (ecx) {
2458         case MSR_IA32_TSC: {
2459                 u64 tsc_offset = data - native_read_tsc();
2460                 u64 g_tsc_offset = 0;
2461
2462                 if (is_nested(svm)) {
2463                         g_tsc_offset = svm->vmcb->control.tsc_offset -
2464                                        svm->nested.hsave->control.tsc_offset;
2465                         svm->nested.hsave->control.tsc_offset = tsc_offset;
2466                 }
2467
2468                 svm->vmcb->control.tsc_offset = tsc_offset + g_tsc_offset;
2469
2470                 break;
2471         }
2472         case MSR_K6_STAR:
2473                 svm->vmcb->save.star = data;
2474                 break;
2475 #ifdef CONFIG_X86_64
2476         case MSR_LSTAR:
2477                 svm->vmcb->save.lstar = data;
2478                 break;
2479         case MSR_CSTAR:
2480                 svm->vmcb->save.cstar = data;
2481                 break;
2482         case MSR_KERNEL_GS_BASE:
2483                 svm->vmcb->save.kernel_gs_base = data;
2484                 break;
2485         case MSR_SYSCALL_MASK:
2486                 svm->vmcb->save.sfmask = data;
2487                 break;
2488 #endif
2489         case MSR_IA32_SYSENTER_CS:
2490                 svm->vmcb->save.sysenter_cs = data;
2491                 break;
2492         case MSR_IA32_SYSENTER_EIP:
2493                 svm->sysenter_eip = data;
2494                 svm->vmcb->save.sysenter_eip = data;
2495                 break;
2496         case MSR_IA32_SYSENTER_ESP:
2497                 svm->sysenter_esp = data;
2498                 svm->vmcb->save.sysenter_esp = data;
2499                 break;
2500         case MSR_IA32_DEBUGCTLMSR:
2501                 if (!svm_has(SVM_FEATURE_LBRV)) {
2502                         pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2503                                         __func__, data);
2504                         break;
2505                 }
2506                 if (data & DEBUGCTL_RESERVED_BITS)
2507                         return 1;
2508
2509                 svm->vmcb->save.dbgctl = data;
2510                 if (data & (1ULL<<0))
2511                         svm_enable_lbrv(svm);
2512                 else
2513                         svm_disable_lbrv(svm);
2514                 break;
2515         case MSR_VM_HSAVE_PA:
2516                 svm->nested.hsave_msr = data;
2517                 break;
2518         case MSR_VM_CR:
2519                 return svm_set_vm_cr(vcpu, data);
2520         case MSR_VM_IGNNE:
2521                 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2522                 break;
2523         default:
2524                 return kvm_set_msr_common(vcpu, ecx, data);
2525         }
2526         return 0;
2527 }
2528
2529 static int wrmsr_interception(struct vcpu_svm *svm)
2530 {
2531         u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2532         u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2533                 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2534
2535
2536         svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2537         if (svm_set_msr(&svm->vcpu, ecx, data)) {
2538                 trace_kvm_msr_write_ex(ecx, data);
2539                 kvm_inject_gp(&svm->vcpu, 0);
2540         } else {
2541                 trace_kvm_msr_write(ecx, data);
2542                 skip_emulated_instruction(&svm->vcpu);
2543         }
2544         return 1;
2545 }
2546
2547 static int msr_interception(struct vcpu_svm *svm)
2548 {
2549         if (svm->vmcb->control.exit_info_1)
2550                 return wrmsr_interception(svm);
2551         else
2552                 return rdmsr_interception(svm);
2553 }
2554
2555 static int interrupt_window_interception(struct vcpu_svm *svm)
2556 {
2557         struct kvm_run *kvm_run = svm->vcpu.run;
2558
2559         svm_clear_vintr(svm);
2560         svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2561         /*
2562          * If the user space waits to inject interrupts, exit as soon as
2563          * possible
2564          */
2565         if (!irqchip_in_kernel(svm->vcpu.kvm) &&
2566             kvm_run->request_interrupt_window &&
2567             !kvm_cpu_has_interrupt(&svm->vcpu)) {
2568                 ++svm->vcpu.stat.irq_window_exits;
2569                 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
2570                 return 0;
2571         }
2572
2573         return 1;
2574 }
2575
2576 static int pause_interception(struct vcpu_svm *svm)
2577 {
2578         kvm_vcpu_on_spin(&(svm->vcpu));
2579         return 1;
2580 }
2581
2582 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
2583         [SVM_EXIT_READ_CR0]                     = emulate_on_interception,
2584         [SVM_EXIT_READ_CR3]                     = emulate_on_interception,
2585         [SVM_EXIT_READ_CR4]                     = emulate_on_interception,
2586         [SVM_EXIT_READ_CR8]                     = emulate_on_interception,
2587         [SVM_EXIT_CR0_SEL_WRITE]                = emulate_on_interception,
2588         [SVM_EXIT_WRITE_CR0]                    = emulate_on_interception,
2589         [SVM_EXIT_WRITE_CR3]                    = emulate_on_interception,
2590         [SVM_EXIT_WRITE_CR4]                    = emulate_on_interception,
2591         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2592         [SVM_EXIT_READ_DR0]                     = emulate_on_interception,
2593         [SVM_EXIT_READ_DR1]                     = emulate_on_interception,
2594         [SVM_EXIT_READ_DR2]                     = emulate_on_interception,
2595         [SVM_EXIT_READ_DR3]                     = emulate_on_interception,
2596         [SVM_EXIT_READ_DR4]                     = emulate_on_interception,
2597         [SVM_EXIT_READ_DR5]                     = emulate_on_interception,
2598         [SVM_EXIT_READ_DR6]                     = emulate_on_interception,
2599         [SVM_EXIT_READ_DR7]                     = emulate_on_interception,
2600         [SVM_EXIT_WRITE_DR0]                    = emulate_on_interception,
2601         [SVM_EXIT_WRITE_DR1]                    = emulate_on_interception,
2602         [SVM_EXIT_WRITE_DR2]                    = emulate_on_interception,
2603         [SVM_EXIT_WRITE_DR3]                    = emulate_on_interception,
2604         [SVM_EXIT_WRITE_DR4]                    = emulate_on_interception,
2605         [SVM_EXIT_WRITE_DR5]                    = emulate_on_interception,
2606         [SVM_EXIT_WRITE_DR6]                    = emulate_on_interception,
2607         [SVM_EXIT_WRITE_DR7]                    = emulate_on_interception,
2608         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2609         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2610         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2611         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2612         [SVM_EXIT_EXCP_BASE + NM_VECTOR]        = nm_interception,
2613         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2614         [SVM_EXIT_INTR]                         = intr_interception,
2615         [SVM_EXIT_NMI]                          = nmi_interception,
2616         [SVM_EXIT_SMI]                          = nop_on_interception,
2617         [SVM_EXIT_INIT]                         = nop_on_interception,
2618         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2619         [SVM_EXIT_CPUID]                        = cpuid_interception,
2620         [SVM_EXIT_IRET]                         = iret_interception,
2621         [SVM_EXIT_INVD]                         = emulate_on_interception,
2622         [SVM_EXIT_PAUSE]                        = pause_interception,
2623         [SVM_EXIT_HLT]                          = halt_interception,
2624         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2625         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2626         [SVM_EXIT_IOIO]                         = io_interception,
2627         [SVM_EXIT_MSR]                          = msr_interception,
2628         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2629         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2630         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2631         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2632         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2633         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2634         [SVM_EXIT_STGI]                         = stgi_interception,
2635         [SVM_EXIT_CLGI]                         = clgi_interception,
2636         [SVM_EXIT_SKINIT]                       = skinit_interception,
2637         [SVM_EXIT_WBINVD]                       = emulate_on_interception,
2638         [SVM_EXIT_MONITOR]                      = invalid_op_interception,
2639         [SVM_EXIT_MWAIT]                        = invalid_op_interception,
2640         [SVM_EXIT_NPF]                          = pf_interception,
2641 };
2642
2643 static int handle_exit(struct kvm_vcpu *vcpu)
2644 {
2645         struct vcpu_svm *svm = to_svm(vcpu);
2646         struct kvm_run *kvm_run = vcpu->run;
2647         u32 exit_code = svm->vmcb->control.exit_code;
2648
2649         trace_kvm_exit(exit_code, vcpu);
2650
2651         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR0_MASK))
2652                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2653         if (npt_enabled)
2654                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2655
2656         if (unlikely(svm->nested.exit_required)) {
2657                 nested_svm_vmexit(svm);
2658                 svm->nested.exit_required = false;
2659
2660                 return 1;
2661         }
2662
2663         if (is_nested(svm)) {
2664                 int vmexit;
2665
2666                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2667                                         svm->vmcb->control.exit_info_1,
2668                                         svm->vmcb->control.exit_info_2,
2669                                         svm->vmcb->control.exit_int_info,
2670                                         svm->vmcb->control.exit_int_info_err);
2671
2672                 vmexit = nested_svm_exit_special(svm);
2673
2674                 if (vmexit == NESTED_EXIT_CONTINUE)
2675                         vmexit = nested_svm_exit_handled(svm);
2676
2677                 if (vmexit == NESTED_EXIT_DONE)
2678                         return 1;
2679         }
2680
2681         svm_complete_interrupts(svm);
2682
2683         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2684                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2685                 kvm_run->fail_entry.hardware_entry_failure_reason
2686                         = svm->vmcb->control.exit_code;
2687                 return 0;
2688         }
2689
2690         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2691             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2692             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH)
2693                 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
2694                        "exit_code 0x%x\n",
2695                        __func__, svm->vmcb->control.exit_int_info,
2696                        exit_code);
2697
2698         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2699             || !svm_exit_handlers[exit_code]) {
2700                 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
2701                 kvm_run->hw.hardware_exit_reason = exit_code;
2702                 return 0;
2703         }
2704
2705         return svm_exit_handlers[exit_code](svm);
2706 }
2707
2708 static void reload_tss(struct kvm_vcpu *vcpu)
2709 {
2710         int cpu = raw_smp_processor_id();
2711
2712         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2713         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2714         load_TR_desc();
2715 }
2716
2717 static void pre_svm_run(struct vcpu_svm *svm)
2718 {
2719         int cpu = raw_smp_processor_id();
2720
2721         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2722
2723         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
2724         /* FIXME: handle wraparound of asid_generation */
2725         if (svm->asid_generation != sd->asid_generation)
2726                 new_asid(svm, sd);
2727 }
2728
2729 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
2730 {
2731         struct vcpu_svm *svm = to_svm(vcpu);
2732
2733         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
2734         vcpu->arch.hflags |= HF_NMI_MASK;
2735         svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2736         ++vcpu->stat.nmi_injections;
2737 }
2738
2739 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
2740 {
2741         struct vmcb_control_area *control;
2742
2743         trace_kvm_inj_virq(irq);
2744
2745         ++svm->vcpu.stat.irq_injections;
2746         control = &svm->vmcb->control;
2747         control->int_vector = irq;
2748         control->int_ctl &= ~V_INTR_PRIO_MASK;
2749         control->int_ctl |= V_IRQ_MASK |
2750                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
2751 }
2752
2753 static void svm_set_irq(struct kvm_vcpu *vcpu)
2754 {
2755         struct vcpu_svm *svm = to_svm(vcpu);
2756
2757         BUG_ON(!(gif_set(svm)));
2758
2759         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
2760                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
2761 }
2762
2763 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
2764 {
2765         struct vcpu_svm *svm = to_svm(vcpu);
2766
2767         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2768                 return;
2769
2770         if (irr == -1)
2771                 return;
2772
2773         if (tpr >= irr)
2774                 svm->vmcb->control.intercept_cr_write |= INTERCEPT_CR8_MASK;
2775 }
2776
2777 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
2778 {
2779         struct vcpu_svm *svm = to_svm(vcpu);
2780         struct vmcb *vmcb = svm->vmcb;
2781         int ret;
2782         ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
2783               !(svm->vcpu.arch.hflags & HF_NMI_MASK);
2784         ret = ret && gif_set(svm) && nested_svm_nmi(svm);
2785
2786         return ret;
2787 }
2788
2789 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
2790 {
2791         struct vcpu_svm *svm = to_svm(vcpu);
2792
2793         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
2794 }
2795
2796 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
2797 {
2798         struct vcpu_svm *svm = to_svm(vcpu);
2799
2800         if (masked) {
2801                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
2802                 svm->vmcb->control.intercept |= (1ULL << INTERCEPT_IRET);
2803         } else {
2804                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
2805                 svm->vmcb->control.intercept &= ~(1ULL << INTERCEPT_IRET);
2806         }
2807 }
2808
2809 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
2810 {
2811         struct vcpu_svm *svm = to_svm(vcpu);
2812         struct vmcb *vmcb = svm->vmcb;
2813         int ret;
2814
2815         if (!gif_set(svm) ||
2816              (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
2817                 return 0;
2818
2819         ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
2820
2821         if (is_nested(svm))
2822                 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
2823
2824         return ret;
2825 }
2826
2827 static void enable_irq_window(struct kvm_vcpu *vcpu)
2828 {
2829         struct vcpu_svm *svm = to_svm(vcpu);
2830
2831         /*
2832          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
2833          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
2834          * get that intercept, this function will be called again though and
2835          * we'll get the vintr intercept.
2836          */
2837         if (gif_set(svm) && nested_svm_intr(svm)) {
2838                 svm_set_vintr(svm);
2839                 svm_inject_irq(svm, 0x0);
2840         }
2841 }
2842
2843 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2844 {
2845         struct vcpu_svm *svm = to_svm(vcpu);
2846
2847         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
2848             == HF_NMI_MASK)
2849                 return; /* IRET will cause a vm exit */
2850
2851         /*
2852          * Something prevents NMI from been injected. Single step over possible
2853          * problem (IRET or exception injection or interrupt shadow)
2854          */
2855         svm->nmi_singlestep = true;
2856         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
2857         update_db_intercept(vcpu);
2858 }
2859
2860 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
2861 {
2862         return 0;
2863 }
2864
2865 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
2866 {
2867         force_new_asid(vcpu);
2868 }
2869
2870 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
2871 {
2872 }
2873
2874 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
2875 {
2876         struct vcpu_svm *svm = to_svm(vcpu);
2877
2878         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2879                 return;
2880
2881         if (!(svm->vmcb->control.intercept_cr_write & INTERCEPT_CR8_MASK)) {
2882                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
2883                 kvm_set_cr8(vcpu, cr8);
2884         }
2885 }
2886
2887 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
2888 {
2889         struct vcpu_svm *svm = to_svm(vcpu);
2890         u64 cr8;
2891
2892         if (is_nested(svm) && (vcpu->arch.hflags & HF_VINTR_MASK))
2893                 return;
2894
2895         cr8 = kvm_get_cr8(vcpu);
2896         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
2897         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
2898 }
2899
2900 static void svm_complete_interrupts(struct vcpu_svm *svm)
2901 {
2902         u8 vector;
2903         int type;
2904         u32 exitintinfo = svm->vmcb->control.exit_int_info;
2905         unsigned int3_injected = svm->int3_injected;
2906
2907         svm->int3_injected = 0;
2908
2909         if (svm->vcpu.arch.hflags & HF_IRET_MASK)
2910                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
2911
2912         svm->vcpu.arch.nmi_injected = false;
2913         kvm_clear_exception_queue(&svm->vcpu);
2914         kvm_clear_interrupt_queue(&svm->vcpu);
2915
2916         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
2917                 return;
2918
2919         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
2920         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
2921
2922         switch (type) {
2923         case SVM_EXITINTINFO_TYPE_NMI:
2924                 svm->vcpu.arch.nmi_injected = true;
2925                 break;
2926         case SVM_EXITINTINFO_TYPE_EXEPT:
2927                 /*
2928                  * In case of software exceptions, do not reinject the vector,
2929                  * but re-execute the instruction instead. Rewind RIP first
2930                  * if we emulated INT3 before.
2931                  */
2932                 if (kvm_exception_is_soft(vector)) {
2933                         if (vector == BP_VECTOR && int3_injected &&
2934                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
2935                                 kvm_rip_write(&svm->vcpu,
2936                                               kvm_rip_read(&svm->vcpu) -
2937                                               int3_injected);
2938                         break;
2939                 }
2940                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
2941                         u32 err = svm->vmcb->control.exit_int_info_err;
2942                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
2943
2944                 } else
2945                         kvm_requeue_exception(&svm->vcpu, vector);
2946                 break;
2947         case SVM_EXITINTINFO_TYPE_INTR:
2948                 kvm_queue_interrupt(&svm->vcpu, vector, false);
2949                 break;
2950         default:
2951                 break;
2952         }
2953 }
2954
2955 #ifdef CONFIG_X86_64
2956 #define R "r"
2957 #else
2958 #define R "e"
2959 #endif
2960
2961 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
2962 {
2963         struct vcpu_svm *svm = to_svm(vcpu);
2964         u16 fs_selector;
2965         u16 gs_selector;
2966         u16 ldt_selector;
2967
2968         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
2969         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
2970         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
2971
2972         /*
2973          * A vmexit emulation is required before the vcpu can be executed
2974          * again.
2975          */
2976         if (unlikely(svm->nested.exit_required))
2977                 return;
2978
2979         pre_svm_run(svm);
2980
2981         sync_lapic_to_cr8(vcpu);
2982
2983         save_host_msrs(vcpu);
2984         fs_selector = kvm_read_fs();
2985         gs_selector = kvm_read_gs();
2986         ldt_selector = kvm_read_ldt();
2987         svm->vmcb->save.cr2 = vcpu->arch.cr2;
2988         /* required for live migration with NPT */
2989         if (npt_enabled)
2990                 svm->vmcb->save.cr3 = vcpu->arch.cr3;
2991
2992         clgi();
2993
2994         local_irq_enable();
2995
2996         asm volatile (
2997                 "push %%"R"bp; \n\t"
2998                 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
2999                 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3000                 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3001                 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3002                 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3003                 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3004 #ifdef CONFIG_X86_64
3005                 "mov %c[r8](%[svm]),  %%r8  \n\t"
3006                 "mov %c[r9](%[svm]),  %%r9  \n\t"
3007                 "mov %c[r10](%[svm]), %%r10 \n\t"
3008                 "mov %c[r11](%[svm]), %%r11 \n\t"
3009                 "mov %c[r12](%[svm]), %%r12 \n\t"
3010                 "mov %c[r13](%[svm]), %%r13 \n\t"
3011                 "mov %c[r14](%[svm]), %%r14 \n\t"
3012                 "mov %c[r15](%[svm]), %%r15 \n\t"
3013 #endif
3014
3015                 /* Enter guest mode */
3016                 "push %%"R"ax \n\t"
3017                 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3018                 __ex(SVM_VMLOAD) "\n\t"
3019                 __ex(SVM_VMRUN) "\n\t"
3020                 __ex(SVM_VMSAVE) "\n\t"
3021                 "pop %%"R"ax \n\t"
3022
3023                 /* Save guest registers, load host registers */
3024                 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3025                 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3026                 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3027                 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3028                 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3029                 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3030 #ifdef CONFIG_X86_64
3031                 "mov %%r8,  %c[r8](%[svm]) \n\t"
3032                 "mov %%r9,  %c[r9](%[svm]) \n\t"
3033                 "mov %%r10, %c[r10](%[svm]) \n\t"
3034                 "mov %%r11, %c[r11](%[svm]) \n\t"
3035                 "mov %%r12, %c[r12](%[svm]) \n\t"
3036                 "mov %%r13, %c[r13](%[svm]) \n\t"
3037                 "mov %%r14, %c[r14](%[svm]) \n\t"
3038                 "mov %%r15, %c[r15](%[svm]) \n\t"
3039 #endif
3040                 "pop %%"R"bp"
3041                 :
3042                 : [svm]"a"(svm),
3043                   [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3044                   [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3045                   [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3046                   [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3047                   [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3048                   [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3049                   [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3050 #ifdef CONFIG_X86_64
3051                   , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3052                   [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3053                   [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3054                   [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3055                   [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3056                   [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3057                   [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3058                   [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3059 #endif
3060                 : "cc", "memory"
3061                 , R"bx", R"cx", R"dx", R"si", R"di"
3062 #ifdef CONFIG_X86_64
3063                 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3064 #endif
3065                 );
3066
3067         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3068         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3069         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3070         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3071
3072         kvm_load_fs(fs_selector);
3073         kvm_load_gs(gs_selector);
3074         kvm_load_ldt(ldt_selector);
3075         load_host_msrs(vcpu);
3076
3077         reload_tss(vcpu);
3078
3079         local_irq_disable();
3080
3081         stgi();
3082
3083         sync_cr8_to_lapic(vcpu);
3084
3085         svm->next_rip = 0;
3086
3087         if (npt_enabled) {
3088                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3089                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3090         }
3091 }
3092
3093 #undef R
3094
3095 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3096 {
3097         struct vcpu_svm *svm = to_svm(vcpu);
3098
3099         if (npt_enabled) {
3100                 svm->vmcb->control.nested_cr3 = root;
3101                 force_new_asid(vcpu);
3102                 return;
3103         }
3104
3105         svm->vmcb->save.cr3 = root;
3106         force_new_asid(vcpu);
3107 }
3108
3109 static int is_disabled(void)
3110 {
3111         u64 vm_cr;
3112
3113         rdmsrl(MSR_VM_CR, vm_cr);
3114         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3115                 return 1;
3116
3117         return 0;
3118 }
3119
3120 static void
3121 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3122 {
3123         /*
3124          * Patch in the VMMCALL instruction:
3125          */
3126         hypercall[0] = 0x0f;
3127         hypercall[1] = 0x01;
3128         hypercall[2] = 0xd9;
3129 }
3130
3131 static void svm_check_processor_compat(void *rtn)
3132 {
3133         *(int *)rtn = 0;
3134 }
3135
3136 static bool svm_cpu_has_accelerated_tpr(void)
3137 {
3138         return false;
3139 }
3140
3141 static int get_npt_level(void)
3142 {
3143 #ifdef CONFIG_X86_64
3144         return PT64_ROOT_LEVEL;
3145 #else
3146         return PT32E_ROOT_LEVEL;
3147 #endif
3148 }
3149
3150 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3151 {
3152         return 0;
3153 }
3154
3155 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3156 {
3157 }
3158
3159 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3160 {
3161         switch (func) {
3162         case 0x8000000A:
3163                 entry->eax = 1; /* SVM revision 1 */
3164                 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3165                                    ASID emulation to nested SVM */
3166                 entry->ecx = 0; /* Reserved */
3167                 entry->edx = 0; /* Do not support any additional features */
3168
3169                 break;
3170         }
3171 }
3172
3173 static const struct trace_print_flags svm_exit_reasons_str[] = {
3174         { SVM_EXIT_READ_CR0,                    "read_cr0" },
3175         { SVM_EXIT_READ_CR3,                    "read_cr3" },
3176         { SVM_EXIT_READ_CR4,                    "read_cr4" },
3177         { SVM_EXIT_READ_CR8,                    "read_cr8" },
3178         { SVM_EXIT_WRITE_CR0,                   "write_cr0" },
3179         { SVM_EXIT_WRITE_CR3,                   "write_cr3" },
3180         { SVM_EXIT_WRITE_CR4,                   "write_cr4" },
3181         { SVM_EXIT_WRITE_CR8,                   "write_cr8" },
3182         { SVM_EXIT_READ_DR0,                    "read_dr0" },
3183         { SVM_EXIT_READ_DR1,                    "read_dr1" },
3184         { SVM_EXIT_READ_DR2,                    "read_dr2" },
3185         { SVM_EXIT_READ_DR3,                    "read_dr3" },
3186         { SVM_EXIT_WRITE_DR0,                   "write_dr0" },
3187         { SVM_EXIT_WRITE_DR1,                   "write_dr1" },
3188         { SVM_EXIT_WRITE_DR2,                   "write_dr2" },
3189         { SVM_EXIT_WRITE_DR3,                   "write_dr3" },
3190         { SVM_EXIT_WRITE_DR5,                   "write_dr5" },
3191         { SVM_EXIT_WRITE_DR7,                   "write_dr7" },
3192         { SVM_EXIT_EXCP_BASE + DB_VECTOR,       "DB excp" },
3193         { SVM_EXIT_EXCP_BASE + BP_VECTOR,       "BP excp" },
3194         { SVM_EXIT_EXCP_BASE + UD_VECTOR,       "UD excp" },
3195         { SVM_EXIT_EXCP_BASE + PF_VECTOR,       "PF excp" },
3196         { SVM_EXIT_EXCP_BASE + NM_VECTOR,       "NM excp" },
3197         { SVM_EXIT_EXCP_BASE + MC_VECTOR,       "MC excp" },
3198         { SVM_EXIT_INTR,                        "interrupt" },
3199         { SVM_EXIT_NMI,                         "nmi" },
3200         { SVM_EXIT_SMI,                         "smi" },
3201         { SVM_EXIT_INIT,                        "init" },
3202         { SVM_EXIT_VINTR,                       "vintr" },
3203         { SVM_EXIT_CPUID,                       "cpuid" },
3204         { SVM_EXIT_INVD,                        "invd" },
3205         { SVM_EXIT_HLT,                         "hlt" },
3206         { SVM_EXIT_INVLPG,                      "invlpg" },
3207         { SVM_EXIT_INVLPGA,                     "invlpga" },
3208         { SVM_EXIT_IOIO,                        "io" },
3209         { SVM_EXIT_MSR,                         "msr" },
3210         { SVM_EXIT_TASK_SWITCH,                 "task_switch" },
3211         { SVM_EXIT_SHUTDOWN,                    "shutdown" },
3212         { SVM_EXIT_VMRUN,                       "vmrun" },
3213         { SVM_EXIT_VMMCALL,                     "hypercall" },
3214         { SVM_EXIT_VMLOAD,                      "vmload" },
3215         { SVM_EXIT_VMSAVE,                      "vmsave" },
3216         { SVM_EXIT_STGI,                        "stgi" },
3217         { SVM_EXIT_CLGI,                        "clgi" },
3218         { SVM_EXIT_SKINIT,                      "skinit" },
3219         { SVM_EXIT_WBINVD,                      "wbinvd" },
3220         { SVM_EXIT_MONITOR,                     "monitor" },
3221         { SVM_EXIT_MWAIT,                       "mwait" },
3222         { SVM_EXIT_NPF,                         "npf" },
3223         { -1, NULL }
3224 };
3225
3226 static int svm_get_lpage_level(void)
3227 {
3228         return PT_PDPE_LEVEL;
3229 }
3230
3231 static bool svm_rdtscp_supported(void)
3232 {
3233         return false;
3234 }
3235
3236 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3237 {
3238         struct vcpu_svm *svm = to_svm(vcpu);
3239
3240         svm->vmcb->control.intercept_exceptions |= 1 << NM_VECTOR;
3241         if (is_nested(svm))
3242                 svm->nested.hsave->control.intercept_exceptions |= 1 << NM_VECTOR;
3243         update_cr0_intercept(svm);
3244 }
3245
3246 static struct kvm_x86_ops svm_x86_ops = {
3247         .cpu_has_kvm_support = has_svm,
3248         .disabled_by_bios = is_disabled,
3249         .hardware_setup = svm_hardware_setup,
3250         .hardware_unsetup = svm_hardware_unsetup,
3251         .check_processor_compatibility = svm_check_processor_compat,
3252         .hardware_enable = svm_hardware_enable,
3253         .hardware_disable = svm_hardware_disable,
3254         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3255
3256         .vcpu_create = svm_create_vcpu,
3257         .vcpu_free = svm_free_vcpu,
3258         .vcpu_reset = svm_vcpu_reset,
3259
3260         .prepare_guest_switch = svm_prepare_guest_switch,
3261         .vcpu_load = svm_vcpu_load,
3262         .vcpu_put = svm_vcpu_put,
3263
3264         .set_guest_debug = svm_guest_debug,
3265         .get_msr = svm_get_msr,
3266         .set_msr = svm_set_msr,
3267         .get_segment_base = svm_get_segment_base,
3268         .get_segment = svm_get_segment,
3269         .set_segment = svm_set_segment,
3270         .get_cpl = svm_get_cpl,
3271         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3272         .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3273         .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3274         .set_cr0 = svm_set_cr0,
3275         .set_cr3 = svm_set_cr3,
3276         .set_cr4 = svm_set_cr4,
3277         .set_efer = svm_set_efer,
3278         .get_idt = svm_get_idt,
3279         .set_idt = svm_set_idt,
3280         .get_gdt = svm_get_gdt,
3281         .set_gdt = svm_set_gdt,
3282         .set_dr7 = svm_set_dr7,
3283         .cache_reg = svm_cache_reg,
3284         .get_rflags = svm_get_rflags,
3285         .set_rflags = svm_set_rflags,
3286         .fpu_activate = svm_fpu_activate,
3287         .fpu_deactivate = svm_fpu_deactivate,
3288
3289         .tlb_flush = svm_flush_tlb,
3290
3291         .run = svm_vcpu_run,
3292         .handle_exit = handle_exit,
3293         .skip_emulated_instruction = skip_emulated_instruction,
3294         .set_interrupt_shadow = svm_set_interrupt_shadow,
3295         .get_interrupt_shadow = svm_get_interrupt_shadow,
3296         .patch_hypercall = svm_patch_hypercall,
3297         .set_irq = svm_set_irq,
3298         .set_nmi = svm_inject_nmi,
3299         .queue_exception = svm_queue_exception,
3300         .interrupt_allowed = svm_interrupt_allowed,
3301         .nmi_allowed = svm_nmi_allowed,
3302         .get_nmi_mask = svm_get_nmi_mask,
3303         .set_nmi_mask = svm_set_nmi_mask,
3304         .enable_nmi_window = enable_nmi_window,
3305         .enable_irq_window = enable_irq_window,
3306         .update_cr8_intercept = update_cr8_intercept,
3307
3308         .set_tss_addr = svm_set_tss_addr,
3309         .get_tdp_level = get_npt_level,
3310         .get_mt_mask = svm_get_mt_mask,
3311
3312         .exit_reasons_str = svm_exit_reasons_str,
3313         .get_lpage_level = svm_get_lpage_level,
3314
3315         .cpuid_update = svm_cpuid_update,
3316
3317         .rdtscp_supported = svm_rdtscp_supported,
3318
3319         .set_supported_cpuid = svm_set_supported_cpuid,
3320 };
3321
3322 static int __init svm_init(void)
3323 {
3324         return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3325                         __alignof__(struct vcpu_svm), THIS_MODULE);
3326 }
3327
3328 static void __exit svm_exit(void)
3329 {
3330         kvm_exit();
3331 }
3332
3333 module_init(svm_init)
3334 module_exit(svm_exit)