2 * Kernel-based Virtual Machine driver for Linux
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
34 #define PT_LEVEL_BITS PT64_LEVEL_BITS
36 #define PT_MAX_FULL_LEVELS 4
37 #define CMPXCHG cmpxchg
39 #define CMPXCHG cmpxchg64
40 #define PT_MAX_FULL_LEVELS 2
43 #define pt_element_t u32
44 #define guest_walker guest_walker32
45 #define FNAME(name) paging##32_##name
46 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
47 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
48 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
49 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
50 #define PT_LEVEL_BITS PT32_LEVEL_BITS
51 #define PT_MAX_FULL_LEVELS 2
52 #define CMPXCHG cmpxchg
54 #error Invalid PTTYPE value
57 #define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
58 #define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
61 * The guest_walker structure emulates the behavior of the hardware page
66 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
67 pt_element_t ptes[PT_MAX_FULL_LEVELS];
68 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
69 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
73 struct x86_exception fault;
76 static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
78 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
81 static int FNAME(cmpxchg_gpte)(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
82 pt_element_t __user *ptep_user, unsigned index,
83 pt_element_t orig_pte, pt_element_t new_pte)
90 npages = get_user_pages_fast((unsigned long)ptep_user, 1, 1, &page);
91 /* Check if the user is doing something meaningless. */
92 if (unlikely(npages != 1))
95 table = kmap_atomic(page, KM_USER0);
96 ret = CMPXCHG(&table[index], orig_pte, new_pte);
97 kunmap_atomic(table, KM_USER0);
99 kvm_release_page_dirty(page);
101 return (ret != orig_pte);
104 static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte,
109 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
110 if (last && !is_dirty_gpte(gpte))
111 access &= ~ACC_WRITE_MASK;
114 if (vcpu->arch.mmu.nx)
115 access &= ~(gpte >> PT64_NX_SHIFT);
120 static bool FNAME(is_last_gpte)(struct guest_walker *walker,
121 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
124 if (walker->level == PT_PAGE_TABLE_LEVEL)
127 if ((walker->level == PT_DIRECTORY_LEVEL) && is_large_pte(gpte) &&
128 (PTTYPE == 64 || is_pse(vcpu)))
131 if ((walker->level == PT_PDPE_LEVEL) && is_large_pte(gpte) &&
132 (mmu->root_level == PT64_ROOT_LEVEL))
139 * Fetch a guest pte for a guest virtual address
141 static int FNAME(walk_addr_generic)(struct guest_walker *walker,
142 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
143 gva_t addr, u32 access)
146 pt_element_t __user *uninitialized_var(ptep_user);
148 unsigned index, pt_access, uninitialized_var(pte_access);
150 bool eperm, last_gpte;
152 const int write_fault = access & PFERR_WRITE_MASK;
153 const int user_fault = access & PFERR_USER_MASK;
154 const int fetch_fault = access & PFERR_FETCH_MASK;
157 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
161 walker->level = mmu->root_level;
162 pte = mmu->get_cr3(vcpu);
165 if (walker->level == PT32E_ROOT_LEVEL) {
166 pte = mmu->get_pdptr(vcpu, (addr >> 30) & 3);
167 trace_kvm_mmu_paging_element(pte, walker->level);
168 if (!is_present_gpte(pte))
173 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
174 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
180 unsigned long host_addr;
182 index = PT_INDEX(addr, walker->level);
184 table_gfn = gpte_to_gfn(pte);
185 offset = index * sizeof(pt_element_t);
186 pte_gpa = gfn_to_gpa(table_gfn) + offset;
187 walker->table_gfn[walker->level - 1] = table_gfn;
188 walker->pte_gpa[walker->level - 1] = pte_gpa;
190 real_gfn = mmu->translate_gpa(vcpu, gfn_to_gpa(table_gfn),
191 PFERR_USER_MASK|PFERR_WRITE_MASK);
192 if (unlikely(real_gfn == UNMAPPED_GVA))
194 real_gfn = gpa_to_gfn(real_gfn);
196 host_addr = gfn_to_hva(vcpu->kvm, real_gfn);
197 if (unlikely(kvm_is_error_hva(host_addr)))
200 ptep_user = (pt_element_t __user *)((void *)host_addr + offset);
201 if (unlikely(__copy_from_user(&pte, ptep_user, sizeof(pte))))
204 trace_kvm_mmu_paging_element(pte, walker->level);
206 if (unlikely(!is_present_gpte(pte)))
209 if (unlikely(is_rsvd_bits_set(&vcpu->arch.mmu, pte,
211 errcode |= PFERR_RSVD_MASK | PFERR_PRESENT_MASK;
215 if (!check_write_user_access(vcpu, write_fault, user_fault,
220 if (unlikely(fetch_fault && (pte & PT64_NX_MASK)))
224 last_gpte = FNAME(is_last_gpte)(walker, vcpu, mmu, pte);
226 pte_access = pt_access &
227 FNAME(gpte_access)(vcpu, pte, true);
228 /* check if the kernel is fetching from user page */
229 if (unlikely(pte_access & PT_USER_MASK) &&
230 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP))
231 if (fetch_fault && !user_fault)
235 if (!eperm && unlikely(!(pte & PT_ACCESSED_MASK))) {
237 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
239 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index,
240 pte, pte|PT_ACCESSED_MASK);
241 if (unlikely(ret < 0))
246 mark_page_dirty(vcpu->kvm, table_gfn);
247 pte |= PT_ACCESSED_MASK;
250 walker->ptes[walker->level - 1] = pte;
253 int lvl = walker->level;
258 gfn = gpte_to_gfn_lvl(pte, lvl);
259 gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT;
262 walker->level == PT_DIRECTORY_LEVEL &&
264 gfn += pse36_gfn_delta(pte);
266 ac = write_fault | fetch_fault | user_fault;
268 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn),
270 if (real_gpa == UNMAPPED_GVA)
273 walker->gfn = real_gpa >> PAGE_SHIFT;
278 pt_access &= FNAME(gpte_access)(vcpu, pte, false);
282 if (unlikely(eperm)) {
283 errcode |= PFERR_PRESENT_MASK;
287 if (write_fault && unlikely(!is_dirty_gpte(pte))) {
290 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
291 ret = FNAME(cmpxchg_gpte)(vcpu, mmu, ptep_user, index,
292 pte, pte|PT_DIRTY_MASK);
293 if (unlikely(ret < 0))
298 mark_page_dirty(vcpu->kvm, table_gfn);
299 pte |= PT_DIRTY_MASK;
300 walker->ptes[walker->level - 1] = pte;
303 walker->pt_access = pt_access;
304 walker->pte_access = pte_access;
305 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
306 __func__, (u64)pte, pte_access, pt_access);
310 errcode |= write_fault | user_fault;
311 if (fetch_fault && (mmu->nx ||
312 kvm_read_cr4_bits(vcpu, X86_CR4_SMEP)))
313 errcode |= PFERR_FETCH_MASK;
315 walker->fault.vector = PF_VECTOR;
316 walker->fault.error_code_valid = true;
317 walker->fault.error_code = errcode;
318 walker->fault.address = addr;
319 walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
321 trace_kvm_mmu_walker_error(walker->fault.error_code);
325 static int FNAME(walk_addr)(struct guest_walker *walker,
326 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
328 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
332 static int FNAME(walk_addr_nested)(struct guest_walker *walker,
333 struct kvm_vcpu *vcpu, gva_t addr,
336 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
340 static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
341 struct kvm_mmu_page *sp, u64 *spte,
344 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
347 if (!is_present_gpte(gpte))
350 if (!(gpte & PT_ACCESSED_MASK))
356 drop_spte(vcpu->kvm, spte);
360 static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
361 u64 *spte, const void *pte)
367 gpte = *(const pt_element_t *)pte;
368 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
371 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
372 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte, true);
373 pfn = gfn_to_pfn_atomic(vcpu->kvm, gpte_to_gfn(gpte));
374 if (mmu_invalid_pfn(pfn)) {
375 kvm_release_pfn_clean(pfn);
380 * we call mmu_set_spte() with host_writable = true because that
381 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
383 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
384 NULL, PT_PAGE_TABLE_LEVEL,
385 gpte_to_gfn(gpte), pfn, true, true);
388 static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
389 struct guest_walker *gw, int level)
391 pt_element_t curr_pte;
392 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
396 if (level == PT_PAGE_TABLE_LEVEL) {
397 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
398 base_gpa = pte_gpa & ~mask;
399 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
401 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
402 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
403 curr_pte = gw->prefetch_ptes[index];
405 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
406 &curr_pte, sizeof(curr_pte));
408 return r || curr_pte != gw->ptes[level - 1];
411 static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
414 struct kvm_mmu_page *sp;
415 pt_element_t *gptep = gw->prefetch_ptes;
419 sp = page_header(__pa(sptep));
421 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
425 return __direct_pte_prefetch(vcpu, sp, sptep);
427 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
430 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
439 if (is_shadow_present_pte(*spte))
444 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
447 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte,
449 gfn = gpte_to_gfn(gpte);
450 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
451 pte_access & ACC_WRITE_MASK);
452 if (mmu_invalid_pfn(pfn)) {
453 kvm_release_pfn_clean(pfn);
457 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
458 NULL, PT_PAGE_TABLE_LEVEL, gfn,
464 * Fetch a shadow pte for a specific level in the paging hierarchy.
466 static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
467 struct guest_walker *gw,
468 int user_fault, int write_fault, int hlevel,
469 int *emulate, pfn_t pfn, bool map_writable,
472 unsigned access = gw->pt_access;
473 struct kvm_mmu_page *sp = NULL;
475 unsigned direct_access;
476 struct kvm_shadow_walk_iterator it;
478 if (!is_present_gpte(gw->ptes[gw->level - 1]))
481 direct_access = gw->pte_access;
483 top_level = vcpu->arch.mmu.root_level;
484 if (top_level == PT32E_ROOT_LEVEL)
485 top_level = PT32_ROOT_LEVEL;
487 * Verify that the top-level gpte is still there. Since the page
488 * is a root page, it is either write protected (and cannot be
489 * changed from now on) or it is invalid (in which case, we don't
490 * really care if it changes underneath us after this point).
492 if (FNAME(gpte_changed)(vcpu, gw, top_level))
493 goto out_gpte_changed;
495 for (shadow_walk_init(&it, vcpu, addr);
496 shadow_walk_okay(&it) && it.level > gw->level;
497 shadow_walk_next(&it)) {
500 drop_large_spte(vcpu, it.sptep);
503 if (!is_shadow_present_pte(*it.sptep)) {
504 table_gfn = gw->table_gfn[it.level - 2];
505 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
506 false, access, it.sptep);
510 * Verify that the gpte in the page we've just write
511 * protected is still there.
513 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
514 goto out_gpte_changed;
517 link_shadow_page(it.sptep, sp);
521 shadow_walk_okay(&it) && it.level > hlevel;
522 shadow_walk_next(&it)) {
525 validate_direct_spte(vcpu, it.sptep, direct_access);
527 drop_large_spte(vcpu, it.sptep);
529 if (is_shadow_present_pte(*it.sptep))
532 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
534 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
535 true, direct_access, it.sptep);
536 link_shadow_page(it.sptep, sp);
539 mmu_set_spte(vcpu, it.sptep, access, gw->pte_access,
540 user_fault, write_fault, emulate, it.level,
541 gw->gfn, pfn, prefault, map_writable);
542 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
548 kvm_mmu_put_page(sp, it.sptep);
549 kvm_release_pfn_clean(pfn);
554 * Page fault handler. There are several causes for a page fault:
555 * - there is no shadow pte for the guest pte
556 * - write access through a shadow pte marked read only so that we can set
558 * - write access to a shadow pte marked read only so we can update the page
559 * dirty bitmap, when userspace requests it
560 * - mmio access; in this case we will never install a present shadow pte
561 * - normal guest page fault due to the guest pte marked not present, not
562 * writable, or not executable
564 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
565 * a negative value on error.
567 static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
570 int write_fault = error_code & PFERR_WRITE_MASK;
571 int user_fault = error_code & PFERR_USER_MASK;
572 struct guest_walker walker;
577 int level = PT_PAGE_TABLE_LEVEL;
579 unsigned long mmu_seq;
582 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
584 if (unlikely(error_code & PFERR_RSVD_MASK))
585 return handle_mmio_page_fault(vcpu, addr, error_code,
586 mmu_is_nested(vcpu));
588 r = mmu_topup_memory_caches(vcpu);
593 * Look up the guest pte for the faulting address.
595 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
598 * The page is not mapped by the guest. Let the guest handle it.
601 pgprintk("%s: guest page fault\n", __func__);
603 inject_page_fault(vcpu, &walker.fault);
604 /* reset fork detector */
605 vcpu->arch.last_pt_write_count = 0;
610 if (walker.level >= PT_DIRECTORY_LEVEL)
611 force_pt_level = mapping_level_dirty_bitmap(vcpu, walker.gfn);
614 if (!force_pt_level) {
615 level = min(walker.level, mapping_level(vcpu, walker.gfn));
616 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
619 mmu_seq = vcpu->kvm->mmu_notifier_seq;
622 if (try_async_pf(vcpu, prefault, walker.gfn, addr, &pfn, write_fault,
626 if (handle_abnormal_pfn(vcpu, mmu_is_nested(vcpu) ? 0 : addr,
627 walker.gfn, pfn, walker.pte_access, &r))
630 spin_lock(&vcpu->kvm->mmu_lock);
631 if (mmu_notifier_retry(vcpu, mmu_seq))
634 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
635 kvm_mmu_free_some_pages(vcpu);
637 transparent_hugepage_adjust(vcpu, &walker.gfn, &pfn, &level);
638 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
639 level, &emulate, pfn, map_writable, prefault);
641 pgprintk("%s: shadow pte %p %llx emulate %d\n", __func__,
642 sptep, *sptep, emulate);
645 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
647 ++vcpu->stat.pf_fixed;
648 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
649 spin_unlock(&vcpu->kvm->mmu_lock);
654 spin_unlock(&vcpu->kvm->mmu_lock);
655 kvm_release_pfn_clean(pfn);
659 static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
661 struct kvm_shadow_walk_iterator iterator;
662 struct kvm_mmu_page *sp;
668 vcpu_clear_mmio_info(vcpu, gva);
670 spin_lock(&vcpu->kvm->mmu_lock);
672 for_each_shadow_entry(vcpu, gva, iterator) {
673 level = iterator.level;
674 sptep = iterator.sptep;
676 sp = page_header(__pa(sptep));
677 if (is_last_spte(*sptep, level)) {
684 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
685 offset = sp->role.quadrant << shift;
687 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
688 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
690 if (is_shadow_present_pte(*sptep)) {
691 if (is_large_pte(*sptep))
692 --vcpu->kvm->stat.lpages;
693 drop_spte(vcpu->kvm, sptep);
695 } else if (is_mmio_spte(*sptep))
696 mmu_spte_clear_no_track(sptep);
701 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
706 kvm_flush_remote_tlbs(vcpu->kvm);
708 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
710 spin_unlock(&vcpu->kvm->mmu_lock);
715 if (mmu_topup_memory_caches(vcpu))
717 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
720 static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
721 struct x86_exception *exception)
723 struct guest_walker walker;
724 gpa_t gpa = UNMAPPED_GVA;
727 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
730 gpa = gfn_to_gpa(walker.gfn);
731 gpa |= vaddr & ~PAGE_MASK;
732 } else if (exception)
733 *exception = walker.fault;
738 static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
740 struct x86_exception *exception)
742 struct guest_walker walker;
743 gpa_t gpa = UNMAPPED_GVA;
746 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
749 gpa = gfn_to_gpa(walker.gfn);
750 gpa |= vaddr & ~PAGE_MASK;
751 } else if (exception)
752 *exception = walker.fault;
758 * Using the cached information from sp->gfns is safe because:
759 * - The spte has a reference to the struct page, so the pfn for a given gfn
760 * can't change unless all sptes pointing to it are nuked first.
763 * We should flush all tlbs if spte is dropped even though guest is
764 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
765 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
766 * used by guest then tlbs are not flushed, so guest is allowed to access the
768 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
770 static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
772 int i, offset, nr_present;
776 offset = nr_present = 0;
778 /* direct kvm_mmu_page can not be unsync. */
779 BUG_ON(sp->role.direct);
782 offset = sp->role.quadrant << PT64_LEVEL_BITS;
784 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
786 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
795 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
797 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
798 sizeof(pt_element_t)))
801 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
802 vcpu->kvm->tlbs_dirty++;
806 gfn = gpte_to_gfn(gpte);
807 pte_access = sp->role.access;
808 pte_access &= FNAME(gpte_access)(vcpu, gpte, true);
810 if (sync_mmio_spte(&sp->spt[i], gfn, pte_access, &nr_present))
813 if (gfn != sp->gfns[i]) {
814 drop_spte(vcpu->kvm, &sp->spt[i]);
815 vcpu->kvm->tlbs_dirty++;
821 host_writable = sp->spt[i] & SPTE_HOST_WRITEABLE;
823 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
824 PT_PAGE_TABLE_LEVEL, gfn,
825 spte_to_pfn(sp->spt[i]), true, false,
835 #undef PT_BASE_ADDR_MASK
837 #undef PT_LVL_ADDR_MASK
838 #undef PT_LVL_OFFSET_MASK
840 #undef PT_MAX_FULL_LEVELS
842 #undef gpte_to_gfn_lvl