arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affilates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/atomic.h>
  37 #include "kvm_cache_regs.h"
  38 #include "irq.h"
  39 #include "trace.h"
  40 #include "x86.h"
  41
  42 #ifndef CONFIG_X86_64
  43 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  44 #else
  45 #define mod_64(x, y) ((x) % (y))
  46 #endif
  47
  48 #define PRId64 "d"
  49 #define PRIx64 "llx"
  50 #define PRIu64 "u"
  51 #define PRIo64 "o"
  52
  53 #define APIC_BUS_CYCLE_NS 1
  54
  55 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  56 #define apic_debug(fmt, arg...)
  57
  58 #define APIC_LVT_NUM                    6
  59 /* 14 is the version for Xeon and Pentium 8.4.8*/
  60 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  61 #define LAPIC_MMIO_LENGTH               (1 << 12)
  62 /* followed define is not in apicdef.h */
  63 #define APIC_SHORT_MASK                 0xc0000
  64 #define APIC_DEST_NOSHORT               0x0
  65 #define APIC_DEST_MASK                  0x800
  66 #define MAX_APIC_VECTOR                 256
  67
  68 #define VEC_POS(v) ((v) & (32 - 1))
  69 #define REG_POS(v) (((v) >> 5) << 4)
  70
  71 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  72 {
  73         return *((u32 *) (apic->regs + reg_off));
  74 }
  75
  76 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  77 {
  78         *((u32 *) (apic->regs + reg_off)) = val;
  79 }
  80
  81 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  82 {
  83         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  84 }
  85
  86 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  87 {
  88         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  89 }
  90
  91 static inline void apic_set_vector(int vec, void *bitmap)
  92 {
  93         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  94 }
  95
  96 static inline void apic_clear_vector(int vec, void *bitmap)
  97 {
  98         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  99 }
 100
 101 static inline int apic_hw_enabled(struct kvm_lapic *apic)
 102 {
 103         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 104 }
 105
 106 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
 107 {
 108         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 109 }
 110
 111 static inline int apic_enabled(struct kvm_lapic *apic)
 112 {
 113         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 114 }
 115
 116 #define LVT_MASK        \
 117         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 118
 119 #define LINT_MASK       \
 120         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 121          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 122
 123 static inline int kvm_apic_id(struct kvm_lapic *apic)
 124 {
 125         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 126 }
 127
 128 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 129 {
 130         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 131 }
 132
 133 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 134 {
 135         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 136 }
 137
 138 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 139 {
 140         return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
 141 }
 142
 143 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 144 {
 145         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 146 }
 147
 148 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 149 {
 150         struct kvm_lapic *apic = vcpu->arch.apic;
 151         struct kvm_cpuid_entry2 *feat;
 152         u32 v = APIC_VERSION;
 153
 154         if (!irqchip_in_kernel(vcpu->kvm))
 155                 return;
 156
 157         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 158         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 159                 v |= APIC_LVR_DIRECTED_EOI;
 160         apic_set_reg(apic, APIC_LVR, v);
 161 }
 162
 163 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
 164 {
 165         return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
 166 }
 167
 168 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 169         LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
 170         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 171         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 172         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 173         LVT_MASK                /* LVTERR */
 174 };
 175
 176 static int find_highest_vector(void *bitmap)
 177 {
 178         u32 *word = bitmap;
 179         int word_offset = MAX_APIC_VECTOR >> 5;
 180
 181         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 182                 continue;
 183
 184         if (likely(!word_offset && !word[0]))
 185                 return -1;
 186         else
 187                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 188 }
 189
 190 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 191 {
 192         apic->irr_pending = true;
 193         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 194 }
 195
 196 static inline int apic_search_irr(struct kvm_lapic *apic)
 197 {
 198         return find_highest_vector(apic->regs + APIC_IRR);
 199 }
 200
 201 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 202 {
 203         int result;
 204
 205         if (!apic->irr_pending)
 206                 return -1;
 207
 208         result = apic_search_irr(apic);
 209         ASSERT(result == -1 || result >= 16);
 210
 211         return result;
 212 }
 213
 214 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 215 {
 216         apic->irr_pending = false;
 217         apic_clear_vector(vec, apic->regs + APIC_IRR);
 218         if (apic_search_irr(apic) != -1)
 219                 apic->irr_pending = true;
 220 }
 221
 222 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 223 {
 224         struct kvm_lapic *apic = vcpu->arch.apic;
 225         int highest_irr;
 226
 227         /* This may race with setting of irr in __apic_accept_irq() and
 228          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 229          * will cause vmexit immediately and the value will be recalculated
 230          * on the next vmentry.
 231          */
 232         if (!apic)
 233                 return 0;
 234         highest_irr = apic_find_highest_irr(apic);
 235
 236         return highest_irr;
 237 }
 238
 239 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 240                              int vector, int level, int trig_mode);
 241
 242 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
 243 {
 244         struct kvm_lapic *apic = vcpu->arch.apic;
 245
 246         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 247                         irq->level, irq->trig_mode);
 248 }
 249
 250 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 251 {
 252         int result;
 253
 254         result = find_highest_vector(apic->regs + APIC_ISR);
 255         ASSERT(result == -1 || result >= 16);
 256
 257         return result;
 258 }
 259
 260 static void apic_update_ppr(struct kvm_lapic *apic)
 261 {
 262         u32 tpr, isrv, ppr;
 263         int isr;
 264
 265         tpr = apic_get_reg(apic, APIC_TASKPRI);
 266         isr = apic_find_highest_isr(apic);
 267         isrv = (isr != -1) ? isr : 0;
 268
 269         if ((tpr & 0xf0) >= (isrv & 0xf0))
 270                 ppr = tpr & 0xff;
 271         else
 272                 ppr = isrv & 0xf0;
 273
 274         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 275                    apic, ppr, isr, isrv);
 276
 277         apic_set_reg(apic, APIC_PROCPRI, ppr);
 278 }
 279
 280 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 281 {
 282         apic_set_reg(apic, APIC_TASKPRI, tpr);
 283         apic_update_ppr(apic);
 284 }
 285
 286 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 287 {
 288         return dest == 0xff || kvm_apic_id(apic) == dest;
 289 }
 290
 291 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 292 {
 293         int result = 0;
 294         u32 logical_id;
 295
 296         if (apic_x2apic_mode(apic)) {
 297                 logical_id = apic_get_reg(apic, APIC_LDR);
 298                 return logical_id & mda;
 299         }
 300
 301         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 302
 303         switch (apic_get_reg(apic, APIC_DFR)) {
 304         case APIC_DFR_FLAT:
 305                 if (logical_id & mda)
 306                         result = 1;
 307                 break;
 308         case APIC_DFR_CLUSTER:
 309                 if (((logical_id >> 4) == (mda >> 0x4))
 310                     && (logical_id & mda & 0xf))
 311                         result = 1;
 312                 break;
 313         default:
 314                 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
 315                        apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 316                 break;
 317         }
 318
 319         return result;
 320 }
 321
 322 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 323                            int short_hand, int dest, int dest_mode)
 324 {
 325         int result = 0;
 326         struct kvm_lapic *target = vcpu->arch.apic;
 327
 328         apic_debug("target %p, source %p, dest 0x%x, "
 329                    "dest_mode 0x%x, short_hand 0x%x\n",
 330                    target, source, dest, dest_mode, short_hand);
 331
 332         ASSERT(target);
 333         switch (short_hand) {
 334         case APIC_DEST_NOSHORT:
 335                 if (dest_mode == 0)
 336                         /* Physical mode. */
 337                         result = kvm_apic_match_physical_addr(target, dest);
 338                 else
 339                         /* Logical mode. */
 340                         result = kvm_apic_match_logical_addr(target, dest);
 341                 break;
 342         case APIC_DEST_SELF:
 343                 result = (target == source);
 344                 break;
 345         case APIC_DEST_ALLINC:
 346                 result = 1;
 347                 break;
 348         case APIC_DEST_ALLBUT:
 349                 result = (target != source);
 350                 break;
 351         default:
 352                 printk(KERN_WARNING "Bad dest shorthand value %x\n",
 353                        short_hand);
 354                 break;
 355         }
 356
 357         return result;
 358 }
 359
 360 /*
 361  * Add a pending IRQ into lapic.
 362  * Return 1 if successfully added and 0 if discarded.
 363  */
 364 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 365                              int vector, int level, int trig_mode)
 366 {
 367         int result = 0;
 368         struct kvm_vcpu *vcpu = apic->vcpu;
 369
 370         switch (delivery_mode) {
 371         case APIC_DM_LOWEST:
 372                 vcpu->arch.apic_arb_prio++;
 373         case APIC_DM_FIXED:
 374                 /* FIXME add logic for vcpu on reset */
 375                 if (unlikely(!apic_enabled(apic)))
 376                         break;
 377
 378                 if (trig_mode) {
 379                         apic_debug("level trig mode for vector %d", vector);
 380                         apic_set_vector(vector, apic->regs + APIC_TMR);
 381                 } else
 382                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 383
 384                 result = !apic_test_and_set_irr(vector, apic);
 385                 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 386                                           trig_mode, vector, !result);
 387                 if (!result) {
 388                         if (trig_mode)
 389                                 apic_debug("level trig mode repeatedly for "
 390                                                 "vector %d", vector);
 391                         break;
 392                 }
 393
 394                 kvm_vcpu_kick(vcpu);
 395                 break;
 396
 397         case APIC_DM_REMRD:
 398                 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
 399                 break;
 400
 401         case APIC_DM_SMI:
 402                 printk(KERN_DEBUG "Ignoring guest SMI\n");
 403                 break;
 404
 405         case APIC_DM_NMI:
 406                 result = 1;
 407                 kvm_inject_nmi(vcpu);
 408                 kvm_vcpu_kick(vcpu);
 409                 break;
 410
 411         case APIC_DM_INIT:
 412                 if (level) {
 413                         result = 1;
 414                         if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
 415                                 printk(KERN_DEBUG
 416                                        "INIT on a runnable vcpu %d\n",
 417                                        vcpu->vcpu_id);
 418                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 419                         kvm_vcpu_kick(vcpu);
 420                 } else {
 421                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 422                                    vcpu->vcpu_id);
 423                 }
 424                 break;
 425
 426         case APIC_DM_STARTUP:
 427                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 428                            vcpu->vcpu_id, vector);
 429                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 430                         result = 1;
 431                         vcpu->arch.sipi_vector = vector;
 432                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 433                         kvm_vcpu_kick(vcpu);
 434                 }
 435                 break;
 436
 437         case APIC_DM_EXTINT:
 438                 /*
 439                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 440                  * before NMI watchdog was enabled. Already handled by
 441                  * kvm_apic_accept_pic_intr().
 442                  */
 443                 break;
 444
 445         default:
 446                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 447                        delivery_mode);
 448                 break;
 449         }
 450         return result;
 451 }
 452
 453 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 454 {
 455         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 456 }
 457
 458 static void apic_set_eoi(struct kvm_lapic *apic)
 459 {
 460         int vector = apic_find_highest_isr(apic);
 461         int trigger_mode;
 462         /*
 463          * Not every write EOI will has corresponding ISR,
 464          * one example is when Kernel check timer on setup_IO_APIC
 465          */
 466         if (vector == -1)
 467                 return;
 468
 469         apic_clear_vector(vector, apic->regs + APIC_ISR);
 470         apic_update_ppr(apic);
 471
 472         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
 473                 trigger_mode = IOAPIC_LEVEL_TRIG;
 474         else
 475                 trigger_mode = IOAPIC_EDGE_TRIG;
 476         if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
 477                 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 478 }
 479
 480 static void apic_send_ipi(struct kvm_lapic *apic)
 481 {
 482         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 483         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 484         struct kvm_lapic_irq irq;
 485
 486         irq.vector = icr_low & APIC_VECTOR_MASK;
 487         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 488         irq.dest_mode = icr_low & APIC_DEST_MASK;
 489         irq.level = icr_low & APIC_INT_ASSERT;
 490         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 491         irq.shorthand = icr_low & APIC_SHORT_MASK;
 492         if (apic_x2apic_mode(apic))
 493                 irq.dest_id = icr_high;
 494         else
 495                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 496
 497         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 498
 499         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 500                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 501                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 502                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 503                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 504                    irq.vector);
 505
 506         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
 507 }
 508
 509 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 510 {
 511         ktime_t remaining;
 512         s64 ns;
 513         u32 tmcct;
 514
 515         ASSERT(apic != NULL);
 516
 517         /* if initial count is 0, current count should also be 0 */
 518         if (apic_get_reg(apic, APIC_TMICT) == 0)
 519                 return 0;
 520
 521         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 522         if (ktime_to_ns(remaining) < 0)
 523                 remaining = ktime_set(0, 0);
 524
 525         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 526         tmcct = div64_u64(ns,
 527                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 528
 529         return tmcct;
 530 }
 531
 532 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 533 {
 534         struct kvm_vcpu *vcpu = apic->vcpu;
 535         struct kvm_run *run = vcpu->run;
 536
 537         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 538         run->tpr_access.rip = kvm_rip_read(vcpu);
 539         run->tpr_access.is_write = write;
 540 }
 541
 542 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 543 {
 544         if (apic->vcpu->arch.tpr_access_reporting)
 545                 __report_tpr_access(apic, write);
 546 }
 547
 548 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 549 {
 550         u32 val = 0;
 551
 552         if (offset >= LAPIC_MMIO_LENGTH)
 553                 return 0;
 554
 555         switch (offset) {
 556         case APIC_ID:
 557                 if (apic_x2apic_mode(apic))
 558                         val = kvm_apic_id(apic);
 559                 else
 560                         val = kvm_apic_id(apic) << 24;
 561                 break;
 562         case APIC_ARBPRI:
 563                 printk(KERN_WARNING "Access APIC ARBPRI register "
 564                        "which is for P6\n");
 565                 break;
 566
 567         case APIC_TMCCT:        /* Timer CCR */
 568                 val = apic_get_tmcct(apic);
 569                 break;
 570
 571         case APIC_TASKPRI:
 572                 report_tpr_access(apic, false);
 573                 /* fall thru */
 574         default:
 575                 apic_update_ppr(apic);
 576                 val = apic_get_reg(apic, offset);
 577                 break;
 578         }
 579
 580         return val;
 581 }
 582
 583 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 584 {
 585         return container_of(dev, struct kvm_lapic, dev);
 586 }
 587
 588 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 589                 void *data)
 590 {
 591         unsigned char alignment = offset & 0xf;
 592         u32 result;
 593         /* this bitmask has a bit cleared for each reserver register */
 594         static const u64 rmask = 0x43ff01ffffffe70cULL;
 595
 596         if ((alignment + len) > 4) {
 597                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 598                            offset, len);
 599                 return 1;
 600         }
 601
 602         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
 603                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
 604                            offset);
 605                 return 1;
 606         }
 607
 608         result = __apic_read(apic, offset & ~0xf);
 609
 610         trace_kvm_apic_read(offset, result);
 611
 612         switch (len) {
 613         case 1:
 614         case 2:
 615         case 4:
 616                 memcpy(data, (char *)&result + alignment, len);
 617                 break;
 618         default:
 619                 printk(KERN_ERR "Local APIC read with len = %x, "
 620                        "should be 1,2, or 4 instead\n", len);
 621                 break;
 622         }
 623         return 0;
 624 }
 625
 626 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
 627 {
 628         return apic_hw_enabled(apic) &&
 629             addr >= apic->base_address &&
 630             addr < apic->base_address + LAPIC_MMIO_LENGTH;
 631 }
 632
 633 static int apic_mmio_read(struct kvm_io_device *this,
 634                            gpa_t address, int len, void *data)
 635 {
 636         struct kvm_lapic *apic = to_lapic(this);
 637         u32 offset = address - apic->base_address;
 638
 639         if (!apic_mmio_in_range(apic, address))
 640                 return -EOPNOTSUPP;
 641
 642         apic_reg_read(apic, offset, len, data);
 643
 644         return 0;
 645 }
 646
 647 static void update_divide_count(struct kvm_lapic *apic)
 648 {
 649         u32 tmp1, tmp2, tdcr;
 650
 651         tdcr = apic_get_reg(apic, APIC_TDCR);
 652         tmp1 = tdcr & 0xf;
 653         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 654         apic->divide_count = 0x1 << (tmp2 & 0x7);
 655
 656         apic_debug("timer divide count is 0x%x\n",
 657                                    apic->divide_count);
 658 }
 659
 660 static void start_apic_timer(struct kvm_lapic *apic)
 661 {
 662         ktime_t now = apic->lapic_timer.timer.base->get_time();
 663
 664         apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) *
 665                     APIC_BUS_CYCLE_NS * apic->divide_count;
 666         atomic_set(&apic->lapic_timer.pending, 0);
 667
 668         if (!apic->lapic_timer.period)
 669                 return;
 670         /*
 671          * Do not allow the guest to program periodic timers with small
 672          * interval, since the hrtimers are not throttled by the host
 673          * scheduler.
 674          */
 675         if (apic_lvtt_period(apic)) {
 676                 if (apic->lapic_timer.period < NSEC_PER_MSEC/2)
 677                         apic->lapic_timer.period = NSEC_PER_MSEC/2;
 678         }
 679
 680         hrtimer_start(&apic->lapic_timer.timer,
 681                       ktime_add_ns(now, apic->lapic_timer.period),
 682                       HRTIMER_MODE_ABS);
 683
 684         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 685                            PRIx64 ", "
 686                            "timer initial count 0x%x, period %lldns, "
 687                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 688                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 689                            apic_get_reg(apic, APIC_TMICT),
 690                            apic->lapic_timer.period,
 691                            ktime_to_ns(ktime_add_ns(now,
 692                                         apic->lapic_timer.period)));
 693 }
 694
 695 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 696 {
 697         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
 698
 699         if (apic_lvt_nmi_mode(lvt0_val)) {
 700                 if (!nmi_wd_enabled) {
 701                         apic_debug("Receive NMI setting on APIC_LVT0 "
 702                                    "for cpu %d\n", apic->vcpu->vcpu_id);
 703                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
 704                 }
 705         } else if (nmi_wd_enabled)
 706                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
 707 }
 708
 709 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 710 {
 711         int ret = 0;
 712
 713         trace_kvm_apic_write(reg, val);
 714
 715         switch (reg) {
 716         case APIC_ID:           /* Local APIC ID */
 717                 if (!apic_x2apic_mode(apic))
 718                         apic_set_reg(apic, APIC_ID, val);
 719                 else
 720                         ret = 1;
 721                 break;
 722
 723         case APIC_TASKPRI:
 724                 report_tpr_access(apic, true);
 725                 apic_set_tpr(apic, val & 0xff);
 726                 break;
 727
 728         case APIC_EOI:
 729                 apic_set_eoi(apic);
 730                 break;
 731
 732         case APIC_LDR:
 733                 if (!apic_x2apic_mode(apic))
 734                         apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 735                 else
 736                         ret = 1;
 737                 break;
 738
 739         case APIC_DFR:
 740                 if (!apic_x2apic_mode(apic))
 741                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 742                 else
 743                         ret = 1;
 744                 break;
 745
 746         case APIC_SPIV: {
 747                 u32 mask = 0x3ff;
 748                 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
 749                         mask |= APIC_SPIV_DIRECTED_EOI;
 750                 apic_set_reg(apic, APIC_SPIV, val & mask);
 751                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 752                         int i;
 753                         u32 lvt_val;
 754
 755                         for (i = 0; i < APIC_LVT_NUM; i++) {
 756                                 lvt_val = apic_get_reg(apic,
 757                                                        APIC_LVTT + 0x10 * i);
 758                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 759                                              lvt_val | APIC_LVT_MASKED);
 760                         }
 761                         atomic_set(&apic->lapic_timer.pending, 0);
 762
 763                 }
 764                 break;
 765         }
 766         case APIC_ICR:
 767                 /* No delay here, so we always clear the pending bit */
 768                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 769                 apic_send_ipi(apic);
 770                 break;
 771
 772         case APIC_ICR2:
 773                 if (!apic_x2apic_mode(apic))
 774                         val &= 0xff000000;
 775                 apic_set_reg(apic, APIC_ICR2, val);
 776                 break;
 777
 778         case APIC_LVT0:
 779                 apic_manage_nmi_watchdog(apic, val);
 780         case APIC_LVTT:
 781         case APIC_LVTTHMR:
 782         case APIC_LVTPC:
 783         case APIC_LVT1:
 784         case APIC_LVTERR:
 785                 /* TODO: Check vector */
 786                 if (!apic_sw_enabled(apic))
 787                         val |= APIC_LVT_MASKED;
 788
 789                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
 790                 apic_set_reg(apic, reg, val);
 791
 792                 break;
 793
 794         case APIC_TMICT:
 795                 hrtimer_cancel(&apic->lapic_timer.timer);
 796                 apic_set_reg(apic, APIC_TMICT, val);
 797                 start_apic_timer(apic);
 798                 break;
 799
 800         case APIC_TDCR:
 801                 if (val & 4)
 802                         printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
 803                 apic_set_reg(apic, APIC_TDCR, val);
 804                 update_divide_count(apic);
 805                 break;
 806
 807         case APIC_ESR:
 808                 if (apic_x2apic_mode(apic) && val != 0) {
 809                         printk(KERN_ERR "KVM_WRITE:ESR not zero %x\n", val);
 810                         ret = 1;
 811                 }
 812                 break;
 813
 814         case APIC_SELF_IPI:
 815                 if (apic_x2apic_mode(apic)) {
 816                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
 817                 } else
 818                         ret = 1;
 819                 break;
 820         default:
 821                 ret = 1;
 822                 break;
 823         }
 824         if (ret)
 825                 apic_debug("Local APIC Write to read-only register %x\n", reg);
 826         return ret;
 827 }
 828
 829 static int apic_mmio_write(struct kvm_io_device *this,
 830                             gpa_t address, int len, const void *data)
 831 {
 832         struct kvm_lapic *apic = to_lapic(this);
 833         unsigned int offset = address - apic->base_address;
 834         u32 val;
 835
 836         if (!apic_mmio_in_range(apic, address))
 837                 return -EOPNOTSUPP;
 838
 839         /*
 840          * APIC register must be aligned on 128-bits boundary.
 841          * 32/64/128 bits registers must be accessed thru 32 bits.
 842          * Refer SDM 8.4.1
 843          */
 844         if (len != 4 || (offset & 0xf)) {
 845                 /* Don't shout loud, $infamous_os would cause only noise. */
 846                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
 847                 return 0;
 848         }
 849
 850         val = *(u32*)data;
 851
 852         /* too common printing */
 853         if (offset != APIC_EOI)
 854                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
 855                            "0x%x\n", __func__, offset, len, val);
 856
 857         apic_reg_write(apic, offset & 0xff0, val);
 858
 859         return 0;
 860 }
 861
 862 void kvm_free_lapic(struct kvm_vcpu *vcpu)
 863 {
 864         if (!vcpu->arch.apic)
 865                 return;
 866
 867         hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
 868
 869         if (vcpu->arch.apic->regs_page)
 870                 __free_page(vcpu->arch.apic->regs_page);
 871
 872         kfree(vcpu->arch.apic);
 873 }
 874
 875 /*
 876  *----------------------------------------------------------------------
 877  * LAPIC interface
 878  *----------------------------------------------------------------------
 879  */
 880
 881 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
 882 {
 883         struct kvm_lapic *apic = vcpu->arch.apic;
 884
 885         if (!apic)
 886                 return;
 887         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
 888                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 889 }
 890
 891 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 892 {
 893         struct kvm_lapic *apic = vcpu->arch.apic;
 894         u64 tpr;
 895
 896         if (!apic)
 897                 return 0;
 898         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
 899
 900         return (tpr & 0xf0) >> 4;
 901 }
 902
 903 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 904 {
 905         struct kvm_lapic *apic = vcpu->arch.apic;
 906
 907         if (!apic) {
 908                 value |= MSR_IA32_APICBASE_BSP;
 909                 vcpu->arch.apic_base = value;
 910                 return;
 911         }
 912
 913         if (!kvm_vcpu_is_bsp(apic->vcpu))
 914                 value &= ~MSR_IA32_APICBASE_BSP;
 915
 916         vcpu->arch.apic_base = value;
 917         if (apic_x2apic_mode(apic)) {
 918                 u32 id = kvm_apic_id(apic);
 919                 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
 920                 apic_set_reg(apic, APIC_LDR, ldr);
 921         }
 922         apic->base_address = apic->vcpu->arch.apic_base &
 923                              MSR_IA32_APICBASE_BASE;
 924
 925         /* with FSB delivery interrupt, we can restart APIC functionality */
 926         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
 927                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
 928
 929 }
 930
 931 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 932 {
 933         struct kvm_lapic *apic;
 934         int i;
 935
 936         apic_debug("%s\n", __func__);
 937
 938         ASSERT(vcpu);
 939         apic = vcpu->arch.apic;
 940         ASSERT(apic != NULL);
 941
 942         /* Stop the timer in case it's a reset to an active apic */
 943         hrtimer_cancel(&apic->lapic_timer.timer);
 944
 945         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
 946         kvm_apic_set_version(apic->vcpu);
 947
 948         for (i = 0; i < APIC_LVT_NUM; i++)
 949                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
 950         apic_set_reg(apic, APIC_LVT0,
 951                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 952
 953         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
 954         apic_set_reg(apic, APIC_SPIV, 0xff);
 955         apic_set_reg(apic, APIC_TASKPRI, 0);
 956         apic_set_reg(apic, APIC_LDR, 0);
 957         apic_set_reg(apic, APIC_ESR, 0);
 958         apic_set_reg(apic, APIC_ICR, 0);
 959         apic_set_reg(apic, APIC_ICR2, 0);
 960         apic_set_reg(apic, APIC_TDCR, 0);
 961         apic_set_reg(apic, APIC_TMICT, 0);
 962         for (i = 0; i < 8; i++) {
 963                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
 964                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
 965                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
 966         }
 967         apic->irr_pending = false;
 968         update_divide_count(apic);
 969         atomic_set(&apic->lapic_timer.pending, 0);
 970         if (kvm_vcpu_is_bsp(vcpu))
 971                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
 972         apic_update_ppr(apic);
 973
 974         vcpu->arch.apic_arb_prio = 0;
 975
 976         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
 977                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
 978                    vcpu, kvm_apic_id(apic),
 979                    vcpu->arch.apic_base, apic->base_address);
 980 }
 981
 982 bool kvm_apic_present(struct kvm_vcpu *vcpu)
 983 {
 984         return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
 985 }
 986
 987 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 988 {
 989         return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
 990 }
 991
 992 /*
 993  *----------------------------------------------------------------------
 994  * timer interface
 995  *----------------------------------------------------------------------
 996  */
 997
 998 static bool lapic_is_periodic(struct kvm_timer *ktimer)
 999 {
1000         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
1001                                               lapic_timer);
1002         return apic_lvtt_period(apic);
1003 }
1004
1005 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1006 {
1007         struct kvm_lapic *lapic = vcpu->arch.apic;
1008
1009         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
1010                 return atomic_read(&lapic->lapic_timer.pending);
1011
1012         return 0;
1013 }
1014
1015 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1016 {
1017         u32 reg = apic_get_reg(apic, lvt_type);
1018         int vector, mode, trig_mode;
1019
1020         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1021                 vector = reg & APIC_VECTOR_MASK;
1022                 mode = reg & APIC_MODE_MASK;
1023                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1024                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1025         }
1026         return 0;
1027 }
1028
1029 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1030 {
1031         struct kvm_lapic *apic = vcpu->arch.apic;
1032
1033         if (apic)
1034                 kvm_apic_local_deliver(apic, APIC_LVT0);
1035 }
1036
1037 static struct kvm_timer_ops lapic_timer_ops = {
1038         .is_periodic = lapic_is_periodic,
1039 };
1040
1041 static const struct kvm_io_device_ops apic_mmio_ops = {
1042         .read     = apic_mmio_read,
1043         .write    = apic_mmio_write,
1044 };
1045
1046 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1047 {
1048         struct kvm_lapic *apic;
1049
1050         ASSERT(vcpu != NULL);
1051         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1052
1053         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1054         if (!apic)
1055                 goto nomem;
1056
1057         vcpu->arch.apic = apic;
1058
1059         apic->regs_page = alloc_page(GFP_KERNEL|__GFP_ZERO);
1060         if (apic->regs_page == NULL) {
1061                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1062                        vcpu->vcpu_id);
1063                 goto nomem_free_apic;
1064         }
1065         apic->regs = page_address(apic->regs_page);
1066         apic->vcpu = vcpu;
1067
1068         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1069                      HRTIMER_MODE_ABS);
1070         apic->lapic_timer.timer.function = kvm_timer_fn;
1071         apic->lapic_timer.t_ops = &lapic_timer_ops;
1072         apic->lapic_timer.kvm = vcpu->kvm;
1073         apic->lapic_timer.vcpu = vcpu;
1074
1075         apic->base_address = APIC_DEFAULT_PHYS_BASE;
1076         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1077
1078         kvm_lapic_reset(vcpu);
1079         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1080
1081         return 0;
1082 nomem_free_apic:
1083         kfree(apic);
1084 nomem:
1085         return -ENOMEM;
1086 }
1087
1088 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1089 {
1090         struct kvm_lapic *apic = vcpu->arch.apic;
1091         int highest_irr;
1092
1093         if (!apic || !apic_enabled(apic))
1094                 return -1;
1095
1096         apic_update_ppr(apic);
1097         highest_irr = apic_find_highest_irr(apic);
1098         if ((highest_irr == -1) ||
1099             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1100                 return -1;
1101         return highest_irr;
1102 }
1103
1104 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1105 {
1106         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1107         int r = 0;
1108
1109         if (!apic_hw_enabled(vcpu->arch.apic))
1110                 r = 1;
1111         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1112             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1113                 r = 1;
1114         return r;
1115 }
1116
1117 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1118 {
1119         struct kvm_lapic *apic = vcpu->arch.apic;
1120
1121         if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1122                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1123                         atomic_dec(&apic->lapic_timer.pending);
1124         }
1125 }
1126
1127 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1128 {
1129         int vector = kvm_apic_has_interrupt(vcpu);
1130         struct kvm_lapic *apic = vcpu->arch.apic;
1131
1132         if (vector == -1)
1133                 return -1;
1134
1135         apic_set_vector(vector, apic->regs + APIC_ISR);
1136         apic_update_ppr(apic);
1137         apic_clear_irr(vector, apic);
1138         return vector;
1139 }
1140
1141 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1142 {
1143         struct kvm_lapic *apic = vcpu->arch.apic;
1144
1145         apic->base_address = vcpu->arch.apic_base &
1146                              MSR_IA32_APICBASE_BASE;
1147         kvm_apic_set_version(vcpu);
1148
1149         apic_update_ppr(apic);
1150         hrtimer_cancel(&apic->lapic_timer.timer);
1151         update_divide_count(apic);
1152         start_apic_timer(apic);
1153         apic->irr_pending = true;
1154 }
1155
1156 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1157 {
1158         struct kvm_lapic *apic = vcpu->arch.apic;
1159         struct hrtimer *timer;
1160
1161         if (!apic)
1162                 return;
1163
1164         timer = &apic->lapic_timer.timer;
1165         if (hrtimer_cancel(timer))
1166                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1167 }
1168
1169 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1170 {
1171         u32 data;
1172         void *vapic;
1173
1174         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1175                 return;
1176
1177         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1178         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1179         kunmap_atomic(vapic, KM_USER0);
1180
1181         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1182 }
1183
1184 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1185 {
1186         u32 data, tpr;
1187         int max_irr, max_isr;
1188         struct kvm_lapic *apic;
1189         void *vapic;
1190
1191         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1192                 return;
1193
1194         apic = vcpu->arch.apic;
1195         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1196         max_irr = apic_find_highest_irr(apic);
1197         if (max_irr < 0)
1198                 max_irr = 0;
1199         max_isr = apic_find_highest_isr(apic);
1200         if (max_isr < 0)
1201                 max_isr = 0;
1202         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1203
1204         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1205         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1206         kunmap_atomic(vapic, KM_USER0);
1207 }
1208
1209 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1210 {
1211         if (!irqchip_in_kernel(vcpu->kvm))
1212                 return;
1213
1214         vcpu->arch.apic->vapic_addr = vapic_addr;
1215 }
1216
1217 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1218 {
1219         struct kvm_lapic *apic = vcpu->arch.apic;
1220         u32 reg = (msr - APIC_BASE_MSR) << 4;
1221
1222         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1223                 return 1;
1224
1225         /* if this is ICR write vector before command */
1226         if (msr == 0x830)
1227                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1228         return apic_reg_write(apic, reg, (u32)data);
1229 }
1230
1231 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1232 {
1233         struct kvm_lapic *apic = vcpu->arch.apic;
1234         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1235
1236         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1237                 return 1;
1238
1239         if (apic_reg_read(apic, reg, 4, &low))
1240                 return 1;
1241         if (msr == 0x830)
1242                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1243
1244         *data = (((u64)high) << 32) | low;
1245
1246         return 0;
1247 }
1248
1249 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1250 {
1251         struct kvm_lapic *apic = vcpu->arch.apic;
1252
1253         if (!irqchip_in_kernel(vcpu->kvm))
1254                 return 1;
1255
1256         /* if this is ICR write vector before command */
1257         if (reg == APIC_ICR)
1258                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1259         return apic_reg_write(apic, reg, (u32)data);
1260 }
1261
1262 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1263 {
1264         struct kvm_lapic *apic = vcpu->arch.apic;
1265         u32 low, high = 0;
1266
1267         if (!irqchip_in_kernel(vcpu->kvm))
1268                 return 1;
1269
1270         if (apic_reg_read(apic, reg, 4, &low))
1271                 return 1;
1272         if (reg == APIC_ICR)
1273                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1274
1275         *data = (((u64)high) << 32) | low;
1276
1277         return 0;
1278 }