arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <linux/atomic.h>
  37 #include "kvm_cache_regs.h"
  38 #include "irq.h"
  39 #include "trace.h"
  40 #include "x86.h"
  41
  42 #ifndef CONFIG_X86_64
  43 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  44 #else
  45 #define mod_64(x, y) ((x) % (y))
  46 #endif
  47
  48 #define PRId64 "d"
  49 #define PRIx64 "llx"
  50 #define PRIu64 "u"
  51 #define PRIo64 "o"
  52
  53 #define APIC_BUS_CYCLE_NS 1
  54
  55 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  56 #define apic_debug(fmt, arg...)
  57
  58 #define APIC_LVT_NUM                    6
  59 /* 14 is the version for Xeon and Pentium 8.4.8*/
  60 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  61 #define LAPIC_MMIO_LENGTH               (1 << 12)
  62 /* followed define is not in apicdef.h */
  63 #define APIC_SHORT_MASK                 0xc0000
  64 #define APIC_DEST_NOSHORT               0x0
  65 #define APIC_DEST_MASK                  0x800
  66 #define MAX_APIC_VECTOR                 256
  67
  68 #define VEC_POS(v) ((v) & (32 - 1))
  69 #define REG_POS(v) (((v) >> 5) << 4)
  70
  71 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  72 {
  73         return *((u32 *) (apic->regs + reg_off));
  74 }
  75
  76 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  77 {
  78         *((u32 *) (apic->regs + reg_off)) = val;
  79 }
  80
  81 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  82 {
  83         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  84 }
  85
  86 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  87 {
  88         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  89 }
  90
  91 static inline void apic_set_vector(int vec, void *bitmap)
  92 {
  93         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  94 }
  95
  96 static inline void apic_clear_vector(int vec, void *bitmap)
  97 {
  98         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  99 }
 100
 101 static inline int apic_hw_enabled(struct kvm_lapic *apic)
 102 {
 103         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 104 }
 105
 106 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
 107 {
 108         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 109 }
 110
 111 static inline int apic_enabled(struct kvm_lapic *apic)
 112 {
 113         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 114 }
 115
 116 #define LVT_MASK        \
 117         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 118
 119 #define LINT_MASK       \
 120         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 121          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 122
 123 static inline int kvm_apic_id(struct kvm_lapic *apic)
 124 {
 125         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 126 }
 127
 128 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 129 {
 130         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 131 }
 132
 133 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 134 {
 135         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 136 }
 137
 138 static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
 139 {
 140         return ((apic_get_reg(apic, APIC_LVTT) &
 141                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_ONESHOT);
 142 }
 143
 144 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 145 {
 146         return ((apic_get_reg(apic, APIC_LVTT) &
 147                 apic->lapic_timer.timer_mode_mask) == APIC_LVT_TIMER_PERIODIC);
 148 }
 149
 150 static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
 151 {
 152         return ((apic_get_reg(apic, APIC_LVTT) &
 153                 apic->lapic_timer.timer_mode_mask) ==
 154                         APIC_LVT_TIMER_TSCDEADLINE);
 155 }
 156
 157 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 158 {
 159         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 160 }
 161
 162 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 163 {
 164         struct kvm_lapic *apic = vcpu->arch.apic;
 165         struct kvm_cpuid_entry2 *feat;
 166         u32 v = APIC_VERSION;
 167
 168         if (!irqchip_in_kernel(vcpu->kvm))
 169                 return;
 170
 171         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 172         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 173                 v |= APIC_LVR_DIRECTED_EOI;
 174         apic_set_reg(apic, APIC_LVR, v);
 175 }
 176
 177 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
 178 {
 179         return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
 180 }
 181
 182 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 183         LVT_MASK ,      /* part LVTT mask, timer mode mask added at runtime */
 184         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 185         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 186         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 187         LVT_MASK                /* LVTERR */
 188 };
 189
 190 static int find_highest_vector(void *bitmap)
 191 {
 192         u32 *word = bitmap;
 193         int word_offset = MAX_APIC_VECTOR >> 5;
 194
 195         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 196                 continue;
 197
 198         if (likely(!word_offset && !word[0]))
 199                 return -1;
 200         else
 201                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 202 }
 203
 204 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 205 {
 206         apic->irr_pending = true;
 207         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 208 }
 209
 210 static inline int apic_search_irr(struct kvm_lapic *apic)
 211 {
 212         return find_highest_vector(apic->regs + APIC_IRR);
 213 }
 214
 215 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 216 {
 217         int result;
 218
 219         if (!apic->irr_pending)
 220                 return -1;
 221
 222         result = apic_search_irr(apic);
 223         ASSERT(result == -1 || result >= 16);
 224
 225         return result;
 226 }
 227
 228 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 229 {
 230         apic->irr_pending = false;
 231         apic_clear_vector(vec, apic->regs + APIC_IRR);
 232         if (apic_search_irr(apic) != -1)
 233                 apic->irr_pending = true;
 234 }
 235
 236 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 237 {
 238         struct kvm_lapic *apic = vcpu->arch.apic;
 239         int highest_irr;
 240
 241         /* This may race with setting of irr in __apic_accept_irq() and
 242          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 243          * will cause vmexit immediately and the value will be recalculated
 244          * on the next vmentry.
 245          */
 246         if (!apic)
 247                 return 0;
 248         highest_irr = apic_find_highest_irr(apic);
 249
 250         return highest_irr;
 251 }
 252
 253 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 254                              int vector, int level, int trig_mode);
 255
 256 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
 257 {
 258         struct kvm_lapic *apic = vcpu->arch.apic;
 259
 260         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 261                         irq->level, irq->trig_mode);
 262 }
 263
 264 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 265 {
 266         int result;
 267
 268         result = find_highest_vector(apic->regs + APIC_ISR);
 269         ASSERT(result == -1 || result >= 16);
 270
 271         return result;
 272 }
 273
 274 static void apic_update_ppr(struct kvm_lapic *apic)
 275 {
 276         u32 tpr, isrv, ppr, old_ppr;
 277         int isr;
 278
 279         old_ppr = apic_get_reg(apic, APIC_PROCPRI);
 280         tpr = apic_get_reg(apic, APIC_TASKPRI);
 281         isr = apic_find_highest_isr(apic);
 282         isrv = (isr != -1) ? isr : 0;
 283
 284         if ((tpr & 0xf0) >= (isrv & 0xf0))
 285                 ppr = tpr & 0xff;
 286         else
 287                 ppr = isrv & 0xf0;
 288
 289         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 290                    apic, ppr, isr, isrv);
 291
 292         if (old_ppr != ppr) {
 293                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 294                 if (ppr < old_ppr)
 295                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 296         }
 297 }
 298
 299 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 300 {
 301         apic_set_reg(apic, APIC_TASKPRI, tpr);
 302         apic_update_ppr(apic);
 303 }
 304
 305 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 306 {
 307         return dest == 0xff || kvm_apic_id(apic) == dest;
 308 }
 309
 310 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 311 {
 312         int result = 0;
 313         u32 logical_id;
 314
 315         if (apic_x2apic_mode(apic)) {
 316                 logical_id = apic_get_reg(apic, APIC_LDR);
 317                 return logical_id & mda;
 318         }
 319
 320         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 321
 322         switch (apic_get_reg(apic, APIC_DFR)) {
 323         case APIC_DFR_FLAT:
 324                 if (logical_id & mda)
 325                         result = 1;
 326                 break;
 327         case APIC_DFR_CLUSTER:
 328                 if (((logical_id >> 4) == (mda >> 0x4))
 329                     && (logical_id & mda & 0xf))
 330                         result = 1;
 331                 break;
 332         default:
 333                 apic_debug("Bad DFR vcpu %d: %08x\n",
 334                            apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 335                 break;
 336         }
 337
 338         return result;
 339 }
 340
 341 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 342                            int short_hand, int dest, int dest_mode)
 343 {
 344         int result = 0;
 345         struct kvm_lapic *target = vcpu->arch.apic;
 346
 347         apic_debug("target %p, source %p, dest 0x%x, "
 348                    "dest_mode 0x%x, short_hand 0x%x\n",
 349                    target, source, dest, dest_mode, short_hand);
 350
 351         ASSERT(target);
 352         switch (short_hand) {
 353         case APIC_DEST_NOSHORT:
 354                 if (dest_mode == 0)
 355                         /* Physical mode. */
 356                         result = kvm_apic_match_physical_addr(target, dest);
 357                 else
 358                         /* Logical mode. */
 359                         result = kvm_apic_match_logical_addr(target, dest);
 360                 break;
 361         case APIC_DEST_SELF:
 362                 result = (target == source);
 363                 break;
 364         case APIC_DEST_ALLINC:
 365                 result = 1;
 366                 break;
 367         case APIC_DEST_ALLBUT:
 368                 result = (target != source);
 369                 break;
 370         default:
 371                 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
 372                            short_hand);
 373                 break;
 374         }
 375
 376         return result;
 377 }
 378
 379 /*
 380  * Add a pending IRQ into lapic.
 381  * Return 1 if successfully added and 0 if discarded.
 382  */
 383 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 384                              int vector, int level, int trig_mode)
 385 {
 386         int result = 0;
 387         struct kvm_vcpu *vcpu = apic->vcpu;
 388
 389         switch (delivery_mode) {
 390         case APIC_DM_LOWEST:
 391                 vcpu->arch.apic_arb_prio++;
 392         case APIC_DM_FIXED:
 393                 /* FIXME add logic for vcpu on reset */
 394                 if (unlikely(!apic_enabled(apic)))
 395                         break;
 396
 397                 if (trig_mode) {
 398                         apic_debug("level trig mode for vector %d", vector);
 399                         apic_set_vector(vector, apic->regs + APIC_TMR);
 400                 } else
 401                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 402
 403                 result = !apic_test_and_set_irr(vector, apic);
 404                 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 405                                           trig_mode, vector, !result);
 406                 if (!result) {
 407                         if (trig_mode)
 408                                 apic_debug("level trig mode repeatedly for "
 409                                                 "vector %d", vector);
 410                         break;
 411                 }
 412
 413                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 414                 kvm_vcpu_kick(vcpu);
 415                 break;
 416
 417         case APIC_DM_REMRD:
 418                 apic_debug("Ignoring delivery mode 3\n");
 419                 break;
 420
 421         case APIC_DM_SMI:
 422                 apic_debug("Ignoring guest SMI\n");
 423                 break;
 424
 425         case APIC_DM_NMI:
 426                 result = 1;
 427                 kvm_inject_nmi(vcpu);
 428                 kvm_vcpu_kick(vcpu);
 429                 break;
 430
 431         case APIC_DM_INIT:
 432                 if (level) {
 433                         result = 1;
 434                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 435                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 436                         kvm_vcpu_kick(vcpu);
 437                 } else {
 438                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 439                                    vcpu->vcpu_id);
 440                 }
 441                 break;
 442
 443         case APIC_DM_STARTUP:
 444                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 445                            vcpu->vcpu_id, vector);
 446                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 447                         result = 1;
 448                         vcpu->arch.sipi_vector = vector;
 449                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 450                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 451                         kvm_vcpu_kick(vcpu);
 452                 }
 453                 break;
 454
 455         case APIC_DM_EXTINT:
 456                 /*
 457                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 458                  * before NMI watchdog was enabled. Already handled by
 459                  * kvm_apic_accept_pic_intr().
 460                  */
 461                 break;
 462
 463         default:
 464                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 465                        delivery_mode);
 466                 break;
 467         }
 468         return result;
 469 }
 470
 471 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 472 {
 473         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 474 }
 475
 476 static void apic_set_eoi(struct kvm_lapic *apic)
 477 {
 478         int vector = apic_find_highest_isr(apic);
 479         int trigger_mode;
 480         /*
 481          * Not every write EOI will has corresponding ISR,
 482          * one example is when Kernel check timer on setup_IO_APIC
 483          */
 484         if (vector == -1)
 485                 return;
 486
 487         apic_clear_vector(vector, apic->regs + APIC_ISR);
 488         apic_update_ppr(apic);
 489
 490         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
 491                 trigger_mode = IOAPIC_LEVEL_TRIG;
 492         else
 493                 trigger_mode = IOAPIC_EDGE_TRIG;
 494         if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
 495                 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 496         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 497 }
 498
 499 static void apic_send_ipi(struct kvm_lapic *apic)
 500 {
 501         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 502         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 503         struct kvm_lapic_irq irq;
 504
 505         irq.vector = icr_low & APIC_VECTOR_MASK;
 506         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 507         irq.dest_mode = icr_low & APIC_DEST_MASK;
 508         irq.level = icr_low & APIC_INT_ASSERT;
 509         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 510         irq.shorthand = icr_low & APIC_SHORT_MASK;
 511         if (apic_x2apic_mode(apic))
 512                 irq.dest_id = icr_high;
 513         else
 514                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 515
 516         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 517
 518         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 519                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 520                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 521                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 522                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 523                    irq.vector);
 524
 525         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
 526 }
 527
 528 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 529 {
 530         ktime_t remaining;
 531         s64 ns;
 532         u32 tmcct;
 533
 534         ASSERT(apic != NULL);
 535
 536         /* if initial count is 0, current count should also be 0 */
 537         if (apic_get_reg(apic, APIC_TMICT) == 0 ||
 538                 apic->lapic_timer.period == 0)
 539                 return 0;
 540
 541         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 542         if (ktime_to_ns(remaining) < 0)
 543                 remaining = ktime_set(0, 0);
 544
 545         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 546         tmcct = div64_u64(ns,
 547                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 548
 549         return tmcct;
 550 }
 551
 552 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 553 {
 554         struct kvm_vcpu *vcpu = apic->vcpu;
 555         struct kvm_run *run = vcpu->run;
 556
 557         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 558         run->tpr_access.rip = kvm_rip_read(vcpu);
 559         run->tpr_access.is_write = write;
 560 }
 561
 562 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 563 {
 564         if (apic->vcpu->arch.tpr_access_reporting)
 565                 __report_tpr_access(apic, write);
 566 }
 567
 568 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 569 {
 570         u32 val = 0;
 571
 572         if (offset >= LAPIC_MMIO_LENGTH)
 573                 return 0;
 574
 575         switch (offset) {
 576         case APIC_ID:
 577                 if (apic_x2apic_mode(apic))
 578                         val = kvm_apic_id(apic);
 579                 else
 580                         val = kvm_apic_id(apic) << 24;
 581                 break;
 582         case APIC_ARBPRI:
 583                 apic_debug("Access APIC ARBPRI register which is for P6\n");
 584                 break;
 585
 586         case APIC_TMCCT:        /* Timer CCR */
 587                 if (apic_lvtt_tscdeadline(apic))
 588                         return 0;
 589
 590                 val = apic_get_tmcct(apic);
 591                 break;
 592
 593         case APIC_TASKPRI:
 594                 report_tpr_access(apic, false);
 595                 /* fall thru */
 596         default:
 597                 apic_update_ppr(apic);
 598                 val = apic_get_reg(apic, offset);
 599                 break;
 600         }
 601
 602         return val;
 603 }
 604
 605 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 606 {
 607         return container_of(dev, struct kvm_lapic, dev);
 608 }
 609
 610 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 611                 void *data)
 612 {
 613         unsigned char alignment = offset & 0xf;
 614         u32 result;
 615         /* this bitmask has a bit cleared for each reserver register */
 616         static const u64 rmask = 0x43ff01ffffffe70cULL;
 617
 618         if ((alignment + len) > 4) {
 619                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 620                            offset, len);
 621                 return 1;
 622         }
 623
 624         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
 625                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
 626                            offset);
 627                 return 1;
 628         }
 629
 630         result = __apic_read(apic, offset & ~0xf);
 631
 632         trace_kvm_apic_read(offset, result);
 633
 634         switch (len) {
 635         case 1:
 636         case 2:
 637         case 4:
 638                 memcpy(data, (char *)&result + alignment, len);
 639                 break;
 640         default:
 641                 printk(KERN_ERR "Local APIC read with len = %x, "
 642                        "should be 1,2, or 4 instead\n", len);
 643                 break;
 644         }
 645         return 0;
 646 }
 647
 648 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
 649 {
 650         return apic_hw_enabled(apic) &&
 651             addr >= apic->base_address &&
 652             addr < apic->base_address + LAPIC_MMIO_LENGTH;
 653 }
 654
 655 static int apic_mmio_read(struct kvm_io_device *this,
 656                            gpa_t address, int len, void *data)
 657 {
 658         struct kvm_lapic *apic = to_lapic(this);
 659         u32 offset = address - apic->base_address;
 660
 661         if (!apic_mmio_in_range(apic, address))
 662                 return -EOPNOTSUPP;
 663
 664         apic_reg_read(apic, offset, len, data);
 665
 666         return 0;
 667 }
 668
 669 static void update_divide_count(struct kvm_lapic *apic)
 670 {
 671         u32 tmp1, tmp2, tdcr;
 672
 673         tdcr = apic_get_reg(apic, APIC_TDCR);
 674         tmp1 = tdcr & 0xf;
 675         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 676         apic->divide_count = 0x1 << (tmp2 & 0x7);
 677
 678         apic_debug("timer divide count is 0x%x\n",
 679                                    apic->divide_count);
 680 }
 681
 682 static void start_apic_timer(struct kvm_lapic *apic)
 683 {
 684         ktime_t now;
 685         atomic_set(&apic->lapic_timer.pending, 0);
 686
 687         if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
 688                 /* lapic timer in oneshot or peroidic mode */
 689                 now = apic->lapic_timer.timer.base->get_time();
 690                 apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT)
 691                             * APIC_BUS_CYCLE_NS * apic->divide_count;
 692
 693                 if (!apic->lapic_timer.period)
 694                         return;
 695                 /*
 696                  * Do not allow the guest to program periodic timers with small
 697                  * interval, since the hrtimers are not throttled by the host
 698                  * scheduler.
 699                  */
 700                 if (apic_lvtt_period(apic)) {
 701                         s64 min_period = min_timer_period_us * 1000LL;
 702
 703                         if (apic->lapic_timer.period < min_period) {
 704                                 pr_info_ratelimited(
 705                                     "kvm: vcpu %i: requested %lld ns "
 706                                     "lapic timer period limited to %lld ns\n",
 707                                     apic->vcpu->vcpu_id,
 708                                     apic->lapic_timer.period, min_period);
 709                                 apic->lapic_timer.period = min_period;
 710                         }
 711                 }
 712
 713                 hrtimer_start(&apic->lapic_timer.timer,
 714                               ktime_add_ns(now, apic->lapic_timer.period),
 715                               HRTIMER_MODE_ABS);
 716
 717                 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 718                            PRIx64 ", "
 719                            "timer initial count 0x%x, period %lldns, "
 720                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 721                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 722                            apic_get_reg(apic, APIC_TMICT),
 723                            apic->lapic_timer.period,
 724                            ktime_to_ns(ktime_add_ns(now,
 725                                         apic->lapic_timer.period)));
 726         } else if (apic_lvtt_tscdeadline(apic)) {
 727                 /* lapic timer in tsc deadline mode */
 728                 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
 729                 u64 ns = 0;
 730                 struct kvm_vcpu *vcpu = apic->vcpu;
 731                 unsigned long this_tsc_khz = vcpu_tsc_khz(vcpu);
 732                 unsigned long flags;
 733
 734                 if (unlikely(!tscdeadline || !this_tsc_khz))
 735                         return;
 736
 737                 local_irq_save(flags);
 738
 739                 now = apic->lapic_timer.timer.base->get_time();
 740                 guest_tsc = kvm_x86_ops->read_l1_tsc(vcpu);
 741                 if (likely(tscdeadline > guest_tsc)) {
 742                         ns = (tscdeadline - guest_tsc) * 1000000ULL;
 743                         do_div(ns, this_tsc_khz);
 744                 }
 745                 hrtimer_start(&apic->lapic_timer.timer,
 746                         ktime_add_ns(now, ns), HRTIMER_MODE_ABS);
 747
 748                 local_irq_restore(flags);
 749         }
 750 }
 751
 752 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 753 {
 754         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
 755
 756         if (apic_lvt_nmi_mode(lvt0_val)) {
 757                 if (!nmi_wd_enabled) {
 758                         apic_debug("Receive NMI setting on APIC_LVT0 "
 759                                    "for cpu %d\n", apic->vcpu->vcpu_id);
 760                         atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
 761                 }
 762         } else if (nmi_wd_enabled)
 763                 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
 764 }
 765
 766 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 767 {
 768         int ret = 0;
 769
 770         trace_kvm_apic_write(reg, val);
 771
 772         switch (reg) {
 773         case APIC_ID:           /* Local APIC ID */
 774                 if (!apic_x2apic_mode(apic))
 775                         apic_set_reg(apic, APIC_ID, val);
 776                 else
 777                         ret = 1;
 778                 break;
 779
 780         case APIC_TASKPRI:
 781                 report_tpr_access(apic, true);
 782                 apic_set_tpr(apic, val & 0xff);
 783                 break;
 784
 785         case APIC_EOI:
 786                 apic_set_eoi(apic);
 787                 break;
 788
 789         case APIC_LDR:
 790                 if (!apic_x2apic_mode(apic))
 791                         apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 792                 else
 793                         ret = 1;
 794                 break;
 795
 796         case APIC_DFR:
 797                 if (!apic_x2apic_mode(apic))
 798                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 799                 else
 800                         ret = 1;
 801                 break;
 802
 803         case APIC_SPIV: {
 804                 u32 mask = 0x3ff;
 805                 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
 806                         mask |= APIC_SPIV_DIRECTED_EOI;
 807                 apic_set_reg(apic, APIC_SPIV, val & mask);
 808                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 809                         int i;
 810                         u32 lvt_val;
 811
 812                         for (i = 0; i < APIC_LVT_NUM; i++) {
 813                                 lvt_val = apic_get_reg(apic,
 814                                                        APIC_LVTT + 0x10 * i);
 815                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 816                                              lvt_val | APIC_LVT_MASKED);
 817                         }
 818                         atomic_set(&apic->lapic_timer.pending, 0);
 819
 820                 }
 821                 break;
 822         }
 823         case APIC_ICR:
 824                 /* No delay here, so we always clear the pending bit */
 825                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 826                 apic_send_ipi(apic);
 827                 break;
 828
 829         case APIC_ICR2:
 830                 if (!apic_x2apic_mode(apic))
 831                         val &= 0xff000000;
 832                 apic_set_reg(apic, APIC_ICR2, val);
 833                 break;
 834
 835         case APIC_LVT0:
 836                 apic_manage_nmi_watchdog(apic, val);
 837         case APIC_LVTTHMR:
 838         case APIC_LVTPC:
 839         case APIC_LVT1:
 840         case APIC_LVTERR:
 841                 /* TODO: Check vector */
 842                 if (!apic_sw_enabled(apic))
 843                         val |= APIC_LVT_MASKED;
 844
 845                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
 846                 apic_set_reg(apic, reg, val);
 847
 848                 break;
 849
 850         case APIC_LVTT:
 851                 if ((apic_get_reg(apic, APIC_LVTT) &
 852                     apic->lapic_timer.timer_mode_mask) !=
 853                    (val & apic->lapic_timer.timer_mode_mask))
 854                         hrtimer_cancel(&apic->lapic_timer.timer);
 855
 856                 if (!apic_sw_enabled(apic))
 857                         val |= APIC_LVT_MASKED;
 858                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
 859                 apic_set_reg(apic, APIC_LVTT, val);
 860                 break;
 861
 862         case APIC_TMICT:
 863                 if (apic_lvtt_tscdeadline(apic))
 864                         break;
 865
 866                 hrtimer_cancel(&apic->lapic_timer.timer);
 867                 apic_set_reg(apic, APIC_TMICT, val);
 868                 start_apic_timer(apic);
 869                 break;
 870
 871         case APIC_TDCR:
 872                 if (val & 4)
 873                         apic_debug("KVM_WRITE:TDCR %x\n", val);
 874                 apic_set_reg(apic, APIC_TDCR, val);
 875                 update_divide_count(apic);
 876                 break;
 877
 878         case APIC_ESR:
 879                 if (apic_x2apic_mode(apic) && val != 0) {
 880                         apic_debug("KVM_WRITE:ESR not zero %x\n", val);
 881                         ret = 1;
 882                 }
 883                 break;
 884
 885         case APIC_SELF_IPI:
 886                 if (apic_x2apic_mode(apic)) {
 887                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
 888                 } else
 889                         ret = 1;
 890                 break;
 891         default:
 892                 ret = 1;
 893                 break;
 894         }
 895         if (ret)
 896                 apic_debug("Local APIC Write to read-only register %x\n", reg);
 897         return ret;
 898 }
 899
 900 static int apic_mmio_write(struct kvm_io_device *this,
 901                             gpa_t address, int len, const void *data)
 902 {
 903         struct kvm_lapic *apic = to_lapic(this);
 904         unsigned int offset = address - apic->base_address;
 905         u32 val;
 906
 907         if (!apic_mmio_in_range(apic, address))
 908                 return -EOPNOTSUPP;
 909
 910         /*
 911          * APIC register must be aligned on 128-bits boundary.
 912          * 32/64/128 bits registers must be accessed thru 32 bits.
 913          * Refer SDM 8.4.1
 914          */
 915         if (len != 4 || (offset & 0xf)) {
 916                 /* Don't shout loud, $infamous_os would cause only noise. */
 917                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
 918                 return 0;
 919         }
 920
 921         val = *(u32*)data;
 922
 923         /* too common printing */
 924         if (offset != APIC_EOI)
 925                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
 926                            "0x%x\n", __func__, offset, len, val);
 927
 928         apic_reg_write(apic, offset & 0xff0, val);
 929
 930         return 0;
 931 }
 932
 933 void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
 934 {
 935         struct kvm_lapic *apic = vcpu->arch.apic;
 936
 937         if (apic)
 938                 apic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
 939 }
 940 EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
 941
 942 void kvm_free_lapic(struct kvm_vcpu *vcpu)
 943 {
 944         if (!vcpu->arch.apic)
 945                 return;
 946
 947         hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
 948
 949         if (vcpu->arch.apic->regs)
 950                 free_page((unsigned long)vcpu->arch.apic->regs);
 951
 952         kfree(vcpu->arch.apic);
 953 }
 954
 955 /*
 956  *----------------------------------------------------------------------
 957  * LAPIC interface
 958  *----------------------------------------------------------------------
 959  */
 960
 961 u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
 962 {
 963         struct kvm_lapic *apic = vcpu->arch.apic;
 964         if (!apic)
 965                 return 0;
 966
 967         if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
 968                 return 0;
 969
 970         return apic->lapic_timer.tscdeadline;
 971 }
 972
 973 void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
 974 {
 975         struct kvm_lapic *apic = vcpu->arch.apic;
 976         if (!apic)
 977                 return;
 978
 979         if (apic_lvtt_oneshot(apic) || apic_lvtt_period(apic))
 980                 return;
 981
 982         hrtimer_cancel(&apic->lapic_timer.timer);
 983         apic->lapic_timer.tscdeadline = data;
 984         start_apic_timer(apic);
 985 }
 986
 987 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
 988 {
 989         struct kvm_lapic *apic = vcpu->arch.apic;
 990
 991         if (!apic)
 992                 return;
 993         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
 994                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 995 }
 996
 997 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 998 {
 999         struct kvm_lapic *apic = vcpu->arch.apic;
1000         u64 tpr;
1001
1002         if (!apic)
1003                 return 0;
1004         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
1005
1006         return (tpr & 0xf0) >> 4;
1007 }
1008
1009 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1010 {
1011         struct kvm_lapic *apic = vcpu->arch.apic;
1012
1013         if (!apic) {
1014                 value |= MSR_IA32_APICBASE_BSP;
1015                 vcpu->arch.apic_base = value;
1016                 return;
1017         }
1018
1019         if (!kvm_vcpu_is_bsp(apic->vcpu))
1020                 value &= ~MSR_IA32_APICBASE_BSP;
1021
1022         vcpu->arch.apic_base = value;
1023         if (apic_x2apic_mode(apic)) {
1024                 u32 id = kvm_apic_id(apic);
1025                 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1026                 apic_set_reg(apic, APIC_LDR, ldr);
1027         }
1028         apic->base_address = apic->vcpu->arch.apic_base &
1029                              MSR_IA32_APICBASE_BASE;
1030
1031         /* with FSB delivery interrupt, we can restart APIC functionality */
1032         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1033                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1034
1035 }
1036
1037 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
1038 {
1039         struct kvm_lapic *apic;
1040         int i;
1041
1042         apic_debug("%s\n", __func__);
1043
1044         ASSERT(vcpu);
1045         apic = vcpu->arch.apic;
1046         ASSERT(apic != NULL);
1047
1048         /* Stop the timer in case it's a reset to an active apic */
1049         hrtimer_cancel(&apic->lapic_timer.timer);
1050
1051         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
1052         kvm_apic_set_version(apic->vcpu);
1053
1054         for (i = 0; i < APIC_LVT_NUM; i++)
1055                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
1056         apic_set_reg(apic, APIC_LVT0,
1057                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
1058
1059         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
1060         apic_set_reg(apic, APIC_SPIV, 0xff);
1061         apic_set_reg(apic, APIC_TASKPRI, 0);
1062         apic_set_reg(apic, APIC_LDR, 0);
1063         apic_set_reg(apic, APIC_ESR, 0);
1064         apic_set_reg(apic, APIC_ICR, 0);
1065         apic_set_reg(apic, APIC_ICR2, 0);
1066         apic_set_reg(apic, APIC_TDCR, 0);
1067         apic_set_reg(apic, APIC_TMICT, 0);
1068         for (i = 0; i < 8; i++) {
1069                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1070                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1071                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
1072         }
1073         apic->irr_pending = false;
1074         update_divide_count(apic);
1075         atomic_set(&apic->lapic_timer.pending, 0);
1076         if (kvm_vcpu_is_bsp(vcpu))
1077                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
1078         apic_update_ppr(apic);
1079
1080         vcpu->arch.apic_arb_prio = 0;
1081
1082         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
1083                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
1084                    vcpu, kvm_apic_id(apic),
1085                    vcpu->arch.apic_base, apic->base_address);
1086 }
1087
1088 bool kvm_apic_present(struct kvm_vcpu *vcpu)
1089 {
1090         return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
1091 }
1092
1093 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
1094 {
1095         return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
1096 }
1097
1098 /*
1099  *----------------------------------------------------------------------
1100  * timer interface
1101  *----------------------------------------------------------------------
1102  */
1103
1104 static bool lapic_is_periodic(struct kvm_timer *ktimer)
1105 {
1106         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
1107                                               lapic_timer);
1108         return apic_lvtt_period(apic);
1109 }
1110
1111 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1112 {
1113         struct kvm_lapic *lapic = vcpu->arch.apic;
1114
1115         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
1116                 return atomic_read(&lapic->lapic_timer.pending);
1117
1118         return 0;
1119 }
1120
1121 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1122 {
1123         u32 reg = apic_get_reg(apic, lvt_type);
1124         int vector, mode, trig_mode;
1125
1126         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1127                 vector = reg & APIC_VECTOR_MASK;
1128                 mode = reg & APIC_MODE_MASK;
1129                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1130                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1131         }
1132         return 0;
1133 }
1134
1135 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1136 {
1137         struct kvm_lapic *apic = vcpu->arch.apic;
1138
1139         if (apic)
1140                 kvm_apic_local_deliver(apic, APIC_LVT0);
1141 }
1142
1143 static struct kvm_timer_ops lapic_timer_ops = {
1144         .is_periodic = lapic_is_periodic,
1145 };
1146
1147 static const struct kvm_io_device_ops apic_mmio_ops = {
1148         .read     = apic_mmio_read,
1149         .write    = apic_mmio_write,
1150 };
1151
1152 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1153 {
1154         struct kvm_lapic *apic;
1155
1156         ASSERT(vcpu != NULL);
1157         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1158
1159         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1160         if (!apic)
1161                 goto nomem;
1162
1163         vcpu->arch.apic = apic;
1164
1165         apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1166         if (!apic->regs) {
1167                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1168                        vcpu->vcpu_id);
1169                 goto nomem_free_apic;
1170         }
1171         apic->vcpu = vcpu;
1172
1173         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1174                      HRTIMER_MODE_ABS);
1175         apic->lapic_timer.timer.function = kvm_timer_fn;
1176         apic->lapic_timer.t_ops = &lapic_timer_ops;
1177         apic->lapic_timer.kvm = vcpu->kvm;
1178         apic->lapic_timer.vcpu = vcpu;
1179
1180         apic->base_address = APIC_DEFAULT_PHYS_BASE;
1181         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1182
1183         kvm_lapic_reset(vcpu);
1184         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1185
1186         return 0;
1187 nomem_free_apic:
1188         kfree(apic);
1189 nomem:
1190         return -ENOMEM;
1191 }
1192
1193 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1194 {
1195         struct kvm_lapic *apic = vcpu->arch.apic;
1196         int highest_irr;
1197
1198         if (!apic || !apic_enabled(apic))
1199                 return -1;
1200
1201         apic_update_ppr(apic);
1202         highest_irr = apic_find_highest_irr(apic);
1203         if ((highest_irr == -1) ||
1204             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1205                 return -1;
1206         return highest_irr;
1207 }
1208
1209 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1210 {
1211         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1212         int r = 0;
1213
1214         if (!apic_hw_enabled(vcpu->arch.apic))
1215                 r = 1;
1216         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1217             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1218                 r = 1;
1219         return r;
1220 }
1221
1222 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1223 {
1224         struct kvm_lapic *apic = vcpu->arch.apic;
1225
1226         if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1227                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1228                         atomic_dec(&apic->lapic_timer.pending);
1229         }
1230 }
1231
1232 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1233 {
1234         int vector = kvm_apic_has_interrupt(vcpu);
1235         struct kvm_lapic *apic = vcpu->arch.apic;
1236
1237         if (vector == -1)
1238                 return -1;
1239
1240         apic_set_vector(vector, apic->regs + APIC_ISR);
1241         apic_update_ppr(apic);
1242         apic_clear_irr(vector, apic);
1243         return vector;
1244 }
1245
1246 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1247 {
1248         struct kvm_lapic *apic = vcpu->arch.apic;
1249
1250         apic->base_address = vcpu->arch.apic_base &
1251                              MSR_IA32_APICBASE_BASE;
1252         kvm_apic_set_version(vcpu);
1253
1254         apic_update_ppr(apic);
1255         hrtimer_cancel(&apic->lapic_timer.timer);
1256         apic_manage_nmi_watchdog(apic, apic_get_reg(apic, APIC_LVT0));
1257         update_divide_count(apic);
1258         start_apic_timer(apic);
1259         apic->irr_pending = true;
1260         kvm_make_request(KVM_REQ_EVENT, vcpu);
1261 }
1262
1263 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1264 {
1265         struct kvm_lapic *apic = vcpu->arch.apic;
1266         struct hrtimer *timer;
1267
1268         if (!apic)
1269                 return;
1270
1271         timer = &apic->lapic_timer.timer;
1272         if (hrtimer_cancel(timer))
1273                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1274 }
1275
1276 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1277 {
1278         u32 data;
1279
1280         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1281                 return;
1282
1283         kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1284                                 sizeof(u32));
1285
1286         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1287 }
1288
1289 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1290 {
1291         u32 data, tpr;
1292         int max_irr, max_isr;
1293         struct kvm_lapic *apic;
1294
1295         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1296                 return;
1297
1298         apic = vcpu->arch.apic;
1299         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1300         max_irr = apic_find_highest_irr(apic);
1301         if (max_irr < 0)
1302                 max_irr = 0;
1303         max_isr = apic_find_highest_isr(apic);
1304         if (max_isr < 0)
1305                 max_isr = 0;
1306         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1307
1308         kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
1309                                 sizeof(u32));
1310 }
1311
1312 int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1313 {
1314         if (!irqchip_in_kernel(vcpu->kvm))
1315                 return 0;
1316
1317         if (vapic_addr && kvm_gfn_to_hva_cache_init(vcpu->kvm,
1318                                           &vcpu->arch.apic->vapic_cache,
1319                                           vapic_addr, sizeof(u32)))
1320                 return -EINVAL;
1321
1322         vcpu->arch.apic->vapic_addr = vapic_addr;
1323         return 0;
1324 }
1325
1326 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1327 {
1328         struct kvm_lapic *apic = vcpu->arch.apic;
1329         u32 reg = (msr - APIC_BASE_MSR) << 4;
1330
1331         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1332                 return 1;
1333
1334         /* if this is ICR write vector before command */
1335         if (msr == 0x830)
1336                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1337         return apic_reg_write(apic, reg, (u32)data);
1338 }
1339
1340 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1341 {
1342         struct kvm_lapic *apic = vcpu->arch.apic;
1343         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1344
1345         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1346                 return 1;
1347
1348         if (apic_reg_read(apic, reg, 4, &low))
1349                 return 1;
1350         if (msr == 0x830)
1351                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1352
1353         *data = (((u64)high) << 32) | low;
1354
1355         return 0;
1356 }
1357
1358 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1359 {
1360         struct kvm_lapic *apic = vcpu->arch.apic;
1361
1362         if (!irqchip_in_kernel(vcpu->kvm))
1363                 return 1;
1364
1365         /* if this is ICR write vector before command */
1366         if (reg == APIC_ICR)
1367                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1368         return apic_reg_write(apic, reg, (u32)data);
1369 }
1370
1371 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1372 {
1373         struct kvm_lapic *apic = vcpu->arch.apic;
1374         u32 low, high = 0;
1375
1376         if (!irqchip_in_kernel(vcpu->kvm))
1377                 return 1;
1378
1379         if (apic_reg_read(apic, reg, 4, &low))
1380                 return 1;
1381         if (reg == APIC_ICR)
1382                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1383
1384         *data = (((u64)high) << 32) | low;
1385
1386         return 0;
1387 }