arch/x86/kvm/lapic.c

   1
   2 /*
   3  * Local APIC virtualization
   4  *
   5  * Copyright (C) 2006 Qumranet, Inc.
   6  * Copyright (C) 2007 Novell
   7  * Copyright (C) 2007 Intel
   8  * Copyright 2009 Red Hat, Inc. and/or its affiliates.
   9  *
  10  * Authors:
  11  *   Dor Laor <dor.laor@qumranet.com>
  12  *   Gregory Haskins <ghaskins@novell.com>
  13  *   Yaozu (Eddie) Dong <eddie.dong@intel.com>
  14  *
  15  * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
  16  *
  17  * This work is licensed under the terms of the GNU GPL, version 2.  See
  18  * the COPYING file in the top-level directory.
  19  */
  20
  21 #include <linux/kvm_host.h>
  22 #include <linux/kvm.h>
  23 #include <linux/mm.h>
  24 #include <linux/highmem.h>
  25 #include <linux/smp.h>
  26 #include <linux/hrtimer.h>
  27 #include <linux/io.h>
  28 #include <linux/module.h>
  29 #include <linux/math64.h>
  30 #include <linux/slab.h>
  31 #include <asm/processor.h>
  32 #include <asm/msr.h>
  33 #include <asm/page.h>
  34 #include <asm/current.h>
  35 #include <asm/apicdef.h>
  36 #include <asm/atomic.h>
  37 #include "kvm_cache_regs.h"
  38 #include "irq.h"
  39 #include "trace.h"
  40 #include "x86.h"
  41
  42 #ifndef CONFIG_X86_64
  43 #define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
  44 #else
  45 #define mod_64(x, y) ((x) % (y))
  46 #endif
  47
  48 #define PRId64 "d"
  49 #define PRIx64 "llx"
  50 #define PRIu64 "u"
  51 #define PRIo64 "o"
  52
  53 #define APIC_BUS_CYCLE_NS 1
  54
  55 /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
  56 #define apic_debug(fmt, arg...)
  57
  58 #define APIC_LVT_NUM                    6
  59 /* 14 is the version for Xeon and Pentium 8.4.8*/
  60 #define APIC_VERSION                    (0x14UL | ((APIC_LVT_NUM - 1) << 16))
  61 #define LAPIC_MMIO_LENGTH               (1 << 12)
  62 /* followed define is not in apicdef.h */
  63 #define APIC_SHORT_MASK                 0xc0000
  64 #define APIC_DEST_NOSHORT               0x0
  65 #define APIC_DEST_MASK                  0x800
  66 #define MAX_APIC_VECTOR                 256
  67
  68 #define VEC_POS(v) ((v) & (32 - 1))
  69 #define REG_POS(v) (((v) >> 5) << 4)
  70
  71 static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
  72 {
  73         return *((u32 *) (apic->regs + reg_off));
  74 }
  75
  76 static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
  77 {
  78         *((u32 *) (apic->regs + reg_off)) = val;
  79 }
  80
  81 static inline int apic_test_and_set_vector(int vec, void *bitmap)
  82 {
  83         return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  84 }
  85
  86 static inline int apic_test_and_clear_vector(int vec, void *bitmap)
  87 {
  88         return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  89 }
  90
  91 static inline void apic_set_vector(int vec, void *bitmap)
  92 {
  93         set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  94 }
  95
  96 static inline void apic_clear_vector(int vec, void *bitmap)
  97 {
  98         clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
  99 }
 100
 101 static inline int apic_hw_enabled(struct kvm_lapic *apic)
 102 {
 103         return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
 104 }
 105
 106 static inline int  apic_sw_enabled(struct kvm_lapic *apic)
 107 {
 108         return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
 109 }
 110
 111 static inline int apic_enabled(struct kvm_lapic *apic)
 112 {
 113         return apic_sw_enabled(apic) && apic_hw_enabled(apic);
 114 }
 115
 116 #define LVT_MASK        \
 117         (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
 118
 119 #define LINT_MASK       \
 120         (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
 121          APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
 122
 123 static inline int kvm_apic_id(struct kvm_lapic *apic)
 124 {
 125         return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
 126 }
 127
 128 static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
 129 {
 130         return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
 131 }
 132
 133 static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
 134 {
 135         return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
 136 }
 137
 138 static inline int apic_lvtt_period(struct kvm_lapic *apic)
 139 {
 140         return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
 141 }
 142
 143 static inline int apic_lvt_nmi_mode(u32 lvt_val)
 144 {
 145         return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
 146 }
 147
 148 void kvm_apic_set_version(struct kvm_vcpu *vcpu)
 149 {
 150         struct kvm_lapic *apic = vcpu->arch.apic;
 151         struct kvm_cpuid_entry2 *feat;
 152         u32 v = APIC_VERSION;
 153
 154         if (!irqchip_in_kernel(vcpu->kvm))
 155                 return;
 156
 157         feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
 158         if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
 159                 v |= APIC_LVR_DIRECTED_EOI;
 160         apic_set_reg(apic, APIC_LVR, v);
 161 }
 162
 163 static inline int apic_x2apic_mode(struct kvm_lapic *apic)
 164 {
 165         return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
 166 }
 167
 168 static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
 169         LVT_MASK | APIC_LVT_TIMER_PERIODIC,     /* LVTT */
 170         LVT_MASK | APIC_MODE_MASK,      /* LVTTHMR */
 171         LVT_MASK | APIC_MODE_MASK,      /* LVTPC */
 172         LINT_MASK, LINT_MASK,   /* LVT0-1 */
 173         LVT_MASK                /* LVTERR */
 174 };
 175
 176 static int find_highest_vector(void *bitmap)
 177 {
 178         u32 *word = bitmap;
 179         int word_offset = MAX_APIC_VECTOR >> 5;
 180
 181         while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
 182                 continue;
 183
 184         if (likely(!word_offset && !word[0]))
 185                 return -1;
 186         else
 187                 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
 188 }
 189
 190 static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
 191 {
 192         apic->irr_pending = true;
 193         return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
 194 }
 195
 196 static inline int apic_search_irr(struct kvm_lapic *apic)
 197 {
 198         return find_highest_vector(apic->regs + APIC_IRR);
 199 }
 200
 201 static inline int apic_find_highest_irr(struct kvm_lapic *apic)
 202 {
 203         int result;
 204
 205         if (!apic->irr_pending)
 206                 return -1;
 207
 208         result = apic_search_irr(apic);
 209         ASSERT(result == -1 || result >= 16);
 210
 211         return result;
 212 }
 213
 214 static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
 215 {
 216         apic->irr_pending = false;
 217         apic_clear_vector(vec, apic->regs + APIC_IRR);
 218         if (apic_search_irr(apic) != -1)
 219                 apic->irr_pending = true;
 220 }
 221
 222 int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
 223 {
 224         struct kvm_lapic *apic = vcpu->arch.apic;
 225         int highest_irr;
 226
 227         /* This may race with setting of irr in __apic_accept_irq() and
 228          * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
 229          * will cause vmexit immediately and the value will be recalculated
 230          * on the next vmentry.
 231          */
 232         if (!apic)
 233                 return 0;
 234         highest_irr = apic_find_highest_irr(apic);
 235
 236         return highest_irr;
 237 }
 238
 239 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 240                              int vector, int level, int trig_mode);
 241
 242 int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
 243 {
 244         struct kvm_lapic *apic = vcpu->arch.apic;
 245
 246         return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
 247                         irq->level, irq->trig_mode);
 248 }
 249
 250 static inline int apic_find_highest_isr(struct kvm_lapic *apic)
 251 {
 252         int result;
 253
 254         result = find_highest_vector(apic->regs + APIC_ISR);
 255         ASSERT(result == -1 || result >= 16);
 256
 257         return result;
 258 }
 259
 260 static void apic_update_ppr(struct kvm_lapic *apic)
 261 {
 262         u32 tpr, isrv, ppr, old_ppr;
 263         int isr;
 264
 265         old_ppr = apic_get_reg(apic, APIC_PROCPRI);
 266         tpr = apic_get_reg(apic, APIC_TASKPRI);
 267         isr = apic_find_highest_isr(apic);
 268         isrv = (isr != -1) ? isr : 0;
 269
 270         if ((tpr & 0xf0) >= (isrv & 0xf0))
 271                 ppr = tpr & 0xff;
 272         else
 273                 ppr = isrv & 0xf0;
 274
 275         apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
 276                    apic, ppr, isr, isrv);
 277
 278         if (old_ppr != ppr) {
 279                 apic_set_reg(apic, APIC_PROCPRI, ppr);
 280                 if (ppr < old_ppr)
 281                         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 282         }
 283 }
 284
 285 static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
 286 {
 287         apic_set_reg(apic, APIC_TASKPRI, tpr);
 288         apic_update_ppr(apic);
 289 }
 290
 291 int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
 292 {
 293         return dest == 0xff || kvm_apic_id(apic) == dest;
 294 }
 295
 296 int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
 297 {
 298         int result = 0;
 299         u32 logical_id;
 300
 301         if (apic_x2apic_mode(apic)) {
 302                 logical_id = apic_get_reg(apic, APIC_LDR);
 303                 return logical_id & mda;
 304         }
 305
 306         logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
 307
 308         switch (apic_get_reg(apic, APIC_DFR)) {
 309         case APIC_DFR_FLAT:
 310                 if (logical_id & mda)
 311                         result = 1;
 312                 break;
 313         case APIC_DFR_CLUSTER:
 314                 if (((logical_id >> 4) == (mda >> 0x4))
 315                     && (logical_id & mda & 0xf))
 316                         result = 1;
 317                 break;
 318         default:
 319                 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
 320                        apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
 321                 break;
 322         }
 323
 324         return result;
 325 }
 326
 327 int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
 328                            int short_hand, int dest, int dest_mode)
 329 {
 330         int result = 0;
 331         struct kvm_lapic *target = vcpu->arch.apic;
 332
 333         apic_debug("target %p, source %p, dest 0x%x, "
 334                    "dest_mode 0x%x, short_hand 0x%x\n",
 335                    target, source, dest, dest_mode, short_hand);
 336
 337         ASSERT(target);
 338         switch (short_hand) {
 339         case APIC_DEST_NOSHORT:
 340                 if (dest_mode == 0)
 341                         /* Physical mode. */
 342                         result = kvm_apic_match_physical_addr(target, dest);
 343                 else
 344                         /* Logical mode. */
 345                         result = kvm_apic_match_logical_addr(target, dest);
 346                 break;
 347         case APIC_DEST_SELF:
 348                 result = (target == source);
 349                 break;
 350         case APIC_DEST_ALLINC:
 351                 result = 1;
 352                 break;
 353         case APIC_DEST_ALLBUT:
 354                 result = (target != source);
 355                 break;
 356         default:
 357                 printk(KERN_WARNING "Bad dest shorthand value %x\n",
 358                        short_hand);
 359                 break;
 360         }
 361
 362         return result;
 363 }
 364
 365 /*
 366  * Add a pending IRQ into lapic.
 367  * Return 1 if successfully added and 0 if discarded.
 368  */
 369 static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
 370                              int vector, int level, int trig_mode)
 371 {
 372         int result = 0;
 373         struct kvm_vcpu *vcpu = apic->vcpu;
 374
 375         switch (delivery_mode) {
 376         case APIC_DM_LOWEST:
 377                 vcpu->arch.apic_arb_prio++;
 378         case APIC_DM_FIXED:
 379                 /* FIXME add logic for vcpu on reset */
 380                 if (unlikely(!apic_enabled(apic)))
 381                         break;
 382
 383                 if (trig_mode) {
 384                         apic_debug("level trig mode for vector %d", vector);
 385                         apic_set_vector(vector, apic->regs + APIC_TMR);
 386                 } else
 387                         apic_clear_vector(vector, apic->regs + APIC_TMR);
 388
 389                 result = !apic_test_and_set_irr(vector, apic);
 390                 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
 391                                           trig_mode, vector, !result);
 392                 if (!result) {
 393                         if (trig_mode)
 394                                 apic_debug("level trig mode repeatedly for "
 395                                                 "vector %d", vector);
 396                         break;
 397                 }
 398
 399                 kvm_make_request(KVM_REQ_EVENT, vcpu);
 400                 kvm_vcpu_kick(vcpu);
 401                 break;
 402
 403         case APIC_DM_REMRD:
 404                 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
 405                 break;
 406
 407         case APIC_DM_SMI:
 408                 printk(KERN_DEBUG "Ignoring guest SMI\n");
 409                 break;
 410
 411         case APIC_DM_NMI:
 412                 result = 1;
 413                 kvm_inject_nmi(vcpu);
 414                 kvm_vcpu_kick(vcpu);
 415                 break;
 416
 417         case APIC_DM_INIT:
 418                 if (level) {
 419                         result = 1;
 420                         if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
 421                                 printk(KERN_DEBUG
 422                                        "INIT on a runnable vcpu %d\n",
 423                                        vcpu->vcpu_id);
 424                         vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
 425                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 426                         kvm_vcpu_kick(vcpu);
 427                 } else {
 428                         apic_debug("Ignoring de-assert INIT to vcpu %d\n",
 429                                    vcpu->vcpu_id);
 430                 }
 431                 break;
 432
 433         case APIC_DM_STARTUP:
 434                 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
 435                            vcpu->vcpu_id, vector);
 436                 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
 437                         result = 1;
 438                         vcpu->arch.sipi_vector = vector;
 439                         vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
 440                         kvm_make_request(KVM_REQ_EVENT, vcpu);
 441                         kvm_vcpu_kick(vcpu);
 442                 }
 443                 break;
 444
 445         case APIC_DM_EXTINT:
 446                 /*
 447                  * Should only be called by kvm_apic_local_deliver() with LVT0,
 448                  * before NMI watchdog was enabled. Already handled by
 449                  * kvm_apic_accept_pic_intr().
 450                  */
 451                 break;
 452
 453         default:
 454                 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
 455                        delivery_mode);
 456                 break;
 457         }
 458         return result;
 459 }
 460
 461 int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
 462 {
 463         return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
 464 }
 465
 466 static void apic_set_eoi(struct kvm_lapic *apic)
 467 {
 468         int vector = apic_find_highest_isr(apic);
 469         int trigger_mode;
 470         /*
 471          * Not every write EOI will has corresponding ISR,
 472          * one example is when Kernel check timer on setup_IO_APIC
 473          */
 474         if (vector == -1)
 475                 return;
 476
 477         apic_clear_vector(vector, apic->regs + APIC_ISR);
 478         apic_update_ppr(apic);
 479
 480         if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
 481                 trigger_mode = IOAPIC_LEVEL_TRIG;
 482         else
 483                 trigger_mode = IOAPIC_EDGE_TRIG;
 484         if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI))
 485                 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
 486         kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
 487 }
 488
 489 static void apic_send_ipi(struct kvm_lapic *apic)
 490 {
 491         u32 icr_low = apic_get_reg(apic, APIC_ICR);
 492         u32 icr_high = apic_get_reg(apic, APIC_ICR2);
 493         struct kvm_lapic_irq irq;
 494
 495         irq.vector = icr_low & APIC_VECTOR_MASK;
 496         irq.delivery_mode = icr_low & APIC_MODE_MASK;
 497         irq.dest_mode = icr_low & APIC_DEST_MASK;
 498         irq.level = icr_low & APIC_INT_ASSERT;
 499         irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
 500         irq.shorthand = icr_low & APIC_SHORT_MASK;
 501         if (apic_x2apic_mode(apic))
 502                 irq.dest_id = icr_high;
 503         else
 504                 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
 505
 506         trace_kvm_apic_ipi(icr_low, irq.dest_id);
 507
 508         apic_debug("icr_high 0x%x, icr_low 0x%x, "
 509                    "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
 510                    "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
 511                    icr_high, icr_low, irq.shorthand, irq.dest_id,
 512                    irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
 513                    irq.vector);
 514
 515         kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
 516 }
 517
 518 static u32 apic_get_tmcct(struct kvm_lapic *apic)
 519 {
 520         ktime_t remaining;
 521         s64 ns;
 522         u32 tmcct;
 523
 524         ASSERT(apic != NULL);
 525
 526         /* if initial count is 0, current count should also be 0 */
 527         if (apic_get_reg(apic, APIC_TMICT) == 0)
 528                 return 0;
 529
 530         remaining = hrtimer_get_remaining(&apic->lapic_timer.timer);
 531         if (ktime_to_ns(remaining) < 0)
 532                 remaining = ktime_set(0, 0);
 533
 534         ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
 535         tmcct = div64_u64(ns,
 536                          (APIC_BUS_CYCLE_NS * apic->divide_count));
 537
 538         return tmcct;
 539 }
 540
 541 static void __report_tpr_access(struct kvm_lapic *apic, bool write)
 542 {
 543         struct kvm_vcpu *vcpu = apic->vcpu;
 544         struct kvm_run *run = vcpu->run;
 545
 546         kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
 547         run->tpr_access.rip = kvm_rip_read(vcpu);
 548         run->tpr_access.is_write = write;
 549 }
 550
 551 static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
 552 {
 553         if (apic->vcpu->arch.tpr_access_reporting)
 554                 __report_tpr_access(apic, write);
 555 }
 556
 557 static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
 558 {
 559         u32 val = 0;
 560
 561         if (offset >= LAPIC_MMIO_LENGTH)
 562                 return 0;
 563
 564         switch (offset) {
 565         case APIC_ID:
 566                 if (apic_x2apic_mode(apic))
 567                         val = kvm_apic_id(apic);
 568                 else
 569                         val = kvm_apic_id(apic) << 24;
 570                 break;
 571         case APIC_ARBPRI:
 572                 printk(KERN_WARNING "Access APIC ARBPRI register "
 573                        "which is for P6\n");
 574                 break;
 575
 576         case APIC_TMCCT:        /* Timer CCR */
 577                 val = apic_get_tmcct(apic);
 578                 break;
 579
 580         case APIC_TASKPRI:
 581                 report_tpr_access(apic, false);
 582                 /* fall thru */
 583         default:
 584                 apic_update_ppr(apic);
 585                 val = apic_get_reg(apic, offset);
 586                 break;
 587         }
 588
 589         return val;
 590 }
 591
 592 static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
 593 {
 594         return container_of(dev, struct kvm_lapic, dev);
 595 }
 596
 597 static int apic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
 598                 void *data)
 599 {
 600         unsigned char alignment = offset & 0xf;
 601         u32 result;
 602         /* this bitmask has a bit cleared for each reserver register */
 603         static const u64 rmask = 0x43ff01ffffffe70cULL;
 604
 605         if ((alignment + len) > 4) {
 606                 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
 607                            offset, len);
 608                 return 1;
 609         }
 610
 611         if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
 612                 apic_debug("KVM_APIC_READ: read reserved register %x\n",
 613                            offset);
 614                 return 1;
 615         }
 616
 617         result = __apic_read(apic, offset & ~0xf);
 618
 619         trace_kvm_apic_read(offset, result);
 620
 621         switch (len) {
 622         case 1:
 623         case 2:
 624         case 4:
 625                 memcpy(data, (char *)&result + alignment, len);
 626                 break;
 627         default:
 628                 printk(KERN_ERR "Local APIC read with len = %x, "
 629                        "should be 1,2, or 4 instead\n", len);
 630                 break;
 631         }
 632         return 0;
 633 }
 634
 635 static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
 636 {
 637         return apic_hw_enabled(apic) &&
 638             addr >= apic->base_address &&
 639             addr < apic->base_address + LAPIC_MMIO_LENGTH;
 640 }
 641
 642 static int apic_mmio_read(struct kvm_io_device *this,
 643                            gpa_t address, int len, void *data)
 644 {
 645         struct kvm_lapic *apic = to_lapic(this);
 646         u32 offset = address - apic->base_address;
 647
 648         if (!apic_mmio_in_range(apic, address))
 649                 return -EOPNOTSUPP;
 650
 651         apic_reg_read(apic, offset, len, data);
 652
 653         return 0;
 654 }
 655
 656 static void update_divide_count(struct kvm_lapic *apic)
 657 {
 658         u32 tmp1, tmp2, tdcr;
 659
 660         tdcr = apic_get_reg(apic, APIC_TDCR);
 661         tmp1 = tdcr & 0xf;
 662         tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
 663         apic->divide_count = 0x1 << (tmp2 & 0x7);
 664
 665         apic_debug("timer divide count is 0x%x\n",
 666                                    apic->divide_count);
 667 }
 668
 669 static void start_apic_timer(struct kvm_lapic *apic)
 670 {
 671         ktime_t now = apic->lapic_timer.timer.base->get_time();
 672
 673         apic->lapic_timer.period = (u64)apic_get_reg(apic, APIC_TMICT) *
 674                     APIC_BUS_CYCLE_NS * apic->divide_count;
 675         atomic_set(&apic->lapic_timer.pending, 0);
 676
 677         if (!apic->lapic_timer.period)
 678                 return;
 679         /*
 680          * Do not allow the guest to program periodic timers with small
 681          * interval, since the hrtimers are not throttled by the host
 682          * scheduler.
 683          */
 684         if (apic_lvtt_period(apic)) {
 685                 if (apic->lapic_timer.period < NSEC_PER_MSEC/2)
 686                         apic->lapic_timer.period = NSEC_PER_MSEC/2;
 687         }
 688
 689         hrtimer_start(&apic->lapic_timer.timer,
 690                       ktime_add_ns(now, apic->lapic_timer.period),
 691                       HRTIMER_MODE_ABS);
 692
 693         apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
 694                            PRIx64 ", "
 695                            "timer initial count 0x%x, period %lldns, "
 696                            "expire @ 0x%016" PRIx64 ".\n", __func__,
 697                            APIC_BUS_CYCLE_NS, ktime_to_ns(now),
 698                            apic_get_reg(apic, APIC_TMICT),
 699                            apic->lapic_timer.period,
 700                            ktime_to_ns(ktime_add_ns(now,
 701                                         apic->lapic_timer.period)));
 702 }
 703
 704 static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
 705 {
 706         int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
 707
 708         if (apic_lvt_nmi_mode(lvt0_val)) {
 709                 if (!nmi_wd_enabled) {
 710                         apic_debug("Receive NMI setting on APIC_LVT0 "
 711                                    "for cpu %d\n", apic->vcpu->vcpu_id);
 712                         apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
 713                 }
 714         } else if (nmi_wd_enabled)
 715                 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
 716 }
 717
 718 static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 719 {
 720         int ret = 0;
 721
 722         trace_kvm_apic_write(reg, val);
 723
 724         switch (reg) {
 725         case APIC_ID:           /* Local APIC ID */
 726                 if (!apic_x2apic_mode(apic))
 727                         apic_set_reg(apic, APIC_ID, val);
 728                 else
 729                         ret = 1;
 730                 break;
 731
 732         case APIC_TASKPRI:
 733                 report_tpr_access(apic, true);
 734                 apic_set_tpr(apic, val & 0xff);
 735                 break;
 736
 737         case APIC_EOI:
 738                 apic_set_eoi(apic);
 739                 break;
 740
 741         case APIC_LDR:
 742                 if (!apic_x2apic_mode(apic))
 743                         apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
 744                 else
 745                         ret = 1;
 746                 break;
 747
 748         case APIC_DFR:
 749                 if (!apic_x2apic_mode(apic))
 750                         apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
 751                 else
 752                         ret = 1;
 753                 break;
 754
 755         case APIC_SPIV: {
 756                 u32 mask = 0x3ff;
 757                 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
 758                         mask |= APIC_SPIV_DIRECTED_EOI;
 759                 apic_set_reg(apic, APIC_SPIV, val & mask);
 760                 if (!(val & APIC_SPIV_APIC_ENABLED)) {
 761                         int i;
 762                         u32 lvt_val;
 763
 764                         for (i = 0; i < APIC_LVT_NUM; i++) {
 765                                 lvt_val = apic_get_reg(apic,
 766                                                        APIC_LVTT + 0x10 * i);
 767                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
 768                                              lvt_val | APIC_LVT_MASKED);
 769                         }
 770                         atomic_set(&apic->lapic_timer.pending, 0);
 771
 772                 }
 773                 break;
 774         }
 775         case APIC_ICR:
 776                 /* No delay here, so we always clear the pending bit */
 777                 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
 778                 apic_send_ipi(apic);
 779                 break;
 780
 781         case APIC_ICR2:
 782                 if (!apic_x2apic_mode(apic))
 783                         val &= 0xff000000;
 784                 apic_set_reg(apic, APIC_ICR2, val);
 785                 break;
 786
 787         case APIC_LVT0:
 788                 apic_manage_nmi_watchdog(apic, val);
 789         case APIC_LVTT:
 790         case APIC_LVTTHMR:
 791         case APIC_LVTPC:
 792         case APIC_LVT1:
 793         case APIC_LVTERR:
 794                 /* TODO: Check vector */
 795                 if (!apic_sw_enabled(apic))
 796                         val |= APIC_LVT_MASKED;
 797
 798                 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
 799                 apic_set_reg(apic, reg, val);
 800
 801                 break;
 802
 803         case APIC_TMICT:
 804                 hrtimer_cancel(&apic->lapic_timer.timer);
 805                 apic_set_reg(apic, APIC_TMICT, val);
 806                 start_apic_timer(apic);
 807                 break;
 808
 809         case APIC_TDCR:
 810                 if (val & 4)
 811                         printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
 812                 apic_set_reg(apic, APIC_TDCR, val);
 813                 update_divide_count(apic);
 814                 break;
 815
 816         case APIC_ESR:
 817                 if (apic_x2apic_mode(apic) && val != 0) {
 818                         printk(KERN_ERR "KVM_WRITE:ESR not zero %x\n", val);
 819                         ret = 1;
 820                 }
 821                 break;
 822
 823         case APIC_SELF_IPI:
 824                 if (apic_x2apic_mode(apic)) {
 825                         apic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
 826                 } else
 827                         ret = 1;
 828                 break;
 829         default:
 830                 ret = 1;
 831                 break;
 832         }
 833         if (ret)
 834                 apic_debug("Local APIC Write to read-only register %x\n", reg);
 835         return ret;
 836 }
 837
 838 static int apic_mmio_write(struct kvm_io_device *this,
 839                             gpa_t address, int len, const void *data)
 840 {
 841         struct kvm_lapic *apic = to_lapic(this);
 842         unsigned int offset = address - apic->base_address;
 843         u32 val;
 844
 845         if (!apic_mmio_in_range(apic, address))
 846                 return -EOPNOTSUPP;
 847
 848         /*
 849          * APIC register must be aligned on 128-bits boundary.
 850          * 32/64/128 bits registers must be accessed thru 32 bits.
 851          * Refer SDM 8.4.1
 852          */
 853         if (len != 4 || (offset & 0xf)) {
 854                 /* Don't shout loud, $infamous_os would cause only noise. */
 855                 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
 856                 return 0;
 857         }
 858
 859         val = *(u32*)data;
 860
 861         /* too common printing */
 862         if (offset != APIC_EOI)
 863                 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
 864                            "0x%x\n", __func__, offset, len, val);
 865
 866         apic_reg_write(apic, offset & 0xff0, val);
 867
 868         return 0;
 869 }
 870
 871 void kvm_free_lapic(struct kvm_vcpu *vcpu)
 872 {
 873         if (!vcpu->arch.apic)
 874                 return;
 875
 876         hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
 877
 878         if (vcpu->arch.apic->regs_page)
 879                 __free_page(vcpu->arch.apic->regs_page);
 880
 881         kfree(vcpu->arch.apic);
 882 }
 883
 884 /*
 885  *----------------------------------------------------------------------
 886  * LAPIC interface
 887  *----------------------------------------------------------------------
 888  */
 889
 890 void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
 891 {
 892         struct kvm_lapic *apic = vcpu->arch.apic;
 893
 894         if (!apic)
 895                 return;
 896         apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
 897                      | (apic_get_reg(apic, APIC_TASKPRI) & 4));
 898 }
 899
 900 u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
 901 {
 902         struct kvm_lapic *apic = vcpu->arch.apic;
 903         u64 tpr;
 904
 905         if (!apic)
 906                 return 0;
 907         tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
 908
 909         return (tpr & 0xf0) >> 4;
 910 }
 911
 912 void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
 913 {
 914         struct kvm_lapic *apic = vcpu->arch.apic;
 915
 916         if (!apic) {
 917                 value |= MSR_IA32_APICBASE_BSP;
 918                 vcpu->arch.apic_base = value;
 919                 return;
 920         }
 921
 922         if (!kvm_vcpu_is_bsp(apic->vcpu))
 923                 value &= ~MSR_IA32_APICBASE_BSP;
 924
 925         vcpu->arch.apic_base = value;
 926         if (apic_x2apic_mode(apic)) {
 927                 u32 id = kvm_apic_id(apic);
 928                 u32 ldr = ((id & ~0xf) << 16) | (1 << (id & 0xf));
 929                 apic_set_reg(apic, APIC_LDR, ldr);
 930         }
 931         apic->base_address = apic->vcpu->arch.apic_base &
 932                              MSR_IA32_APICBASE_BASE;
 933
 934         /* with FSB delivery interrupt, we can restart APIC functionality */
 935         apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
 936                    "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
 937
 938 }
 939
 940 void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 941 {
 942         struct kvm_lapic *apic;
 943         int i;
 944
 945         apic_debug("%s\n", __func__);
 946
 947         ASSERT(vcpu);
 948         apic = vcpu->arch.apic;
 949         ASSERT(apic != NULL);
 950
 951         /* Stop the timer in case it's a reset to an active apic */
 952         hrtimer_cancel(&apic->lapic_timer.timer);
 953
 954         apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
 955         kvm_apic_set_version(apic->vcpu);
 956
 957         for (i = 0; i < APIC_LVT_NUM; i++)
 958                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
 959         apic_set_reg(apic, APIC_LVT0,
 960                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 961
 962         apic_set_reg(apic, APIC_DFR, 0xffffffffU);
 963         apic_set_reg(apic, APIC_SPIV, 0xff);
 964         apic_set_reg(apic, APIC_TASKPRI, 0);
 965         apic_set_reg(apic, APIC_LDR, 0);
 966         apic_set_reg(apic, APIC_ESR, 0);
 967         apic_set_reg(apic, APIC_ICR, 0);
 968         apic_set_reg(apic, APIC_ICR2, 0);
 969         apic_set_reg(apic, APIC_TDCR, 0);
 970         apic_set_reg(apic, APIC_TMICT, 0);
 971         for (i = 0; i < 8; i++) {
 972                 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
 973                 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
 974                 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
 975         }
 976         apic->irr_pending = false;
 977         update_divide_count(apic);
 978         atomic_set(&apic->lapic_timer.pending, 0);
 979         if (kvm_vcpu_is_bsp(vcpu))
 980                 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
 981         apic_update_ppr(apic);
 982
 983         vcpu->arch.apic_arb_prio = 0;
 984
 985         apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
 986                    "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
 987                    vcpu, kvm_apic_id(apic),
 988                    vcpu->arch.apic_base, apic->base_address);
 989 }
 990
 991 bool kvm_apic_present(struct kvm_vcpu *vcpu)
 992 {
 993         return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
 994 }
 995
 996 int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
 997 {
 998         return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
 999 }
1000
1001 /*
1002  *----------------------------------------------------------------------
1003  * timer interface
1004  *----------------------------------------------------------------------
1005  */
1006
1007 static bool lapic_is_periodic(struct kvm_timer *ktimer)
1008 {
1009         struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
1010                                               lapic_timer);
1011         return apic_lvtt_period(apic);
1012 }
1013
1014 int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1015 {
1016         struct kvm_lapic *lapic = vcpu->arch.apic;
1017
1018         if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
1019                 return atomic_read(&lapic->lapic_timer.pending);
1020
1021         return 0;
1022 }
1023
1024 static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1025 {
1026         u32 reg = apic_get_reg(apic, lvt_type);
1027         int vector, mode, trig_mode;
1028
1029         if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
1030                 vector = reg & APIC_VECTOR_MASK;
1031                 mode = reg & APIC_MODE_MASK;
1032                 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
1033                 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
1034         }
1035         return 0;
1036 }
1037
1038 void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
1039 {
1040         struct kvm_lapic *apic = vcpu->arch.apic;
1041
1042         if (apic)
1043                 kvm_apic_local_deliver(apic, APIC_LVT0);
1044 }
1045
1046 static struct kvm_timer_ops lapic_timer_ops = {
1047         .is_periodic = lapic_is_periodic,
1048 };
1049
1050 static const struct kvm_io_device_ops apic_mmio_ops = {
1051         .read     = apic_mmio_read,
1052         .write    = apic_mmio_write,
1053 };
1054
1055 int kvm_create_lapic(struct kvm_vcpu *vcpu)
1056 {
1057         struct kvm_lapic *apic;
1058
1059         ASSERT(vcpu != NULL);
1060         apic_debug("apic_init %d\n", vcpu->vcpu_id);
1061
1062         apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1063         if (!apic)
1064                 goto nomem;
1065
1066         vcpu->arch.apic = apic;
1067
1068         apic->regs_page = alloc_page(GFP_KERNEL|__GFP_ZERO);
1069         if (apic->regs_page == NULL) {
1070                 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1071                        vcpu->vcpu_id);
1072                 goto nomem_free_apic;
1073         }
1074         apic->regs = page_address(apic->regs_page);
1075         apic->vcpu = vcpu;
1076
1077         hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
1078                      HRTIMER_MODE_ABS);
1079         apic->lapic_timer.timer.function = kvm_timer_fn;
1080         apic->lapic_timer.t_ops = &lapic_timer_ops;
1081         apic->lapic_timer.kvm = vcpu->kvm;
1082         apic->lapic_timer.vcpu = vcpu;
1083
1084         apic->base_address = APIC_DEFAULT_PHYS_BASE;
1085         vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
1086
1087         kvm_lapic_reset(vcpu);
1088         kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
1089
1090         return 0;
1091 nomem_free_apic:
1092         kfree(apic);
1093 nomem:
1094         return -ENOMEM;
1095 }
1096
1097 int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1098 {
1099         struct kvm_lapic *apic = vcpu->arch.apic;
1100         int highest_irr;
1101
1102         if (!apic || !apic_enabled(apic))
1103                 return -1;
1104
1105         apic_update_ppr(apic);
1106         highest_irr = apic_find_highest_irr(apic);
1107         if ((highest_irr == -1) ||
1108             ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1109                 return -1;
1110         return highest_irr;
1111 }
1112
1113 int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1114 {
1115         u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
1116         int r = 0;
1117
1118         if (!apic_hw_enabled(vcpu->arch.apic))
1119                 r = 1;
1120         if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1121             GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1122                 r = 1;
1123         return r;
1124 }
1125
1126 void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1127 {
1128         struct kvm_lapic *apic = vcpu->arch.apic;
1129
1130         if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
1131                 if (kvm_apic_local_deliver(apic, APIC_LVTT))
1132                         atomic_dec(&apic->lapic_timer.pending);
1133         }
1134 }
1135
1136 int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1137 {
1138         int vector = kvm_apic_has_interrupt(vcpu);
1139         struct kvm_lapic *apic = vcpu->arch.apic;
1140
1141         if (vector == -1)
1142                 return -1;
1143
1144         apic_set_vector(vector, apic->regs + APIC_ISR);
1145         apic_update_ppr(apic);
1146         apic_clear_irr(vector, apic);
1147         return vector;
1148 }
1149
1150 void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1151 {
1152         struct kvm_lapic *apic = vcpu->arch.apic;
1153
1154         apic->base_address = vcpu->arch.apic_base &
1155                              MSR_IA32_APICBASE_BASE;
1156         kvm_apic_set_version(vcpu);
1157
1158         apic_update_ppr(apic);
1159         hrtimer_cancel(&apic->lapic_timer.timer);
1160         update_divide_count(apic);
1161         start_apic_timer(apic);
1162         apic->irr_pending = true;
1163         kvm_make_request(KVM_REQ_EVENT, vcpu);
1164 }
1165
1166 void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
1167 {
1168         struct kvm_lapic *apic = vcpu->arch.apic;
1169         struct hrtimer *timer;
1170
1171         if (!apic)
1172                 return;
1173
1174         timer = &apic->lapic_timer.timer;
1175         if (hrtimer_cancel(timer))
1176                 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
1177 }
1178
1179 void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1180 {
1181         u32 data;
1182         void *vapic;
1183
1184         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1185                 return;
1186
1187         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1188         data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1189         kunmap_atomic(vapic, KM_USER0);
1190
1191         apic_set_tpr(vcpu->arch.apic, data & 0xff);
1192 }
1193
1194 void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1195 {
1196         u32 data, tpr;
1197         int max_irr, max_isr;
1198         struct kvm_lapic *apic;
1199         void *vapic;
1200
1201         if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1202                 return;
1203
1204         apic = vcpu->arch.apic;
1205         tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1206         max_irr = apic_find_highest_irr(apic);
1207         if (max_irr < 0)
1208                 max_irr = 0;
1209         max_isr = apic_find_highest_isr(apic);
1210         if (max_isr < 0)
1211                 max_isr = 0;
1212         data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1213
1214         vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1215         *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1216         kunmap_atomic(vapic, KM_USER0);
1217 }
1218
1219 void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1220 {
1221         if (!irqchip_in_kernel(vcpu->kvm))
1222                 return;
1223
1224         vcpu->arch.apic->vapic_addr = vapic_addr;
1225 }
1226
1227 int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
1228 {
1229         struct kvm_lapic *apic = vcpu->arch.apic;
1230         u32 reg = (msr - APIC_BASE_MSR) << 4;
1231
1232         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1233                 return 1;
1234
1235         /* if this is ICR write vector before command */
1236         if (msr == 0x830)
1237                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1238         return apic_reg_write(apic, reg, (u32)data);
1239 }
1240
1241 int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
1242 {
1243         struct kvm_lapic *apic = vcpu->arch.apic;
1244         u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
1245
1246         if (!irqchip_in_kernel(vcpu->kvm) || !apic_x2apic_mode(apic))
1247                 return 1;
1248
1249         if (apic_reg_read(apic, reg, 4, &low))
1250                 return 1;
1251         if (msr == 0x830)
1252                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1253
1254         *data = (((u64)high) << 32) | low;
1255
1256         return 0;
1257 }
1258
1259 int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
1260 {
1261         struct kvm_lapic *apic = vcpu->arch.apic;
1262
1263         if (!irqchip_in_kernel(vcpu->kvm))
1264                 return 1;
1265
1266         /* if this is ICR write vector before command */
1267         if (reg == APIC_ICR)
1268                 apic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
1269         return apic_reg_write(apic, reg, (u32)data);
1270 }
1271
1272 int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
1273 {
1274         struct kvm_lapic *apic = vcpu->arch.apic;
1275         u32 low, high = 0;
1276
1277         if (!irqchip_in_kernel(vcpu->kvm))
1278                 return 1;
1279
1280         if (apic_reg_read(apic, reg, 4, &low))
1281                 return 1;
1282         if (reg == APIC_ICR)
1283                 apic_reg_read(apic, APIC_ICR2, 4, &high);
1284
1285         *data = (((u64)high) << 32) | low;
1286
1287         return 0;
1288 }