arch/x86/kvm/i8259.c

   1 /*
   2  * 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  * Copyright (c) 2007 Intel Corporation
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  * Authors:
  25  *   Yaozu (Eddie) Dong <Eddie.dong@intel.com>
  26  *   Port from Qemu.
  27  */
  28 #include <linux/mm.h>
  29 #include <linux/slab.h>
  30 #include <linux/bitops.h>
  31 #include "irq.h"
  32
  33 #include <linux/kvm_host.h>
  34 #include "trace.h"
  35
  36 static void pic_clear_isr(struct kvm_kpic_state *s, int irq)
  37 {
  38         s->isr &= ~(1 << irq);
  39         s->isr_ack |= (1 << irq);
  40         if (s != &s->pics_state->pics[0])
  41                 irq += 8;
  42         /*
  43          * We are dropping lock while calling ack notifiers since ack
  44          * notifier callbacks for assigned devices call into PIC recursively.
  45          * Other interrupt may be delivered to PIC while lock is dropped but
  46          * it should be safe since PIC state is already updated at this stage.
  47          */
  48         raw_spin_unlock(&s->pics_state->lock);
  49         kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq);
  50         raw_spin_lock(&s->pics_state->lock);
  51 }
  52
  53 void kvm_pic_clear_isr_ack(struct kvm *kvm)
  54 {
  55         struct kvm_pic *s = pic_irqchip(kvm);
  56
  57         raw_spin_lock(&s->lock);
  58         s->pics[0].isr_ack = 0xff;
  59         s->pics[1].isr_ack = 0xff;
  60         raw_spin_unlock(&s->lock);
  61 }
  62
  63 /*
  64  * set irq level. If an edge is detected, then the IRR is set to 1
  65  */
  66 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level)
  67 {
  68         int mask, ret = 1;
  69         mask = 1 << irq;
  70         if (s->elcr & mask)     /* level triggered */
  71                 if (level) {
  72                         ret = !(s->irr & mask);
  73                         s->irr |= mask;
  74                         s->last_irr |= mask;
  75                 } else {
  76                         s->irr &= ~mask;
  77                         s->last_irr &= ~mask;
  78                 }
  79         else    /* edge triggered */
  80                 if (level) {
  81                         if ((s->last_irr & mask) == 0) {
  82                                 ret = !(s->irr & mask);
  83                                 s->irr |= mask;
  84                         }
  85                         s->last_irr |= mask;
  86                 } else
  87                         s->last_irr &= ~mask;
  88
  89         return (s->imr & mask) ? -1 : ret;
  90 }
  91
  92 /*
  93  * return the highest priority found in mask (highest = smallest
  94  * number). Return 8 if no irq
  95  */
  96 static inline int get_priority(struct kvm_kpic_state *s, int mask)
  97 {
  98         int priority;
  99         if (mask == 0)
 100                 return 8;
 101         priority = 0;
 102         while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 103                 priority++;
 104         return priority;
 105 }
 106
 107 /*
 108  * return the pic wanted interrupt. return -1 if none
 109  */
 110 static int pic_get_irq(struct kvm_kpic_state *s)
 111 {
 112         int mask, cur_priority, priority;
 113
 114         mask = s->irr & ~s->imr;
 115         priority = get_priority(s, mask);
 116         if (priority == 8)
 117                 return -1;
 118         /*
 119          * compute current priority. If special fully nested mode on the
 120          * master, the IRQ coming from the slave is not taken into account
 121          * for the priority computation.
 122          */
 123         mask = s->isr;
 124         if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 125                 mask &= ~(1 << 2);
 126         cur_priority = get_priority(s, mask);
 127         if (priority < cur_priority)
 128                 /*
 129                  * higher priority found: an irq should be generated
 130                  */
 131                 return (priority + s->priority_add) & 7;
 132         else
 133                 return -1;
 134 }
 135
 136 /*
 137  * raise irq to CPU if necessary. must be called every time the active
 138  * irq may change
 139  */
 140 static void pic_update_irq(struct kvm_pic *s)
 141 {
 142         int irq2, irq;
 143
 144         irq2 = pic_get_irq(&s->pics[1]);
 145         if (irq2 >= 0) {
 146                 /*
 147                  * if irq request by slave pic, signal master PIC
 148                  */
 149                 pic_set_irq1(&s->pics[0], 2, 1);
 150                 pic_set_irq1(&s->pics[0], 2, 0);
 151         }
 152         irq = pic_get_irq(&s->pics[0]);
 153         if (irq >= 0)
 154                 s->irq_request(s->irq_request_opaque, 1);
 155         else
 156                 s->irq_request(s->irq_request_opaque, 0);
 157 }
 158
 159 void kvm_pic_update_irq(struct kvm_pic *s)
 160 {
 161         raw_spin_lock(&s->lock);
 162         pic_update_irq(s);
 163         raw_spin_unlock(&s->lock);
 164 }
 165
 166 int kvm_pic_set_irq(void *opaque, int irq, int level)
 167 {
 168         struct kvm_pic *s = opaque;
 169         int ret = -1;
 170
 171         raw_spin_lock(&s->lock);
 172         if (irq >= 0 && irq < PIC_NUM_PINS) {
 173                 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 174                 pic_update_irq(s);
 175                 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr,
 176                                       s->pics[irq >> 3].imr, ret == 0);
 177         }
 178         raw_spin_unlock(&s->lock);
 179
 180         return ret;
 181 }
 182
 183 /*
 184  * acknowledge interrupt 'irq'
 185  */
 186 static inline void pic_intack(struct kvm_kpic_state *s, int irq)
 187 {
 188         s->isr |= 1 << irq;
 189         /*
 190          * We don't clear a level sensitive interrupt here
 191          */
 192         if (!(s->elcr & (1 << irq)))
 193                 s->irr &= ~(1 << irq);
 194
 195         if (s->auto_eoi) {
 196                 if (s->rotate_on_auto_eoi)
 197                         s->priority_add = (irq + 1) & 7;
 198                 pic_clear_isr(s, irq);
 199         }
 200
 201 }
 202
 203 int kvm_pic_read_irq(struct kvm *kvm)
 204 {
 205         int irq, irq2, intno;
 206         struct kvm_pic *s = pic_irqchip(kvm);
 207
 208         raw_spin_lock(&s->lock);
 209         irq = pic_get_irq(&s->pics[0]);
 210         if (irq >= 0) {
 211                 pic_intack(&s->pics[0], irq);
 212                 if (irq == 2) {
 213                         irq2 = pic_get_irq(&s->pics[1]);
 214                         if (irq2 >= 0)
 215                                 pic_intack(&s->pics[1], irq2);
 216                         else
 217                                 /*
 218                                  * spurious IRQ on slave controller
 219                                  */
 220                                 irq2 = 7;
 221                         intno = s->pics[1].irq_base + irq2;
 222                         irq = irq2 + 8;
 223                 } else
 224                         intno = s->pics[0].irq_base + irq;
 225         } else {
 226                 /*
 227                  * spurious IRQ on host controller
 228                  */
 229                 irq = 7;
 230                 intno = s->pics[0].irq_base + irq;
 231         }
 232         pic_update_irq(s);
 233         raw_spin_unlock(&s->lock);
 234
 235         return intno;
 236 }
 237
 238 void kvm_pic_reset(struct kvm_kpic_state *s)
 239 {
 240         int irq;
 241         struct kvm *kvm = s->pics_state->irq_request_opaque;
 242         struct kvm_vcpu *vcpu0 = kvm->bsp_vcpu;
 243         u8 irr = s->irr, isr = s->imr;
 244
 245         s->last_irr = 0;
 246         s->irr = 0;
 247         s->imr = 0;
 248         s->isr = 0;
 249         s->isr_ack = 0xff;
 250         s->priority_add = 0;
 251         s->irq_base = 0;
 252         s->read_reg_select = 0;
 253         s->poll = 0;
 254         s->special_mask = 0;
 255         s->init_state = 0;
 256         s->auto_eoi = 0;
 257         s->rotate_on_auto_eoi = 0;
 258         s->special_fully_nested_mode = 0;
 259         s->init4 = 0;
 260
 261         for (irq = 0; irq < PIC_NUM_PINS/2; irq++) {
 262                 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0))
 263                         if (irr & (1 << irq) || isr & (1 << irq)) {
 264                                 pic_clear_isr(s, irq);
 265                         }
 266         }
 267 }
 268
 269 static void pic_ioport_write(void *opaque, u32 addr, u32 val)
 270 {
 271         struct kvm_kpic_state *s = opaque;
 272         int priority, cmd, irq;
 273
 274         addr &= 1;
 275         if (addr == 0) {
 276                 if (val & 0x10) {
 277                         kvm_pic_reset(s);       /* init */
 278                         /*
 279                          * deassert a pending interrupt
 280                          */
 281                         s->pics_state->irq_request(s->pics_state->
 282                                                    irq_request_opaque, 0);
 283                         s->init_state = 1;
 284                         s->init4 = val & 1;
 285                         if (val & 0x02)
 286                                 printk(KERN_ERR "single mode not supported");
 287                         if (val & 0x08)
 288                                 printk(KERN_ERR
 289                                        "level sensitive irq not supported");
 290                 } else if (val & 0x08) {
 291                         if (val & 0x04)
 292                                 s->poll = 1;
 293                         if (val & 0x02)
 294                                 s->read_reg_select = val & 1;
 295                         if (val & 0x40)
 296                                 s->special_mask = (val >> 5) & 1;
 297                 } else {
 298                         cmd = val >> 5;
 299                         switch (cmd) {
 300                         case 0:
 301                         case 4:
 302                                 s->rotate_on_auto_eoi = cmd >> 2;
 303                                 break;
 304                         case 1: /* end of interrupt */
 305                         case 5:
 306                                 priority = get_priority(s, s->isr);
 307                                 if (priority != 8) {
 308                                         irq = (priority + s->priority_add) & 7;
 309                                         if (cmd == 5)
 310                                                 s->priority_add = (irq + 1) & 7;
 311                                         pic_clear_isr(s, irq);
 312                                         pic_update_irq(s->pics_state);
 313                                 }
 314                                 break;
 315                         case 3:
 316                                 irq = val & 7;
 317                                 pic_clear_isr(s, irq);
 318                                 pic_update_irq(s->pics_state);
 319                                 break;
 320                         case 6:
 321                                 s->priority_add = (val + 1) & 7;
 322                                 pic_update_irq(s->pics_state);
 323                                 break;
 324                         case 7:
 325                                 irq = val & 7;
 326                                 s->priority_add = (irq + 1) & 7;
 327                                 pic_clear_isr(s, irq);
 328                                 pic_update_irq(s->pics_state);
 329                                 break;
 330                         default:
 331                                 break;  /* no operation */
 332                         }
 333                 }
 334         } else
 335                 switch (s->init_state) {
 336                 case 0:         /* normal mode */
 337                         s->imr = val;
 338                         pic_update_irq(s->pics_state);
 339                         break;
 340                 case 1:
 341                         s->irq_base = val & 0xf8;
 342                         s->init_state = 2;
 343                         break;
 344                 case 2:
 345                         if (s->init4)
 346                                 s->init_state = 3;
 347                         else
 348                                 s->init_state = 0;
 349                         break;
 350                 case 3:
 351                         s->special_fully_nested_mode = (val >> 4) & 1;
 352                         s->auto_eoi = (val >> 1) & 1;
 353                         s->init_state = 0;
 354                         break;
 355                 }
 356 }
 357
 358 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1)
 359 {
 360         int ret;
 361
 362         ret = pic_get_irq(s);
 363         if (ret >= 0) {
 364                 if (addr1 >> 7) {
 365                         s->pics_state->pics[0].isr &= ~(1 << 2);
 366                         s->pics_state->pics[0].irr &= ~(1 << 2);
 367                 }
 368                 s->irr &= ~(1 << ret);
 369                 pic_clear_isr(s, ret);
 370                 if (addr1 >> 7 || ret != 2)
 371                         pic_update_irq(s->pics_state);
 372         } else {
 373                 ret = 0x07;
 374                 pic_update_irq(s->pics_state);
 375         }
 376
 377         return ret;
 378 }
 379
 380 static u32 pic_ioport_read(void *opaque, u32 addr1)
 381 {
 382         struct kvm_kpic_state *s = opaque;
 383         unsigned int addr;
 384         int ret;
 385
 386         addr = addr1;
 387         addr &= 1;
 388         if (s->poll) {
 389                 ret = pic_poll_read(s, addr1);
 390                 s->poll = 0;
 391         } else
 392                 if (addr == 0)
 393                         if (s->read_reg_select)
 394                                 ret = s->isr;
 395                         else
 396                                 ret = s->irr;
 397                 else
 398                         ret = s->imr;
 399         return ret;
 400 }
 401
 402 static void elcr_ioport_write(void *opaque, u32 addr, u32 val)
 403 {
 404         struct kvm_kpic_state *s = opaque;
 405         s->elcr = val & s->elcr_mask;
 406 }
 407
 408 static u32 elcr_ioport_read(void *opaque, u32 addr1)
 409 {
 410         struct kvm_kpic_state *s = opaque;
 411         return s->elcr;
 412 }
 413
 414 static int picdev_in_range(gpa_t addr)
 415 {
 416         switch (addr) {
 417         case 0x20:
 418         case 0x21:
 419         case 0xa0:
 420         case 0xa1:
 421         case 0x4d0:
 422         case 0x4d1:
 423                 return 1;
 424         default:
 425                 return 0;
 426         }
 427 }
 428
 429 static inline struct kvm_pic *to_pic(struct kvm_io_device *dev)
 430 {
 431         return container_of(dev, struct kvm_pic, dev);
 432 }
 433
 434 static int picdev_write(struct kvm_io_device *this,
 435                          gpa_t addr, int len, const void *val)
 436 {
 437         struct kvm_pic *s = to_pic(this);
 438         unsigned char data = *(unsigned char *)val;
 439         if (!picdev_in_range(addr))
 440                 return -EOPNOTSUPP;
 441
 442         if (len != 1) {
 443                 if (printk_ratelimit())
 444                         printk(KERN_ERR "PIC: non byte write\n");
 445                 return 0;
 446         }
 447         raw_spin_lock(&s->lock);
 448         switch (addr) {
 449         case 0x20:
 450         case 0x21:
 451         case 0xa0:
 452         case 0xa1:
 453                 pic_ioport_write(&s->pics[addr >> 7], addr, data);
 454                 break;
 455         case 0x4d0:
 456         case 0x4d1:
 457                 elcr_ioport_write(&s->pics[addr & 1], addr, data);
 458                 break;
 459         }
 460         raw_spin_unlock(&s->lock);
 461         return 0;
 462 }
 463
 464 static int picdev_read(struct kvm_io_device *this,
 465                        gpa_t addr, int len, void *val)
 466 {
 467         struct kvm_pic *s = to_pic(this);
 468         unsigned char data = 0;
 469         if (!picdev_in_range(addr))
 470                 return -EOPNOTSUPP;
 471
 472         if (len != 1) {
 473                 if (printk_ratelimit())
 474                         printk(KERN_ERR "PIC: non byte read\n");
 475                 return 0;
 476         }
 477         raw_spin_lock(&s->lock);
 478         switch (addr) {
 479         case 0x20:
 480         case 0x21:
 481         case 0xa0:
 482         case 0xa1:
 483                 data = pic_ioport_read(&s->pics[addr >> 7], addr);
 484                 break;
 485         case 0x4d0:
 486         case 0x4d1:
 487                 data = elcr_ioport_read(&s->pics[addr & 1], addr);
 488                 break;
 489         }
 490         *(unsigned char *)val = data;
 491         raw_spin_unlock(&s->lock);
 492         return 0;
 493 }
 494
 495 /*
 496  * callback when PIC0 irq status changed
 497  */
 498 static void pic_irq_request(void *opaque, int level)
 499 {
 500         struct kvm *kvm = opaque;
 501         struct kvm_vcpu *vcpu = kvm->bsp_vcpu;
 502         struct kvm_pic *s = pic_irqchip(kvm);
 503         int irq = pic_get_irq(&s->pics[0]);
 504
 505         s->output = level;
 506         if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) {
 507                 s->pics[0].isr_ack &= ~(1 << irq);
 508                 kvm_vcpu_kick(vcpu);
 509         }
 510 }
 511
 512 static const struct kvm_io_device_ops picdev_ops = {
 513         .read     = picdev_read,
 514         .write    = picdev_write,
 515 };
 516
 517 struct kvm_pic *kvm_create_pic(struct kvm *kvm)
 518 {
 519         struct kvm_pic *s;
 520         int ret;
 521
 522         s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL);
 523         if (!s)
 524                 return NULL;
 525         raw_spin_lock_init(&s->lock);
 526         s->kvm = kvm;
 527         s->pics[0].elcr_mask = 0xf8;
 528         s->pics[1].elcr_mask = 0xde;
 529         s->irq_request = pic_irq_request;
 530         s->irq_request_opaque = kvm;
 531         s->pics[0].pics_state = s;
 532         s->pics[1].pics_state = s;
 533
 534         /*
 535          * Initialize PIO device
 536          */
 537         kvm_iodevice_init(&s->dev, &picdev_ops);
 538         mutex_lock(&kvm->slots_lock);
 539         ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &s->dev);
 540         mutex_unlock(&kvm->slots_lock);
 541         if (ret < 0) {
 542                 kfree(s);
 543                 return NULL;
 544         }
 545
 546         return s;
 547 }
 548
 549 void kvm_destroy_pic(struct kvm *kvm)
 550 {
 551         struct kvm_pic *vpic = kvm->arch.vpic;
 552
 553         if (vpic) {
 554                 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev);
 555                 kvm->arch.vpic = NULL;
 556                 kfree(vpic);
 557         }
 558 }