arch/x86/kernel/pci-calgary_64.c

   1 /*
   2  * Derived from arch/powerpc/kernel/iommu.c
   3  *
   4  * Copyright IBM Corporation, 2006-2007
   5  * Copyright (C) 2006  Jon Mason <jdmason@kudzu.us>
   6  *
   7  * Author: Jon Mason <jdmason@kudzu.us>
   8  * Author: Muli Ben-Yehuda <muli@il.ibm.com>
   9
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  23  */
  24
  25 #include <linux/kernel.h>
  26 #include <linux/init.h>
  27 #include <linux/types.h>
  28 #include <linux/slab.h>
  29 #include <linux/mm.h>
  30 #include <linux/spinlock.h>
  31 #include <linux/string.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/bitops.h>
  34 #include <linux/pci_ids.h>
  35 #include <linux/pci.h>
  36 #include <linux/delay.h>
  37 #include <linux/scatterlist.h>
  38 #include <linux/iommu-helper.h>
  39 #include <asm/gart.h>
  40 #include <asm/calgary.h>
  41 #include <asm/tce.h>
  42 #include <asm/pci-direct.h>
  43 #include <asm/system.h>
  44 #include <asm/dma.h>
  45 #include <asm/rio.h>
  46 #include <asm/bios_ebda.h>
  47
  48 #ifdef CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT
  49 int use_calgary __read_mostly = 1;
  50 #else
  51 int use_calgary __read_mostly = 0;
  52 #endif /* CONFIG_CALGARY_DEFAULT_ENABLED */
  53
  54 #define PCI_DEVICE_ID_IBM_CALGARY 0x02a1
  55 #define PCI_DEVICE_ID_IBM_CALIOC2 0x0308
  56
  57 /* register offsets inside the host bridge space */
  58 #define CALGARY_CONFIG_REG      0x0108
  59 #define PHB_CSR_OFFSET          0x0110 /* Channel Status */
  60 #define PHB_PLSSR_OFFSET        0x0120
  61 #define PHB_CONFIG_RW_OFFSET    0x0160
  62 #define PHB_IOBASE_BAR_LOW      0x0170
  63 #define PHB_IOBASE_BAR_HIGH     0x0180
  64 #define PHB_MEM_1_LOW           0x0190
  65 #define PHB_MEM_1_HIGH          0x01A0
  66 #define PHB_IO_ADDR_SIZE        0x01B0
  67 #define PHB_MEM_1_SIZE          0x01C0
  68 #define PHB_MEM_ST_OFFSET       0x01D0
  69 #define PHB_AER_OFFSET          0x0200
  70 #define PHB_CONFIG_0_HIGH       0x0220
  71 #define PHB_CONFIG_0_LOW        0x0230
  72 #define PHB_CONFIG_0_END        0x0240
  73 #define PHB_MEM_2_LOW           0x02B0
  74 #define PHB_MEM_2_HIGH          0x02C0
  75 #define PHB_MEM_2_SIZE_HIGH     0x02D0
  76 #define PHB_MEM_2_SIZE_LOW      0x02E0
  77 #define PHB_DOSHOLE_OFFSET      0x08E0
  78
  79 /* CalIOC2 specific */
  80 #define PHB_SAVIOR_L2           0x0DB0
  81 #define PHB_PAGE_MIG_CTRL       0x0DA8
  82 #define PHB_PAGE_MIG_DEBUG      0x0DA0
  83 #define PHB_ROOT_COMPLEX_STATUS 0x0CB0
  84
  85 /* PHB_CONFIG_RW */
  86 #define PHB_TCE_ENABLE          0x20000000
  87 #define PHB_SLOT_DISABLE        0x1C000000
  88 #define PHB_DAC_DISABLE         0x01000000
  89 #define PHB_MEM2_ENABLE         0x00400000
  90 #define PHB_MCSR_ENABLE         0x00100000
  91 /* TAR (Table Address Register) */
  92 #define TAR_SW_BITS             0x0000ffffffff800fUL
  93 #define TAR_VALID               0x0000000000000008UL
  94 /* CSR (Channel/DMA Status Register) */
  95 #define CSR_AGENT_MASK          0xffe0ffff
  96 /* CCR (Calgary Configuration Register) */
  97 #define CCR_2SEC_TIMEOUT        0x000000000000000EUL
  98 /* PMCR/PMDR (Page Migration Control/Debug Registers */
  99 #define PMR_SOFTSTOP            0x80000000
 100 #define PMR_SOFTSTOPFAULT       0x40000000
 101 #define PMR_HARDSTOP            0x20000000
 102
 103 #define MAX_NUM_OF_PHBS         8 /* how many PHBs in total? */
 104 #define MAX_NUM_CHASSIS         8 /* max number of chassis */
 105 /* MAX_PHB_BUS_NUM is the maximal possible dev->bus->number */
 106 #define MAX_PHB_BUS_NUM         (MAX_NUM_OF_PHBS * MAX_NUM_CHASSIS * 2)
 107 #define PHBS_PER_CALGARY        4
 108
 109 /* register offsets in Calgary's internal register space */
 110 static const unsigned long tar_offsets[] = {
 111         0x0580 /* TAR0 */,
 112         0x0588 /* TAR1 */,
 113         0x0590 /* TAR2 */,
 114         0x0598 /* TAR3 */
 115 };
 116
 117 static const unsigned long split_queue_offsets[] = {
 118         0x4870 /* SPLIT QUEUE 0 */,
 119         0x5870 /* SPLIT QUEUE 1 */,
 120         0x6870 /* SPLIT QUEUE 2 */,
 121         0x7870 /* SPLIT QUEUE 3 */
 122 };
 123
 124 static const unsigned long phb_offsets[] = {
 125         0x8000 /* PHB0 */,
 126         0x9000 /* PHB1 */,
 127         0xA000 /* PHB2 */,
 128         0xB000 /* PHB3 */
 129 };
 130
 131 /* PHB debug registers */
 132
 133 static const unsigned long phb_debug_offsets[] = {
 134         0x4000  /* PHB 0 DEBUG */,
 135         0x5000  /* PHB 1 DEBUG */,
 136         0x6000  /* PHB 2 DEBUG */,
 137         0x7000  /* PHB 3 DEBUG */
 138 };
 139
 140 /*
 141  * STUFF register for each debug PHB,
 142  * byte 1 = start bus number, byte 2 = end bus number
 143  */
 144
 145 #define PHB_DEBUG_STUFF_OFFSET  0x0020
 146
 147 #define EMERGENCY_PAGES 32 /* = 128KB */
 148
 149 unsigned int specified_table_size = TCE_TABLE_SIZE_UNSPECIFIED;
 150 static int translate_empty_slots __read_mostly = 0;
 151 static int calgary_detected __read_mostly = 0;
 152
 153 static struct rio_table_hdr     *rio_table_hdr __initdata;
 154 static struct scal_detail       *scal_devs[MAX_NUMNODES] __initdata;
 155 static struct rio_detail        *rio_devs[MAX_NUMNODES * 4] __initdata;
 156
 157 struct calgary_bus_info {
 158         void *tce_space;
 159         unsigned char translation_disabled;
 160         signed char phbid;
 161         void __iomem *bbar;
 162 };
 163
 164 static void calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 165 static void calgary_tce_cache_blast(struct iommu_table *tbl);
 166 static void calgary_dump_error_regs(struct iommu_table *tbl);
 167 static void calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev);
 168 static void calioc2_tce_cache_blast(struct iommu_table *tbl);
 169 static void calioc2_dump_error_regs(struct iommu_table *tbl);
 170
 171 static struct cal_chipset_ops calgary_chip_ops = {
 172         .handle_quirks = calgary_handle_quirks,
 173         .tce_cache_blast = calgary_tce_cache_blast,
 174         .dump_error_regs = calgary_dump_error_regs
 175 };
 176
 177 static struct cal_chipset_ops calioc2_chip_ops = {
 178         .handle_quirks = calioc2_handle_quirks,
 179         .tce_cache_blast = calioc2_tce_cache_blast,
 180         .dump_error_regs = calioc2_dump_error_regs
 181 };
 182
 183 static struct calgary_bus_info bus_info[MAX_PHB_BUS_NUM] = { { NULL, 0, 0 }, };
 184
 185 /* enable this to stress test the chip's TCE cache */
 186 #ifdef CONFIG_IOMMU_DEBUG
 187 static int debugging = 1;
 188
 189 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 190         int expected, unsigned long start, unsigned long end)
 191 {
 192         unsigned long idx = start;
 193
 194         BUG_ON(start >= end);
 195
 196         while (idx < end) {
 197                 if (!!test_bit(idx, bitmap) != expected)
 198                         return idx;
 199                 ++idx;
 200         }
 201
 202         /* all bits have the expected value */
 203         return ~0UL;
 204 }
 205 #else /* debugging is disabled */
 206 static int debugging;
 207
 208 static inline unsigned long verify_bit_range(unsigned long* bitmap,
 209         int expected, unsigned long start, unsigned long end)
 210 {
 211         return ~0UL;
 212 }
 213
 214 #endif /* CONFIG_IOMMU_DEBUG */
 215
 216 static inline unsigned int num_dma_pages(unsigned long dma, unsigned int dmalen)
 217 {
 218         unsigned int npages;
 219
 220         npages = PAGE_ALIGN(dma + dmalen) - (dma & PAGE_MASK);
 221         npages >>= PAGE_SHIFT;
 222
 223         return npages;
 224 }
 225
 226 static inline int translation_enabled(struct iommu_table *tbl)
 227 {
 228         /* only PHBs with translation enabled have an IOMMU table */
 229         return (tbl != NULL);
 230 }
 231
 232 static void iommu_range_reserve(struct iommu_table *tbl,
 233         unsigned long start_addr, unsigned int npages)
 234 {
 235         unsigned long index;
 236         unsigned long end;
 237         unsigned long badbit;
 238         unsigned long flags;
 239
 240         index = start_addr >> PAGE_SHIFT;
 241
 242         /* bail out if we're asked to reserve a region we don't cover */
 243         if (index >= tbl->it_size)
 244                 return;
 245
 246         end = index + npages;
 247         if (end > tbl->it_size) /* don't go off the table */
 248                 end = tbl->it_size;
 249
 250         spin_lock_irqsave(&tbl->it_lock, flags);
 251
 252         badbit = verify_bit_range(tbl->it_map, 0, index, end);
 253         if (badbit != ~0UL) {
 254                 if (printk_ratelimit())
 255                         printk(KERN_ERR "Calgary: entry already allocated at "
 256                                "0x%lx tbl %p dma 0x%lx npages %u\n",
 257                                badbit, tbl, start_addr, npages);
 258         }
 259
 260         set_bit_string(tbl->it_map, index, npages);
 261
 262         spin_unlock_irqrestore(&tbl->it_lock, flags);
 263 }
 264
 265 static unsigned long iommu_range_alloc(struct device *dev,
 266                                        struct iommu_table *tbl,
 267                                        unsigned int npages)
 268 {
 269         unsigned long flags;
 270         unsigned long offset;
 271         unsigned long boundary_size;
 272
 273         boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
 274                               PAGE_SIZE) >> PAGE_SHIFT;
 275
 276         BUG_ON(npages == 0);
 277
 278         spin_lock_irqsave(&tbl->it_lock, flags);
 279
 280         offset = iommu_area_alloc(tbl->it_map, tbl->it_size, tbl->it_hint,
 281                                   npages, 0, boundary_size, 0);
 282         if (offset == ~0UL) {
 283                 tbl->chip_ops->tce_cache_blast(tbl);
 284
 285                 offset = iommu_area_alloc(tbl->it_map, tbl->it_size, 0,
 286                                           npages, 0, boundary_size, 0);
 287                 if (offset == ~0UL) {
 288                         printk(KERN_WARNING "Calgary: IOMMU full.\n");
 289                         spin_unlock_irqrestore(&tbl->it_lock, flags);
 290                         if (panic_on_overflow)
 291                                 panic("Calgary: fix the allocator.\n");
 292                         else
 293                                 return bad_dma_address;
 294                 }
 295         }
 296
 297         tbl->it_hint = offset + npages;
 298         BUG_ON(tbl->it_hint > tbl->it_size);
 299
 300         spin_unlock_irqrestore(&tbl->it_lock, flags);
 301
 302         return offset;
 303 }
 304
 305 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
 306                               void *vaddr, unsigned int npages, int direction)
 307 {
 308         unsigned long entry;
 309         dma_addr_t ret = bad_dma_address;
 310
 311         entry = iommu_range_alloc(dev, tbl, npages);
 312
 313         if (unlikely(entry == bad_dma_address))
 314                 goto error;
 315
 316         /* set the return dma address */
 317         ret = (entry << PAGE_SHIFT) | ((unsigned long)vaddr & ~PAGE_MASK);
 318
 319         /* put the TCEs in the HW table */
 320         tce_build(tbl, entry, npages, (unsigned long)vaddr & PAGE_MASK,
 321                   direction);
 322
 323         return ret;
 324
 325 error:
 326         printk(KERN_WARNING "Calgary: failed to allocate %u pages in "
 327                "iommu %p\n", npages, tbl);
 328         return bad_dma_address;
 329 }
 330
 331 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
 332         unsigned int npages)
 333 {
 334         unsigned long entry;
 335         unsigned long badbit;
 336         unsigned long badend;
 337         unsigned long flags;
 338
 339         /* were we called with bad_dma_address? */
 340         badend = bad_dma_address + (EMERGENCY_PAGES * PAGE_SIZE);
 341         if (unlikely((dma_addr >= bad_dma_address) && (dma_addr < badend))) {
 342                 printk(KERN_ERR "Calgary: driver tried unmapping bad DMA "
 343                        "address 0x%Lx\n", dma_addr);
 344                 WARN_ON(1);
 345                 return;
 346         }
 347
 348         entry = dma_addr >> PAGE_SHIFT;
 349
 350         BUG_ON(entry + npages > tbl->it_size);
 351
 352         tce_free(tbl, entry, npages);
 353
 354         spin_lock_irqsave(&tbl->it_lock, flags);
 355
 356         badbit = verify_bit_range(tbl->it_map, 1, entry, entry + npages);
 357         if (badbit != ~0UL) {
 358                 if (printk_ratelimit())
 359                         printk(KERN_ERR "Calgary: bit is off at 0x%lx "
 360                                "tbl %p dma 0x%Lx entry 0x%lx npages %u\n",
 361                                badbit, tbl, dma_addr, entry, npages);
 362         }
 363
 364         iommu_area_free(tbl->it_map, entry, npages);
 365
 366         spin_unlock_irqrestore(&tbl->it_lock, flags);
 367 }
 368
 369 static inline struct iommu_table *find_iommu_table(struct device *dev)
 370 {
 371         struct pci_dev *pdev;
 372         struct pci_bus *pbus;
 373         struct iommu_table *tbl;
 374
 375         pdev = to_pci_dev(dev);
 376
 377         pbus = pdev->bus;
 378
 379         /* is the device behind a bridge? Look for the root bus */
 380         while (pbus->parent)
 381                 pbus = pbus->parent;
 382
 383         tbl = pci_iommu(pbus);
 384
 385         BUG_ON(tbl && (tbl->it_busno != pbus->number));
 386
 387         return tbl;
 388 }
 389
 390 static void calgary_unmap_sg(struct device *dev,
 391         struct scatterlist *sglist, int nelems, int direction)
 392 {
 393         struct iommu_table *tbl = find_iommu_table(dev);
 394         struct scatterlist *s;
 395         int i;
 396
 397         if (!translation_enabled(tbl))
 398                 return;
 399
 400         for_each_sg(sglist, s, nelems, i) {
 401                 unsigned int npages;
 402                 dma_addr_t dma = s->dma_address;
 403                 unsigned int dmalen = s->dma_length;
 404
 405                 if (dmalen == 0)
 406                         break;
 407
 408                 npages = num_dma_pages(dma, dmalen);
 409                 iommu_free(tbl, dma, npages);
 410         }
 411 }
 412
 413 static int calgary_nontranslate_map_sg(struct device* dev,
 414         struct scatterlist *sg, int nelems, int direction)
 415 {
 416         struct scatterlist *s;
 417         int i;
 418
 419         for_each_sg(sg, s, nelems, i) {
 420                 struct page *p = sg_page(s);
 421
 422                 BUG_ON(!p);
 423                 s->dma_address = virt_to_bus(sg_virt(s));
 424                 s->dma_length = s->length;
 425         }
 426         return nelems;
 427 }
 428
 429 static int calgary_map_sg(struct device *dev, struct scatterlist *sg,
 430         int nelems, int direction)
 431 {
 432         struct iommu_table *tbl = find_iommu_table(dev);
 433         struct scatterlist *s;
 434         unsigned long vaddr;
 435         unsigned int npages;
 436         unsigned long entry;
 437         int i;
 438
 439         if (!translation_enabled(tbl))
 440                 return calgary_nontranslate_map_sg(dev, sg, nelems, direction);
 441
 442         for_each_sg(sg, s, nelems, i) {
 443                 BUG_ON(!sg_page(s));
 444
 445                 vaddr = (unsigned long) sg_virt(s);
 446                 npages = num_dma_pages(vaddr, s->length);
 447
 448                 entry = iommu_range_alloc(dev, tbl, npages);
 449                 if (entry == bad_dma_address) {
 450                         /* makes sure unmap knows to stop */
 451                         s->dma_length = 0;
 452                         goto error;
 453                 }
 454
 455                 s->dma_address = (entry << PAGE_SHIFT) | s->offset;
 456
 457                 /* insert into HW table */
 458                 tce_build(tbl, entry, npages, vaddr & PAGE_MASK,
 459                           direction);
 460
 461                 s->dma_length = s->length;
 462         }
 463
 464         return nelems;
 465 error:
 466         calgary_unmap_sg(dev, sg, nelems, direction);
 467         for_each_sg(sg, s, nelems, i) {
 468                 sg->dma_address = bad_dma_address;
 469                 sg->dma_length = 0;
 470         }
 471         return 0;
 472 }
 473
 474 static dma_addr_t calgary_map_single(struct device *dev, phys_addr_t paddr,
 475         size_t size, int direction)
 476 {
 477         dma_addr_t dma_handle = bad_dma_address;
 478         void *vaddr = phys_to_virt(paddr);
 479         unsigned long uaddr;
 480         unsigned int npages;
 481         struct iommu_table *tbl = find_iommu_table(dev);
 482
 483         uaddr = (unsigned long)vaddr;
 484         npages = num_dma_pages(uaddr, size);
 485
 486         if (translation_enabled(tbl))
 487                 dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction);
 488         else
 489                 dma_handle = virt_to_bus(vaddr);
 490
 491         return dma_handle;
 492 }
 493
 494 static void calgary_unmap_single(struct device *dev, dma_addr_t dma_handle,
 495         size_t size, int direction)
 496 {
 497         struct iommu_table *tbl = find_iommu_table(dev);
 498         unsigned int npages;
 499
 500         if (!translation_enabled(tbl))
 501                 return;
 502
 503         npages = num_dma_pages(dma_handle, size);
 504         iommu_free(tbl, dma_handle, npages);
 505 }
 506
 507 static void* calgary_alloc_coherent(struct device *dev, size_t size,
 508         dma_addr_t *dma_handle, gfp_t flag)
 509 {
 510         void *ret = NULL;
 511         dma_addr_t mapping;
 512         unsigned int npages, order;
 513         struct iommu_table *tbl = find_iommu_table(dev);
 514
 515         size = PAGE_ALIGN(size); /* size rounded up to full pages */
 516         npages = size >> PAGE_SHIFT;
 517         order = get_order(size);
 518
 519         /* alloc enough pages (and possibly more) */
 520         ret = (void *)__get_free_pages(flag, order);
 521         if (!ret)
 522                 goto error;
 523         memset(ret, 0, size);
 524
 525         if (translation_enabled(tbl)) {
 526                 /* set up tces to cover the allocated range */
 527                 mapping = iommu_alloc(dev, tbl, ret, npages, DMA_BIDIRECTIONAL);
 528                 if (mapping == bad_dma_address)
 529                         goto free;
 530
 531                 *dma_handle = mapping;
 532         } else /* non translated slot */
 533                 *dma_handle = virt_to_bus(ret);
 534
 535         return ret;
 536
 537 free:
 538         free_pages((unsigned long)ret, get_order(size));
 539         ret = NULL;
 540 error:
 541         return ret;
 542 }
 543
 544 static const struct dma_mapping_ops calgary_dma_ops = {
 545         .alloc_coherent = calgary_alloc_coherent,
 546         .map_single = calgary_map_single,
 547         .unmap_single = calgary_unmap_single,
 548         .map_sg = calgary_map_sg,
 549         .unmap_sg = calgary_unmap_sg,
 550 };
 551
 552 static inline void __iomem * busno_to_bbar(unsigned char num)
 553 {
 554         return bus_info[num].bbar;
 555 }
 556
 557 static inline int busno_to_phbid(unsigned char num)
 558 {
 559         return bus_info[num].phbid;
 560 }
 561
 562 static inline unsigned long split_queue_offset(unsigned char num)
 563 {
 564         size_t idx = busno_to_phbid(num);
 565
 566         return split_queue_offsets[idx];
 567 }
 568
 569 static inline unsigned long tar_offset(unsigned char num)
 570 {
 571         size_t idx = busno_to_phbid(num);
 572
 573         return tar_offsets[idx];
 574 }
 575
 576 static inline unsigned long phb_offset(unsigned char num)
 577 {
 578         size_t idx = busno_to_phbid(num);
 579
 580         return phb_offsets[idx];
 581 }
 582
 583 static inline void __iomem* calgary_reg(void __iomem *bar, unsigned long offset)
 584 {
 585         unsigned long target = ((unsigned long)bar) | offset;
 586         return (void __iomem*)target;
 587 }
 588
 589 static inline int is_calioc2(unsigned short device)
 590 {
 591         return (device == PCI_DEVICE_ID_IBM_CALIOC2);
 592 }
 593
 594 static inline int is_calgary(unsigned short device)
 595 {
 596         return (device == PCI_DEVICE_ID_IBM_CALGARY);
 597 }
 598
 599 static inline int is_cal_pci_dev(unsigned short device)
 600 {
 601         return (is_calgary(device) || is_calioc2(device));
 602 }
 603
 604 static void calgary_tce_cache_blast(struct iommu_table *tbl)
 605 {
 606         u64 val;
 607         u32 aer;
 608         int i = 0;
 609         void __iomem *bbar = tbl->bbar;
 610         void __iomem *target;
 611
 612         /* disable arbitration on the bus */
 613         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 614         aer = readl(target);
 615         writel(0, target);
 616
 617         /* read plssr to ensure it got there */
 618         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 619         val = readl(target);
 620
 621         /* poll split queues until all DMA activity is done */
 622         target = calgary_reg(bbar, split_queue_offset(tbl->it_busno));
 623         do {
 624                 val = readq(target);
 625                 i++;
 626         } while ((val & 0xff) != 0xff && i < 100);
 627         if (i == 100)
 628                 printk(KERN_WARNING "Calgary: PCI bus not quiesced, "
 629                        "continuing anyway\n");
 630
 631         /* invalidate TCE cache */
 632         target = calgary_reg(bbar, tar_offset(tbl->it_busno));
 633         writeq(tbl->tar_val, target);
 634
 635         /* enable arbitration */
 636         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_AER_OFFSET);
 637         writel(aer, target);
 638         (void)readl(target); /* flush */
 639 }
 640
 641 static void calioc2_tce_cache_blast(struct iommu_table *tbl)
 642 {
 643         void __iomem *bbar = tbl->bbar;
 644         void __iomem *target;
 645         u64 val64;
 646         u32 val;
 647         int i = 0;
 648         int count = 1;
 649         unsigned char bus = tbl->it_busno;
 650
 651 begin:
 652         printk(KERN_DEBUG "Calgary: CalIOC2 bus 0x%x entering tce cache blast "
 653                "sequence - count %d\n", bus, count);
 654
 655         /* 1. using the Page Migration Control reg set SoftStop */
 656         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 657         val = be32_to_cpu(readl(target));
 658         printk(KERN_DEBUG "1a. read 0x%x [LE] from %p\n", val, target);
 659         val |= PMR_SOFTSTOP;
 660         printk(KERN_DEBUG "1b. writing 0x%x [LE] to %p\n", val, target);
 661         writel(cpu_to_be32(val), target);
 662
 663         /* 2. poll split queues until all DMA activity is done */
 664         printk(KERN_DEBUG "2a. starting to poll split queues\n");
 665         target = calgary_reg(bbar, split_queue_offset(bus));
 666         do {
 667                 val64 = readq(target);
 668                 i++;
 669         } while ((val64 & 0xff) != 0xff && i < 100);
 670         if (i == 100)
 671                 printk(KERN_WARNING "CalIOC2: PCI bus not quiesced, "
 672                        "continuing anyway\n");
 673
 674         /* 3. poll Page Migration DEBUG for SoftStopFault */
 675         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 676         val = be32_to_cpu(readl(target));
 677         printk(KERN_DEBUG "3. read 0x%x [LE] from %p\n", val, target);
 678
 679         /* 4. if SoftStopFault - goto (1) */
 680         if (val & PMR_SOFTSTOPFAULT) {
 681                 if (++count < 100)
 682                         goto begin;
 683                 else {
 684                         printk(KERN_WARNING "CalIOC2: too many SoftStopFaults, "
 685                                "aborting TCE cache flush sequence!\n");
 686                         return; /* pray for the best */
 687                 }
 688         }
 689
 690         /* 5. Slam into HardStop by reading PHB_PAGE_MIG_CTRL */
 691         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 692         printk(KERN_DEBUG "5a. slamming into HardStop by reading %p\n", target);
 693         val = be32_to_cpu(readl(target));
 694         printk(KERN_DEBUG "5b. read 0x%x [LE] from %p\n", val, target);
 695         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_DEBUG);
 696         val = be32_to_cpu(readl(target));
 697         printk(KERN_DEBUG "5c. read 0x%x [LE] from %p (debug)\n", val, target);
 698
 699         /* 6. invalidate TCE cache */
 700         printk(KERN_DEBUG "6. invalidating TCE cache\n");
 701         target = calgary_reg(bbar, tar_offset(bus));
 702         writeq(tbl->tar_val, target);
 703
 704         /* 7. Re-read PMCR */
 705         printk(KERN_DEBUG "7a. Re-reading PMCR\n");
 706         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 707         val = be32_to_cpu(readl(target));
 708         printk(KERN_DEBUG "7b. read 0x%x [LE] from %p\n", val, target);
 709
 710         /* 8. Remove HardStop */
 711         printk(KERN_DEBUG "8a. removing HardStop from PMCR\n");
 712         target = calgary_reg(bbar, phb_offset(bus) | PHB_PAGE_MIG_CTRL);
 713         val = 0;
 714         printk(KERN_DEBUG "8b. writing 0x%x [LE] to %p\n", val, target);
 715         writel(cpu_to_be32(val), target);
 716         val = be32_to_cpu(readl(target));
 717         printk(KERN_DEBUG "8c. read 0x%x [LE] from %p\n", val, target);
 718 }
 719
 720 static void __init calgary_reserve_mem_region(struct pci_dev *dev, u64 start,
 721         u64 limit)
 722 {
 723         unsigned int numpages;
 724
 725         limit = limit | 0xfffff;
 726         limit++;
 727
 728         numpages = ((limit - start) >> PAGE_SHIFT);
 729         iommu_range_reserve(pci_iommu(dev->bus), start, numpages);
 730 }
 731
 732 static void __init calgary_reserve_peripheral_mem_1(struct pci_dev *dev)
 733 {
 734         void __iomem *target;
 735         u64 low, high, sizelow;
 736         u64 start, limit;
 737         struct iommu_table *tbl = pci_iommu(dev->bus);
 738         unsigned char busnum = dev->bus->number;
 739         void __iomem *bbar = tbl->bbar;
 740
 741         /* peripheral MEM_1 region */
 742         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_LOW);
 743         low = be32_to_cpu(readl(target));
 744         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_HIGH);
 745         high = be32_to_cpu(readl(target));
 746         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_1_SIZE);
 747         sizelow = be32_to_cpu(readl(target));
 748
 749         start = (high << 32) | low;
 750         limit = sizelow;
 751
 752         calgary_reserve_mem_region(dev, start, limit);
 753 }
 754
 755 static void __init calgary_reserve_peripheral_mem_2(struct pci_dev *dev)
 756 {
 757         void __iomem *target;
 758         u32 val32;
 759         u64 low, high, sizelow, sizehigh;
 760         u64 start, limit;
 761         struct iommu_table *tbl = pci_iommu(dev->bus);
 762         unsigned char busnum = dev->bus->number;
 763         void __iomem *bbar = tbl->bbar;
 764
 765         /* is it enabled? */
 766         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
 767         val32 = be32_to_cpu(readl(target));
 768         if (!(val32 & PHB_MEM2_ENABLE))
 769                 return;
 770
 771         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_LOW);
 772         low = be32_to_cpu(readl(target));
 773         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_HIGH);
 774         high = be32_to_cpu(readl(target));
 775         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_LOW);
 776         sizelow = be32_to_cpu(readl(target));
 777         target = calgary_reg(bbar, phb_offset(busnum) | PHB_MEM_2_SIZE_HIGH);
 778         sizehigh = be32_to_cpu(readl(target));
 779
 780         start = (high << 32) | low;
 781         limit = (sizehigh << 32) | sizelow;
 782
 783         calgary_reserve_mem_region(dev, start, limit);
 784 }
 785
 786 /*
 787  * some regions of the IO address space do not get translated, so we
 788  * must not give devices IO addresses in those regions. The regions
 789  * are the 640KB-1MB region and the two PCI peripheral memory holes.
 790  * Reserve all of them in the IOMMU bitmap to avoid giving them out
 791  * later.
 792  */
 793 static void __init calgary_reserve_regions(struct pci_dev *dev)
 794 {
 795         unsigned int npages;
 796         u64 start;
 797         struct iommu_table *tbl = pci_iommu(dev->bus);
 798
 799         /* reserve EMERGENCY_PAGES from bad_dma_address and up */
 800         iommu_range_reserve(tbl, bad_dma_address, EMERGENCY_PAGES);
 801
 802         /* avoid the BIOS/VGA first 640KB-1MB region */
 803         /* for CalIOC2 - avoid the entire first MB */
 804         if (is_calgary(dev->device)) {
 805                 start = (640 * 1024);
 806                 npages = ((1024 - 640) * 1024) >> PAGE_SHIFT;
 807         } else { /* calioc2 */
 808                 start = 0;
 809                 npages = (1 * 1024 * 1024) >> PAGE_SHIFT;
 810         }
 811         iommu_range_reserve(tbl, start, npages);
 812
 813         /* reserve the two PCI peripheral memory regions in IO space */
 814         calgary_reserve_peripheral_mem_1(dev);
 815         calgary_reserve_peripheral_mem_2(dev);
 816 }
 817
 818 static int __init calgary_setup_tar(struct pci_dev *dev, void __iomem *bbar)
 819 {
 820         u64 val64;
 821         u64 table_phys;
 822         void __iomem *target;
 823         int ret;
 824         struct iommu_table *tbl;
 825
 826         /* build TCE tables for each PHB */
 827         ret = build_tce_table(dev, bbar);
 828         if (ret)
 829                 return ret;
 830
 831         tbl = pci_iommu(dev->bus);
 832         tbl->it_base = (unsigned long)bus_info[dev->bus->number].tce_space;
 833         tce_free(tbl, 0, tbl->it_size);
 834
 835         if (is_calgary(dev->device))
 836                 tbl->chip_ops = &calgary_chip_ops;
 837         else if (is_calioc2(dev->device))
 838                 tbl->chip_ops = &calioc2_chip_ops;
 839         else
 840                 BUG();
 841
 842         calgary_reserve_regions(dev);
 843
 844         /* set TARs for each PHB */
 845         target = calgary_reg(bbar, tar_offset(dev->bus->number));
 846         val64 = be64_to_cpu(readq(target));
 847
 848         /* zero out all TAR bits under sw control */
 849         val64 &= ~TAR_SW_BITS;
 850         table_phys = (u64)__pa(tbl->it_base);
 851
 852         val64 |= table_phys;
 853
 854         BUG_ON(specified_table_size > TCE_TABLE_SIZE_8M);
 855         val64 |= (u64) specified_table_size;
 856
 857         tbl->tar_val = cpu_to_be64(val64);
 858
 859         writeq(tbl->tar_val, target);
 860         readq(target); /* flush */
 861
 862         return 0;
 863 }
 864
 865 static void __init calgary_free_bus(struct pci_dev *dev)
 866 {
 867         u64 val64;
 868         struct iommu_table *tbl = pci_iommu(dev->bus);
 869         void __iomem *target;
 870         unsigned int bitmapsz;
 871
 872         target = calgary_reg(tbl->bbar, tar_offset(dev->bus->number));
 873         val64 = be64_to_cpu(readq(target));
 874         val64 &= ~TAR_SW_BITS;
 875         writeq(cpu_to_be64(val64), target);
 876         readq(target); /* flush */
 877
 878         bitmapsz = tbl->it_size / BITS_PER_BYTE;
 879         free_pages((unsigned long)tbl->it_map, get_order(bitmapsz));
 880         tbl->it_map = NULL;
 881
 882         kfree(tbl);
 883
 884         set_pci_iommu(dev->bus, NULL);
 885
 886         /* Can't free bootmem allocated memory after system is up :-( */
 887         bus_info[dev->bus->number].tce_space = NULL;
 888 }
 889
 890 static void calgary_dump_error_regs(struct iommu_table *tbl)
 891 {
 892         void __iomem *bbar = tbl->bbar;
 893         void __iomem *target;
 894         u32 csr, plssr;
 895
 896         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 897         csr = be32_to_cpu(readl(target));
 898
 899         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_PLSSR_OFFSET);
 900         plssr = be32_to_cpu(readl(target));
 901
 902         /* If no error, the agent ID in the CSR is not valid */
 903         printk(KERN_EMERG "Calgary: DMA error on Calgary PHB 0x%x, "
 904                "0x%08x@CSR 0x%08x@PLSSR\n", tbl->it_busno, csr, plssr);
 905 }
 906
 907 static void calioc2_dump_error_regs(struct iommu_table *tbl)
 908 {
 909         void __iomem *bbar = tbl->bbar;
 910         u32 csr, csmr, plssr, mck, rcstat;
 911         void __iomem *target;
 912         unsigned long phboff = phb_offset(tbl->it_busno);
 913         unsigned long erroff;
 914         u32 errregs[7];
 915         int i;
 916
 917         /* dump CSR */
 918         target = calgary_reg(bbar, phboff | PHB_CSR_OFFSET);
 919         csr = be32_to_cpu(readl(target));
 920         /* dump PLSSR */
 921         target = calgary_reg(bbar, phboff | PHB_PLSSR_OFFSET);
 922         plssr = be32_to_cpu(readl(target));
 923         /* dump CSMR */
 924         target = calgary_reg(bbar, phboff | 0x290);
 925         csmr = be32_to_cpu(readl(target));
 926         /* dump mck */
 927         target = calgary_reg(bbar, phboff | 0x800);
 928         mck = be32_to_cpu(readl(target));
 929
 930         printk(KERN_EMERG "Calgary: DMA error on CalIOC2 PHB 0x%x\n",
 931                tbl->it_busno);
 932
 933         printk(KERN_EMERG "Calgary: 0x%08x@CSR 0x%08x@PLSSR 0x%08x@CSMR 0x%08x@MCK\n",
 934                csr, plssr, csmr, mck);
 935
 936         /* dump rest of error regs */
 937         printk(KERN_EMERG "Calgary: ");
 938         for (i = 0; i < ARRAY_SIZE(errregs); i++) {
 939                 /* err regs are at 0x810 - 0x870 */
 940                 erroff = (0x810 + (i * 0x10));
 941                 target = calgary_reg(bbar, phboff | erroff);
 942                 errregs[i] = be32_to_cpu(readl(target));
 943                 printk("0x%08x@0x%lx ", errregs[i], erroff);
 944         }
 945         printk("\n");
 946
 947         /* root complex status */
 948         target = calgary_reg(bbar, phboff | PHB_ROOT_COMPLEX_STATUS);
 949         rcstat = be32_to_cpu(readl(target));
 950         printk(KERN_EMERG "Calgary: 0x%08x@0x%x\n", rcstat,
 951                PHB_ROOT_COMPLEX_STATUS);
 952 }
 953
 954 static void calgary_watchdog(unsigned long data)
 955 {
 956         struct pci_dev *dev = (struct pci_dev *)data;
 957         struct iommu_table *tbl = pci_iommu(dev->bus);
 958         void __iomem *bbar = tbl->bbar;
 959         u32 val32;
 960         void __iomem *target;
 961
 962         target = calgary_reg(bbar, phb_offset(tbl->it_busno) | PHB_CSR_OFFSET);
 963         val32 = be32_to_cpu(readl(target));
 964
 965         /* If no error, the agent ID in the CSR is not valid */
 966         if (val32 & CSR_AGENT_MASK) {
 967                 tbl->chip_ops->dump_error_regs(tbl);
 968
 969                 /* reset error */
 970                 writel(0, target);
 971
 972                 /* Disable bus that caused the error */
 973                 target = calgary_reg(bbar, phb_offset(tbl->it_busno) |
 974                                      PHB_CONFIG_RW_OFFSET);
 975                 val32 = be32_to_cpu(readl(target));
 976                 val32 |= PHB_SLOT_DISABLE;
 977                 writel(cpu_to_be32(val32), target);
 978                 readl(target); /* flush */
 979         } else {
 980                 /* Reset the timer */
 981                 mod_timer(&tbl->watchdog_timer, jiffies + 2 * HZ);
 982         }
 983 }
 984
 985 static void __init calgary_set_split_completion_timeout(void __iomem *bbar,
 986         unsigned char busnum, unsigned long timeout)
 987 {
 988         u64 val64;
 989         void __iomem *target;
 990         unsigned int phb_shift = ~0; /* silence gcc */
 991         u64 mask;
 992
 993         switch (busno_to_phbid(busnum)) {
 994         case 0: phb_shift = (63 - 19);
 995                 break;
 996         case 1: phb_shift = (63 - 23);
 997                 break;
 998         case 2: phb_shift = (63 - 27);
 999                 break;
1000         case 3: phb_shift = (63 - 35);
1001                 break;
1002         default:
1003                 BUG_ON(busno_to_phbid(busnum));
1004         }
1005
1006         target = calgary_reg(bbar, CALGARY_CONFIG_REG);
1007         val64 = be64_to_cpu(readq(target));
1008
1009         /* zero out this PHB's timer bits */
1010         mask = ~(0xFUL << phb_shift);
1011         val64 &= mask;
1012         val64 |= (timeout << phb_shift);
1013         writeq(cpu_to_be64(val64), target);
1014         readq(target); /* flush */
1015 }
1016
1017 static void __init calioc2_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1018 {
1019         unsigned char busnum = dev->bus->number;
1020         void __iomem *bbar = tbl->bbar;
1021         void __iomem *target;
1022         u32 val;
1023
1024         /*
1025          * CalIOC2 designers recommend setting bit 8 in 0xnDB0 to 1
1026          */
1027         target = calgary_reg(bbar, phb_offset(busnum) | PHB_SAVIOR_L2);
1028         val = cpu_to_be32(readl(target));
1029         val |= 0x00800000;
1030         writel(cpu_to_be32(val), target);
1031 }
1032
1033 static void __init calgary_handle_quirks(struct iommu_table *tbl, struct pci_dev *dev)
1034 {
1035         unsigned char busnum = dev->bus->number;
1036
1037         /*
1038          * Give split completion a longer timeout on bus 1 for aic94xx
1039          * http://bugzilla.kernel.org/show_bug.cgi?id=7180
1040          */
1041         if (is_calgary(dev->device) && (busnum == 1))
1042                 calgary_set_split_completion_timeout(tbl->bbar, busnum,
1043                                                      CCR_2SEC_TIMEOUT);
1044 }
1045
1046 static void __init calgary_enable_translation(struct pci_dev *dev)
1047 {
1048         u32 val32;
1049         unsigned char busnum;
1050         void __iomem *target;
1051         void __iomem *bbar;
1052         struct iommu_table *tbl;
1053
1054         busnum = dev->bus->number;
1055         tbl = pci_iommu(dev->bus);
1056         bbar = tbl->bbar;
1057
1058         /* enable TCE in PHB Config Register */
1059         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1060         val32 = be32_to_cpu(readl(target));
1061         val32 |= PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE;
1062
1063         printk(KERN_INFO "Calgary: enabling translation on %s PHB %#x\n",
1064                (dev->device == PCI_DEVICE_ID_IBM_CALGARY) ?
1065                "Calgary" : "CalIOC2", busnum);
1066         printk(KERN_INFO "Calgary: errant DMAs will now be prevented on this "
1067                "bus.\n");
1068
1069         writel(cpu_to_be32(val32), target);
1070         readl(target); /* flush */
1071
1072         init_timer(&tbl->watchdog_timer);
1073         tbl->watchdog_timer.function = &calgary_watchdog;
1074         tbl->watchdog_timer.data = (unsigned long)dev;
1075         mod_timer(&tbl->watchdog_timer, jiffies);
1076 }
1077
1078 static void __init calgary_disable_translation(struct pci_dev *dev)
1079 {
1080         u32 val32;
1081         unsigned char busnum;
1082         void __iomem *target;
1083         void __iomem *bbar;
1084         struct iommu_table *tbl;
1085
1086         busnum = dev->bus->number;
1087         tbl = pci_iommu(dev->bus);
1088         bbar = tbl->bbar;
1089
1090         /* disable TCE in PHB Config Register */
1091         target = calgary_reg(bbar, phb_offset(busnum) | PHB_CONFIG_RW_OFFSET);
1092         val32 = be32_to_cpu(readl(target));
1093         val32 &= ~(PHB_TCE_ENABLE | PHB_DAC_DISABLE | PHB_MCSR_ENABLE);
1094
1095         printk(KERN_INFO "Calgary: disabling translation on PHB %#x!\n", busnum);
1096         writel(cpu_to_be32(val32), target);
1097         readl(target); /* flush */
1098
1099         del_timer_sync(&tbl->watchdog_timer);
1100 }
1101
1102 static void __init calgary_init_one_nontraslated(struct pci_dev *dev)
1103 {
1104         pci_dev_get(dev);
1105         set_pci_iommu(dev->bus, NULL);
1106
1107         /* is the device behind a bridge? */
1108         if (dev->bus->parent)
1109                 dev->bus->parent->self = dev;
1110         else
1111                 dev->bus->self = dev;
1112 }
1113
1114 static int __init calgary_init_one(struct pci_dev *dev)
1115 {
1116         void __iomem *bbar;
1117         struct iommu_table *tbl;
1118         int ret;
1119
1120         BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
1121
1122         bbar = busno_to_bbar(dev->bus->number);
1123         ret = calgary_setup_tar(dev, bbar);
1124         if (ret)
1125                 goto done;
1126
1127         pci_dev_get(dev);
1128
1129         if (dev->bus->parent) {
1130                 if (dev->bus->parent->self)
1131                         printk(KERN_WARNING "Calgary: IEEEE, dev %p has "
1132                                "bus->parent->self!\n", dev);
1133                 dev->bus->parent->self = dev;
1134         } else
1135                 dev->bus->self = dev;
1136
1137         tbl = pci_iommu(dev->bus);
1138         tbl->chip_ops->handle_quirks(tbl, dev);
1139
1140         calgary_enable_translation(dev);
1141
1142         return 0;
1143
1144 done:
1145         return ret;
1146 }
1147
1148 static int __init calgary_locate_bbars(void)
1149 {
1150         int ret;
1151         int rioidx, phb, bus;
1152         void __iomem *bbar;
1153         void __iomem *target;
1154         unsigned long offset;
1155         u8 start_bus, end_bus;
1156         u32 val;
1157
1158         ret = -ENODATA;
1159         for (rioidx = 0; rioidx < rio_table_hdr->num_rio_dev; rioidx++) {
1160                 struct rio_detail *rio = rio_devs[rioidx];
1161
1162                 if ((rio->type != COMPAT_CALGARY) && (rio->type != ALT_CALGARY))
1163                         continue;
1164
1165                 /* map entire 1MB of Calgary config space */
1166                 bbar = ioremap_nocache(rio->BBAR, 1024 * 1024);
1167                 if (!bbar)
1168                         goto error;
1169
1170                 for (phb = 0; phb < PHBS_PER_CALGARY; phb++) {
1171                         offset = phb_debug_offsets[phb] | PHB_DEBUG_STUFF_OFFSET;
1172                         target = calgary_reg(bbar, offset);
1173
1174                         val = be32_to_cpu(readl(target));
1175
1176                         start_bus = (u8)((val & 0x00FF0000) >> 16);
1177                         end_bus = (u8)((val & 0x0000FF00) >> 8);
1178
1179                         if (end_bus) {
1180                                 for (bus = start_bus; bus <= end_bus; bus++) {
1181                                         bus_info[bus].bbar = bbar;
1182                                         bus_info[bus].phbid = phb;
1183                                 }
1184                         } else {
1185                                 bus_info[start_bus].bbar = bbar;
1186                                 bus_info[start_bus].phbid = phb;
1187                         }
1188                 }
1189         }
1190
1191         return 0;
1192
1193 error:
1194         /* scan bus_info and iounmap any bbars we previously ioremap'd */
1195         for (bus = 0; bus < ARRAY_SIZE(bus_info); bus++)
1196                 if (bus_info[bus].bbar)
1197                         iounmap(bus_info[bus].bbar);
1198
1199         return ret;
1200 }
1201
1202 static int __init calgary_init(void)
1203 {
1204         int ret;
1205         struct pci_dev *dev = NULL;
1206         struct calgary_bus_info *info;
1207
1208         ret = calgary_locate_bbars();
1209         if (ret)
1210                 return ret;
1211
1212         do {
1213                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1214                 if (!dev)
1215                         break;
1216                 if (!is_cal_pci_dev(dev->device))
1217                         continue;
1218
1219                 info = &bus_info[dev->bus->number];
1220                 if (info->translation_disabled) {
1221                         calgary_init_one_nontraslated(dev);
1222                         continue;
1223                 }
1224
1225                 if (!info->tce_space && !translate_empty_slots)
1226                         continue;
1227
1228                 ret = calgary_init_one(dev);
1229                 if (ret)
1230                         goto error;
1231         } while (1);
1232
1233         return ret;
1234
1235 error:
1236         do {
1237                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1238                 if (!dev)
1239                         break;
1240                 if (!is_cal_pci_dev(dev->device))
1241                         continue;
1242
1243                 info = &bus_info[dev->bus->number];
1244                 if (info->translation_disabled) {
1245                         pci_dev_put(dev);
1246                         continue;
1247                 }
1248                 if (!info->tce_space && !translate_empty_slots)
1249                         continue;
1250
1251                 calgary_disable_translation(dev);
1252                 calgary_free_bus(dev);
1253                 pci_dev_put(dev); /* Undo calgary_init_one()'s pci_dev_get() */
1254         } while (1);
1255
1256         return ret;
1257 }
1258
1259 static inline int __init determine_tce_table_size(u64 ram)
1260 {
1261         int ret;
1262
1263         if (specified_table_size != TCE_TABLE_SIZE_UNSPECIFIED)
1264                 return specified_table_size;
1265
1266         /*
1267          * Table sizes are from 0 to 7 (TCE_TABLE_SIZE_64K to
1268          * TCE_TABLE_SIZE_8M). Table size 0 has 8K entries and each
1269          * larger table size has twice as many entries, so shift the
1270          * max ram address by 13 to divide by 8K and then look at the
1271          * order of the result to choose between 0-7.
1272          */
1273         ret = get_order(ram >> 13);
1274         if (ret > TCE_TABLE_SIZE_8M)
1275                 ret = TCE_TABLE_SIZE_8M;
1276
1277         return ret;
1278 }
1279
1280 static int __init build_detail_arrays(void)
1281 {
1282         unsigned long ptr;
1283         int i, scal_detail_size, rio_detail_size;
1284
1285         if (rio_table_hdr->num_scal_dev > MAX_NUMNODES){
1286                 printk(KERN_WARNING
1287                         "Calgary: MAX_NUMNODES too low! Defined as %d, "
1288                         "but system has %d nodes.\n",
1289                         MAX_NUMNODES, rio_table_hdr->num_scal_dev);
1290                 return -ENODEV;
1291         }
1292
1293         switch (rio_table_hdr->version){
1294         case 2:
1295                 scal_detail_size = 11;
1296                 rio_detail_size = 13;
1297                 break;
1298         case 3:
1299                 scal_detail_size = 12;
1300                 rio_detail_size = 15;
1301                 break;
1302         default:
1303                 printk(KERN_WARNING
1304                        "Calgary: Invalid Rio Grande Table Version: %d\n",
1305                        rio_table_hdr->version);
1306                 return -EPROTO;
1307         }
1308
1309         ptr = ((unsigned long)rio_table_hdr) + 3;
1310         for (i = 0; i < rio_table_hdr->num_scal_dev;
1311                     i++, ptr += scal_detail_size)
1312                 scal_devs[i] = (struct scal_detail *)ptr;
1313
1314         for (i = 0; i < rio_table_hdr->num_rio_dev;
1315                     i++, ptr += rio_detail_size)
1316                 rio_devs[i] = (struct rio_detail *)ptr;
1317
1318         return 0;
1319 }
1320
1321 static int __init calgary_bus_has_devices(int bus, unsigned short pci_dev)
1322 {
1323         int dev;
1324         u32 val;
1325
1326         if (pci_dev == PCI_DEVICE_ID_IBM_CALIOC2) {
1327                 /*
1328                  * FIXME: properly scan for devices accross the
1329                  * PCI-to-PCI bridge on every CalIOC2 port.
1330                  */
1331                 return 1;
1332         }
1333
1334         for (dev = 1; dev < 8; dev++) {
1335                 val = read_pci_config(bus, dev, 0, 0);
1336                 if (val != 0xffffffff)
1337                         break;
1338         }
1339         return (val != 0xffffffff);
1340 }
1341
1342 void __init detect_calgary(void)
1343 {
1344         int bus;
1345         void *tbl;
1346         int calgary_found = 0;
1347         unsigned long ptr;
1348         unsigned int offset, prev_offset;
1349         int ret;
1350
1351         /*
1352          * if the user specified iommu=off or iommu=soft or we found
1353          * another HW IOMMU already, bail out.
1354          */
1355         if (swiotlb || no_iommu || iommu_detected)
1356                 return;
1357
1358         if (!use_calgary)
1359                 return;
1360
1361         if (!early_pci_allowed())
1362                 return;
1363
1364         printk(KERN_DEBUG "Calgary: detecting Calgary via BIOS EBDA area\n");
1365
1366         ptr = (unsigned long)phys_to_virt(get_bios_ebda());
1367
1368         rio_table_hdr = NULL;
1369         prev_offset = 0;
1370         offset = 0x180;
1371         /*
1372          * The next offset is stored in the 1st word.
1373          * Only parse up until the offset increases:
1374          */
1375         while (offset > prev_offset) {
1376                 /* The block id is stored in the 2nd word */
1377                 if (*((unsigned short *)(ptr + offset + 2)) == 0x4752){
1378                         /* set the pointer past the offset & block id */
1379                         rio_table_hdr = (struct rio_table_hdr *)(ptr + offset + 4);
1380                         break;
1381                 }
1382                 prev_offset = offset;
1383                 offset = *((unsigned short *)(ptr + offset));
1384         }
1385         if (!rio_table_hdr) {
1386                 printk(KERN_DEBUG "Calgary: Unable to locate Rio Grande table "
1387                        "in EBDA - bailing!\n");
1388                 return;
1389         }
1390
1391         ret = build_detail_arrays();
1392         if (ret) {
1393                 printk(KERN_DEBUG "Calgary: build_detail_arrays ret %d\n", ret);
1394                 return;
1395         }
1396
1397         specified_table_size = determine_tce_table_size(max_pfn * PAGE_SIZE);
1398
1399         for (bus = 0; bus < MAX_PHB_BUS_NUM; bus++) {
1400                 struct calgary_bus_info *info = &bus_info[bus];
1401                 unsigned short pci_device;
1402                 u32 val;
1403
1404                 val = read_pci_config(bus, 0, 0, 0);
1405                 pci_device = (val & 0xFFFF0000) >> 16;
1406
1407                 if (!is_cal_pci_dev(pci_device))
1408                         continue;
1409
1410                 if (info->translation_disabled)
1411                         continue;
1412
1413                 if (calgary_bus_has_devices(bus, pci_device) ||
1414                     translate_empty_slots) {
1415                         tbl = alloc_tce_table();
1416                         if (!tbl)
1417                                 goto cleanup;
1418                         info->tce_space = tbl;
1419                         calgary_found = 1;
1420                 }
1421         }
1422
1423         printk(KERN_DEBUG "Calgary: finished detection, Calgary %s\n",
1424                calgary_found ? "found" : "not found");
1425
1426         if (calgary_found) {
1427                 iommu_detected = 1;
1428                 calgary_detected = 1;
1429                 printk(KERN_INFO "PCI-DMA: Calgary IOMMU detected.\n");
1430                 printk(KERN_INFO "PCI-DMA: Calgary TCE table spec is %d, "
1431                        "CONFIG_IOMMU_DEBUG is %s.\n", specified_table_size,
1432                        debugging ? "enabled" : "disabled");
1433         }
1434         return;
1435
1436 cleanup:
1437         for (--bus; bus >= 0; --bus) {
1438                 struct calgary_bus_info *info = &bus_info[bus];
1439
1440                 if (info->tce_space)
1441                         free_tce_table(info->tce_space);
1442         }
1443 }
1444
1445 int __init calgary_iommu_init(void)
1446 {
1447         int ret;
1448
1449         if (no_iommu || swiotlb)
1450                 return -ENODEV;
1451
1452         if (!calgary_detected)
1453                 return -ENODEV;
1454
1455         /* ok, we're trying to use Calgary - let's roll */
1456         printk(KERN_INFO "PCI-DMA: Using Calgary IOMMU\n");
1457
1458         ret = calgary_init();
1459         if (ret) {
1460                 printk(KERN_ERR "PCI-DMA: Calgary init failed %d, "
1461                        "falling back to no_iommu\n", ret);
1462                 if (max_pfn > MAX_DMA32_PFN)
1463                         printk(KERN_ERR "WARNING more than 4GB of memory, "
1464                                         "32bit PCI may malfunction.\n");
1465                 return ret;
1466         }
1467
1468         force_iommu = 1;
1469         bad_dma_address = 0x0;
1470         dma_ops = &calgary_dma_ops;
1471
1472         return 0;
1473 }
1474
1475 static int __init calgary_parse_options(char *p)
1476 {
1477         unsigned int bridge;
1478         size_t len;
1479         char* endp;
1480
1481         while (*p) {
1482                 if (!strncmp(p, "64k", 3))
1483                         specified_table_size = TCE_TABLE_SIZE_64K;
1484                 else if (!strncmp(p, "128k", 4))
1485                         specified_table_size = TCE_TABLE_SIZE_128K;
1486                 else if (!strncmp(p, "256k", 4))
1487                         specified_table_size = TCE_TABLE_SIZE_256K;
1488                 else if (!strncmp(p, "512k", 4))
1489                         specified_table_size = TCE_TABLE_SIZE_512K;
1490                 else if (!strncmp(p, "1M", 2))
1491                         specified_table_size = TCE_TABLE_SIZE_1M;
1492                 else if (!strncmp(p, "2M", 2))
1493                         specified_table_size = TCE_TABLE_SIZE_2M;
1494                 else if (!strncmp(p, "4M", 2))
1495                         specified_table_size = TCE_TABLE_SIZE_4M;
1496                 else if (!strncmp(p, "8M", 2))
1497                         specified_table_size = TCE_TABLE_SIZE_8M;
1498
1499                 len = strlen("translate_empty_slots");
1500                 if (!strncmp(p, "translate_empty_slots", len))
1501                         translate_empty_slots = 1;
1502
1503                 len = strlen("disable");
1504                 if (!strncmp(p, "disable", len)) {
1505                         p += len;
1506                         if (*p == '=')
1507                                 ++p;
1508                         if (*p == '\0')
1509                                 break;
1510                         bridge = simple_strtol(p, &endp, 0);
1511                         if (p == endp)
1512                                 break;
1513
1514                         if (bridge < MAX_PHB_BUS_NUM) {
1515                                 printk(KERN_INFO "Calgary: disabling "
1516                                        "translation for PHB %#x\n", bridge);
1517                                 bus_info[bridge].translation_disabled = 1;
1518                         }
1519                 }
1520
1521                 p = strpbrk(p, ",");
1522                 if (!p)
1523                         break;
1524
1525                 p++; /* skip ',' */
1526         }
1527         return 1;
1528 }
1529 __setup("calgary=", calgary_parse_options);
1530
1531 static void __init calgary_fixup_one_tce_space(struct pci_dev *dev)
1532 {
1533         struct iommu_table *tbl;
1534         unsigned int npages;
1535         int i;
1536
1537         tbl = pci_iommu(dev->bus);
1538
1539         for (i = 0; i < 4; i++) {
1540                 struct resource *r = &dev->resource[PCI_BRIDGE_RESOURCES + i];
1541
1542                 /* Don't give out TCEs that map MEM resources */
1543                 if (!(r->flags & IORESOURCE_MEM))
1544                         continue;
1545
1546                 /* 0-based? we reserve the whole 1st MB anyway */
1547                 if (!r->start)
1548                         continue;
1549
1550                 /* cover the whole region */
1551                 npages = (r->end - r->start) >> PAGE_SHIFT;
1552                 npages++;
1553
1554                 iommu_range_reserve(tbl, r->start, npages);
1555         }
1556 }
1557
1558 static int __init calgary_fixup_tce_spaces(void)
1559 {
1560         struct pci_dev *dev = NULL;
1561         struct calgary_bus_info *info;
1562
1563         if (no_iommu || swiotlb || !calgary_detected)
1564                 return -ENODEV;
1565
1566         printk(KERN_DEBUG "Calgary: fixing up tce spaces\n");
1567
1568         do {
1569                 dev = pci_get_device(PCI_VENDOR_ID_IBM, PCI_ANY_ID, dev);
1570                 if (!dev)
1571                         break;
1572                 if (!is_cal_pci_dev(dev->device))
1573                         continue;
1574
1575                 info = &bus_info[dev->bus->number];
1576                 if (info->translation_disabled)
1577                         continue;
1578
1579                 if (!info->tce_space)
1580                         continue;
1581
1582                 calgary_fixup_one_tce_space(dev);
1583
1584         } while (1);
1585
1586         return 0;
1587 }
1588
1589 /*
1590  * We need to be call after pcibios_assign_resources (fs_initcall level)
1591  * and before device_initcall.
1592  */
1593 rootfs_initcall(calgary_fixup_tce_spaces);