2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/acpi.h>
31 #include <linux/sysdev.h>
32 #include <linux/msi.h>
33 #include <linux/htirq.h>
34 #include <linux/dmar.h>
35 #include <linux/jiffies.h>
37 #include <acpi/acpi_bus.h>
39 #include <linux/bootmem.h>
45 #include <asm/proto.h>
49 #include <asm/msidef.h>
50 #include <asm/hypertransport.h>
53 #include <mach_apic.h>
58 unsigned move_cleanup_count;
60 u8 move_in_progress : 1;
63 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
64 static struct irq_cfg irq_cfg[NR_IRQS] __read_mostly = {
65 [0] = { .domain = CPU_MASK_ALL, .vector = IRQ0_VECTOR, },
66 [1] = { .domain = CPU_MASK_ALL, .vector = IRQ1_VECTOR, },
67 [2] = { .domain = CPU_MASK_ALL, .vector = IRQ2_VECTOR, },
68 [3] = { .domain = CPU_MASK_ALL, .vector = IRQ3_VECTOR, },
69 [4] = { .domain = CPU_MASK_ALL, .vector = IRQ4_VECTOR, },
70 [5] = { .domain = CPU_MASK_ALL, .vector = IRQ5_VECTOR, },
71 [6] = { .domain = CPU_MASK_ALL, .vector = IRQ6_VECTOR, },
72 [7] = { .domain = CPU_MASK_ALL, .vector = IRQ7_VECTOR, },
73 [8] = { .domain = CPU_MASK_ALL, .vector = IRQ8_VECTOR, },
74 [9] = { .domain = CPU_MASK_ALL, .vector = IRQ9_VECTOR, },
75 [10] = { .domain = CPU_MASK_ALL, .vector = IRQ10_VECTOR, },
76 [11] = { .domain = CPU_MASK_ALL, .vector = IRQ11_VECTOR, },
77 [12] = { .domain = CPU_MASK_ALL, .vector = IRQ12_VECTOR, },
78 [13] = { .domain = CPU_MASK_ALL, .vector = IRQ13_VECTOR, },
79 [14] = { .domain = CPU_MASK_ALL, .vector = IRQ14_VECTOR, },
80 [15] = { .domain = CPU_MASK_ALL, .vector = IRQ15_VECTOR, },
83 static int assign_irq_vector(int irq, cpumask_t mask);
85 int first_system_vector = 0xfe;
87 char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
89 #define __apicdebuginit __init
91 int sis_apic_bug; /* not actually supported, dummy for compile */
93 static int no_timer_check;
95 static int disable_timer_pin_1 __initdata;
97 int timer_through_8259 __initdata;
99 /* Where if anywhere is the i8259 connect in external int mode */
100 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
102 static DEFINE_SPINLOCK(ioapic_lock);
103 DEFINE_SPINLOCK(vector_lock);
106 * # of IRQ routing registers
108 int nr_ioapic_registers[MAX_IO_APICS];
110 /* I/O APIC entries */
111 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
114 /* MP IRQ source entries */
115 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
117 /* # of MP IRQ source entries */
121 * Rough estimation of how many shared IRQs there are, can
122 * be changed anytime.
124 #define MAX_PLUS_SHARED_IRQS NR_IRQS
125 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
128 * This is performance-critical, we want to do it O(1)
130 * the indexing order of this array favors 1:1 mappings
131 * between pins and IRQs.
134 static struct irq_pin_list {
135 short apic, pin, next;
136 } irq_2_pin[PIN_MAP_SIZE];
140 unsigned int unused[3];
144 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
146 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
147 + (mp_ioapics[idx].mpc_apicaddr & ~PAGE_MASK);
150 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
152 struct io_apic __iomem *io_apic = io_apic_base(apic);
153 writel(reg, &io_apic->index);
154 return readl(&io_apic->data);
157 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
159 struct io_apic __iomem *io_apic = io_apic_base(apic);
160 writel(reg, &io_apic->index);
161 writel(value, &io_apic->data);
165 * Re-write a value: to be used for read-modify-write
166 * cycles where the read already set up the index register.
168 static inline void io_apic_modify(unsigned int apic, unsigned int value)
170 struct io_apic __iomem *io_apic = io_apic_base(apic);
171 writel(value, &io_apic->data);
174 static bool io_apic_level_ack_pending(unsigned int irq)
176 struct irq_pin_list *entry;
179 spin_lock_irqsave(&ioapic_lock, flags);
180 entry = irq_2_pin + irq;
188 reg = io_apic_read(entry->apic, 0x10 + pin*2);
189 /* Is the remote IRR bit set? */
190 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
191 spin_unlock_irqrestore(&ioapic_lock, flags);
196 entry = irq_2_pin + entry->next;
198 spin_unlock_irqrestore(&ioapic_lock, flags);
204 * Synchronize the IO-APIC and the CPU by doing
205 * a dummy read from the IO-APIC
207 static inline void io_apic_sync(unsigned int apic)
209 struct io_apic __iomem *io_apic = io_apic_base(apic);
210 readl(&io_apic->data);
213 #define __DO_ACTION(R, ACTION, FINAL) \
217 struct irq_pin_list *entry = irq_2_pin + irq; \
219 BUG_ON(irq >= NR_IRQS); \
225 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
227 io_apic_modify(entry->apic, reg); \
231 entry = irq_2_pin + entry->next; \
236 struct { u32 w1, w2; };
237 struct IO_APIC_route_entry entry;
240 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
242 union entry_union eu;
244 spin_lock_irqsave(&ioapic_lock, flags);
245 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
246 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
247 spin_unlock_irqrestore(&ioapic_lock, flags);
252 * When we write a new IO APIC routing entry, we need to write the high
253 * word first! If the mask bit in the low word is clear, we will enable
254 * the interrupt, and we need to make sure the entry is fully populated
255 * before that happens.
258 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
260 union entry_union eu;
262 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
263 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
266 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
269 spin_lock_irqsave(&ioapic_lock, flags);
270 __ioapic_write_entry(apic, pin, e);
271 spin_unlock_irqrestore(&ioapic_lock, flags);
275 * When we mask an IO APIC routing entry, we need to write the low
276 * word first, in order to set the mask bit before we change the
279 static void ioapic_mask_entry(int apic, int pin)
282 union entry_union eu = { .entry.mask = 1 };
284 spin_lock_irqsave(&ioapic_lock, flags);
285 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
286 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
287 spin_unlock_irqrestore(&ioapic_lock, flags);
291 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, u8 vector)
294 struct irq_pin_list *entry = irq_2_pin + irq;
296 BUG_ON(irq >= NR_IRQS);
303 io_apic_write(apic, 0x11 + pin*2, dest);
304 reg = io_apic_read(apic, 0x10 + pin*2);
305 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
307 io_apic_modify(apic, reg);
310 entry = irq_2_pin + entry->next;
314 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
316 struct irq_cfg *cfg = irq_cfg + irq;
321 cpus_and(tmp, mask, cpu_online_map);
325 if (assign_irq_vector(irq, mask))
328 cpus_and(tmp, cfg->domain, mask);
329 dest = cpu_mask_to_apicid(tmp);
332 * Only the high 8 bits are valid.
334 dest = SET_APIC_LOGICAL_ID(dest);
336 spin_lock_irqsave(&ioapic_lock, flags);
337 __target_IO_APIC_irq(irq, dest, cfg->vector);
338 irq_desc[irq].affinity = mask;
339 spin_unlock_irqrestore(&ioapic_lock, flags);
344 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
345 * shared ISA-space IRQs, so we have to support them. We are super
346 * fast in the common case, and fast for shared ISA-space IRQs.
348 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
350 static int first_free_entry = NR_IRQS;
351 struct irq_pin_list *entry = irq_2_pin + irq;
353 BUG_ON(irq >= NR_IRQS);
355 entry = irq_2_pin + entry->next;
357 if (entry->pin != -1) {
358 entry->next = first_free_entry;
359 entry = irq_2_pin + entry->next;
360 if (++first_free_entry >= PIN_MAP_SIZE)
361 panic("io_apic.c: ran out of irq_2_pin entries!");
368 * Reroute an IRQ to a different pin.
370 static void __init replace_pin_at_irq(unsigned int irq,
371 int oldapic, int oldpin,
372 int newapic, int newpin)
374 struct irq_pin_list *entry = irq_2_pin + irq;
377 if (entry->apic == oldapic && entry->pin == oldpin) {
378 entry->apic = newapic;
383 entry = irq_2_pin + entry->next;
388 #define DO_ACTION(name,R,ACTION, FINAL) \
390 static void name##_IO_APIC_irq (unsigned int irq) \
391 __DO_ACTION(R, ACTION, FINAL)
394 DO_ACTION(__mask, 0, |= IO_APIC_REDIR_MASKED, io_apic_sync(entry->apic))
397 DO_ACTION(__unmask, 0, &= ~IO_APIC_REDIR_MASKED, )
399 static void mask_IO_APIC_irq (unsigned int irq)
403 spin_lock_irqsave(&ioapic_lock, flags);
404 __mask_IO_APIC_irq(irq);
405 spin_unlock_irqrestore(&ioapic_lock, flags);
408 static void unmask_IO_APIC_irq (unsigned int irq)
412 spin_lock_irqsave(&ioapic_lock, flags);
413 __unmask_IO_APIC_irq(irq);
414 spin_unlock_irqrestore(&ioapic_lock, flags);
417 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
419 struct IO_APIC_route_entry entry;
421 /* Check delivery_mode to be sure we're not clearing an SMI pin */
422 entry = ioapic_read_entry(apic, pin);
423 if (entry.delivery_mode == dest_SMI)
426 * Disable it in the IO-APIC irq-routing table:
428 ioapic_mask_entry(apic, pin);
431 static void clear_IO_APIC (void)
435 for (apic = 0; apic < nr_ioapics; apic++)
436 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
437 clear_IO_APIC_pin(apic, pin);
440 int skip_ioapic_setup;
443 static int __init parse_noapic(char *str)
445 disable_ioapic_setup();
448 early_param("noapic", parse_noapic);
450 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
451 static int __init disable_timer_pin_setup(char *arg)
453 disable_timer_pin_1 = 1;
456 __setup("disable_timer_pin_1", disable_timer_pin_setup);
460 * Find the IRQ entry number of a certain pin.
462 static int find_irq_entry(int apic, int pin, int type)
466 for (i = 0; i < mp_irq_entries; i++)
467 if (mp_irqs[i].mpc_irqtype == type &&
468 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
469 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
470 mp_irqs[i].mpc_dstirq == pin)
477 * Find the pin to which IRQ[irq] (ISA) is connected
479 static int __init find_isa_irq_pin(int irq, int type)
483 for (i = 0; i < mp_irq_entries; i++) {
484 int lbus = mp_irqs[i].mpc_srcbus;
486 if (test_bit(lbus, mp_bus_not_pci) &&
487 (mp_irqs[i].mpc_irqtype == type) &&
488 (mp_irqs[i].mpc_srcbusirq == irq))
490 return mp_irqs[i].mpc_dstirq;
495 static int __init find_isa_irq_apic(int irq, int type)
499 for (i = 0; i < mp_irq_entries; i++) {
500 int lbus = mp_irqs[i].mpc_srcbus;
502 if (test_bit(lbus, mp_bus_not_pci) &&
503 (mp_irqs[i].mpc_irqtype == type) &&
504 (mp_irqs[i].mpc_srcbusirq == irq))
507 if (i < mp_irq_entries) {
509 for(apic = 0; apic < nr_ioapics; apic++) {
510 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic)
519 * Find a specific PCI IRQ entry.
520 * Not an __init, possibly needed by modules
522 static int pin_2_irq(int idx, int apic, int pin);
524 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
526 int apic, i, best_guess = -1;
528 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
530 if (mp_bus_id_to_pci_bus[bus] == -1) {
531 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
534 for (i = 0; i < mp_irq_entries; i++) {
535 int lbus = mp_irqs[i].mpc_srcbus;
537 for (apic = 0; apic < nr_ioapics; apic++)
538 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
539 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
542 if (!test_bit(lbus, mp_bus_not_pci) &&
543 !mp_irqs[i].mpc_irqtype &&
545 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
546 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
548 if (!(apic || IO_APIC_IRQ(irq)))
551 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
554 * Use the first all-but-pin matching entry as a
555 * best-guess fuzzy result for broken mptables.
561 BUG_ON(best_guess >= NR_IRQS);
565 /* ISA interrupts are always polarity zero edge triggered,
566 * when listed as conforming in the MP table. */
568 #define default_ISA_trigger(idx) (0)
569 #define default_ISA_polarity(idx) (0)
571 /* PCI interrupts are always polarity one level triggered,
572 * when listed as conforming in the MP table. */
574 #define default_PCI_trigger(idx) (1)
575 #define default_PCI_polarity(idx) (1)
577 static int MPBIOS_polarity(int idx)
579 int bus = mp_irqs[idx].mpc_srcbus;
583 * Determine IRQ line polarity (high active or low active):
585 switch (mp_irqs[idx].mpc_irqflag & 3)
587 case 0: /* conforms, ie. bus-type dependent polarity */
588 if (test_bit(bus, mp_bus_not_pci))
589 polarity = default_ISA_polarity(idx);
591 polarity = default_PCI_polarity(idx);
593 case 1: /* high active */
598 case 2: /* reserved */
600 printk(KERN_WARNING "broken BIOS!!\n");
604 case 3: /* low active */
609 default: /* invalid */
611 printk(KERN_WARNING "broken BIOS!!\n");
619 static int MPBIOS_trigger(int idx)
621 int bus = mp_irqs[idx].mpc_srcbus;
625 * Determine IRQ trigger mode (edge or level sensitive):
627 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
629 case 0: /* conforms, ie. bus-type dependent */
630 if (test_bit(bus, mp_bus_not_pci))
631 trigger = default_ISA_trigger(idx);
633 trigger = default_PCI_trigger(idx);
640 case 2: /* reserved */
642 printk(KERN_WARNING "broken BIOS!!\n");
651 default: /* invalid */
653 printk(KERN_WARNING "broken BIOS!!\n");
661 static inline int irq_polarity(int idx)
663 return MPBIOS_polarity(idx);
666 static inline int irq_trigger(int idx)
668 return MPBIOS_trigger(idx);
671 static int pin_2_irq(int idx, int apic, int pin)
674 int bus = mp_irqs[idx].mpc_srcbus;
677 * Debugging check, we are in big trouble if this message pops up!
679 if (mp_irqs[idx].mpc_dstirq != pin)
680 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
682 if (test_bit(bus, mp_bus_not_pci)) {
683 irq = mp_irqs[idx].mpc_srcbusirq;
686 * PCI IRQs are mapped in order
690 irq += nr_ioapic_registers[i++];
693 BUG_ON(irq >= NR_IRQS);
697 static int __assign_irq_vector(int irq, cpumask_t mask)
700 * NOTE! The local APIC isn't very good at handling
701 * multiple interrupts at the same interrupt level.
702 * As the interrupt level is determined by taking the
703 * vector number and shifting that right by 4, we
704 * want to spread these out a bit so that they don't
705 * all fall in the same interrupt level.
707 * Also, we've got to be careful not to trash gate
708 * 0x80, because int 0x80 is hm, kind of importantish. ;)
710 static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
711 unsigned int old_vector;
715 BUG_ON((unsigned)irq >= NR_IRQS);
718 /* Only try and allocate irqs on cpus that are present */
719 cpus_and(mask, mask, cpu_online_map);
721 if ((cfg->move_in_progress) || cfg->move_cleanup_count)
724 old_vector = cfg->vector;
727 cpus_and(tmp, cfg->domain, mask);
728 if (!cpus_empty(tmp))
732 for_each_cpu_mask(cpu, mask) {
733 cpumask_t domain, new_mask;
737 domain = vector_allocation_domain(cpu);
738 cpus_and(new_mask, domain, cpu_online_map);
740 vector = current_vector;
741 offset = current_offset;
744 if (vector >= first_system_vector) {
745 /* If we run out of vectors on large boxen, must share them. */
746 offset = (offset + 1) % 8;
747 vector = FIRST_DEVICE_VECTOR + offset;
749 if (unlikely(current_vector == vector))
751 if (vector == IA32_SYSCALL_VECTOR)
753 for_each_cpu_mask(new_cpu, new_mask)
754 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
757 current_vector = vector;
758 current_offset = offset;
760 cfg->move_in_progress = 1;
761 cfg->old_domain = cfg->domain;
763 for_each_cpu_mask(new_cpu, new_mask)
764 per_cpu(vector_irq, new_cpu)[vector] = irq;
765 cfg->vector = vector;
766 cfg->domain = domain;
772 static int assign_irq_vector(int irq, cpumask_t mask)
777 spin_lock_irqsave(&vector_lock, flags);
778 err = __assign_irq_vector(irq, mask);
779 spin_unlock_irqrestore(&vector_lock, flags);
783 static void __clear_irq_vector(int irq)
789 BUG_ON((unsigned)irq >= NR_IRQS);
791 BUG_ON(!cfg->vector);
793 vector = cfg->vector;
794 cpus_and(mask, cfg->domain, cpu_online_map);
795 for_each_cpu_mask(cpu, mask)
796 per_cpu(vector_irq, cpu)[vector] = -1;
799 cpus_clear(cfg->domain);
802 void __setup_vector_irq(int cpu)
804 /* Initialize vector_irq on a new cpu */
805 /* This function must be called with vector_lock held */
808 /* Mark the inuse vectors */
809 for (irq = 0; irq < NR_IRQS; ++irq) {
810 if (!cpu_isset(cpu, irq_cfg[irq].domain))
812 vector = irq_cfg[irq].vector;
813 per_cpu(vector_irq, cpu)[vector] = irq;
815 /* Mark the free vectors */
816 for (vector = 0; vector < NR_VECTORS; ++vector) {
817 irq = per_cpu(vector_irq, cpu)[vector];
820 if (!cpu_isset(cpu, irq_cfg[irq].domain))
821 per_cpu(vector_irq, cpu)[vector] = -1;
826 static struct irq_chip ioapic_chip;
828 static void ioapic_register_intr(int irq, unsigned long trigger)
831 irq_desc[irq].status |= IRQ_LEVEL;
832 set_irq_chip_and_handler_name(irq, &ioapic_chip,
833 handle_fasteoi_irq, "fasteoi");
835 irq_desc[irq].status &= ~IRQ_LEVEL;
836 set_irq_chip_and_handler_name(irq, &ioapic_chip,
837 handle_edge_irq, "edge");
841 static void setup_IO_APIC_irq(int apic, int pin, unsigned int irq,
842 int trigger, int polarity)
844 struct irq_cfg *cfg = irq_cfg + irq;
845 struct IO_APIC_route_entry entry;
848 if (!IO_APIC_IRQ(irq))
852 if (assign_irq_vector(irq, mask))
855 cpus_and(mask, cfg->domain, mask);
857 apic_printk(APIC_VERBOSE,KERN_DEBUG
858 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
859 "IRQ %d Mode:%i Active:%i)\n",
860 apic, mp_ioapics[apic].mpc_apicid, pin, cfg->vector,
861 irq, trigger, polarity);
864 * add it to the IO-APIC irq-routing table:
866 memset(&entry,0,sizeof(entry));
868 entry.delivery_mode = INT_DELIVERY_MODE;
869 entry.dest_mode = INT_DEST_MODE;
870 entry.dest = cpu_mask_to_apicid(mask);
871 entry.mask = 0; /* enable IRQ */
872 entry.trigger = trigger;
873 entry.polarity = polarity;
874 entry.vector = cfg->vector;
876 /* Mask level triggered irqs.
877 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
882 ioapic_register_intr(irq, trigger);
884 disable_8259A_irq(irq);
886 ioapic_write_entry(apic, pin, entry);
889 static void __init setup_IO_APIC_irqs(void)
891 int apic, pin, idx, irq, first_notcon = 1;
893 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
895 for (apic = 0; apic < nr_ioapics; apic++) {
896 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
898 idx = find_irq_entry(apic,pin,mp_INT);
901 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
904 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
908 apic_printk(APIC_VERBOSE, " not connected.\n");
912 irq = pin_2_irq(idx, apic, pin);
913 add_pin_to_irq(irq, apic, pin);
915 setup_IO_APIC_irq(apic, pin, irq,
916 irq_trigger(idx), irq_polarity(idx));
921 apic_printk(APIC_VERBOSE, " not connected.\n");
925 * Set up the timer pin, possibly with the 8259A-master behind.
927 static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
930 struct IO_APIC_route_entry entry;
932 memset(&entry, 0, sizeof(entry));
935 * We use logical delivery to get the timer IRQ
938 entry.dest_mode = INT_DEST_MODE;
939 entry.mask = 1; /* mask IRQ now */
940 entry.dest = cpu_mask_to_apicid(TARGET_CPUS);
941 entry.delivery_mode = INT_DELIVERY_MODE;
944 entry.vector = vector;
947 * The timer IRQ doesn't have to know that behind the
948 * scene we may have a 8259A-master in AEOI mode ...
950 set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
953 * Add it to the IO-APIC irq-routing table:
955 ioapic_write_entry(apic, pin, entry);
958 void __apicdebuginit print_IO_APIC(void)
961 union IO_APIC_reg_00 reg_00;
962 union IO_APIC_reg_01 reg_01;
963 union IO_APIC_reg_02 reg_02;
966 if (apic_verbosity == APIC_QUIET)
969 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
970 for (i = 0; i < nr_ioapics; i++)
971 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
972 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
975 * We are a bit conservative about what we expect. We have to
976 * know about every hardware change ASAP.
978 printk(KERN_INFO "testing the IO APIC.......................\n");
980 for (apic = 0; apic < nr_ioapics; apic++) {
982 spin_lock_irqsave(&ioapic_lock, flags);
983 reg_00.raw = io_apic_read(apic, 0);
984 reg_01.raw = io_apic_read(apic, 1);
985 if (reg_01.bits.version >= 0x10)
986 reg_02.raw = io_apic_read(apic, 2);
987 spin_unlock_irqrestore(&ioapic_lock, flags);
990 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
991 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
992 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
994 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
995 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
997 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
998 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
1000 if (reg_01.bits.version >= 0x10) {
1001 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1002 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1005 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1007 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1008 " Stat Dmod Deli Vect: \n");
1010 for (i = 0; i <= reg_01.bits.entries; i++) {
1011 struct IO_APIC_route_entry entry;
1013 entry = ioapic_read_entry(apic, i);
1015 printk(KERN_DEBUG " %02x %03X ",
1020 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
1025 entry.delivery_status,
1027 entry.delivery_mode,
1032 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1033 for (i = 0; i < NR_IRQS; i++) {
1034 struct irq_pin_list *entry = irq_2_pin + i;
1037 printk(KERN_DEBUG "IRQ%d ", i);
1039 printk("-> %d:%d", entry->apic, entry->pin);
1042 entry = irq_2_pin + entry->next;
1047 printk(KERN_INFO ".................................... done.\n");
1054 static __apicdebuginit void print_APIC_bitfield (int base)
1059 if (apic_verbosity == APIC_QUIET)
1062 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1063 for (i = 0; i < 8; i++) {
1064 v = apic_read(base + i*0x10);
1065 for (j = 0; j < 32; j++) {
1075 void __apicdebuginit print_local_APIC(void * dummy)
1077 unsigned int v, ver, maxlvt;
1079 if (apic_verbosity == APIC_QUIET)
1082 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1083 smp_processor_id(), hard_smp_processor_id());
1084 v = apic_read(APIC_ID);
1085 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(read_apic_id()));
1086 v = apic_read(APIC_LVR);
1087 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1088 ver = GET_APIC_VERSION(v);
1089 maxlvt = lapic_get_maxlvt();
1091 v = apic_read(APIC_TASKPRI);
1092 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1094 v = apic_read(APIC_ARBPRI);
1095 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1096 v & APIC_ARBPRI_MASK);
1097 v = apic_read(APIC_PROCPRI);
1098 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1100 v = apic_read(APIC_EOI);
1101 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1102 v = apic_read(APIC_RRR);
1103 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1104 v = apic_read(APIC_LDR);
1105 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1106 v = apic_read(APIC_DFR);
1107 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1108 v = apic_read(APIC_SPIV);
1109 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1111 printk(KERN_DEBUG "... APIC ISR field:\n");
1112 print_APIC_bitfield(APIC_ISR);
1113 printk(KERN_DEBUG "... APIC TMR field:\n");
1114 print_APIC_bitfield(APIC_TMR);
1115 printk(KERN_DEBUG "... APIC IRR field:\n");
1116 print_APIC_bitfield(APIC_IRR);
1118 v = apic_read(APIC_ESR);
1119 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1121 v = apic_read(APIC_ICR);
1122 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1123 v = apic_read(APIC_ICR2);
1124 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1126 v = apic_read(APIC_LVTT);
1127 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1129 if (maxlvt > 3) { /* PC is LVT#4. */
1130 v = apic_read(APIC_LVTPC);
1131 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1133 v = apic_read(APIC_LVT0);
1134 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1135 v = apic_read(APIC_LVT1);
1136 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1138 if (maxlvt > 2) { /* ERR is LVT#3. */
1139 v = apic_read(APIC_LVTERR);
1140 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1143 v = apic_read(APIC_TMICT);
1144 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1145 v = apic_read(APIC_TMCCT);
1146 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1147 v = apic_read(APIC_TDCR);
1148 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1152 void print_all_local_APICs (void)
1154 on_each_cpu(print_local_APIC, NULL, 1, 1);
1157 void __apicdebuginit print_PIC(void)
1160 unsigned long flags;
1162 if (apic_verbosity == APIC_QUIET)
1165 printk(KERN_DEBUG "\nprinting PIC contents\n");
1167 spin_lock_irqsave(&i8259A_lock, flags);
1169 v = inb(0xa1) << 8 | inb(0x21);
1170 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1172 v = inb(0xa0) << 8 | inb(0x20);
1173 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1177 v = inb(0xa0) << 8 | inb(0x20);
1181 spin_unlock_irqrestore(&i8259A_lock, flags);
1183 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1185 v = inb(0x4d1) << 8 | inb(0x4d0);
1186 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1191 void __init enable_IO_APIC(void)
1193 union IO_APIC_reg_01 reg_01;
1194 int i8259_apic, i8259_pin;
1196 unsigned long flags;
1198 for (i = 0; i < PIN_MAP_SIZE; i++) {
1199 irq_2_pin[i].pin = -1;
1200 irq_2_pin[i].next = 0;
1204 * The number of IO-APIC IRQ registers (== #pins):
1206 for (apic = 0; apic < nr_ioapics; apic++) {
1207 spin_lock_irqsave(&ioapic_lock, flags);
1208 reg_01.raw = io_apic_read(apic, 1);
1209 spin_unlock_irqrestore(&ioapic_lock, flags);
1210 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
1212 for(apic = 0; apic < nr_ioapics; apic++) {
1214 /* See if any of the pins is in ExtINT mode */
1215 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1216 struct IO_APIC_route_entry entry;
1217 entry = ioapic_read_entry(apic, pin);
1219 /* If the interrupt line is enabled and in ExtInt mode
1220 * I have found the pin where the i8259 is connected.
1222 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1223 ioapic_i8259.apic = apic;
1224 ioapic_i8259.pin = pin;
1230 /* Look to see what if the MP table has reported the ExtINT */
1231 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1232 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1233 /* Trust the MP table if nothing is setup in the hardware */
1234 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1235 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1236 ioapic_i8259.pin = i8259_pin;
1237 ioapic_i8259.apic = i8259_apic;
1239 /* Complain if the MP table and the hardware disagree */
1240 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1241 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1243 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1247 * Do not trust the IO-APIC being empty at bootup
1253 * Not an __init, needed by the reboot code
1255 void disable_IO_APIC(void)
1258 * Clear the IO-APIC before rebooting:
1263 * If the i8259 is routed through an IOAPIC
1264 * Put that IOAPIC in virtual wire mode
1265 * so legacy interrupts can be delivered.
1267 if (ioapic_i8259.pin != -1) {
1268 struct IO_APIC_route_entry entry;
1270 memset(&entry, 0, sizeof(entry));
1271 entry.mask = 0; /* Enabled */
1272 entry.trigger = 0; /* Edge */
1274 entry.polarity = 0; /* High */
1275 entry.delivery_status = 0;
1276 entry.dest_mode = 0; /* Physical */
1277 entry.delivery_mode = dest_ExtINT; /* ExtInt */
1279 entry.dest = GET_APIC_ID(read_apic_id());
1282 * Add it to the IO-APIC irq-routing table:
1284 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
1287 disconnect_bsp_APIC(ioapic_i8259.pin != -1);
1291 * There is a nasty bug in some older SMP boards, their mptable lies
1292 * about the timer IRQ. We do the following to work around the situation:
1294 * - timer IRQ defaults to IO-APIC IRQ
1295 * - if this function detects that timer IRQs are defunct, then we fall
1296 * back to ISA timer IRQs
1298 static int __init timer_irq_works(void)
1300 unsigned long t1 = jiffies;
1301 unsigned long flags;
1303 local_save_flags(flags);
1305 /* Let ten ticks pass... */
1306 mdelay((10 * 1000) / HZ);
1307 local_irq_restore(flags);
1310 * Expect a few ticks at least, to be sure some possible
1311 * glue logic does not lock up after one or two first
1312 * ticks in a non-ExtINT mode. Also the local APIC
1313 * might have cached one ExtINT interrupt. Finally, at
1314 * least one tick may be lost due to delays.
1318 if (time_after(jiffies, t1 + 4))
1324 * In the SMP+IOAPIC case it might happen that there are an unspecified
1325 * number of pending IRQ events unhandled. These cases are very rare,
1326 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1327 * better to do it this way as thus we do not have to be aware of
1328 * 'pending' interrupts in the IRQ path, except at this point.
1331 * Edge triggered needs to resend any interrupt
1332 * that was delayed but this is now handled in the device
1337 * Starting up a edge-triggered IO-APIC interrupt is
1338 * nasty - we need to make sure that we get the edge.
1339 * If it is already asserted for some reason, we need
1340 * return 1 to indicate that is was pending.
1342 * This is not complete - we should be able to fake
1343 * an edge even if it isn't on the 8259A...
1346 static unsigned int startup_ioapic_irq(unsigned int irq)
1348 int was_pending = 0;
1349 unsigned long flags;
1351 spin_lock_irqsave(&ioapic_lock, flags);
1353 disable_8259A_irq(irq);
1354 if (i8259A_irq_pending(irq))
1357 __unmask_IO_APIC_irq(irq);
1358 spin_unlock_irqrestore(&ioapic_lock, flags);
1363 static int ioapic_retrigger_irq(unsigned int irq)
1365 struct irq_cfg *cfg = &irq_cfg[irq];
1367 unsigned long flags;
1369 spin_lock_irqsave(&vector_lock, flags);
1370 mask = cpumask_of_cpu(first_cpu(cfg->domain));
1371 send_IPI_mask(mask, cfg->vector);
1372 spin_unlock_irqrestore(&vector_lock, flags);
1378 * Level and edge triggered IO-APIC interrupts need different handling,
1379 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1380 * handled with the level-triggered descriptor, but that one has slightly
1381 * more overhead. Level-triggered interrupts cannot be handled with the
1382 * edge-triggered handler, without risking IRQ storms and other ugly
1387 asmlinkage void smp_irq_move_cleanup_interrupt(void)
1389 unsigned vector, me;
1394 me = smp_processor_id();
1395 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
1397 struct irq_desc *desc;
1398 struct irq_cfg *cfg;
1399 irq = __get_cpu_var(vector_irq)[vector];
1403 desc = irq_desc + irq;
1404 cfg = irq_cfg + irq;
1405 spin_lock(&desc->lock);
1406 if (!cfg->move_cleanup_count)
1409 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain))
1412 __get_cpu_var(vector_irq)[vector] = -1;
1413 cfg->move_cleanup_count--;
1415 spin_unlock(&desc->lock);
1421 static void irq_complete_move(unsigned int irq)
1423 struct irq_cfg *cfg = irq_cfg + irq;
1424 unsigned vector, me;
1426 if (likely(!cfg->move_in_progress))
1429 vector = ~get_irq_regs()->orig_ax;
1430 me = smp_processor_id();
1431 if ((vector == cfg->vector) && cpu_isset(me, cfg->domain)) {
1432 cpumask_t cleanup_mask;
1434 cpus_and(cleanup_mask, cfg->old_domain, cpu_online_map);
1435 cfg->move_cleanup_count = cpus_weight(cleanup_mask);
1436 send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
1437 cfg->move_in_progress = 0;
1441 static inline void irq_complete_move(unsigned int irq) {}
1444 static void ack_apic_edge(unsigned int irq)
1446 irq_complete_move(irq);
1447 move_native_irq(irq);
1451 static void ack_apic_level(unsigned int irq)
1453 int do_unmask_irq = 0;
1455 irq_complete_move(irq);
1456 #ifdef CONFIG_GENERIC_PENDING_IRQ
1457 /* If we are moving the irq we need to mask it */
1458 if (unlikely(irq_desc[irq].status & IRQ_MOVE_PENDING)) {
1460 mask_IO_APIC_irq(irq);
1465 * We must acknowledge the irq before we move it or the acknowledge will
1466 * not propagate properly.
1470 /* Now we can move and renable the irq */
1471 if (unlikely(do_unmask_irq)) {
1472 /* Only migrate the irq if the ack has been received.
1474 * On rare occasions the broadcast level triggered ack gets
1475 * delayed going to ioapics, and if we reprogram the
1476 * vector while Remote IRR is still set the irq will never
1479 * To prevent this scenario we read the Remote IRR bit
1480 * of the ioapic. This has two effects.
1481 * - On any sane system the read of the ioapic will
1482 * flush writes (and acks) going to the ioapic from
1484 * - We get to see if the ACK has actually been delivered.
1486 * Based on failed experiments of reprogramming the
1487 * ioapic entry from outside of irq context starting
1488 * with masking the ioapic entry and then polling until
1489 * Remote IRR was clear before reprogramming the
1490 * ioapic I don't trust the Remote IRR bit to be
1491 * completey accurate.
1493 * However there appears to be no other way to plug
1494 * this race, so if the Remote IRR bit is not
1495 * accurate and is causing problems then it is a hardware bug
1496 * and you can go talk to the chipset vendor about it.
1498 if (!io_apic_level_ack_pending(irq))
1499 move_masked_irq(irq);
1500 unmask_IO_APIC_irq(irq);
1504 static struct irq_chip ioapic_chip __read_mostly = {
1506 .startup = startup_ioapic_irq,
1507 .mask = mask_IO_APIC_irq,
1508 .unmask = unmask_IO_APIC_irq,
1509 .ack = ack_apic_edge,
1510 .eoi = ack_apic_level,
1512 .set_affinity = set_ioapic_affinity_irq,
1514 .retrigger = ioapic_retrigger_irq,
1517 static inline void init_IO_APIC_traps(void)
1522 * NOTE! The local APIC isn't very good at handling
1523 * multiple interrupts at the same interrupt level.
1524 * As the interrupt level is determined by taking the
1525 * vector number and shifting that right by 4, we
1526 * want to spread these out a bit so that they don't
1527 * all fall in the same interrupt level.
1529 * Also, we've got to be careful not to trash gate
1530 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1532 for (irq = 0; irq < NR_IRQS ; irq++) {
1533 if (IO_APIC_IRQ(irq) && !irq_cfg[irq].vector) {
1535 * Hmm.. We don't have an entry for this,
1536 * so default to an old-fashioned 8259
1537 * interrupt if we can..
1540 make_8259A_irq(irq);
1542 /* Strange. Oh, well.. */
1543 irq_desc[irq].chip = &no_irq_chip;
1548 static void enable_lapic_irq (unsigned int irq)
1552 v = apic_read(APIC_LVT0);
1553 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
1556 static void disable_lapic_irq (unsigned int irq)
1560 v = apic_read(APIC_LVT0);
1561 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
1564 static void ack_lapic_irq (unsigned int irq)
1569 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1571 static struct hw_interrupt_type lapic_irq_type __read_mostly = {
1572 .name = "local-APIC",
1573 .typename = "local-APIC-edge",
1574 .startup = NULL, /* startup_irq() not used for IRQ0 */
1575 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1576 .enable = enable_lapic_irq,
1577 .disable = disable_lapic_irq,
1578 .ack = ack_lapic_irq,
1579 .end = end_lapic_irq,
1582 static void __init setup_nmi(void)
1585 * Dirty trick to enable the NMI watchdog ...
1586 * We put the 8259A master into AEOI mode and
1587 * unmask on all local APICs LVT0 as NMI.
1589 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1590 * is from Maciej W. Rozycki - so we do not have to EOI from
1591 * the NMI handler or the timer interrupt.
1593 printk(KERN_INFO "activating NMI Watchdog ...");
1595 enable_NMI_through_LVT0();
1601 * This looks a bit hackish but it's about the only one way of sending
1602 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1603 * not support the ExtINT mode, unfortunately. We need to send these
1604 * cycles as some i82489DX-based boards have glue logic that keeps the
1605 * 8259A interrupt line asserted until INTA. --macro
1607 static inline void __init unlock_ExtINT_logic(void)
1610 struct IO_APIC_route_entry entry0, entry1;
1611 unsigned char save_control, save_freq_select;
1613 pin = find_isa_irq_pin(8, mp_INT);
1614 apic = find_isa_irq_apic(8, mp_INT);
1618 entry0 = ioapic_read_entry(apic, pin);
1620 clear_IO_APIC_pin(apic, pin);
1622 memset(&entry1, 0, sizeof(entry1));
1624 entry1.dest_mode = 0; /* physical delivery */
1625 entry1.mask = 0; /* unmask IRQ now */
1626 entry1.dest = hard_smp_processor_id();
1627 entry1.delivery_mode = dest_ExtINT;
1628 entry1.polarity = entry0.polarity;
1632 ioapic_write_entry(apic, pin, entry1);
1634 save_control = CMOS_READ(RTC_CONTROL);
1635 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1636 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1638 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1643 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1647 CMOS_WRITE(save_control, RTC_CONTROL);
1648 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1649 clear_IO_APIC_pin(apic, pin);
1651 ioapic_write_entry(apic, pin, entry0);
1655 * This code may look a bit paranoid, but it's supposed to cooperate with
1656 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1657 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1658 * fanatically on his truly buggy board.
1660 * FIXME: really need to revamp this for modern platforms only.
1662 static inline void __init check_timer(void)
1664 struct irq_cfg *cfg = irq_cfg + 0;
1665 int apic1, pin1, apic2, pin2;
1666 unsigned long flags;
1669 local_irq_save(flags);
1672 * get/set the timer IRQ vector:
1674 disable_8259A_irq(0);
1675 assign_irq_vector(0, TARGET_CPUS);
1678 * As IRQ0 is to be enabled in the 8259A, the virtual
1679 * wire has to be disabled in the local APIC.
1681 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1684 pin1 = find_isa_irq_pin(0, mp_INT);
1685 apic1 = find_isa_irq_apic(0, mp_INT);
1686 pin2 = ioapic_i8259.pin;
1687 apic2 = ioapic_i8259.apic;
1689 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
1690 cfg->vector, apic1, pin1, apic2, pin2);
1693 * Some BIOS writers are clueless and report the ExtINTA
1694 * I/O APIC input from the cascaded 8259A as the timer
1695 * interrupt input. So just in case, if only one pin
1696 * was found above, try it both directly and through the
1703 } else if (pin2 == -1) {
1708 replace_pin_at_irq(0, 0, 0, apic1, pin1);
1711 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
1715 * Ok, does IRQ0 through the IOAPIC work?
1718 add_pin_to_irq(0, apic1, pin1);
1719 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
1721 unmask_IO_APIC_irq(0);
1722 if (!no_timer_check && timer_irq_works()) {
1723 nmi_watchdog_default();
1724 if (nmi_watchdog == NMI_IO_APIC) {
1726 enable_8259A_irq(0);
1728 if (disable_timer_pin_1 > 0)
1729 clear_IO_APIC_pin(0, pin1);
1732 clear_IO_APIC_pin(apic1, pin1);
1734 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: "
1735 "8254 timer not connected to IO-APIC\n");
1737 apic_printk(APIC_VERBOSE,KERN_INFO
1738 "...trying to set up timer (IRQ0) "
1739 "through the 8259A ... ");
1740 apic_printk(APIC_VERBOSE,"\n..... (found apic %d pin %d) ...",
1743 * legacy devices should be connected to IO APIC #0
1745 replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
1746 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
1747 unmask_IO_APIC_irq(0);
1748 enable_8259A_irq(0);
1749 if (timer_irq_works()) {
1750 apic_printk(APIC_VERBOSE," works.\n");
1751 timer_through_8259 = 1;
1752 nmi_watchdog_default();
1753 if (nmi_watchdog == NMI_IO_APIC) {
1754 disable_8259A_irq(0);
1756 enable_8259A_irq(0);
1761 * Cleanup, just in case ...
1763 disable_8259A_irq(0);
1764 clear_IO_APIC_pin(apic2, pin2);
1765 apic_printk(APIC_VERBOSE," failed.\n");
1768 if (nmi_watchdog == NMI_IO_APIC) {
1769 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1770 nmi_watchdog = NMI_NONE;
1773 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1775 irq_desc[0].chip = &lapic_irq_type;
1776 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
1777 enable_8259A_irq(0);
1779 if (timer_irq_works()) {
1780 apic_printk(APIC_VERBOSE," works.\n");
1783 disable_8259A_irq(0);
1784 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
1785 apic_printk(APIC_VERBOSE," failed.\n");
1787 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1791 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1793 unlock_ExtINT_logic();
1795 if (timer_irq_works()) {
1796 apic_printk(APIC_VERBOSE," works.\n");
1799 apic_printk(APIC_VERBOSE," failed :(.\n");
1800 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1802 local_irq_restore(flags);
1805 static int __init notimercheck(char *s)
1810 __setup("no_timer_check", notimercheck);
1814 * IRQs that are handled by the PIC in the MPS IOAPIC case.
1815 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1816 * Linux doesn't really care, as it's not actually used
1817 * for any interrupt handling anyway.
1819 #define PIC_IRQS (1<<2)
1821 void __init setup_IO_APIC(void)
1825 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
1829 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1831 io_apic_irqs = ~PIC_IRQS;
1833 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1836 setup_IO_APIC_irqs();
1837 init_IO_APIC_traps();
1843 struct sysfs_ioapic_data {
1844 struct sys_device dev;
1845 struct IO_APIC_route_entry entry[0];
1847 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1849 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
1851 struct IO_APIC_route_entry *entry;
1852 struct sysfs_ioapic_data *data;
1855 data = container_of(dev, struct sysfs_ioapic_data, dev);
1856 entry = data->entry;
1857 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
1858 *entry = ioapic_read_entry(dev->id, i);
1863 static int ioapic_resume(struct sys_device *dev)
1865 struct IO_APIC_route_entry *entry;
1866 struct sysfs_ioapic_data *data;
1867 unsigned long flags;
1868 union IO_APIC_reg_00 reg_00;
1871 data = container_of(dev, struct sysfs_ioapic_data, dev);
1872 entry = data->entry;
1874 spin_lock_irqsave(&ioapic_lock, flags);
1875 reg_00.raw = io_apic_read(dev->id, 0);
1876 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1877 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1878 io_apic_write(dev->id, 0, reg_00.raw);
1880 spin_unlock_irqrestore(&ioapic_lock, flags);
1881 for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
1882 ioapic_write_entry(dev->id, i, entry[i]);
1887 static struct sysdev_class ioapic_sysdev_class = {
1889 .suspend = ioapic_suspend,
1890 .resume = ioapic_resume,
1893 static int __init ioapic_init_sysfs(void)
1895 struct sys_device * dev;
1898 error = sysdev_class_register(&ioapic_sysdev_class);
1902 for (i = 0; i < nr_ioapics; i++ ) {
1903 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1904 * sizeof(struct IO_APIC_route_entry);
1905 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
1906 if (!mp_ioapic_data[i]) {
1907 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1910 dev = &mp_ioapic_data[i]->dev;
1912 dev->cls = &ioapic_sysdev_class;
1913 error = sysdev_register(dev);
1915 kfree(mp_ioapic_data[i]);
1916 mp_ioapic_data[i] = NULL;
1917 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1925 device_initcall(ioapic_init_sysfs);
1928 * Dynamic irq allocate and deallocation
1930 int create_irq(void)
1932 /* Allocate an unused irq */
1935 unsigned long flags;
1938 spin_lock_irqsave(&vector_lock, flags);
1939 for (new = (NR_IRQS - 1); new >= 0; new--) {
1940 if (platform_legacy_irq(new))
1942 if (irq_cfg[new].vector != 0)
1944 if (__assign_irq_vector(new, TARGET_CPUS) == 0)
1948 spin_unlock_irqrestore(&vector_lock, flags);
1951 dynamic_irq_init(irq);
1956 void destroy_irq(unsigned int irq)
1958 unsigned long flags;
1960 dynamic_irq_cleanup(irq);
1962 spin_lock_irqsave(&vector_lock, flags);
1963 __clear_irq_vector(irq);
1964 spin_unlock_irqrestore(&vector_lock, flags);
1968 * MSI message composition
1970 #ifdef CONFIG_PCI_MSI
1971 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
1973 struct irq_cfg *cfg = irq_cfg + irq;
1979 err = assign_irq_vector(irq, tmp);
1981 cpus_and(tmp, cfg->domain, tmp);
1982 dest = cpu_mask_to_apicid(tmp);
1984 msg->address_hi = MSI_ADDR_BASE_HI;
1987 ((INT_DEST_MODE == 0) ?
1988 MSI_ADDR_DEST_MODE_PHYSICAL:
1989 MSI_ADDR_DEST_MODE_LOGICAL) |
1990 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1991 MSI_ADDR_REDIRECTION_CPU:
1992 MSI_ADDR_REDIRECTION_LOWPRI) |
1993 MSI_ADDR_DEST_ID(dest);
1996 MSI_DATA_TRIGGER_EDGE |
1997 MSI_DATA_LEVEL_ASSERT |
1998 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
1999 MSI_DATA_DELIVERY_FIXED:
2000 MSI_DATA_DELIVERY_LOWPRI) |
2001 MSI_DATA_VECTOR(cfg->vector);
2007 static void set_msi_irq_affinity(unsigned int irq, cpumask_t mask)
2009 struct irq_cfg *cfg = irq_cfg + irq;
2014 cpus_and(tmp, mask, cpu_online_map);
2015 if (cpus_empty(tmp))
2018 if (assign_irq_vector(irq, mask))
2021 cpus_and(tmp, cfg->domain, mask);
2022 dest = cpu_mask_to_apicid(tmp);
2024 read_msi_msg(irq, &msg);
2026 msg.data &= ~MSI_DATA_VECTOR_MASK;
2027 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2028 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2029 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2031 write_msi_msg(irq, &msg);
2032 irq_desc[irq].affinity = mask;
2034 #endif /* CONFIG_SMP */
2037 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
2038 * which implement the MSI or MSI-X Capability Structure.
2040 static struct irq_chip msi_chip = {
2042 .unmask = unmask_msi_irq,
2043 .mask = mask_msi_irq,
2044 .ack = ack_apic_edge,
2046 .set_affinity = set_msi_irq_affinity,
2048 .retrigger = ioapic_retrigger_irq,
2051 int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2059 ret = msi_compose_msg(dev, irq, &msg);
2065 set_irq_msi(irq, desc);
2066 write_msi_msg(irq, &msg);
2068 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
2073 void arch_teardown_msi_irq(unsigned int irq)
2080 static void dmar_msi_set_affinity(unsigned int irq, cpumask_t mask)
2082 struct irq_cfg *cfg = irq_cfg + irq;
2087 cpus_and(tmp, mask, cpu_online_map);
2088 if (cpus_empty(tmp))
2091 if (assign_irq_vector(irq, mask))
2094 cpus_and(tmp, cfg->domain, mask);
2095 dest = cpu_mask_to_apicid(tmp);
2097 dmar_msi_read(irq, &msg);
2099 msg.data &= ~MSI_DATA_VECTOR_MASK;
2100 msg.data |= MSI_DATA_VECTOR(cfg->vector);
2101 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
2102 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
2104 dmar_msi_write(irq, &msg);
2105 irq_desc[irq].affinity = mask;
2107 #endif /* CONFIG_SMP */
2109 struct irq_chip dmar_msi_type = {
2111 .unmask = dmar_msi_unmask,
2112 .mask = dmar_msi_mask,
2113 .ack = ack_apic_edge,
2115 .set_affinity = dmar_msi_set_affinity,
2117 .retrigger = ioapic_retrigger_irq,
2120 int arch_setup_dmar_msi(unsigned int irq)
2125 ret = msi_compose_msg(NULL, irq, &msg);
2128 dmar_msi_write(irq, &msg);
2129 set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
2135 #endif /* CONFIG_PCI_MSI */
2137 * Hypertransport interrupt support
2139 #ifdef CONFIG_HT_IRQ
2143 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
2145 struct ht_irq_msg msg;
2146 fetch_ht_irq_msg(irq, &msg);
2148 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
2149 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
2151 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
2152 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
2154 write_ht_irq_msg(irq, &msg);
2157 static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
2159 struct irq_cfg *cfg = irq_cfg + irq;
2163 cpus_and(tmp, mask, cpu_online_map);
2164 if (cpus_empty(tmp))
2167 if (assign_irq_vector(irq, mask))
2170 cpus_and(tmp, cfg->domain, mask);
2171 dest = cpu_mask_to_apicid(tmp);
2173 target_ht_irq(irq, dest, cfg->vector);
2174 irq_desc[irq].affinity = mask;
2178 static struct irq_chip ht_irq_chip = {
2180 .mask = mask_ht_irq,
2181 .unmask = unmask_ht_irq,
2182 .ack = ack_apic_edge,
2184 .set_affinity = set_ht_irq_affinity,
2186 .retrigger = ioapic_retrigger_irq,
2189 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2191 struct irq_cfg *cfg = irq_cfg + irq;
2196 err = assign_irq_vector(irq, tmp);
2198 struct ht_irq_msg msg;
2201 cpus_and(tmp, cfg->domain, tmp);
2202 dest = cpu_mask_to_apicid(tmp);
2204 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2208 HT_IRQ_LOW_DEST_ID(dest) |
2209 HT_IRQ_LOW_VECTOR(cfg->vector) |
2210 ((INT_DEST_MODE == 0) ?
2211 HT_IRQ_LOW_DM_PHYSICAL :
2212 HT_IRQ_LOW_DM_LOGICAL) |
2213 HT_IRQ_LOW_RQEOI_EDGE |
2214 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2215 HT_IRQ_LOW_MT_FIXED :
2216 HT_IRQ_LOW_MT_ARBITRATED) |
2217 HT_IRQ_LOW_IRQ_MASKED;
2219 write_ht_irq_msg(irq, &msg);
2221 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2222 handle_edge_irq, "edge");
2226 #endif /* CONFIG_HT_IRQ */
2228 /* --------------------------------------------------------------------------
2229 ACPI-based IOAPIC Configuration
2230 -------------------------------------------------------------------------- */
2234 #define IO_APIC_MAX_ID 0xFE
2236 int __init io_apic_get_redir_entries (int ioapic)
2238 union IO_APIC_reg_01 reg_01;
2239 unsigned long flags;
2241 spin_lock_irqsave(&ioapic_lock, flags);
2242 reg_01.raw = io_apic_read(ioapic, 1);
2243 spin_unlock_irqrestore(&ioapic_lock, flags);
2245 return reg_01.bits.entries;
2249 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
2251 if (!IO_APIC_IRQ(irq)) {
2252 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
2258 * IRQs < 16 are already in the irq_2_pin[] map
2261 add_pin_to_irq(irq, ioapic, pin);
2263 setup_IO_APIC_irq(ioapic, pin, irq, triggering, polarity);
2269 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
2273 if (skip_ioapic_setup)
2276 for (i = 0; i < mp_irq_entries; i++)
2277 if (mp_irqs[i].mpc_irqtype == mp_INT &&
2278 mp_irqs[i].mpc_srcbusirq == bus_irq)
2280 if (i >= mp_irq_entries)
2283 *trigger = irq_trigger(i);
2284 *polarity = irq_polarity(i);
2288 #endif /* CONFIG_ACPI */
2291 * This function currently is only a helper for the i386 smp boot process where
2292 * we need to reprogram the ioredtbls to cater for the cpus which have come online
2293 * so mask in all cases should simply be TARGET_CPUS
2296 void __init setup_ioapic_dest(void)
2298 int pin, ioapic, irq, irq_entry;
2300 if (skip_ioapic_setup == 1)
2303 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
2304 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
2305 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
2306 if (irq_entry == -1)
2308 irq = pin_2_irq(irq_entry, ioapic, pin);
2310 /* setup_IO_APIC_irqs could fail to get vector for some device
2311 * when you have too many devices, because at that time only boot
2314 if (!irq_cfg[irq].vector)
2315 setup_IO_APIC_irq(ioapic, pin, irq,
2316 irq_trigger(irq_entry),
2317 irq_polarity(irq_entry));
2319 set_ioapic_affinity_irq(irq, TARGET_CPUS);
2326 #define IOAPIC_RESOURCE_NAME_SIZE 11
2328 static struct resource *ioapic_resources;
2330 static struct resource * __init ioapic_setup_resources(void)
2333 struct resource *res;
2337 if (nr_ioapics <= 0)
2340 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
2343 mem = alloc_bootmem(n);
2347 mem += sizeof(struct resource) * nr_ioapics;
2349 for (i = 0; i < nr_ioapics; i++) {
2351 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
2352 sprintf(mem, "IOAPIC %u", i);
2353 mem += IOAPIC_RESOURCE_NAME_SIZE;
2357 ioapic_resources = res;
2362 void __init ioapic_init_mappings(void)
2364 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
2365 struct resource *ioapic_res;
2368 ioapic_res = ioapic_setup_resources();
2369 for (i = 0; i < nr_ioapics; i++) {
2370 if (smp_found_config) {
2371 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
2373 ioapic_phys = (unsigned long)
2374 alloc_bootmem_pages(PAGE_SIZE);
2375 ioapic_phys = __pa(ioapic_phys);
2377 set_fixmap_nocache(idx, ioapic_phys);
2378 apic_printk(APIC_VERBOSE,
2379 "mapped IOAPIC to %016lx (%016lx)\n",
2380 __fix_to_virt(idx), ioapic_phys);
2383 if (ioapic_res != NULL) {
2384 ioapic_res->start = ioapic_phys;
2385 ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
2391 static int __init ioapic_insert_resources(void)
2394 struct resource *r = ioapic_resources;
2398 "IO APIC resources could be not be allocated.\n");
2402 for (i = 0; i < nr_ioapics; i++) {
2403 insert_resource(&iomem_resource, r);
2410 /* Insert the IO APIC resources after PCI initialization has occured to handle
2411 * IO APICS that are mapped in on a BAR in PCI space. */
2412 late_initcall(ioapic_insert_resources);