2 * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
8 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com>
12 #include <linux/linkage.h>
13 #include <linux/threads.h>
14 #include <linux/init.h>
15 #include <asm/segment.h>
16 #include <asm/pgtable.h>
19 #include <asm/cache.h>
20 #include <asm/processor-flags.h>
21 #include <asm/percpu.h>
23 #ifdef CONFIG_PARAVIRT
24 #include <asm/asm-offsets.h>
25 #include <asm/paravirt.h>
27 #define GET_CR2_INTO_RCX movq %cr2, %rcx
30 /* we are not able to switch in one step to the final KERNEL ADDRESS SPACE
31 * because we need identity-mapped pages.
35 #define pud_index(x) (((x) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
37 L4_PAGE_OFFSET = pgd_index(__PAGE_OFFSET)
38 L3_PAGE_OFFSET = pud_index(__PAGE_OFFSET)
39 L4_START_KERNEL = pgd_index(__START_KERNEL_map)
40 L3_START_KERNEL = pud_index(__START_KERNEL_map)
49 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
50 * and someone has loaded an identity mapped page table
51 * for us. These identity mapped page tables map all of the
52 * kernel pages and possibly all of memory.
54 * %esi holds a physical pointer to real_mode_data.
56 * We come here either directly from a 64bit bootloader, or from
57 * arch/x86_64/boot/compressed/head.S.
59 * We only come here initially at boot nothing else comes here.
61 * Since we may be loaded at an address different from what we were
62 * compiled to run at we first fixup the physical addresses in our page
63 * tables and then reload them.
66 /* Sanitize CPU configuration */
69 /* Compute the delta between the address I am compiled to run at and the
70 * address I am actually running at.
72 leaq _text(%rip), %rbp
73 subq $_text - __START_KERNEL_map, %rbp
75 /* Is the address not 2M aligned? */
77 andl $~PMD_PAGE_MASK, %eax
81 /* Is the address too large? */
82 leaq _text(%rip), %rdx
83 movq $PGDIR_SIZE, %rax
87 /* Fixup the physical addresses in the page table
89 addq %rbp, init_level4_pgt + 0(%rip)
90 addq %rbp, init_level4_pgt + (L4_PAGE_OFFSET*8)(%rip)
91 addq %rbp, init_level4_pgt + (L4_START_KERNEL*8)(%rip)
93 addq %rbp, level3_ident_pgt + 0(%rip)
95 addq %rbp, level3_kernel_pgt + (510*8)(%rip)
96 addq %rbp, level3_kernel_pgt + (511*8)(%rip)
98 addq %rbp, level2_fixmap_pgt + (506*8)(%rip)
100 /* Add an Identity mapping if I am above 1G */
101 leaq _text(%rip), %rdi
102 andq $PMD_PAGE_MASK, %rdi
105 shrq $PUD_SHIFT, %rax
106 andq $(PTRS_PER_PUD - 1), %rax
109 leaq (level2_spare_pgt - __START_KERNEL_map + _KERNPG_TABLE)(%rbp), %rdx
110 leaq level3_ident_pgt(%rip), %rbx
111 movq %rdx, 0(%rbx, %rax, 8)
114 shrq $PMD_SHIFT, %rax
115 andq $(PTRS_PER_PMD - 1), %rax
116 leaq __PAGE_KERNEL_IDENT_LARGE_EXEC(%rdi), %rdx
117 leaq level2_spare_pgt(%rip), %rbx
118 movq %rdx, 0(%rbx, %rax, 8)
122 * Fixup the kernel text+data virtual addresses. Note that
123 * we might write invalid pmds, when the kernel is relocated
124 * cleanup_highmap() fixes this up along with the mappings
128 leaq level2_kernel_pgt(%rip), %rdi
130 /* See if it is a valid page table entry */
134 /* Go to the next page */
139 /* Fixup phys_base */
140 addq %rbp, phys_base(%rip)
142 /* Fixup trampoline */
143 addq %rbp, trampoline_level4_pgt + 0(%rip)
144 addq %rbp, trampoline_level4_pgt + (511*8)(%rip)
146 /* Due to ENTRY(), sometimes the empty space gets filled with
147 * zeros. Better take a jmp than relying on empty space being
148 * filled with 0x90 (nop)
150 jmp secondary_startup_64
151 ENTRY(secondary_startup_64)
153 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 1,
154 * and someone has loaded a mapped page table.
156 * %esi holds a physical pointer to real_mode_data.
158 * We come here either from startup_64 (using physical addresses)
159 * or from trampoline.S (using virtual addresses).
161 * Using virtual addresses from trampoline.S removes the need
162 * to have any identity mapped pages in the kernel page table
163 * after the boot processor executes this code.
166 /* Sanitize CPU configuration */
169 /* Enable PAE mode and PGE */
170 movl $(X86_CR4_PAE | X86_CR4_PGE), %eax
173 /* Setup early boot stage 4 level pagetables. */
174 movq $(init_level4_pgt - __START_KERNEL_map), %rax
175 addq phys_base(%rip), %rax
178 /* Ensure I am executing from virtual addresses */
183 /* Check if nx is implemented */
184 movl $0x80000001, %eax
188 /* Setup EFER (Extended Feature Enable Register) */
191 btsl $_EFER_SCE, %eax /* Enable System Call */
192 btl $20,%edi /* No Execute supported? */
195 1: wrmsr /* Make changes effective */
198 #define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
199 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
201 movl $CR0_STATE, %eax
202 /* Make changes effective */
205 /* Setup a boot time stack */
206 movq stack_start(%rip),%rsp
208 /* zero EFLAGS after setting rsp */
213 * We must switch to a new descriptor in kernel space for the GDT
214 * because soon the kernel won't have access anymore to the userspace
215 * addresses where we're currently running on. We have to do that here
216 * because in 32bit we couldn't load a 64bit linear address.
218 lgdt early_gdt_descr(%rip)
220 /* set up data segments */
227 * We don't really need to load %fs or %gs, but load them anyway
228 * to kill any stale realmode selectors. This allows execution
236 * The base of %gs always points to the bottom of the irqstack
237 * union. If the stack protector canary is enabled, it is
238 * located at %gs:40. Note that, on SMP, the boot cpu uses
239 * init data section till per cpu areas are set up.
241 movl $MSR_GS_BASE,%ecx
242 movl initial_gs(%rip),%eax
243 movl initial_gs+4(%rip),%edx
246 /* esi is pointer to real mode structure with interesting info.
250 /* Finally jump to run C code and to be on real kernel address
251 * Since we are running on identity-mapped space we have to jump
252 * to the full 64bit address, this is only possible as indirect
253 * jump. In addition we need to ensure %cs is set so we make this
256 movq initial_code(%rip),%rax
257 pushq $0 # fake return address to stop unwinder
258 pushq $__KERNEL_CS # set correct cs
259 pushq %rax # target address in negative space
262 #include "verify_cpu.S"
264 /* SMP bootup changes these two */
268 .quad x86_64_start_kernel
270 .quad INIT_PER_CPU_VAR(irq_stack_union)
273 .quad init_thread_union+THREAD_SIZE-8
280 .section ".init.text","ax"
281 #ifdef CONFIG_EARLY_PRINTK
282 .globl early_idt_handlers
285 .rept NUM_EXCEPTION_VECTORS
287 jmp early_idt_handler
292 ENTRY(early_idt_handler)
293 #ifdef CONFIG_EARLY_PRINTK
294 cmpl $2,early_recursion_flag(%rip)
296 incl early_recursion_flag(%rip)
299 xorl %r8d,%r8d # zero for error code
300 movl %esi,%ecx # get vector number
301 # Test %ecx against mask of vectors that push error code.
308 popq %r8 # get error code
309 0: movq 0(%rsp),%rcx # get ip
310 movq 8(%rsp),%rdx # get cs
312 leaq early_idt_msg(%rip),%rdi
314 cmpl $2,early_recursion_flag(%rip)
317 #ifdef CONFIG_KALLSYMS
318 leaq early_idt_ripmsg(%rip),%rdi
319 movq 0(%rsp),%rsi # get rip again
322 #endif /* EARLY_PRINTK */
326 #ifdef CONFIG_EARLY_PRINTK
327 early_recursion_flag:
331 .asciz "PANIC: early exception %02lx rip %lx:%lx error %lx cr2 %lx\n"
334 #endif /* CONFIG_EARLY_PRINTK */
337 #define NEXT_PAGE(name) \
341 /* Automate the creation of 1 to 1 mapping pmd entries */
342 #define PMDS(START, PERM, COUNT) \
345 .quad (START) + (i << PMD_SHIFT) + (PERM) ; \
351 * This default setting generates an ident mapping at address 0x100000
352 * and a mapping for the kernel that precisely maps virtual address
353 * 0xffffffff80000000 to physical address 0x000000. (always using
354 * 2Mbyte large pages provided by PAE mode)
356 NEXT_PAGE(init_level4_pgt)
357 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
358 .org init_level4_pgt + L4_PAGE_OFFSET*8, 0
359 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
360 .org init_level4_pgt + L4_START_KERNEL*8, 0
361 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
362 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE
364 NEXT_PAGE(level3_ident_pgt)
365 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE
368 NEXT_PAGE(level3_kernel_pgt)
369 .fill L3_START_KERNEL,8,0
370 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */
371 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE
372 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
374 NEXT_PAGE(level2_fixmap_pgt)
376 .quad level1_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE
377 /* 8MB reserved for vsyscalls + a 2MB hole = 4 + 1 entries */
380 NEXT_PAGE(level1_fixmap_pgt)
383 NEXT_PAGE(level2_ident_pgt)
384 /* Since I easily can, map the first 1G.
385 * Don't set NX because code runs from these pages.
387 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD)
389 NEXT_PAGE(level2_kernel_pgt)
391 * 512 MB kernel mapping. We spend a full page on this pagetable
394 * The kernel code+data+bss must not be bigger than that.
396 * (NOTE: at +512MB starts the module area, see MODULES_VADDR.
397 * If you want to increase this then increase MODULES_VADDR
400 PMDS(0, __PAGE_KERNEL_LARGE_EXEC,
401 KERNEL_IMAGE_SIZE/PMD_SIZE)
403 NEXT_PAGE(level2_spare_pgt)
411 .globl early_gdt_descr
413 .word GDT_ENTRIES*8-1
414 early_gdt_descr_base:
415 .quad INIT_PER_CPU_VAR(gdt_page)
418 /* This must match the first entry in level2_kernel_pgt */
419 .quad 0x0000000000000000
421 #include "../../x86/xen/xen-head.S"
423 .section .bss, "aw", @nobits
424 .align L1_CACHE_BYTES
426 .skip IDT_ENTRIES * 16
430 ENTRY(empty_zero_page)