arch/x86/kernel/cpu/perf_event_intel.c

   1 #ifdef CONFIG_CPU_SUP_INTEL
   2
   3 /*
   4  * Intel PerfMon, used on Core and later.
   5  */
   6 static const u64 intel_perfmon_event_map[] =
   7 {
   8   [PERF_COUNT_HW_CPU_CYCLES]            = 0x003c,
   9   [PERF_COUNT_HW_INSTRUCTIONS]          = 0x00c0,
  10   [PERF_COUNT_HW_CACHE_REFERENCES]      = 0x4f2e,
  11   [PERF_COUNT_HW_CACHE_MISSES]          = 0x412e,
  12   [PERF_COUNT_HW_BRANCH_INSTRUCTIONS]   = 0x00c4,
  13   [PERF_COUNT_HW_BRANCH_MISSES]         = 0x00c5,
  14   [PERF_COUNT_HW_BUS_CYCLES]            = 0x013c,
  15 };
  16
  17 static struct event_constraint intel_core_event_constraints[] =
  18 {
  19         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  20         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  21         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  22         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  23         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  24         INTEL_EVENT_CONSTRAINT(0xc1, 0x1), /* FP_COMP_INSTR_RET */
  25         EVENT_CONSTRAINT_END
  26 };
  27
  28 static struct event_constraint intel_core2_event_constraints[] =
  29 {
  30         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  31         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  32         /*
  33          * Core2 has Fixed Counter 2 listed as CPU_CLK_UNHALTED.REF and event
  34          * 0x013c as CPU_CLK_UNHALTED.BUS and specifies there is a fixed
  35          * ratio between these counters.
  36          */
  37         /* FIXED_EVENT_CONSTRAINT(0x013c, 2),  CPU_CLK_UNHALTED.REF */
  38         INTEL_EVENT_CONSTRAINT(0x10, 0x1), /* FP_COMP_OPS_EXE */
  39         INTEL_EVENT_CONSTRAINT(0x11, 0x2), /* FP_ASSIST */
  40         INTEL_EVENT_CONSTRAINT(0x12, 0x2), /* MUL */
  41         INTEL_EVENT_CONSTRAINT(0x13, 0x2), /* DIV */
  42         INTEL_EVENT_CONSTRAINT(0x14, 0x1), /* CYCLES_DIV_BUSY */
  43         INTEL_EVENT_CONSTRAINT(0x18, 0x1), /* IDLE_DURING_DIV */
  44         INTEL_EVENT_CONSTRAINT(0x19, 0x2), /* DELAYED_BYPASS */
  45         INTEL_EVENT_CONSTRAINT(0xa1, 0x1), /* RS_UOPS_DISPATCH_CYCLES */
  46         INTEL_EVENT_CONSTRAINT(0xc9, 0x1), /* ITLB_MISS_RETIRED (T30-9) */
  47         INTEL_EVENT_CONSTRAINT(0xcb, 0x1), /* MEM_LOAD_RETIRED */
  48         EVENT_CONSTRAINT_END
  49 };
  50
  51 static struct event_constraint intel_nehalem_event_constraints[] =
  52 {
  53         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  54         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  55         /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
  56         INTEL_EVENT_CONSTRAINT(0x40, 0x3), /* L1D_CACHE_LD */
  57         INTEL_EVENT_CONSTRAINT(0x41, 0x3), /* L1D_CACHE_ST */
  58         INTEL_EVENT_CONSTRAINT(0x42, 0x3), /* L1D_CACHE_LOCK */
  59         INTEL_EVENT_CONSTRAINT(0x43, 0x3), /* L1D_ALL_REF */
  60         INTEL_EVENT_CONSTRAINT(0x48, 0x3), /* L1D_PEND_MISS */
  61         INTEL_EVENT_CONSTRAINT(0x4e, 0x3), /* L1D_PREFETCH */
  62         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  63         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  64         EVENT_CONSTRAINT_END
  65 };
  66
  67 static struct event_constraint intel_westmere_event_constraints[] =
  68 {
  69         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  70         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  71         /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
  72         INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
  73         INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
  74         INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
  75         INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
  76         EVENT_CONSTRAINT_END
  77 };
  78
  79 static struct event_constraint intel_gen_event_constraints[] =
  80 {
  81         FIXED_EVENT_CONSTRAINT(0x00c0, 0), /* INST_RETIRED.ANY */
  82         FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
  83         /* FIXED_EVENT_CONSTRAINT(0x013c, 2), CPU_CLK_UNHALTED.REF */
  84         EVENT_CONSTRAINT_END
  85 };
  86
  87 static u64 intel_pmu_event_map(int hw_event)
  88 {
  89         return intel_perfmon_event_map[hw_event];
  90 }
  91
  92 static __initconst const u64 westmere_hw_cache_event_ids
  93                                 [PERF_COUNT_HW_CACHE_MAX]
  94                                 [PERF_COUNT_HW_CACHE_OP_MAX]
  95                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
  96 {
  97  [ C(L1D) ] = {
  98         [ C(OP_READ) ] = {
  99                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 100                 [ C(RESULT_MISS)   ] = 0x0151, /* L1D.REPL                     */
 101         },
 102         [ C(OP_WRITE) ] = {
 103                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 104                 [ C(RESULT_MISS)   ] = 0x0251, /* L1D.M_REPL                   */
 105         },
 106         [ C(OP_PREFETCH) ] = {
 107                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 108                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 109         },
 110  },
 111  [ C(L1I ) ] = {
 112         [ C(OP_READ) ] = {
 113                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 114                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 115         },
 116         [ C(OP_WRITE) ] = {
 117                 [ C(RESULT_ACCESS) ] = -1,
 118                 [ C(RESULT_MISS)   ] = -1,
 119         },
 120         [ C(OP_PREFETCH) ] = {
 121                 [ C(RESULT_ACCESS) ] = 0x0,
 122                 [ C(RESULT_MISS)   ] = 0x0,
 123         },
 124  },
 125  [ C(LL  ) ] = {
 126         [ C(OP_READ) ] = {
 127                 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS               */
 128                 [ C(RESULT_MISS)   ] = 0x0224, /* L2_RQSTS.LD_MISS             */
 129         },
 130         [ C(OP_WRITE) ] = {
 131                 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS                */
 132                 [ C(RESULT_MISS)   ] = 0x0824, /* L2_RQSTS.RFO_MISS            */
 133         },
 134         [ C(OP_PREFETCH) ] = {
 135                 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference                */
 136                 [ C(RESULT_MISS)   ] = 0x412e, /* LLC Misses                   */
 137         },
 138  },
 139  [ C(DTLB) ] = {
 140         [ C(OP_READ) ] = {
 141                 [ C(RESULT_ACCESS) ] = 0x010b, /* MEM_INST_RETIRED.LOADS       */
 142                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 143         },
 144         [ C(OP_WRITE) ] = {
 145                 [ C(RESULT_ACCESS) ] = 0x020b, /* MEM_INST_RETURED.STORES      */
 146                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 147         },
 148         [ C(OP_PREFETCH) ] = {
 149                 [ C(RESULT_ACCESS) ] = 0x0,
 150                 [ C(RESULT_MISS)   ] = 0x0,
 151         },
 152  },
 153  [ C(ITLB) ] = {
 154         [ C(OP_READ) ] = {
 155                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 156                 [ C(RESULT_MISS)   ] = 0x0185, /* ITLB_MISSES.ANY              */
 157         },
 158         [ C(OP_WRITE) ] = {
 159                 [ C(RESULT_ACCESS) ] = -1,
 160                 [ C(RESULT_MISS)   ] = -1,
 161         },
 162         [ C(OP_PREFETCH) ] = {
 163                 [ C(RESULT_ACCESS) ] = -1,
 164                 [ C(RESULT_MISS)   ] = -1,
 165         },
 166  },
 167  [ C(BPU ) ] = {
 168         [ C(OP_READ) ] = {
 169                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 170                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 171         },
 172         [ C(OP_WRITE) ] = {
 173                 [ C(RESULT_ACCESS) ] = -1,
 174                 [ C(RESULT_MISS)   ] = -1,
 175         },
 176         [ C(OP_PREFETCH) ] = {
 177                 [ C(RESULT_ACCESS) ] = -1,
 178                 [ C(RESULT_MISS)   ] = -1,
 179         },
 180  },
 181 };
 182
 183 static __initconst const u64 nehalem_hw_cache_event_ids
 184                                 [PERF_COUNT_HW_CACHE_MAX]
 185                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 186                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 187 {
 188  [ C(L1D) ] = {
 189         [ C(OP_READ) ] = {
 190                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI            */
 191                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE         */
 192         },
 193         [ C(OP_WRITE) ] = {
 194                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI            */
 195                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE         */
 196         },
 197         [ C(OP_PREFETCH) ] = {
 198                 [ C(RESULT_ACCESS) ] = 0x014e, /* L1D_PREFETCH.REQUESTS        */
 199                 [ C(RESULT_MISS)   ] = 0x024e, /* L1D_PREFETCH.MISS            */
 200         },
 201  },
 202  [ C(L1I ) ] = {
 203         [ C(OP_READ) ] = {
 204                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                    */
 205                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                   */
 206         },
 207         [ C(OP_WRITE) ] = {
 208                 [ C(RESULT_ACCESS) ] = -1,
 209                 [ C(RESULT_MISS)   ] = -1,
 210         },
 211         [ C(OP_PREFETCH) ] = {
 212                 [ C(RESULT_ACCESS) ] = 0x0,
 213                 [ C(RESULT_MISS)   ] = 0x0,
 214         },
 215  },
 216  [ C(LL  ) ] = {
 217         [ C(OP_READ) ] = {
 218                 [ C(RESULT_ACCESS) ] = 0x0324, /* L2_RQSTS.LOADS               */
 219                 [ C(RESULT_MISS)   ] = 0x0224, /* L2_RQSTS.LD_MISS             */
 220         },
 221         [ C(OP_WRITE) ] = {
 222                 [ C(RESULT_ACCESS) ] = 0x0c24, /* L2_RQSTS.RFOS                */
 223                 [ C(RESULT_MISS)   ] = 0x0824, /* L2_RQSTS.RFO_MISS            */
 224         },
 225         [ C(OP_PREFETCH) ] = {
 226                 [ C(RESULT_ACCESS) ] = 0x4f2e, /* LLC Reference                */
 227                 [ C(RESULT_MISS)   ] = 0x412e, /* LLC Misses                   */
 228         },
 229  },
 230  [ C(DTLB) ] = {
 231         [ C(OP_READ) ] = {
 232                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI   (alias)  */
 233                 [ C(RESULT_MISS)   ] = 0x0108, /* DTLB_LOAD_MISSES.ANY         */
 234         },
 235         [ C(OP_WRITE) ] = {
 236                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI   (alias)  */
 237                 [ C(RESULT_MISS)   ] = 0x010c, /* MEM_STORE_RETIRED.DTLB_MISS  */
 238         },
 239         [ C(OP_PREFETCH) ] = {
 240                 [ C(RESULT_ACCESS) ] = 0x0,
 241                 [ C(RESULT_MISS)   ] = 0x0,
 242         },
 243  },
 244  [ C(ITLB) ] = {
 245         [ C(OP_READ) ] = {
 246                 [ C(RESULT_ACCESS) ] = 0x01c0, /* INST_RETIRED.ANY_P           */
 247                 [ C(RESULT_MISS)   ] = 0x20c8, /* ITLB_MISS_RETIRED            */
 248         },
 249         [ C(OP_WRITE) ] = {
 250                 [ C(RESULT_ACCESS) ] = -1,
 251                 [ C(RESULT_MISS)   ] = -1,
 252         },
 253         [ C(OP_PREFETCH) ] = {
 254                 [ C(RESULT_ACCESS) ] = -1,
 255                 [ C(RESULT_MISS)   ] = -1,
 256         },
 257  },
 258  [ C(BPU ) ] = {
 259         [ C(OP_READ) ] = {
 260                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ALL_BRANCHES */
 261                 [ C(RESULT_MISS)   ] = 0x03e8, /* BPU_CLEARS.ANY               */
 262         },
 263         [ C(OP_WRITE) ] = {
 264                 [ C(RESULT_ACCESS) ] = -1,
 265                 [ C(RESULT_MISS)   ] = -1,
 266         },
 267         [ C(OP_PREFETCH) ] = {
 268                 [ C(RESULT_ACCESS) ] = -1,
 269                 [ C(RESULT_MISS)   ] = -1,
 270         },
 271  },
 272 };
 273
 274 static __initconst const u64 core2_hw_cache_event_ids
 275                                 [PERF_COUNT_HW_CACHE_MAX]
 276                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 277                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 278 {
 279  [ C(L1D) ] = {
 280         [ C(OP_READ) ] = {
 281                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI          */
 282                 [ C(RESULT_MISS)   ] = 0x0140, /* L1D_CACHE_LD.I_STATE       */
 283         },
 284         [ C(OP_WRITE) ] = {
 285                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI          */
 286                 [ C(RESULT_MISS)   ] = 0x0141, /* L1D_CACHE_ST.I_STATE       */
 287         },
 288         [ C(OP_PREFETCH) ] = {
 289                 [ C(RESULT_ACCESS) ] = 0x104e, /* L1D_PREFETCH.REQUESTS      */
 290                 [ C(RESULT_MISS)   ] = 0,
 291         },
 292  },
 293  [ C(L1I ) ] = {
 294         [ C(OP_READ) ] = {
 295                 [ C(RESULT_ACCESS) ] = 0x0080, /* L1I.READS                  */
 296                 [ C(RESULT_MISS)   ] = 0x0081, /* L1I.MISSES                 */
 297         },
 298         [ C(OP_WRITE) ] = {
 299                 [ C(RESULT_ACCESS) ] = -1,
 300                 [ C(RESULT_MISS)   ] = -1,
 301         },
 302         [ C(OP_PREFETCH) ] = {
 303                 [ C(RESULT_ACCESS) ] = 0,
 304                 [ C(RESULT_MISS)   ] = 0,
 305         },
 306  },
 307  [ C(LL  ) ] = {
 308         [ C(OP_READ) ] = {
 309                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
 310                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
 311         },
 312         [ C(OP_WRITE) ] = {
 313                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
 314                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
 315         },
 316         [ C(OP_PREFETCH) ] = {
 317                 [ C(RESULT_ACCESS) ] = 0,
 318                 [ C(RESULT_MISS)   ] = 0,
 319         },
 320  },
 321  [ C(DTLB) ] = {
 322         [ C(OP_READ) ] = {
 323                 [ C(RESULT_ACCESS) ] = 0x0f40, /* L1D_CACHE_LD.MESI  (alias) */
 324                 [ C(RESULT_MISS)   ] = 0x0208, /* DTLB_MISSES.MISS_LD        */
 325         },
 326         [ C(OP_WRITE) ] = {
 327                 [ C(RESULT_ACCESS) ] = 0x0f41, /* L1D_CACHE_ST.MESI  (alias) */
 328                 [ C(RESULT_MISS)   ] = 0x0808, /* DTLB_MISSES.MISS_ST        */
 329         },
 330         [ C(OP_PREFETCH) ] = {
 331                 [ C(RESULT_ACCESS) ] = 0,
 332                 [ C(RESULT_MISS)   ] = 0,
 333         },
 334  },
 335  [ C(ITLB) ] = {
 336         [ C(OP_READ) ] = {
 337                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
 338                 [ C(RESULT_MISS)   ] = 0x1282, /* ITLBMISSES                 */
 339         },
 340         [ C(OP_WRITE) ] = {
 341                 [ C(RESULT_ACCESS) ] = -1,
 342                 [ C(RESULT_MISS)   ] = -1,
 343         },
 344         [ C(OP_PREFETCH) ] = {
 345                 [ C(RESULT_ACCESS) ] = -1,
 346                 [ C(RESULT_MISS)   ] = -1,
 347         },
 348  },
 349  [ C(BPU ) ] = {
 350         [ C(OP_READ) ] = {
 351                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
 352                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
 353         },
 354         [ C(OP_WRITE) ] = {
 355                 [ C(RESULT_ACCESS) ] = -1,
 356                 [ C(RESULT_MISS)   ] = -1,
 357         },
 358         [ C(OP_PREFETCH) ] = {
 359                 [ C(RESULT_ACCESS) ] = -1,
 360                 [ C(RESULT_MISS)   ] = -1,
 361         },
 362  },
 363 };
 364
 365 static __initconst const u64 atom_hw_cache_event_ids
 366                                 [PERF_COUNT_HW_CACHE_MAX]
 367                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 368                                 [PERF_COUNT_HW_CACHE_RESULT_MAX] =
 369 {
 370  [ C(L1D) ] = {
 371         [ C(OP_READ) ] = {
 372                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE.LD               */
 373                 [ C(RESULT_MISS)   ] = 0,
 374         },
 375         [ C(OP_WRITE) ] = {
 376                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE.ST               */
 377                 [ C(RESULT_MISS)   ] = 0,
 378         },
 379         [ C(OP_PREFETCH) ] = {
 380                 [ C(RESULT_ACCESS) ] = 0x0,
 381                 [ C(RESULT_MISS)   ] = 0,
 382         },
 383  },
 384  [ C(L1I ) ] = {
 385         [ C(OP_READ) ] = {
 386                 [ C(RESULT_ACCESS) ] = 0x0380, /* L1I.READS                  */
 387                 [ C(RESULT_MISS)   ] = 0x0280, /* L1I.MISSES                 */
 388         },
 389         [ C(OP_WRITE) ] = {
 390                 [ C(RESULT_ACCESS) ] = -1,
 391                 [ C(RESULT_MISS)   ] = -1,
 392         },
 393         [ C(OP_PREFETCH) ] = {
 394                 [ C(RESULT_ACCESS) ] = 0,
 395                 [ C(RESULT_MISS)   ] = 0,
 396         },
 397  },
 398  [ C(LL  ) ] = {
 399         [ C(OP_READ) ] = {
 400                 [ C(RESULT_ACCESS) ] = 0x4f29, /* L2_LD.MESI                 */
 401                 [ C(RESULT_MISS)   ] = 0x4129, /* L2_LD.ISTATE               */
 402         },
 403         [ C(OP_WRITE) ] = {
 404                 [ C(RESULT_ACCESS) ] = 0x4f2A, /* L2_ST.MESI                 */
 405                 [ C(RESULT_MISS)   ] = 0x412A, /* L2_ST.ISTATE               */
 406         },
 407         [ C(OP_PREFETCH) ] = {
 408                 [ C(RESULT_ACCESS) ] = 0,
 409                 [ C(RESULT_MISS)   ] = 0,
 410         },
 411  },
 412  [ C(DTLB) ] = {
 413         [ C(OP_READ) ] = {
 414                 [ C(RESULT_ACCESS) ] = 0x2140, /* L1D_CACHE_LD.MESI  (alias) */
 415                 [ C(RESULT_MISS)   ] = 0x0508, /* DTLB_MISSES.MISS_LD        */
 416         },
 417         [ C(OP_WRITE) ] = {
 418                 [ C(RESULT_ACCESS) ] = 0x2240, /* L1D_CACHE_ST.MESI  (alias) */
 419                 [ C(RESULT_MISS)   ] = 0x0608, /* DTLB_MISSES.MISS_ST        */
 420         },
 421         [ C(OP_PREFETCH) ] = {
 422                 [ C(RESULT_ACCESS) ] = 0,
 423                 [ C(RESULT_MISS)   ] = 0,
 424         },
 425  },
 426  [ C(ITLB) ] = {
 427         [ C(OP_READ) ] = {
 428                 [ C(RESULT_ACCESS) ] = 0x00c0, /* INST_RETIRED.ANY_P         */
 429                 [ C(RESULT_MISS)   ] = 0x0282, /* ITLB.MISSES                */
 430         },
 431         [ C(OP_WRITE) ] = {
 432                 [ C(RESULT_ACCESS) ] = -1,
 433                 [ C(RESULT_MISS)   ] = -1,
 434         },
 435         [ C(OP_PREFETCH) ] = {
 436                 [ C(RESULT_ACCESS) ] = -1,
 437                 [ C(RESULT_MISS)   ] = -1,
 438         },
 439  },
 440  [ C(BPU ) ] = {
 441         [ C(OP_READ) ] = {
 442                 [ C(RESULT_ACCESS) ] = 0x00c4, /* BR_INST_RETIRED.ANY        */
 443                 [ C(RESULT_MISS)   ] = 0x00c5, /* BP_INST_RETIRED.MISPRED    */
 444         },
 445         [ C(OP_WRITE) ] = {
 446                 [ C(RESULT_ACCESS) ] = -1,
 447                 [ C(RESULT_MISS)   ] = -1,
 448         },
 449         [ C(OP_PREFETCH) ] = {
 450                 [ C(RESULT_ACCESS) ] = -1,
 451                 [ C(RESULT_MISS)   ] = -1,
 452         },
 453  },
 454 };
 455
 456 static void intel_pmu_disable_all(void)
 457 {
 458         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 459
 460         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0);
 461
 462         if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask))
 463                 intel_pmu_disable_bts();
 464
 465         intel_pmu_pebs_disable_all();
 466         intel_pmu_lbr_disable_all();
 467 }
 468
 469 static void intel_pmu_enable_all(int added)
 470 {
 471         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 472
 473         intel_pmu_pebs_enable_all();
 474         intel_pmu_lbr_enable_all();
 475         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, x86_pmu.intel_ctrl);
 476
 477         if (test_bit(X86_PMC_IDX_FIXED_BTS, cpuc->active_mask)) {
 478                 struct perf_event *event =
 479                         cpuc->events[X86_PMC_IDX_FIXED_BTS];
 480
 481                 if (WARN_ON_ONCE(!event))
 482                         return;
 483
 484                 intel_pmu_enable_bts(event->hw.config);
 485         }
 486 }
 487
 488 /*
 489  * Workaround for:
 490  *   Intel Errata AAK100 (model 26)
 491  *   Intel Errata AAP53  (model 30)
 492  *   Intel Errata BD53   (model 44)
 493  *
 494  * The official story:
 495  *   These chips need to be 'reset' when adding counters by programming the
 496  *   magic three (non-counting) events 0x4300B5, 0x4300D2, and 0x4300B1 either
 497  *   in sequence on the same PMC or on different PMCs.
 498  *
 499  * In practise it appears some of these events do in fact count, and
 500  * we need to programm all 4 events.
 501  */
 502 static void intel_pmu_nhm_workaround(void)
 503 {
 504         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 505         static const unsigned long nhm_magic[4] = {
 506                 0x4300B5,
 507                 0x4300D2,
 508                 0x4300B1,
 509                 0x4300B1
 510         };
 511         struct perf_event *event;
 512         int i;
 513
 514         /*
 515          * The Errata requires below steps:
 516          * 1) Clear MSR_IA32_PEBS_ENABLE and MSR_CORE_PERF_GLOBAL_CTRL;
 517          * 2) Configure 4 PERFEVTSELx with the magic events and clear
 518          *    the corresponding PMCx;
 519          * 3) set bit0~bit3 of MSR_CORE_PERF_GLOBAL_CTRL;
 520          * 4) Clear MSR_CORE_PERF_GLOBAL_CTRL;
 521          * 5) Clear 4 pairs of ERFEVTSELx and PMCx;
 522          */
 523
 524         /*
 525          * The real steps we choose are a little different from above.
 526          * A) To reduce MSR operations, we don't run step 1) as they
 527          *    are already cleared before this function is called;
 528          * B) Call x86_perf_event_update to save PMCx before configuring
 529          *    PERFEVTSELx with magic number;
 530          * C) With step 5), we do clear only when the PERFEVTSELx is
 531          *    not used currently.
 532          * D) Call x86_perf_event_set_period to restore PMCx;
 533          */
 534
 535         /* We always operate 4 pairs of PERF Counters */
 536         for (i = 0; i < 4; i++) {
 537                 event = cpuc->events[i];
 538                 if (event)
 539                         x86_perf_event_update(event);
 540         }
 541
 542         for (i = 0; i < 4; i++) {
 543                 wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, nhm_magic[i]);
 544                 wrmsrl(MSR_ARCH_PERFMON_PERFCTR0 + i, 0x0);
 545         }
 546
 547         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0xf);
 548         wrmsrl(MSR_CORE_PERF_GLOBAL_CTRL, 0x0);
 549
 550         for (i = 0; i < 4; i++) {
 551                 event = cpuc->events[i];
 552
 553                 if (event) {
 554                         x86_perf_event_set_period(event);
 555                         __x86_pmu_enable_event(&event->hw,
 556                                         ARCH_PERFMON_EVENTSEL_ENABLE);
 557                 } else
 558                         wrmsrl(MSR_ARCH_PERFMON_EVENTSEL0 + i, 0x0);
 559         }
 560 }
 561
 562 static void intel_pmu_nhm_enable_all(int added)
 563 {
 564         if (added)
 565                 intel_pmu_nhm_workaround();
 566         intel_pmu_enable_all(added);
 567 }
 568
 569 static inline u64 intel_pmu_get_status(void)
 570 {
 571         u64 status;
 572
 573         rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS, status);
 574
 575         return status;
 576 }
 577
 578 static inline void intel_pmu_ack_status(u64 ack)
 579 {
 580         wrmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL, ack);
 581 }
 582
 583 static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
 584 {
 585         int idx = hwc->idx - X86_PMC_IDX_FIXED;
 586         u64 ctrl_val, mask;
 587
 588         mask = 0xfULL << (idx * 4);
 589
 590         rdmsrl(hwc->config_base, ctrl_val);
 591         ctrl_val &= ~mask;
 592         wrmsrl(hwc->config_base, ctrl_val);
 593 }
 594
 595 static void intel_pmu_disable_event(struct perf_event *event)
 596 {
 597         struct hw_perf_event *hwc = &event->hw;
 598
 599         if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
 600                 intel_pmu_disable_bts();
 601                 intel_pmu_drain_bts_buffer();
 602                 return;
 603         }
 604
 605         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
 606                 intel_pmu_disable_fixed(hwc);
 607                 return;
 608         }
 609
 610         x86_pmu_disable_event(event);
 611
 612         if (unlikely(event->attr.precise_ip))
 613                 intel_pmu_pebs_disable(event);
 614 }
 615
 616 static void intel_pmu_enable_fixed(struct hw_perf_event *hwc)
 617 {
 618         int idx = hwc->idx - X86_PMC_IDX_FIXED;
 619         u64 ctrl_val, bits, mask;
 620
 621         /*
 622          * Enable IRQ generation (0x8),
 623          * and enable ring-3 counting (0x2) and ring-0 counting (0x1)
 624          * if requested:
 625          */
 626         bits = 0x8ULL;
 627         if (hwc->config & ARCH_PERFMON_EVENTSEL_USR)
 628                 bits |= 0x2;
 629         if (hwc->config & ARCH_PERFMON_EVENTSEL_OS)
 630                 bits |= 0x1;
 631
 632         /*
 633          * ANY bit is supported in v3 and up
 634          */
 635         if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY)
 636                 bits |= 0x4;
 637
 638         bits <<= (idx * 4);
 639         mask = 0xfULL << (idx * 4);
 640
 641         rdmsrl(hwc->config_base, ctrl_val);
 642         ctrl_val &= ~mask;
 643         ctrl_val |= bits;
 644         wrmsrl(hwc->config_base, ctrl_val);
 645 }
 646
 647 static void intel_pmu_enable_event(struct perf_event *event)
 648 {
 649         struct hw_perf_event *hwc = &event->hw;
 650
 651         if (unlikely(hwc->idx == X86_PMC_IDX_FIXED_BTS)) {
 652                 if (!__this_cpu_read(cpu_hw_events.enabled))
 653                         return;
 654
 655                 intel_pmu_enable_bts(hwc->config);
 656                 return;
 657         }
 658
 659         if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL)) {
 660                 intel_pmu_enable_fixed(hwc);
 661                 return;
 662         }
 663
 664         if (unlikely(event->attr.precise_ip))
 665                 intel_pmu_pebs_enable(event);
 666
 667         __x86_pmu_enable_event(hwc, ARCH_PERFMON_EVENTSEL_ENABLE);
 668 }
 669
 670 /*
 671  * Save and restart an expired event. Called by NMI contexts,
 672  * so it has to be careful about preempting normal event ops:
 673  */
 674 static int intel_pmu_save_and_restart(struct perf_event *event)
 675 {
 676         x86_perf_event_update(event);
 677         return x86_perf_event_set_period(event);
 678 }
 679
 680 static void intel_pmu_reset(void)
 681 {
 682         struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
 683         unsigned long flags;
 684         int idx;
 685
 686         if (!x86_pmu.num_counters)
 687                 return;
 688
 689         local_irq_save(flags);
 690
 691         printk("clearing PMU state on CPU#%d\n", smp_processor_id());
 692
 693         for (idx = 0; idx < x86_pmu.num_counters; idx++) {
 694                 checking_wrmsrl(x86_pmu.eventsel + idx, 0ull);
 695                 checking_wrmsrl(x86_pmu.perfctr  + idx, 0ull);
 696         }
 697         for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++)
 698                 checking_wrmsrl(MSR_ARCH_PERFMON_FIXED_CTR0 + idx, 0ull);
 699
 700         if (ds)
 701                 ds->bts_index = ds->bts_buffer_base;
 702
 703         local_irq_restore(flags);
 704 }
 705
 706 /*
 707  * This handler is triggered by the local APIC, so the APIC IRQ handling
 708  * rules apply:
 709  */
 710 static int intel_pmu_handle_irq(struct pt_regs *regs)
 711 {
 712         struct perf_sample_data data;
 713         struct cpu_hw_events *cpuc;
 714         int bit, loops;
 715         u64 status;
 716         int handled;
 717
 718         perf_sample_data_init(&data, 0);
 719
 720         cpuc = &__get_cpu_var(cpu_hw_events);
 721
 722         intel_pmu_disable_all();
 723         handled = intel_pmu_drain_bts_buffer();
 724         status = intel_pmu_get_status();
 725         if (!status) {
 726                 intel_pmu_enable_all(0);
 727                 return handled;
 728         }
 729
 730         loops = 0;
 731 again:
 732         intel_pmu_ack_status(status);
 733         if (++loops > 100) {
 734                 WARN_ONCE(1, "perfevents: irq loop stuck!\n");
 735                 perf_event_print_debug();
 736                 intel_pmu_reset();
 737                 goto done;
 738         }
 739
 740         inc_irq_stat(apic_perf_irqs);
 741
 742         intel_pmu_lbr_read();
 743
 744         /*
 745          * PEBS overflow sets bit 62 in the global status register
 746          */
 747         if (__test_and_clear_bit(62, (unsigned long *)&status)) {
 748                 handled++;
 749                 x86_pmu.drain_pebs(regs);
 750         }
 751
 752         for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
 753                 struct perf_event *event = cpuc->events[bit];
 754
 755                 handled++;
 756
 757                 if (!test_bit(bit, cpuc->active_mask))
 758                         continue;
 759
 760                 if (!intel_pmu_save_and_restart(event))
 761                         continue;
 762
 763                 data.period = event->hw.last_period;
 764
 765                 if (perf_event_overflow(event, 1, &data, regs))
 766                         x86_pmu_stop(event, 0);
 767         }
 768
 769         /*
 770          * Repeat if there is more work to be done:
 771          */
 772         status = intel_pmu_get_status();
 773         if (status)
 774                 goto again;
 775
 776 done:
 777         intel_pmu_enable_all(0);
 778         return handled;
 779 }
 780
 781 static struct event_constraint *
 782 intel_bts_constraints(struct perf_event *event)
 783 {
 784         struct hw_perf_event *hwc = &event->hw;
 785         unsigned int hw_event, bts_event;
 786
 787         hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
 788         bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
 789
 790         if (unlikely(hw_event == bts_event && hwc->sample_period == 1))
 791                 return &bts_constraint;
 792
 793         return NULL;
 794 }
 795
 796 static struct event_constraint *
 797 intel_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event)
 798 {
 799         struct event_constraint *c;
 800
 801         c = intel_bts_constraints(event);
 802         if (c)
 803                 return c;
 804
 805         c = intel_pebs_constraints(event);
 806         if (c)
 807                 return c;
 808
 809         return x86_get_event_constraints(cpuc, event);
 810 }
 811
 812 static int intel_pmu_hw_config(struct perf_event *event)
 813 {
 814         int ret = x86_pmu_hw_config(event);
 815
 816         if (ret)
 817                 return ret;
 818
 819         if (event->attr.precise_ip &&
 820             (event->hw.config & X86_RAW_EVENT_MASK) == 0x003c) {
 821                 /*
 822                  * Use an alternative encoding for CPU_CLK_UNHALTED.THREAD_P
 823                  * (0x003c) so that we can use it with PEBS.
 824                  *
 825                  * The regular CPU_CLK_UNHALTED.THREAD_P event (0x003c) isn't
 826                  * PEBS capable. However we can use INST_RETIRED.ANY_P
 827                  * (0x00c0), which is a PEBS capable event, to get the same
 828                  * count.
 829                  *
 830                  * INST_RETIRED.ANY_P counts the number of cycles that retires
 831                  * CNTMASK instructions. By setting CNTMASK to a value (16)
 832                  * larger than the maximum number of instructions that can be
 833                  * retired per cycle (4) and then inverting the condition, we
 834                  * count all cycles that retire 16 or less instructions, which
 835                  * is every cycle.
 836                  *
 837                  * Thereby we gain a PEBS capable cycle counter.
 838                  */
 839                 u64 alt_config = 0x108000c0; /* INST_RETIRED.TOTAL_CYCLES */
 840
 841                 alt_config |= (event->hw.config & ~X86_RAW_EVENT_MASK);
 842                 event->hw.config = alt_config;
 843         }
 844
 845         if (event->attr.type != PERF_TYPE_RAW)
 846                 return 0;
 847
 848         if (!(event->attr.config & ARCH_PERFMON_EVENTSEL_ANY))
 849                 return 0;
 850
 851         if (x86_pmu.version < 3)
 852                 return -EINVAL;
 853
 854         if (perf_paranoid_cpu() && !capable(CAP_SYS_ADMIN))
 855                 return -EACCES;
 856
 857         event->hw.config |= ARCH_PERFMON_EVENTSEL_ANY;
 858
 859         return 0;
 860 }
 861
 862 static __initconst const struct x86_pmu core_pmu = {
 863         .name                   = "core",
 864         .handle_irq             = x86_pmu_handle_irq,
 865         .disable_all            = x86_pmu_disable_all,
 866         .enable_all             = x86_pmu_enable_all,
 867         .enable                 = x86_pmu_enable_event,
 868         .disable                = x86_pmu_disable_event,
 869         .hw_config              = x86_pmu_hw_config,
 870         .schedule_events        = x86_schedule_events,
 871         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
 872         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
 873         .event_map              = intel_pmu_event_map,
 874         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
 875         .apic                   = 1,
 876         /*
 877          * Intel PMCs cannot be accessed sanely above 32 bit width,
 878          * so we install an artificial 1<<31 period regardless of
 879          * the generic event period:
 880          */
 881         .max_period             = (1ULL << 31) - 1,
 882         .get_event_constraints  = intel_get_event_constraints,
 883         .event_constraints      = intel_core_event_constraints,
 884 };
 885
 886 static void intel_pmu_cpu_starting(int cpu)
 887 {
 888         init_debug_store_on_cpu(cpu);
 889         /*
 890          * Deal with CPUs that don't clear their LBRs on power-up.
 891          */
 892         intel_pmu_lbr_reset();
 893 }
 894
 895 static void intel_pmu_cpu_dying(int cpu)
 896 {
 897         fini_debug_store_on_cpu(cpu);
 898 }
 899
 900 static __initconst const struct x86_pmu intel_pmu = {
 901         .name                   = "Intel",
 902         .handle_irq             = intel_pmu_handle_irq,
 903         .disable_all            = intel_pmu_disable_all,
 904         .enable_all             = intel_pmu_enable_all,
 905         .enable                 = intel_pmu_enable_event,
 906         .disable                = intel_pmu_disable_event,
 907         .hw_config              = intel_pmu_hw_config,
 908         .schedule_events        = x86_schedule_events,
 909         .eventsel               = MSR_ARCH_PERFMON_EVENTSEL0,
 910         .perfctr                = MSR_ARCH_PERFMON_PERFCTR0,
 911         .event_map              = intel_pmu_event_map,
 912         .max_events             = ARRAY_SIZE(intel_perfmon_event_map),
 913         .apic                   = 1,
 914         /*
 915          * Intel PMCs cannot be accessed sanely above 32 bit width,
 916          * so we install an artificial 1<<31 period regardless of
 917          * the generic event period:
 918          */
 919         .max_period             = (1ULL << 31) - 1,
 920         .get_event_constraints  = intel_get_event_constraints,
 921
 922         .cpu_starting           = intel_pmu_cpu_starting,
 923         .cpu_dying              = intel_pmu_cpu_dying,
 924 };
 925
 926 static void intel_clovertown_quirks(void)
 927 {
 928         /*
 929          * PEBS is unreliable due to:
 930          *
 931          *   AJ67  - PEBS may experience CPL leaks
 932          *   AJ68  - PEBS PMI may be delayed by one event
 933          *   AJ69  - GLOBAL_STATUS[62] will only be set when DEBUGCTL[12]
 934          *   AJ106 - FREEZE_LBRS_ON_PMI doesn't work in combination with PEBS
 935          *
 936          * AJ67 could be worked around by restricting the OS/USR flags.
 937          * AJ69 could be worked around by setting PMU_FREEZE_ON_PMI.
 938          *
 939          * AJ106 could possibly be worked around by not allowing LBR
 940          *       usage from PEBS, including the fixup.
 941          * AJ68  could possibly be worked around by always programming
 942          *       a pebs_event_reset[0] value and coping with the lost events.
 943          *
 944          * But taken together it might just make sense to not enable PEBS on
 945          * these chips.
 946          */
 947         printk(KERN_WARNING "PEBS disabled due to CPU errata.\n");
 948         x86_pmu.pebs = 0;
 949         x86_pmu.pebs_constraints = NULL;
 950 }
 951
 952 static __init int intel_pmu_init(void)
 953 {
 954         union cpuid10_edx edx;
 955         union cpuid10_eax eax;
 956         unsigned int unused;
 957         unsigned int ebx;
 958         int version;
 959
 960         if (!cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON)) {
 961                 switch (boot_cpu_data.x86) {
 962                 case 0x6:
 963                         return p6_pmu_init();
 964                 case 0xf:
 965                         return p4_pmu_init();
 966                 }
 967                 return -ENODEV;
 968         }
 969
 970         /*
 971          * Check whether the Architectural PerfMon supports
 972          * Branch Misses Retired hw_event or not.
 973          */
 974         cpuid(10, &eax.full, &ebx, &unused, &edx.full);
 975         if (eax.split.mask_length <= ARCH_PERFMON_BRANCH_MISSES_RETIRED)
 976                 return -ENODEV;
 977
 978         version = eax.split.version_id;
 979         if (version < 2)
 980                 x86_pmu = core_pmu;
 981         else
 982                 x86_pmu = intel_pmu;
 983
 984         x86_pmu.version                 = version;
 985         x86_pmu.num_counters            = eax.split.num_counters;
 986         x86_pmu.cntval_bits             = eax.split.bit_width;
 987         x86_pmu.cntval_mask             = (1ULL << eax.split.bit_width) - 1;
 988
 989         /*
 990          * Quirk: v2 perfmon does not report fixed-purpose events, so
 991          * assume at least 3 events:
 992          */
 993         if (version > 1)
 994                 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3);
 995
 996         /*
 997          * v2 and above have a perf capabilities MSR
 998          */
 999         if (version > 1) {
1000                 u64 capabilities;
1001
1002                 rdmsrl(MSR_IA32_PERF_CAPABILITIES, capabilities);
1003                 x86_pmu.intel_cap.capabilities = capabilities;
1004         }
1005
1006         intel_ds_init();
1007
1008         /*
1009          * Install the hw-cache-events table:
1010          */
1011         switch (boot_cpu_data.x86_model) {
1012         case 14: /* 65 nm core solo/duo, "Yonah" */
1013                 pr_cont("Core events, ");
1014                 break;
1015
1016         case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
1017                 x86_pmu.quirks = intel_clovertown_quirks;
1018         case 22: /* single-core 65 nm celeron/core2solo "Merom-L"/"Conroe-L" */
1019         case 23: /* current 45 nm celeron/core2/xeon "Penryn"/"Wolfdale" */
1020         case 29: /* six-core 45 nm xeon "Dunnington" */
1021                 memcpy(hw_cache_event_ids, core2_hw_cache_event_ids,
1022                        sizeof(hw_cache_event_ids));
1023
1024                 intel_pmu_lbr_init_core();
1025
1026                 x86_pmu.event_constraints = intel_core2_event_constraints;
1027                 pr_cont("Core2 events, ");
1028                 break;
1029
1030         case 26: /* 45 nm nehalem, "Bloomfield" */
1031         case 30: /* 45 nm nehalem, "Lynnfield" */
1032         case 46: /* 45 nm nehalem-ex, "Beckton" */
1033                 memcpy(hw_cache_event_ids, nehalem_hw_cache_event_ids,
1034                        sizeof(hw_cache_event_ids));
1035
1036                 intel_pmu_lbr_init_nhm();
1037
1038                 x86_pmu.event_constraints = intel_nehalem_event_constraints;
1039                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
1040                 pr_cont("Nehalem events, ");
1041                 break;
1042
1043         case 28: /* Atom */
1044                 memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
1045                        sizeof(hw_cache_event_ids));
1046
1047                 intel_pmu_lbr_init_atom();
1048
1049                 x86_pmu.event_constraints = intel_gen_event_constraints;
1050                 pr_cont("Atom events, ");
1051                 break;
1052
1053         case 37: /* 32 nm nehalem, "Clarkdale" */
1054         case 44: /* 32 nm nehalem, "Gulftown" */
1055                 memcpy(hw_cache_event_ids, westmere_hw_cache_event_ids,
1056                        sizeof(hw_cache_event_ids));
1057
1058                 intel_pmu_lbr_init_nhm();
1059
1060                 x86_pmu.event_constraints = intel_westmere_event_constraints;
1061                 x86_pmu.enable_all = intel_pmu_nhm_enable_all;
1062                 pr_cont("Westmere events, ");
1063                 break;
1064
1065         default:
1066                 /*
1067                  * default constraints for v2 and up
1068                  */
1069                 x86_pmu.event_constraints = intel_gen_event_constraints;
1070                 pr_cont("generic architected perfmon, ");
1071         }
1072         return 0;
1073 }
1074
1075 #else /* CONFIG_CPU_SUP_INTEL */
1076
1077 static int intel_pmu_init(void)
1078 {
1079         return 0;
1080 }
1081
1082 #endif /* CONFIG_CPU_SUP_INTEL */