2 * Performance events - AMD IBS
4 * Copyright (C) 2011 Advanced Micro Devices, Inc., Robert Richter
6 * For licencing details see kernel-base/COPYING
9 #include <linux/perf_event.h>
10 #include <linux/module.h>
11 #include <linux/pci.h>
17 #if defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD)
19 static struct pmu perf_ibs;
21 static int perf_ibs_init(struct perf_event *event)
23 if (perf_ibs.type != event->attr.type)
28 static int perf_ibs_add(struct perf_event *event, int flags)
33 static void perf_ibs_del(struct perf_event *event, int flags)
37 static struct pmu perf_ibs = {
38 .event_init= perf_ibs_init,
43 static __init int perf_event_ibs_init(void)
46 return -ENODEV; /* ibs not supported by the cpu */
48 perf_pmu_register(&perf_ibs, "ibs", -1);
49 printk(KERN_INFO "perf: AMD IBS detected (0x%08x)\n", ibs_caps);
54 #else /* defined(CONFIG_PERF_EVENTS) && defined(CONFIG_CPU_SUP_AMD) */
56 static __init int perf_event_ibs_init(void) { return 0; }
60 /* IBS - apic initialization, for perf and oprofile */
62 static __init u32 __get_ibs_caps(void)
65 unsigned int max_level;
67 if (!boot_cpu_has(X86_FEATURE_IBS))
70 /* check IBS cpuid feature flags */
71 max_level = cpuid_eax(0x80000000);
72 if (max_level < IBS_CPUID_FEATURES)
73 return IBS_CAPS_DEFAULT;
75 caps = cpuid_eax(IBS_CPUID_FEATURES);
76 if (!(caps & IBS_CAPS_AVAIL))
77 /* cpuid flags not valid */
78 return IBS_CAPS_DEFAULT;
83 u32 get_ibs_caps(void)
88 EXPORT_SYMBOL(get_ibs_caps);
90 static inline int get_eilvt(int offset)
92 return !setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 1);
95 static inline int put_eilvt(int offset)
97 return !setup_APIC_eilvt(offset, 0, 0, 1);
101 * Check and reserve APIC extended interrupt LVT offset for IBS if available.
103 static inline int ibs_eilvt_valid(void)
111 rdmsrl(MSR_AMD64_IBSCTL, val);
112 offset = val & IBSCTL_LVT_OFFSET_MASK;
114 if (!(val & IBSCTL_LVT_OFFSET_VALID)) {
115 pr_err(FW_BUG "cpu %d, invalid IBS interrupt offset %d (MSR%08X=0x%016llx)\n",
116 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
120 if (!get_eilvt(offset)) {
121 pr_err(FW_BUG "cpu %d, IBS interrupt offset %d not available (MSR%08X=0x%016llx)\n",
122 smp_processor_id(), offset, MSR_AMD64_IBSCTL, val);
133 static int setup_ibs_ctl(int ibs_eilvt_off)
135 struct pci_dev *cpu_cfg;
142 cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD,
143 PCI_DEVICE_ID_AMD_10H_NB_MISC,
148 pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off
149 | IBSCTL_LVT_OFFSET_VALID);
150 pci_read_config_dword(cpu_cfg, IBSCTL, &value);
151 if (value != (ibs_eilvt_off | IBSCTL_LVT_OFFSET_VALID)) {
152 pci_dev_put(cpu_cfg);
153 printk(KERN_DEBUG "Failed to setup IBS LVT offset, "
154 "IBSCTL = 0x%08x\n", value);
160 printk(KERN_DEBUG "No CPU node configured for IBS\n");
168 * This runs only on the current cpu. We try to find an LVT offset and
169 * setup the local APIC. For this we must disable preemption. On
170 * success we initialize all nodes with this offset. This updates then
171 * the offset in the IBS_CTL per-node msr. The per-core APIC setup of
172 * the IBS interrupt vector is handled by perf_ibs_cpu_notifier that
173 * is using the new offset.
175 static int force_ibs_eilvt_setup(void)
181 /* find the next free available EILVT entry, skip offset 0 */
182 for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
183 if (get_eilvt(offset))
188 if (offset == APIC_EILVT_NR_MAX) {
189 printk(KERN_DEBUG "No EILVT entry available\n");
193 ret = setup_ibs_ctl(offset);
197 if (!ibs_eilvt_valid()) {
202 pr_err(FW_BUG "using offset %d for IBS interrupts\n", offset);
203 pr_err(FW_BUG "workaround enabled for IBS LVT offset\n");
213 static inline int get_ibs_lvt_offset(void)
217 rdmsrl(MSR_AMD64_IBSCTL, val);
218 if (!(val & IBSCTL_LVT_OFFSET_VALID))
221 return val & IBSCTL_LVT_OFFSET_MASK;
224 static void setup_APIC_ibs(void *dummy)
228 offset = get_ibs_lvt_offset();
232 if (!setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_NMI, 0))
235 pr_warn("perf: IBS APIC setup failed on cpu #%d\n",
239 static void clear_APIC_ibs(void *dummy)
243 offset = get_ibs_lvt_offset();
245 setup_APIC_eilvt(offset, 0, APIC_EILVT_MSG_FIX, 1);
249 perf_ibs_cpu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
251 switch (action & ~CPU_TASKS_FROZEN) {
253 setup_APIC_ibs(NULL);
256 clear_APIC_ibs(NULL);
265 static __init int amd_ibs_init(void)
270 caps = __get_ibs_caps();
272 return -ENODEV; /* ibs not supported by the cpu */
274 if (!ibs_eilvt_valid()) {
275 ret = force_ibs_eilvt_setup();
277 pr_err("Failed to setup IBS, %d\n", ret);
284 /* make ibs_caps visible to other cpus: */
286 perf_cpu_notifier(perf_ibs_cpu_notifier);
287 smp_call_function(setup_APIC_ibs, NULL, 1);
290 return perf_event_ibs_init();
293 /* Since we need the pci subsystem to init ibs we can't do this earlier: */
294 device_initcall(amd_ibs_init);