2 * Performance events x86 architecture header
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
19 * register -------------------------------
20 * | HT | no HT | HT | no HT |
21 *-----------------------------------------
22 * offcore | core | core | cpu | core |
23 * lbr_sel | core | core | cpu | core |
24 * ld_lat | cpu | core | cpu | core |
25 *-----------------------------------------
27 * Given that there is a small number of shared regs,
28 * we can pre-allocate their slot in the per-cpu
29 * per-core reg tables.
32 EXTRA_REG_NONE = -1, /* not used */
34 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
35 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
37 EXTRA_REG_MAX /* number of entries needed */
40 struct event_constraint {
42 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
51 int nb_id; /* NorthBridge id */
52 int refcnt; /* reference count */
53 struct perf_event *owners[X86_PMC_IDX_MAX];
54 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
57 /* The maximal number of PEBS events: */
58 #define MAX_PEBS_EVENTS 4
61 * A debug store configuration.
63 * We only support architectures that use 64bit fields.
68 u64 bts_absolute_maximum;
69 u64 bts_interrupt_threshold;
72 u64 pebs_absolute_maximum;
73 u64 pebs_interrupt_threshold;
74 u64 pebs_event_reset[MAX_PEBS_EVENTS];
81 raw_spinlock_t lock; /* per-core: protect structure */
82 u64 config; /* extra MSR config */
83 u64 reg; /* extra MSR number */
84 atomic_t ref; /* reference count */
90 * Used to coordinate shared registers between HT threads or
91 * among events on a single PMU.
93 struct intel_shared_regs {
94 struct er_account regs[EXTRA_REG_MAX];
95 int refcnt; /* per-core: #HT threads */
96 unsigned core_id; /* per-core: core id */
99 #define MAX_LBR_ENTRIES 16
101 struct cpu_hw_events {
103 * Generic x86 PMC bits
105 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
106 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
107 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
113 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
114 u64 tags[X86_PMC_IDX_MAX];
115 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
117 unsigned int group_flag;
120 * Intel DebugStore bits
122 struct debug_store *ds;
130 struct perf_branch_stack lbr_stack;
131 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
134 * Intel host/guest exclude bits
136 u64 intel_ctrl_guest_mask;
137 u64 intel_ctrl_host_mask;
138 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
141 * manage shared (per-core, per-cpu) registers
142 * used on Intel NHM/WSM/SNB
144 struct intel_shared_regs *shared_regs;
149 struct amd_nb *amd_nb;
150 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
151 u64 perf_ctr_virt_mask;
153 void *kfree_on_online;
156 #define __EVENT_CONSTRAINT(c, n, m, w) {\
157 { .idxmsk64 = (n) }, \
163 #define EVENT_CONSTRAINT(c, n, m) \
164 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
167 * Constraint on the Event code.
169 #define INTEL_EVENT_CONSTRAINT(c, n) \
170 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
173 * Constraint on the Event code + UMask + fixed-mask
175 * filter mask to validate fixed counter events.
176 * the following filters disqualify for fixed counters:
180 * The other filters are supported by fixed counters.
181 * The any-thread option is supported starting with v3.
183 #define FIXED_EVENT_CONSTRAINT(c, n) \
184 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
187 * Constraint on the Event code + UMask
189 #define INTEL_UEVENT_CONSTRAINT(c, n) \
190 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
192 #define EVENT_CONSTRAINT_END \
193 EVENT_CONSTRAINT(0, 0, 0)
195 #define for_each_event_constraint(e, c) \
196 for ((e) = (c); (e)->weight; (e)++)
199 * Extra registers for specific events.
201 * Some events need large masks and require external MSRs.
202 * Those extra MSRs end up being shared for all events on
203 * a PMU and sometimes between PMU of sibling HT threads.
204 * In either case, the kernel needs to handle conflicting
205 * accesses to those extra, shared, regs. The data structure
206 * to manage those registers is stored in cpu_hw_event.
213 int idx; /* per_xxx->regs[] reg index */
216 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
219 .config_mask = (m), \
220 .valid_mask = (vm), \
221 .idx = EXTRA_REG_##i \
224 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
225 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
227 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
229 union perf_capabilities {
241 * struct x86_pmu - generic x86 pmu
245 * Generic x86 PMC bits
249 int (*handle_irq)(struct pt_regs *);
250 void (*disable_all)(void);
251 void (*enable_all)(int added);
252 void (*enable)(struct perf_event *);
253 void (*disable)(struct perf_event *);
254 int (*hw_config)(struct perf_event *event);
255 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
258 u64 (*event_map)(int);
261 int num_counters_fixed;
266 struct event_constraint *
267 (*get_event_constraints)(struct cpu_hw_events *cpuc,
268 struct perf_event *event);
270 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
271 struct perf_event *event);
272 struct event_constraint *event_constraints;
273 void (*quirks)(void);
274 int perfctr_second_write;
276 int (*cpu_prepare)(int cpu);
277 void (*cpu_starting)(int cpu);
278 void (*cpu_dying)(int cpu);
279 void (*cpu_dead)(int cpu);
282 * Intel Arch Perfmon v2+
285 union perf_capabilities intel_cap;
288 * Intel DebugStore bits
291 int bts_active, pebs_active;
292 int pebs_record_size;
293 void (*drain_pebs)(struct pt_regs *regs);
294 struct event_constraint *pebs_constraints;
299 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
300 int lbr_nr; /* hardware stack size */
303 * Extra registers for events
305 struct extra_reg *extra_regs;
306 unsigned int er_flags;
309 * Intel host/guest support (KVM)
311 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
314 #define ERF_NO_HT_SHARING 1
315 #define ERF_HAS_RSP_1 2
317 extern struct x86_pmu x86_pmu __read_mostly;
319 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
321 int x86_perf_event_set_period(struct perf_event *event);
324 * Generalized hw caching related hw_event table, filled
325 * in on a per model basis. A value of 0 means
326 * 'not supported', -1 means 'hw_event makes no sense on
327 * this CPU', any other value means the raw hw_event
331 #define C(x) PERF_COUNT_HW_CACHE_##x
333 extern u64 __read_mostly hw_cache_event_ids
334 [PERF_COUNT_HW_CACHE_MAX]
335 [PERF_COUNT_HW_CACHE_OP_MAX]
336 [PERF_COUNT_HW_CACHE_RESULT_MAX];
337 extern u64 __read_mostly hw_cache_extra_regs
338 [PERF_COUNT_HW_CACHE_MAX]
339 [PERF_COUNT_HW_CACHE_OP_MAX]
340 [PERF_COUNT_HW_CACHE_RESULT_MAX];
342 u64 x86_perf_event_update(struct perf_event *event);
344 static inline int x86_pmu_addr_offset(int index)
348 /* offset = X86_FEATURE_PERFCTR_CORE ? index << 1 : index */
349 alternative_io(ASM_NOP2,
351 X86_FEATURE_PERFCTR_CORE,
358 static inline unsigned int x86_pmu_config_addr(int index)
360 return x86_pmu.eventsel + x86_pmu_addr_offset(index);
363 static inline unsigned int x86_pmu_event_addr(int index)
365 return x86_pmu.perfctr + x86_pmu_addr_offset(index);
368 int x86_setup_perfctr(struct perf_event *event);
370 int x86_pmu_hw_config(struct perf_event *event);
372 void x86_pmu_disable_all(void);
374 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
377 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
379 if (hwc->extra_reg.reg)
380 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
381 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
384 void x86_pmu_enable_all(int added);
386 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
388 void x86_pmu_stop(struct perf_event *event, int flags);
390 static inline void x86_pmu_disable_event(struct perf_event *event)
392 struct hw_perf_event *hwc = &event->hw;
394 wrmsrl(hwc->config_base, hwc->config);
397 void x86_pmu_enable_event(struct perf_event *event);
399 int x86_pmu_handle_irq(struct pt_regs *regs);
401 extern struct event_constraint emptyconstraint;
403 extern struct event_constraint unconstrained;
405 #ifdef CONFIG_CPU_SUP_AMD
407 int amd_pmu_init(void);
409 #else /* CONFIG_CPU_SUP_AMD */
411 static inline int amd_pmu_init(void)
416 #endif /* CONFIG_CPU_SUP_AMD */
418 #ifdef CONFIG_CPU_SUP_INTEL
420 int intel_pmu_save_and_restart(struct perf_event *event);
422 struct event_constraint *
423 x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event);
425 struct intel_shared_regs *allocate_shared_regs(int cpu);
427 int intel_pmu_init(void);
429 void init_debug_store_on_cpu(int cpu);
431 void fini_debug_store_on_cpu(int cpu);
433 void release_ds_buffers(void);
435 void reserve_ds_buffers(void);
437 extern struct event_constraint bts_constraint;
439 void intel_pmu_enable_bts(u64 config);
441 void intel_pmu_disable_bts(void);
443 int intel_pmu_drain_bts_buffer(void);
445 extern struct event_constraint intel_core2_pebs_event_constraints[];
447 extern struct event_constraint intel_atom_pebs_event_constraints[];
449 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
451 extern struct event_constraint intel_westmere_pebs_event_constraints[];
453 extern struct event_constraint intel_snb_pebs_event_constraints[];
455 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
457 void intel_pmu_pebs_enable(struct perf_event *event);
459 void intel_pmu_pebs_disable(struct perf_event *event);
461 void intel_pmu_pebs_enable_all(void);
463 void intel_pmu_pebs_disable_all(void);
465 void intel_ds_init(void);
467 void intel_pmu_lbr_reset(void);
469 void intel_pmu_lbr_enable(struct perf_event *event);
471 void intel_pmu_lbr_disable(struct perf_event *event);
473 void intel_pmu_lbr_enable_all(void);
475 void intel_pmu_lbr_disable_all(void);
477 void intel_pmu_lbr_read(void);
479 void intel_pmu_lbr_init_core(void);
481 void intel_pmu_lbr_init_nhm(void);
483 void intel_pmu_lbr_init_atom(void);
485 int p4_pmu_init(void);
487 int p6_pmu_init(void);
489 #else /* CONFIG_CPU_SUP_INTEL */
491 static inline void reserve_ds_buffers(void)
495 static inline void release_ds_buffers(void)
499 static inline int intel_pmu_init(void)
504 static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
509 #endif /* CONFIG_CPU_SUP_INTEL */