2 * (c) 2005, 2006 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
7 * Written by Jacob Shin - AMD, Inc.
9 * Support : jacob.shin@amd.com
12 * - added support for AMD Family 0x10 processors
14 * All MC4_MISCi registers are shared between multi-cores
16 #include <linux/interrupt.h>
17 #include <linux/notifier.h>
18 #include <linux/kobject.h>
19 #include <linux/percpu.h>
20 #include <linux/sysdev.h>
21 #include <linux/errno.h>
22 #include <linux/sched.h>
23 #include <linux/sysfs.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/cpu.h>
27 #include <linux/smp.h>
36 #define THRESHOLD_MAX 0xFFF
37 #define INT_TYPE_APIC 0x00020000
38 #define MASK_VALID_HI 0x80000000
39 #define MASK_CNTP_HI 0x40000000
40 #define MASK_LOCKED_HI 0x20000000
41 #define MASK_LVTOFF_HI 0x00F00000
42 #define MASK_COUNT_EN_HI 0x00080000
43 #define MASK_INT_TYPE_HI 0x00060000
44 #define MASK_OVERFLOW_HI 0x00010000
45 #define MASK_ERR_COUNT_HI 0x00000FFF
46 #define MASK_BLKPTR_LO 0xFF000000
47 #define MCG_XBLK_ADDR 0xC0000400
49 struct threshold_block {
55 bool interrupt_capable;
58 struct list_head miscj;
61 struct threshold_bank {
63 struct threshold_block *blocks;
66 static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);
68 static unsigned char shared_bank[NR_BANKS] = {
72 static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
74 static void amd_threshold_interrupt(void);
80 struct thresh_restart {
81 struct threshold_block *b;
88 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
91 * bank 4 supports APIC LVT interrupts implicitly since forever.
97 * IntP: interrupt present; if this bit is set, the thresholding
98 * bank can generate APIC LVT interrupts
100 return msr_high_bits & BIT(28);
103 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
105 int msr = (hi & MASK_LVTOFF_HI) >> 20;
108 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
109 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
110 b->bank, b->block, b->address, hi, lo);
115 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
116 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
117 b->cpu, apic, b->bank, b->block, b->address, hi, lo);
125 * Called via smp_call_function_single(), must be called with correct
128 static void threshold_restart_bank(void *_tr)
130 struct thresh_restart *tr = _tr;
133 rdmsr(tr->b->address, lo, hi);
135 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
136 tr->reset = 1; /* limit cannot be lower than err count */
138 if (tr->reset) { /* reset err count and overflow bit */
140 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
141 (THRESHOLD_MAX - tr->b->threshold_limit);
142 } else if (tr->old_limit) { /* change limit w/o reset */
143 int new_count = (hi & THRESHOLD_MAX) +
144 (tr->old_limit - tr->b->threshold_limit);
146 hi = (hi & ~MASK_ERR_COUNT_HI) |
147 (new_count & THRESHOLD_MAX);
151 hi &= ~MASK_INT_TYPE_HI;
153 if (!tr->b->interrupt_capable)
156 if (tr->set_lvt_off) {
157 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
158 /* set new lvt offset */
159 hi &= ~MASK_LVTOFF_HI;
160 hi |= tr->lvt_off << 20;
164 if (tr->b->interrupt_enable)
169 hi |= MASK_COUNT_EN_HI;
170 wrmsr(tr->b->address, lo, hi);
173 static void mce_threshold_block_init(struct threshold_block *b, int offset)
175 struct thresh_restart tr = {
181 b->threshold_limit = THRESHOLD_MAX;
182 threshold_restart_bank(&tr);
185 static int setup_APIC_mce(int reserved, int new)
187 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
188 APIC_EILVT_MSG_FIX, 0))
194 /* cpu init entry point, called from mce.c with preempt off */
195 void mce_amd_feature_init(struct cpuinfo_x86 *c)
197 struct threshold_block b;
198 unsigned int cpu = smp_processor_id();
199 u32 low = 0, high = 0, address = 0;
200 unsigned int bank, block;
203 for (bank = 0; bank < NR_BANKS; ++bank) {
204 for (block = 0; block < NR_BLOCKS; ++block) {
206 address = MSR_IA32_MC0_MISC + bank * 4;
207 else if (block == 1) {
208 address = (low & MASK_BLKPTR_LO) >> 21;
212 address += MCG_XBLK_ADDR;
216 if (rdmsr_safe(address, &low, &high))
219 if (!(high & MASK_VALID_HI))
222 if (!(high & MASK_CNTP_HI) ||
223 (high & MASK_LOCKED_HI))
227 per_cpu(bank_map, cpu) |= (1 << bank);
229 if (shared_bank[bank] && c->cpu_core_id)
232 memset(&b, 0, sizeof(b));
237 b.interrupt_capable = lvt_interrupt_supported(bank, high);
239 if (b.interrupt_capable) {
240 int new = (high & MASK_LVTOFF_HI) >> 20;
241 offset = setup_APIC_mce(offset, new);
244 mce_threshold_block_init(&b, offset);
245 mce_threshold_vector = amd_threshold_interrupt;
251 * APIC Interrupt Handler
255 * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
256 * the interrupt goes off when error_count reaches threshold_limit.
257 * the handler will simply log mcelog w/ software defined bank number.
259 static void amd_threshold_interrupt(void)
261 u32 low = 0, high = 0, address = 0;
262 unsigned int bank, block;
267 /* assume first bank caused it */
268 for (bank = 0; bank < NR_BANKS; ++bank) {
269 if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
271 for (block = 0; block < NR_BLOCKS; ++block) {
273 address = MSR_IA32_MC0_MISC + bank * 4;
274 } else if (block == 1) {
275 address = (low & MASK_BLKPTR_LO) >> 21;
278 address += MCG_XBLK_ADDR;
283 if (rdmsr_safe(address, &low, &high))
286 if (!(high & MASK_VALID_HI)) {
293 if (!(high & MASK_CNTP_HI) ||
294 (high & MASK_LOCKED_HI))
298 * Log the machine check that caused the threshold
301 machine_check_poll(MCP_TIMESTAMP,
302 &__get_cpu_var(mce_poll_banks));
304 if (high & MASK_OVERFLOW_HI) {
305 rdmsrl(address, m.misc);
306 rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
308 m.bank = K8_MCE_THRESHOLD_BASE
322 struct threshold_attr {
323 struct attribute attr;
324 ssize_t (*show) (struct threshold_block *, char *);
325 ssize_t (*store) (struct threshold_block *, const char *, size_t count);
328 #define SHOW_FIELDS(name) \
329 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
331 return sprintf(buf, "%lx\n", (unsigned long) b->name); \
333 SHOW_FIELDS(interrupt_enable)
334 SHOW_FIELDS(threshold_limit)
337 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
339 struct thresh_restart tr;
342 if (!b->interrupt_capable)
345 if (strict_strtoul(buf, 0, &new) < 0)
348 b->interrupt_enable = !!new;
350 memset(&tr, 0, sizeof(tr));
353 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
359 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
361 struct thresh_restart tr;
364 if (strict_strtoul(buf, 0, &new) < 0)
367 if (new > THRESHOLD_MAX)
372 memset(&tr, 0, sizeof(tr));
373 tr.old_limit = b->threshold_limit;
374 b->threshold_limit = new;
377 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
382 struct threshold_block_cross_cpu {
383 struct threshold_block *tb;
387 static void local_error_count_handler(void *_tbcc)
389 struct threshold_block_cross_cpu *tbcc = _tbcc;
390 struct threshold_block *b = tbcc->tb;
393 rdmsr(b->address, low, high);
394 tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);
397 static ssize_t show_error_count(struct threshold_block *b, char *buf)
399 struct threshold_block_cross_cpu tbcc = { .tb = b, };
401 smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1);
402 return sprintf(buf, "%lx\n", tbcc.retval);
405 static ssize_t store_error_count(struct threshold_block *b,
406 const char *buf, size_t count)
408 struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };
410 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
414 #define RW_ATTR(val) \
415 static struct threshold_attr val = { \
416 .attr = {.name = __stringify(val), .mode = 0644 }, \
417 .show = show_## val, \
418 .store = store_## val, \
421 RW_ATTR(interrupt_enable);
422 RW_ATTR(threshold_limit);
423 RW_ATTR(error_count);
425 static struct attribute *default_attrs[] = {
426 &interrupt_enable.attr,
427 &threshold_limit.attr,
432 #define to_block(k) container_of(k, struct threshold_block, kobj)
433 #define to_attr(a) container_of(a, struct threshold_attr, attr)
435 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
437 struct threshold_block *b = to_block(kobj);
438 struct threshold_attr *a = to_attr(attr);
441 ret = a->show ? a->show(b, buf) : -EIO;
446 static ssize_t store(struct kobject *kobj, struct attribute *attr,
447 const char *buf, size_t count)
449 struct threshold_block *b = to_block(kobj);
450 struct threshold_attr *a = to_attr(attr);
453 ret = a->store ? a->store(b, buf, count) : -EIO;
458 static const struct sysfs_ops threshold_ops = {
463 static struct kobj_type threshold_ktype = {
464 .sysfs_ops = &threshold_ops,
465 .default_attrs = default_attrs,
468 static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
473 struct threshold_block *b = NULL;
477 if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
480 if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
483 if (!(high & MASK_VALID_HI)) {
490 if (!(high & MASK_CNTP_HI) ||
491 (high & MASK_LOCKED_HI))
494 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
501 b->address = address;
502 b->interrupt_enable = 0;
503 b->interrupt_capable = lvt_interrupt_supported(bank, high);
504 b->threshold_limit = THRESHOLD_MAX;
506 INIT_LIST_HEAD(&b->miscj);
508 if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
510 &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
512 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
515 err = kobject_init_and_add(&b->kobj, &threshold_ktype,
516 per_cpu(threshold_banks, cpu)[bank]->kobj,
522 address = (low & MASK_BLKPTR_LO) >> 21;
525 address += MCG_XBLK_ADDR;
530 err = allocate_threshold_blocks(cpu, bank, ++block, address);
535 kobject_uevent(&b->kobj, KOBJ_ADD);
541 kobject_put(&b->kobj);
548 static __cpuinit long
549 local_allocate_threshold_blocks(int cpu, unsigned int bank)
551 return allocate_threshold_blocks(cpu, bank, 0,
552 MSR_IA32_MC0_MISC + bank * 4);
555 /* symlinks sibling shared banks to first core. first core owns dir/files. */
556 static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
559 struct threshold_bank *b = NULL;
562 sprintf(name, "threshold_bank%i", bank);
565 if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */
566 i = cpumask_first(cpu_llc_shared_mask(cpu));
568 /* first core not up yet */
569 if (cpu_data(i).cpu_core_id)
573 if (per_cpu(threshold_banks, cpu)[bank])
576 b = per_cpu(threshold_banks, i)[bank];
581 err = sysfs_create_link(&per_cpu(mce_sysdev, cpu).kobj,
586 cpumask_copy(b->cpus, cpu_llc_shared_mask(cpu));
587 per_cpu(threshold_banks, cpu)[bank] = b;
593 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
598 if (!zalloc_cpumask_var(&b->cpus, GFP_KERNEL)) {
604 b->kobj = kobject_create_and_add(name, &per_cpu(mce_sysdev, cpu).kobj);
609 cpumask_setall(b->cpus);
611 cpumask_set_cpu(cpu, b->cpus);
614 per_cpu(threshold_banks, cpu)[bank] = b;
616 err = local_allocate_threshold_blocks(cpu, bank);
620 for_each_cpu(i, b->cpus) {
624 err = sysfs_create_link(&per_cpu(mce_sysdev, i).kobj,
629 per_cpu(threshold_banks, i)[bank] = b;
635 per_cpu(threshold_banks, cpu)[bank] = NULL;
636 free_cpumask_var(b->cpus);
642 /* create dir/files for all valid threshold banks */
643 static __cpuinit int threshold_create_device(unsigned int cpu)
648 for (bank = 0; bank < NR_BANKS; ++bank) {
649 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
651 err = threshold_create_bank(cpu, bank);
660 * let's be hotplug friendly.
661 * in case of multiple core processors, the first core always takes ownership
662 * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
665 static void deallocate_threshold_block(unsigned int cpu,
668 struct threshold_block *pos = NULL;
669 struct threshold_block *tmp = NULL;
670 struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
675 list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
676 kobject_put(&pos->kobj);
677 list_del(&pos->miscj);
681 kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
682 per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
685 static void threshold_remove_bank(unsigned int cpu, int bank)
687 struct threshold_bank *b;
691 b = per_cpu(threshold_banks, cpu)[bank];
697 sprintf(name, "threshold_bank%i", bank);
700 /* sibling symlink */
701 if (shared_bank[bank] && b->blocks->cpu != cpu) {
702 sysfs_remove_link(&per_cpu(mce_sysdev, cpu).kobj, name);
703 per_cpu(threshold_banks, cpu)[bank] = NULL;
709 /* remove all sibling symlinks before unregistering */
710 for_each_cpu(i, b->cpus) {
714 sysfs_remove_link(&per_cpu(mce_sysdev, i).kobj, name);
715 per_cpu(threshold_banks, i)[bank] = NULL;
718 deallocate_threshold_block(cpu, bank);
721 kobject_del(b->kobj);
722 kobject_put(b->kobj);
723 free_cpumask_var(b->cpus);
725 per_cpu(threshold_banks, cpu)[bank] = NULL;
728 static void threshold_remove_device(unsigned int cpu)
732 for (bank = 0; bank < NR_BANKS; ++bank) {
733 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
735 threshold_remove_bank(cpu, bank);
739 /* get notified when a cpu comes on/off */
740 static void __cpuinit
741 amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)
745 case CPU_ONLINE_FROZEN:
746 threshold_create_device(cpu);
749 case CPU_DEAD_FROZEN:
750 threshold_remove_device(cpu);
757 static __init int threshold_init_device(void)
761 /* to hit CPUs online before the notifier is up */
762 for_each_online_cpu(lcpu) {
763 int err = threshold_create_device(lcpu);
768 threshold_cpu_callback = amd_64_threshold_cpu_callback;
772 device_initcall(threshold_init_device);