2 * (c) 2005, 2006 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
7 * Written by Jacob Shin - AMD, Inc.
9 * Support : jacob.shin@amd.com
12 * - added support for AMD Family 0x10 processors
14 * All MC4_MISCi registers are shared between multi-cores
16 #include <linux/interrupt.h>
17 #include <linux/notifier.h>
18 #include <linux/kobject.h>
19 #include <linux/percpu.h>
20 #include <linux/sysdev.h>
21 #include <linux/errno.h>
22 #include <linux/sched.h>
23 #include <linux/sysfs.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/cpu.h>
27 #include <linux/smp.h>
36 #define THRESHOLD_MAX 0xFFF
37 #define INT_TYPE_APIC 0x00020000
38 #define MASK_VALID_HI 0x80000000
39 #define MASK_CNTP_HI 0x40000000
40 #define MASK_LOCKED_HI 0x20000000
41 #define MASK_LVTOFF_HI 0x00F00000
42 #define MASK_COUNT_EN_HI 0x00080000
43 #define MASK_INT_TYPE_HI 0x00060000
44 #define MASK_OVERFLOW_HI 0x00010000
45 #define MASK_ERR_COUNT_HI 0x00000FFF
46 #define MASK_BLKPTR_LO 0xFF000000
47 #define MCG_XBLK_ADDR 0xC0000400
49 struct threshold_block {
55 bool interrupt_capable;
58 struct list_head miscj;
61 struct threshold_bank {
63 struct threshold_block *blocks;
66 static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);
69 static unsigned char shared_bank[NR_BANKS] = {
74 static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
76 static void amd_threshold_interrupt(void);
82 struct thresh_restart {
83 struct threshold_block *b;
90 static bool lvt_interrupt_supported(unsigned int bank, u32 msr_high_bits)
93 * bank 4 supports APIC LVT interrupts implicitly since forever.
99 * IntP: interrupt present; if this bit is set, the thresholding
100 * bank can generate APIC LVT interrupts
102 return msr_high_bits & BIT(28);
105 static int lvt_off_valid(struct threshold_block *b, int apic, u32 lo, u32 hi)
107 int msr = (hi & MASK_LVTOFF_HI) >> 20;
110 pr_err(FW_BUG "cpu %d, failed to setup threshold interrupt "
111 "for bank %d, block %d (MSR%08X=0x%x%08x)\n", b->cpu,
112 b->bank, b->block, b->address, hi, lo);
117 pr_err(FW_BUG "cpu %d, invalid threshold interrupt offset %d "
118 "for bank %d, block %d (MSR%08X=0x%x%08x)\n",
119 b->cpu, apic, b->bank, b->block, b->address, hi, lo);
127 * Called via smp_call_function_single(), must be called with correct
130 static void threshold_restart_bank(void *_tr)
132 struct thresh_restart *tr = _tr;
135 rdmsr(tr->b->address, lo, hi);
137 if (tr->b->threshold_limit < (hi & THRESHOLD_MAX))
138 tr->reset = 1; /* limit cannot be lower than err count */
140 if (tr->reset) { /* reset err count and overflow bit */
142 (hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
143 (THRESHOLD_MAX - tr->b->threshold_limit);
144 } else if (tr->old_limit) { /* change limit w/o reset */
145 int new_count = (hi & THRESHOLD_MAX) +
146 (tr->old_limit - tr->b->threshold_limit);
148 hi = (hi & ~MASK_ERR_COUNT_HI) |
149 (new_count & THRESHOLD_MAX);
153 hi &= ~MASK_INT_TYPE_HI;
155 if (!tr->b->interrupt_capable)
158 if (tr->set_lvt_off) {
159 if (lvt_off_valid(tr->b, tr->lvt_off, lo, hi)) {
160 /* set new lvt offset */
161 hi &= ~MASK_LVTOFF_HI;
162 hi |= tr->lvt_off << 20;
166 if (tr->b->interrupt_enable)
171 hi |= MASK_COUNT_EN_HI;
172 wrmsr(tr->b->address, lo, hi);
175 static void mce_threshold_block_init(struct threshold_block *b, int offset)
177 struct thresh_restart tr = {
183 b->threshold_limit = THRESHOLD_MAX;
184 threshold_restart_bank(&tr);
187 static int setup_APIC_mce(int reserved, int new)
189 if (reserved < 0 && !setup_APIC_eilvt(new, THRESHOLD_APIC_VECTOR,
190 APIC_EILVT_MSG_FIX, 0))
196 /* cpu init entry point, called from mce.c with preempt off */
197 void mce_amd_feature_init(struct cpuinfo_x86 *c)
199 struct threshold_block b;
200 unsigned int cpu = smp_processor_id();
201 u32 low = 0, high = 0, address = 0;
202 unsigned int bank, block;
205 for (bank = 0; bank < NR_BANKS; ++bank) {
206 for (block = 0; block < NR_BLOCKS; ++block) {
208 address = MSR_IA32_MC0_MISC + bank * 4;
209 else if (block == 1) {
210 address = (low & MASK_BLKPTR_LO) >> 21;
214 address += MCG_XBLK_ADDR;
218 if (rdmsr_safe(address, &low, &high))
221 if (!(high & MASK_VALID_HI))
224 if (!(high & MASK_CNTP_HI) ||
225 (high & MASK_LOCKED_HI))
229 per_cpu(bank_map, cpu) |= (1 << bank);
231 if (shared_bank[bank] && c->cpu_core_id)
235 memset(&b, 0, sizeof(b));
240 b.interrupt_capable = lvt_interrupt_supported(bank, high);
242 if (b.interrupt_capable) {
243 int new = (high & MASK_LVTOFF_HI) >> 20;
244 offset = setup_APIC_mce(offset, new);
247 mce_threshold_block_init(&b, offset);
248 mce_threshold_vector = amd_threshold_interrupt;
254 * APIC Interrupt Handler
258 * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
259 * the interrupt goes off when error_count reaches threshold_limit.
260 * the handler will simply log mcelog w/ software defined bank number.
262 static void amd_threshold_interrupt(void)
264 u32 low = 0, high = 0, address = 0;
265 unsigned int bank, block;
270 /* assume first bank caused it */
271 for (bank = 0; bank < NR_BANKS; ++bank) {
272 if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
274 for (block = 0; block < NR_BLOCKS; ++block) {
276 address = MSR_IA32_MC0_MISC + bank * 4;
277 } else if (block == 1) {
278 address = (low & MASK_BLKPTR_LO) >> 21;
281 address += MCG_XBLK_ADDR;
286 if (rdmsr_safe(address, &low, &high))
289 if (!(high & MASK_VALID_HI)) {
296 if (!(high & MASK_CNTP_HI) ||
297 (high & MASK_LOCKED_HI))
301 * Log the machine check that caused the threshold
304 machine_check_poll(MCP_TIMESTAMP,
305 &__get_cpu_var(mce_poll_banks));
307 if (high & MASK_OVERFLOW_HI) {
308 rdmsrl(address, m.misc);
309 rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
311 m.bank = K8_MCE_THRESHOLD_BASE
325 struct threshold_attr {
326 struct attribute attr;
327 ssize_t (*show) (struct threshold_block *, char *);
328 ssize_t (*store) (struct threshold_block *, const char *, size_t count);
331 #define SHOW_FIELDS(name) \
332 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
334 return sprintf(buf, "%lx\n", (unsigned long) b->name); \
336 SHOW_FIELDS(interrupt_enable)
337 SHOW_FIELDS(threshold_limit)
340 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
342 struct thresh_restart tr;
345 if (!b->interrupt_capable)
348 if (strict_strtoul(buf, 0, &new) < 0)
351 b->interrupt_enable = !!new;
353 memset(&tr, 0, sizeof(tr));
356 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
362 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
364 struct thresh_restart tr;
367 if (strict_strtoul(buf, 0, &new) < 0)
370 if (new > THRESHOLD_MAX)
375 memset(&tr, 0, sizeof(tr));
376 tr.old_limit = b->threshold_limit;
377 b->threshold_limit = new;
380 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
385 struct threshold_block_cross_cpu {
386 struct threshold_block *tb;
390 static void local_error_count_handler(void *_tbcc)
392 struct threshold_block_cross_cpu *tbcc = _tbcc;
393 struct threshold_block *b = tbcc->tb;
396 rdmsr(b->address, low, high);
397 tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);
400 static ssize_t show_error_count(struct threshold_block *b, char *buf)
402 struct threshold_block_cross_cpu tbcc = { .tb = b, };
404 smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1);
405 return sprintf(buf, "%lx\n", tbcc.retval);
408 static ssize_t store_error_count(struct threshold_block *b,
409 const char *buf, size_t count)
411 struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };
413 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
417 #define RW_ATTR(val) \
418 static struct threshold_attr val = { \
419 .attr = {.name = __stringify(val), .mode = 0644 }, \
420 .show = show_## val, \
421 .store = store_## val, \
424 RW_ATTR(interrupt_enable);
425 RW_ATTR(threshold_limit);
426 RW_ATTR(error_count);
428 static struct attribute *default_attrs[] = {
429 &interrupt_enable.attr,
430 &threshold_limit.attr,
435 #define to_block(k) container_of(k, struct threshold_block, kobj)
436 #define to_attr(a) container_of(a, struct threshold_attr, attr)
438 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
440 struct threshold_block *b = to_block(kobj);
441 struct threshold_attr *a = to_attr(attr);
444 ret = a->show ? a->show(b, buf) : -EIO;
449 static ssize_t store(struct kobject *kobj, struct attribute *attr,
450 const char *buf, size_t count)
452 struct threshold_block *b = to_block(kobj);
453 struct threshold_attr *a = to_attr(attr);
456 ret = a->store ? a->store(b, buf, count) : -EIO;
461 static const struct sysfs_ops threshold_ops = {
466 static struct kobj_type threshold_ktype = {
467 .sysfs_ops = &threshold_ops,
468 .default_attrs = default_attrs,
471 static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
476 struct threshold_block *b = NULL;
480 if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
483 if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
486 if (!(high & MASK_VALID_HI)) {
493 if (!(high & MASK_CNTP_HI) ||
494 (high & MASK_LOCKED_HI))
497 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
504 b->address = address;
505 b->interrupt_enable = 0;
506 b->interrupt_capable = lvt_interrupt_supported(bank, high);
507 b->threshold_limit = THRESHOLD_MAX;
509 INIT_LIST_HEAD(&b->miscj);
511 if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
513 &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
515 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
518 err = kobject_init_and_add(&b->kobj, &threshold_ktype,
519 per_cpu(threshold_banks, cpu)[bank]->kobj,
525 address = (low & MASK_BLKPTR_LO) >> 21;
528 address += MCG_XBLK_ADDR;
533 err = allocate_threshold_blocks(cpu, bank, ++block, address);
538 kobject_uevent(&b->kobj, KOBJ_ADD);
544 kobject_put(&b->kobj);
551 static __cpuinit long
552 local_allocate_threshold_blocks(int cpu, unsigned int bank)
554 return allocate_threshold_blocks(cpu, bank, 0,
555 MSR_IA32_MC0_MISC + bank * 4);
558 /* symlinks sibling shared banks to first core. first core owns dir/files. */
559 static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
562 struct threshold_bank *b = NULL;
565 sprintf(name, "threshold_bank%i", bank);
568 if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */
569 i = cpumask_first(cpu_llc_shared_mask(cpu));
571 /* first core not up yet */
572 if (cpu_data(i).cpu_core_id)
576 if (per_cpu(threshold_banks, cpu)[bank])
579 b = per_cpu(threshold_banks, i)[bank];
584 err = sysfs_create_link(&per_cpu(mce_sysdev, cpu).kobj,
589 cpumask_copy(b->cpus, cpu_llc_shared_mask(cpu));
590 per_cpu(threshold_banks, cpu)[bank] = b;
596 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
601 if (!zalloc_cpumask_var(&b->cpus, GFP_KERNEL)) {
607 b->kobj = kobject_create_and_add(name, &per_cpu(mce_sysdev, cpu).kobj);
612 cpumask_setall(b->cpus);
614 cpumask_set_cpu(cpu, b->cpus);
617 per_cpu(threshold_banks, cpu)[bank] = b;
619 err = local_allocate_threshold_blocks(cpu, bank);
623 for_each_cpu(i, b->cpus) {
627 err = sysfs_create_link(&per_cpu(mce_sysdev, i).kobj,
632 per_cpu(threshold_banks, i)[bank] = b;
638 per_cpu(threshold_banks, cpu)[bank] = NULL;
639 free_cpumask_var(b->cpus);
645 /* create dir/files for all valid threshold banks */
646 static __cpuinit int threshold_create_device(unsigned int cpu)
651 for (bank = 0; bank < NR_BANKS; ++bank) {
652 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
654 err = threshold_create_bank(cpu, bank);
663 * let's be hotplug friendly.
664 * in case of multiple core processors, the first core always takes ownership
665 * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
668 static void deallocate_threshold_block(unsigned int cpu,
671 struct threshold_block *pos = NULL;
672 struct threshold_block *tmp = NULL;
673 struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
678 list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
679 kobject_put(&pos->kobj);
680 list_del(&pos->miscj);
684 kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
685 per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
688 static void threshold_remove_bank(unsigned int cpu, int bank)
690 struct threshold_bank *b;
694 b = per_cpu(threshold_banks, cpu)[bank];
700 sprintf(name, "threshold_bank%i", bank);
703 /* sibling symlink */
704 if (shared_bank[bank] && b->blocks->cpu != cpu) {
705 sysfs_remove_link(&per_cpu(mce_sysdev, cpu).kobj, name);
706 per_cpu(threshold_banks, cpu)[bank] = NULL;
712 /* remove all sibling symlinks before unregistering */
713 for_each_cpu(i, b->cpus) {
717 sysfs_remove_link(&per_cpu(mce_sysdev, i).kobj, name);
718 per_cpu(threshold_banks, i)[bank] = NULL;
721 deallocate_threshold_block(cpu, bank);
724 kobject_del(b->kobj);
725 kobject_put(b->kobj);
726 free_cpumask_var(b->cpus);
728 per_cpu(threshold_banks, cpu)[bank] = NULL;
731 static void threshold_remove_device(unsigned int cpu)
735 for (bank = 0; bank < NR_BANKS; ++bank) {
736 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
738 threshold_remove_bank(cpu, bank);
742 /* get notified when a cpu comes on/off */
743 static void __cpuinit
744 amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)
748 case CPU_ONLINE_FROZEN:
749 threshold_create_device(cpu);
752 case CPU_DEAD_FROZEN:
753 threshold_remove_device(cpu);
760 static __init int threshold_init_device(void)
764 /* to hit CPUs online before the notifier is up */
765 for_each_online_cpu(lcpu) {
766 int err = threshold_create_device(lcpu);
771 threshold_cpu_callback = amd_64_threshold_cpu_callback;
775 device_initcall(threshold_init_device);