2 * (c) 2005, 2006 Advanced Micro Devices, Inc.
3 * Your use of this code is subject to the terms and conditions of the
4 * GNU general public license version 2. See "COPYING" or
5 * http://www.gnu.org/licenses/gpl.html
7 * Written by Jacob Shin - AMD, Inc.
9 * Support : jacob.shin@amd.com
12 * - added support for AMD Family 0x10 processors
14 * All MC4_MISCi registers are shared between multi-cores
16 #include <linux/interrupt.h>
17 #include <linux/notifier.h>
18 #include <linux/kobject.h>
19 #include <linux/percpu.h>
20 #include <linux/sysdev.h>
21 #include <linux/errno.h>
22 #include <linux/sched.h>
23 #include <linux/sysfs.h>
24 #include <linux/slab.h>
25 #include <linux/init.h>
26 #include <linux/cpu.h>
27 #include <linux/smp.h>
34 #define PFX "mce_threshold: "
35 #define VERSION "version 1.1.1"
38 #define THRESHOLD_MAX 0xFFF
39 #define INT_TYPE_APIC 0x00020000
40 #define MASK_VALID_HI 0x80000000
41 #define MASK_CNTP_HI 0x40000000
42 #define MASK_LOCKED_HI 0x20000000
43 #define MASK_LVTOFF_HI 0x00F00000
44 #define MASK_COUNT_EN_HI 0x00080000
45 #define MASK_INT_TYPE_HI 0x00060000
46 #define MASK_OVERFLOW_HI 0x00010000
47 #define MASK_ERR_COUNT_HI 0x00000FFF
48 #define MASK_BLKPTR_LO 0xFF000000
49 #define MCG_XBLK_ADDR 0xC0000400
51 struct threshold_block {
59 struct list_head miscj;
62 /* defaults used early on boot */
63 static struct threshold_block threshold_defaults = {
64 .interrupt_enable = 0,
65 .threshold_limit = THRESHOLD_MAX,
68 struct threshold_bank {
70 struct threshold_block *blocks;
73 static DEFINE_PER_CPU(struct threshold_bank * [NR_BANKS], threshold_banks);
76 static unsigned char shared_bank[NR_BANKS] = {
81 static DEFINE_PER_CPU(unsigned char, bank_map); /* see which banks are on */
83 static void amd_threshold_interrupt(void);
89 struct thresh_restart {
90 struct threshold_block *b;
95 /* must be called with correct cpu affinity */
96 /* Called via smp_call_function_single() */
97 static void threshold_restart_bank(void *_tr)
99 struct thresh_restart *tr = _tr;
100 u32 mci_misc_hi, mci_misc_lo;
102 rdmsr(tr->b->address, mci_misc_lo, mci_misc_hi);
104 if (tr->b->threshold_limit < (mci_misc_hi & THRESHOLD_MAX))
105 tr->reset = 1; /* limit cannot be lower than err count */
107 if (tr->reset) { /* reset err count and overflow bit */
109 (mci_misc_hi & ~(MASK_ERR_COUNT_HI | MASK_OVERFLOW_HI)) |
110 (THRESHOLD_MAX - tr->b->threshold_limit);
111 } else if (tr->old_limit) { /* change limit w/o reset */
112 int new_count = (mci_misc_hi & THRESHOLD_MAX) +
113 (tr->old_limit - tr->b->threshold_limit);
115 mci_misc_hi = (mci_misc_hi & ~MASK_ERR_COUNT_HI) |
116 (new_count & THRESHOLD_MAX);
119 tr->b->interrupt_enable ?
120 (mci_misc_hi = (mci_misc_hi & ~MASK_INT_TYPE_HI) | INT_TYPE_APIC) :
121 (mci_misc_hi &= ~MASK_INT_TYPE_HI);
123 mci_misc_hi |= MASK_COUNT_EN_HI;
124 wrmsr(tr->b->address, mci_misc_lo, mci_misc_hi);
127 /* cpu init entry point, called from mce.c with preempt off */
128 void mce_amd_feature_init(struct cpuinfo_x86 *c)
130 unsigned int cpu = smp_processor_id();
131 u32 low = 0, high = 0, address = 0;
132 unsigned int bank, block;
133 struct thresh_restart tr;
136 for (bank = 0; bank < NR_BANKS; ++bank) {
137 for (block = 0; block < NR_BLOCKS; ++block) {
139 address = MSR_IA32_MC0_MISC + bank * 4;
140 else if (block == 1) {
141 address = (low & MASK_BLKPTR_LO) >> 21;
145 address += MCG_XBLK_ADDR;
149 if (rdmsr_safe(address, &low, &high))
152 if (!(high & MASK_VALID_HI))
155 if (!(high & MASK_CNTP_HI) ||
156 (high & MASK_LOCKED_HI))
160 per_cpu(bank_map, cpu) |= (1 << bank);
162 if (shared_bank[bank] && c->cpu_core_id)
165 lvt_off = setup_APIC_eilvt_mce(THRESHOLD_APIC_VECTOR,
166 APIC_EILVT_MSG_FIX, 0);
168 high &= ~MASK_LVTOFF_HI;
169 high |= lvt_off << 20;
170 wrmsr(address, low, high);
172 threshold_defaults.address = address;
173 tr.b = &threshold_defaults;
176 threshold_restart_bank(&tr);
178 mce_threshold_vector = amd_threshold_interrupt;
184 * APIC Interrupt Handler
188 * threshold interrupt handler will service THRESHOLD_APIC_VECTOR.
189 * the interrupt goes off when error_count reaches threshold_limit.
190 * the handler will simply log mcelog w/ software defined bank number.
192 static void amd_threshold_interrupt(void)
194 u32 low = 0, high = 0, address = 0;
195 unsigned int bank, block;
200 /* assume first bank caused it */
201 for (bank = 0; bank < NR_BANKS; ++bank) {
202 if (!(per_cpu(bank_map, m.cpu) & (1 << bank)))
204 for (block = 0; block < NR_BLOCKS; ++block) {
206 address = MSR_IA32_MC0_MISC + bank * 4;
207 } else if (block == 1) {
208 address = (low & MASK_BLKPTR_LO) >> 21;
211 address += MCG_XBLK_ADDR;
216 if (rdmsr_safe(address, &low, &high))
219 if (!(high & MASK_VALID_HI)) {
226 if (!(high & MASK_CNTP_HI) ||
227 (high & MASK_LOCKED_HI))
231 * Log the machine check that caused the threshold
234 machine_check_poll(MCP_TIMESTAMP,
235 &__get_cpu_var(mce_poll_banks));
237 if (high & MASK_OVERFLOW_HI) {
238 rdmsrl(address, m.misc);
239 rdmsrl(MSR_IA32_MC0_STATUS + bank * 4,
241 m.bank = K8_MCE_THRESHOLD_BASE
255 struct threshold_attr {
256 struct attribute attr;
257 ssize_t (*show) (struct threshold_block *, char *);
258 ssize_t (*store) (struct threshold_block *, const char *, size_t count);
261 #define SHOW_FIELDS(name) \
262 static ssize_t show_ ## name(struct threshold_block *b, char *buf) \
264 return sprintf(buf, "%lx\n", (unsigned long) b->name); \
266 SHOW_FIELDS(interrupt_enable)
267 SHOW_FIELDS(threshold_limit)
270 store_interrupt_enable(struct threshold_block *b, const char *buf, size_t size)
272 struct thresh_restart tr;
275 if (strict_strtoul(buf, 0, &new) < 0)
278 b->interrupt_enable = !!new;
284 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
290 store_threshold_limit(struct threshold_block *b, const char *buf, size_t size)
292 struct thresh_restart tr;
295 if (strict_strtoul(buf, 0, &new) < 0)
298 if (new > THRESHOLD_MAX)
303 tr.old_limit = b->threshold_limit;
304 b->threshold_limit = new;
308 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
313 struct threshold_block_cross_cpu {
314 struct threshold_block *tb;
318 static void local_error_count_handler(void *_tbcc)
320 struct threshold_block_cross_cpu *tbcc = _tbcc;
321 struct threshold_block *b = tbcc->tb;
324 rdmsr(b->address, low, high);
325 tbcc->retval = (high & 0xFFF) - (THRESHOLD_MAX - b->threshold_limit);
328 static ssize_t show_error_count(struct threshold_block *b, char *buf)
330 struct threshold_block_cross_cpu tbcc = { .tb = b, };
332 smp_call_function_single(b->cpu, local_error_count_handler, &tbcc, 1);
333 return sprintf(buf, "%lx\n", tbcc.retval);
336 static ssize_t store_error_count(struct threshold_block *b,
337 const char *buf, size_t count)
339 struct thresh_restart tr = { .b = b, .reset = 1, .old_limit = 0 };
341 smp_call_function_single(b->cpu, threshold_restart_bank, &tr, 1);
345 #define RW_ATTR(val) \
346 static struct threshold_attr val = { \
347 .attr = {.name = __stringify(val), .mode = 0644 }, \
348 .show = show_## val, \
349 .store = store_## val, \
352 RW_ATTR(interrupt_enable);
353 RW_ATTR(threshold_limit);
354 RW_ATTR(error_count);
356 static struct attribute *default_attrs[] = {
357 &interrupt_enable.attr,
358 &threshold_limit.attr,
363 #define to_block(k) container_of(k, struct threshold_block, kobj)
364 #define to_attr(a) container_of(a, struct threshold_attr, attr)
366 static ssize_t show(struct kobject *kobj, struct attribute *attr, char *buf)
368 struct threshold_block *b = to_block(kobj);
369 struct threshold_attr *a = to_attr(attr);
372 ret = a->show ? a->show(b, buf) : -EIO;
377 static ssize_t store(struct kobject *kobj, struct attribute *attr,
378 const char *buf, size_t count)
380 struct threshold_block *b = to_block(kobj);
381 struct threshold_attr *a = to_attr(attr);
384 ret = a->store ? a->store(b, buf, count) : -EIO;
389 static const struct sysfs_ops threshold_ops = {
394 static struct kobj_type threshold_ktype = {
395 .sysfs_ops = &threshold_ops,
396 .default_attrs = default_attrs,
399 static __cpuinit int allocate_threshold_blocks(unsigned int cpu,
404 struct threshold_block *b = NULL;
408 if ((bank >= NR_BANKS) || (block >= NR_BLOCKS))
411 if (rdmsr_safe_on_cpu(cpu, address, &low, &high))
414 if (!(high & MASK_VALID_HI)) {
421 if (!(high & MASK_CNTP_HI) ||
422 (high & MASK_LOCKED_HI))
425 b = kzalloc(sizeof(struct threshold_block), GFP_KERNEL);
432 b->address = address;
433 b->interrupt_enable = 0;
434 b->threshold_limit = THRESHOLD_MAX;
436 INIT_LIST_HEAD(&b->miscj);
438 if (per_cpu(threshold_banks, cpu)[bank]->blocks) {
440 &per_cpu(threshold_banks, cpu)[bank]->blocks->miscj);
442 per_cpu(threshold_banks, cpu)[bank]->blocks = b;
445 err = kobject_init_and_add(&b->kobj, &threshold_ktype,
446 per_cpu(threshold_banks, cpu)[bank]->kobj,
452 address = (low & MASK_BLKPTR_LO) >> 21;
455 address += MCG_XBLK_ADDR;
460 err = allocate_threshold_blocks(cpu, bank, ++block, address);
465 kobject_uevent(&b->kobj, KOBJ_ADD);
471 kobject_put(&b->kobj);
477 static __cpuinit long
478 local_allocate_threshold_blocks(int cpu, unsigned int bank)
480 return allocate_threshold_blocks(cpu, bank, 0,
481 MSR_IA32_MC0_MISC + bank * 4);
484 /* symlinks sibling shared banks to first core. first core owns dir/files. */
485 static __cpuinit int threshold_create_bank(unsigned int cpu, unsigned int bank)
488 struct threshold_bank *b = NULL;
491 struct cpuinfo_x86 *c = &cpu_data(cpu);
494 sprintf(name, "threshold_bank%i", bank);
497 if (cpu_data(cpu).cpu_core_id && shared_bank[bank]) { /* symlink */
498 i = cpumask_first(c->llc_shared_map);
500 /* first core not up yet */
501 if (cpu_data(i).cpu_core_id)
505 if (per_cpu(threshold_banks, cpu)[bank])
508 b = per_cpu(threshold_banks, i)[bank];
513 err = sysfs_create_link(&per_cpu(mce_dev, cpu).kobj,
518 cpumask_copy(b->cpus, c->llc_shared_map);
519 per_cpu(threshold_banks, cpu)[bank] = b;
525 b = kzalloc(sizeof(struct threshold_bank), GFP_KERNEL);
530 if (!zalloc_cpumask_var(&b->cpus, GFP_KERNEL)) {
536 b->kobj = kobject_create_and_add(name, &per_cpu(mce_dev, cpu).kobj);
541 cpumask_setall(b->cpus);
543 cpumask_set_cpu(cpu, b->cpus);
546 per_cpu(threshold_banks, cpu)[bank] = b;
548 err = local_allocate_threshold_blocks(cpu, bank);
552 for_each_cpu(i, b->cpus) {
556 err = sysfs_create_link(&per_cpu(mce_dev, i).kobj,
561 per_cpu(threshold_banks, i)[bank] = b;
567 per_cpu(threshold_banks, cpu)[bank] = NULL;
568 free_cpumask_var(b->cpus);
574 /* create dir/files for all valid threshold banks */
575 static __cpuinit int threshold_create_device(unsigned int cpu)
580 for (bank = 0; bank < NR_BANKS; ++bank) {
581 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
583 err = threshold_create_bank(cpu, bank);
592 * let's be hotplug friendly.
593 * in case of multiple core processors, the first core always takes ownership
594 * of shared sysfs dir/files, and rest of the cores will be symlinked to it.
597 static void deallocate_threshold_block(unsigned int cpu,
600 struct threshold_block *pos = NULL;
601 struct threshold_block *tmp = NULL;
602 struct threshold_bank *head = per_cpu(threshold_banks, cpu)[bank];
607 list_for_each_entry_safe(pos, tmp, &head->blocks->miscj, miscj) {
608 kobject_put(&pos->kobj);
609 list_del(&pos->miscj);
613 kfree(per_cpu(threshold_banks, cpu)[bank]->blocks);
614 per_cpu(threshold_banks, cpu)[bank]->blocks = NULL;
617 static void threshold_remove_bank(unsigned int cpu, int bank)
619 struct threshold_bank *b;
623 b = per_cpu(threshold_banks, cpu)[bank];
629 sprintf(name, "threshold_bank%i", bank);
632 /* sibling symlink */
633 if (shared_bank[bank] && b->blocks->cpu != cpu) {
634 sysfs_remove_link(&per_cpu(mce_dev, cpu).kobj, name);
635 per_cpu(threshold_banks, cpu)[bank] = NULL;
641 /* remove all sibling symlinks before unregistering */
642 for_each_cpu(i, b->cpus) {
646 sysfs_remove_link(&per_cpu(mce_dev, i).kobj, name);
647 per_cpu(threshold_banks, i)[bank] = NULL;
650 deallocate_threshold_block(cpu, bank);
653 kobject_del(b->kobj);
654 kobject_put(b->kobj);
655 free_cpumask_var(b->cpus);
657 per_cpu(threshold_banks, cpu)[bank] = NULL;
660 static void threshold_remove_device(unsigned int cpu)
664 for (bank = 0; bank < NR_BANKS; ++bank) {
665 if (!(per_cpu(bank_map, cpu) & (1 << bank)))
667 threshold_remove_bank(cpu, bank);
671 /* get notified when a cpu comes on/off */
672 static void __cpuinit
673 amd_64_threshold_cpu_callback(unsigned long action, unsigned int cpu)
677 case CPU_ONLINE_FROZEN:
678 threshold_create_device(cpu);
681 case CPU_DEAD_FROZEN:
682 threshold_remove_device(cpu);
689 static __init int threshold_init_device(void)
693 /* to hit CPUs online before the notifier is up */
694 for_each_online_cpu(lcpu) {
695 int err = threshold_create_device(lcpu);
700 threshold_cpu_callback = amd_64_threshold_cpu_callback;
704 device_initcall(threshold_init_device);