2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/irq_work.h>
40 #include <linux/export.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_chrdev_read_mutex);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/mce.h>
58 int mce_disabled __read_mostly;
60 #define MISC_MCELOG_MINOR 227
62 #define SPINUNIT 100 /* 100ns */
66 DEFINE_PER_CPU(unsigned, mce_exception_count);
70 * 0: always panic on uncorrected errors, log corrected errors
71 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
72 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
73 * 3: never panic or SIGBUS, log all errors (for testing only)
75 static int tolerant __read_mostly = 1;
76 static int banks __read_mostly;
77 static int rip_msr __read_mostly;
78 static int mce_bootlog __read_mostly = -1;
79 static int monarch_timeout __read_mostly = -1;
80 static int mce_panic_timeout __read_mostly;
81 static int mce_dont_log_ce __read_mostly;
82 int mce_cmci_disabled __read_mostly;
83 int mce_ignore_ce __read_mostly;
84 int mce_ser __read_mostly;
86 struct mce_bank *mce_banks __read_mostly;
88 /* User mode helper program triggered by machine check event */
89 static unsigned long mce_need_notify;
90 static char mce_helper[128];
91 static char *mce_helper_argv[2] = { mce_helper, NULL };
93 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
95 static DEFINE_PER_CPU(struct mce, mces_seen);
96 static int cpu_missing;
99 * CPU/chipset specific EDAC code can register a notifier call here to print
100 * MCE errors in a human-readable form.
102 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
103 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
105 /* MCA banks polled by the period polling timer for corrected events */
106 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
107 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
110 static DEFINE_PER_CPU(struct work_struct, mce_work);
112 /* Do initial initialization of a struct mce */
113 void mce_setup(struct mce *m)
115 memset(m, 0, sizeof(struct mce));
116 m->cpu = m->extcpu = smp_processor_id();
118 /* We hope get_seconds stays lockless */
119 m->time = get_seconds();
120 m->cpuvendor = boot_cpu_data.x86_vendor;
121 m->cpuid = cpuid_eax(1);
122 m->socketid = cpu_data(m->extcpu).phys_proc_id;
123 m->apicid = cpu_data(m->extcpu).initial_apicid;
124 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
127 DEFINE_PER_CPU(struct mce, injectm);
128 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
131 * Lockless MCE logging infrastructure.
132 * This avoids deadlocks on printk locks without having to break locks. Also
133 * separate MCEs from kernel messages to avoid bogus bug reports.
136 static struct mce_log mcelog = {
137 .signature = MCE_LOG_SIGNATURE,
139 .recordlen = sizeof(struct mce),
142 void mce_log(struct mce *mce)
144 unsigned next, entry;
147 /* Emit the trace record: */
148 trace_mce_record(mce);
150 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
151 if (ret == NOTIFY_STOP)
157 entry = rcu_dereference_check_mce(mcelog.next);
161 * When the buffer fills up discard new entries.
162 * Assume that the earlier errors are the more
165 if (entry >= MCE_LOG_LEN) {
166 set_bit(MCE_OVERFLOW,
167 (unsigned long *)&mcelog.flags);
170 /* Old left over entry. Skip: */
171 if (mcelog.entry[entry].finished) {
179 if (cmpxchg(&mcelog.next, entry, next) == entry)
182 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
184 mcelog.entry[entry].finished = 1;
188 set_bit(0, &mce_need_notify);
191 static void print_mce(struct mce *m)
195 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
196 m->extcpu, m->mcgstatus, m->bank, m->status);
199 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
200 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
203 if (m->cs == __KERNEL_CS)
204 print_symbol("{%s}", m->ip);
208 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
210 pr_cont("ADDR %llx ", m->addr);
212 pr_cont("MISC %llx ", m->misc);
216 * Note this output is parsed by external tools and old fields
217 * should not be changed.
219 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
220 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
221 cpu_data(m->extcpu).microcode);
224 * Print out human-readable details about the MCE error,
225 * (if the CPU has an implementation for that)
227 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
228 if (ret == NOTIFY_STOP)
231 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
234 #define PANIC_TIMEOUT 5 /* 5 seconds */
236 static atomic_t mce_paniced;
238 static int fake_panic;
239 static atomic_t mce_fake_paniced;
241 /* Panic in progress. Enable interrupts and wait for final IPI */
242 static void wait_for_panic(void)
244 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
248 while (timeout-- > 0)
250 if (panic_timeout == 0)
251 panic_timeout = mce_panic_timeout;
252 panic("Panicing machine check CPU died");
255 static void mce_panic(char *msg, struct mce *final, char *exp)
261 * Make sure only one CPU runs in machine check panic
263 if (atomic_inc_return(&mce_paniced) > 1)
270 /* Don't log too much for fake panic */
271 if (atomic_inc_return(&mce_fake_paniced) > 1)
274 /* First print corrected ones that are still unlogged */
275 for (i = 0; i < MCE_LOG_LEN; i++) {
276 struct mce *m = &mcelog.entry[i];
277 if (!(m->status & MCI_STATUS_VAL))
279 if (!(m->status & MCI_STATUS_UC)) {
282 apei_err = apei_write_mce(m);
285 /* Now print uncorrected but with the final one last */
286 for (i = 0; i < MCE_LOG_LEN; i++) {
287 struct mce *m = &mcelog.entry[i];
288 if (!(m->status & MCI_STATUS_VAL))
290 if (!(m->status & MCI_STATUS_UC))
292 if (!final || memcmp(m, final, sizeof(struct mce))) {
295 apei_err = apei_write_mce(m);
301 apei_err = apei_write_mce(final);
304 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
306 pr_emerg(HW_ERR "Machine check: %s\n", exp);
308 if (panic_timeout == 0)
309 panic_timeout = mce_panic_timeout;
312 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
315 /* Support code for software error injection */
317 static int msr_to_offset(u32 msr)
319 unsigned bank = __this_cpu_read(injectm.bank);
322 return offsetof(struct mce, ip);
323 if (msr == MSR_IA32_MCx_STATUS(bank))
324 return offsetof(struct mce, status);
325 if (msr == MSR_IA32_MCx_ADDR(bank))
326 return offsetof(struct mce, addr);
327 if (msr == MSR_IA32_MCx_MISC(bank))
328 return offsetof(struct mce, misc);
329 if (msr == MSR_IA32_MCG_STATUS)
330 return offsetof(struct mce, mcgstatus);
334 /* MSR access wrappers used for error injection */
335 static u64 mce_rdmsrl(u32 msr)
339 if (__this_cpu_read(injectm.finished)) {
340 int offset = msr_to_offset(msr);
344 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
347 if (rdmsrl_safe(msr, &v)) {
348 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
350 * Return zero in case the access faulted. This should
351 * not happen normally but can happen if the CPU does
352 * something weird, or if the code is buggy.
360 static void mce_wrmsrl(u32 msr, u64 v)
362 if (__this_cpu_read(injectm.finished)) {
363 int offset = msr_to_offset(msr);
366 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
373 * Collect all global (w.r.t. this processor) status about this machine
374 * check into our "mce" struct so that we can use it later to assess
375 * the severity of the problem as we read per-bank specific details.
377 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
381 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
384 * Get the address of the instruction at the time of
385 * the machine check error.
387 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
392 * When in VM86 mode make the cs look like ring 3
393 * always. This is a lie, but it's better than passing
394 * the additional vm86 bit around everywhere.
396 if (v8086_mode(regs))
399 /* Use accurate RIP reporting if available. */
401 m->ip = mce_rdmsrl(rip_msr);
406 * Simple lockless ring to communicate PFNs from the exception handler with the
407 * process context work function. This is vastly simplified because there's
408 * only a single reader and a single writer.
410 #define MCE_RING_SIZE 16 /* we use one entry less */
413 unsigned short start;
415 unsigned long ring[MCE_RING_SIZE];
417 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
419 /* Runs with CPU affinity in workqueue */
420 static int mce_ring_empty(void)
422 struct mce_ring *r = &__get_cpu_var(mce_ring);
424 return r->start == r->end;
427 static int mce_ring_get(unsigned long *pfn)
434 r = &__get_cpu_var(mce_ring);
435 if (r->start == r->end)
437 *pfn = r->ring[r->start];
438 r->start = (r->start + 1) % MCE_RING_SIZE;
445 /* Always runs in MCE context with preempt off */
446 static int mce_ring_add(unsigned long pfn)
448 struct mce_ring *r = &__get_cpu_var(mce_ring);
451 next = (r->end + 1) % MCE_RING_SIZE;
452 if (next == r->start)
454 r->ring[r->end] = pfn;
460 int mce_available(struct cpuinfo_x86 *c)
464 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
467 static void mce_schedule_work(void)
469 if (!mce_ring_empty()) {
470 struct work_struct *work = &__get_cpu_var(mce_work);
471 if (!work_pending(work))
476 DEFINE_PER_CPU(struct irq_work, mce_irq_work);
478 static void mce_irq_work_cb(struct irq_work *entry)
484 static void mce_report_event(struct pt_regs *regs)
486 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
489 * Triggering the work queue here is just an insurance
490 * policy in case the syscall exit notify handler
491 * doesn't run soon enough or ends up running on the
492 * wrong CPU (can happen when audit sleeps)
498 irq_work_queue(&__get_cpu_var(mce_irq_work));
501 DEFINE_PER_CPU(unsigned, mce_poll_count);
504 * Poll for corrected events or events that happened before reset.
505 * Those are just logged through /dev/mcelog.
507 * This is executed in standard interrupt context.
509 * Note: spec recommends to panic for fatal unsignalled
510 * errors here. However this would be quite problematic --
511 * we would need to reimplement the Monarch handling and
512 * it would mess up the exclusion between exception handler
513 * and poll hander -- * so we skip this for now.
514 * These cases should not happen anyways, or only when the CPU
515 * is already totally * confused. In this case it's likely it will
516 * not fully execute the machine check handler either.
518 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
523 percpu_inc(mce_poll_count);
525 mce_gather_info(&m, NULL);
527 for (i = 0; i < banks; i++) {
528 if (!mce_banks[i].ctl || !test_bit(i, *b))
537 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
538 if (!(m.status & MCI_STATUS_VAL))
542 * Uncorrected or signalled events are handled by the exception
543 * handler when it is enabled, so don't process those here.
545 * TBD do the same check for MCI_STATUS_EN here?
547 if (!(flags & MCP_UC) &&
548 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
551 if (m.status & MCI_STATUS_MISCV)
552 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
553 if (m.status & MCI_STATUS_ADDRV)
554 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
556 if (!(flags & MCP_TIMESTAMP))
559 * Don't get the IP here because it's unlikely to
560 * have anything to do with the actual error location.
562 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce)
566 * Clear state for this bank.
568 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
572 * Don't clear MCG_STATUS here because it's only defined for
578 EXPORT_SYMBOL_GPL(machine_check_poll);
581 * Do a quick check if any of the events requires a panic.
582 * This decides if we keep the events around or clear them.
584 static int mce_no_way_out(struct mce *m, char **msg)
588 for (i = 0; i < banks; i++) {
589 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
590 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
597 * Variable to establish order between CPUs while scanning.
598 * Each CPU spins initially until executing is equal its number.
600 static atomic_t mce_executing;
603 * Defines order of CPUs on entry. First CPU becomes Monarch.
605 static atomic_t mce_callin;
608 * Check if a timeout waiting for other CPUs happened.
610 static int mce_timed_out(u64 *t)
613 * The others already did panic for some reason.
614 * Bail out like in a timeout.
615 * rmb() to tell the compiler that system_state
616 * might have been modified by someone else.
619 if (atomic_read(&mce_paniced))
621 if (!monarch_timeout)
623 if ((s64)*t < SPINUNIT) {
624 /* CHECKME: Make panic default for 1 too? */
626 mce_panic("Timeout synchronizing machine check over CPUs",
633 touch_nmi_watchdog();
638 * The Monarch's reign. The Monarch is the CPU who entered
639 * the machine check handler first. It waits for the others to
640 * raise the exception too and then grades them. When any
641 * error is fatal panic. Only then let the others continue.
643 * The other CPUs entering the MCE handler will be controlled by the
644 * Monarch. They are called Subjects.
646 * This way we prevent any potential data corruption in a unrecoverable case
647 * and also makes sure always all CPU's errors are examined.
649 * Also this detects the case of a machine check event coming from outer
650 * space (not detected by any CPUs) In this case some external agent wants
651 * us to shut down, so panic too.
653 * The other CPUs might still decide to panic if the handler happens
654 * in a unrecoverable place, but in this case the system is in a semi-stable
655 * state and won't corrupt anything by itself. It's ok to let the others
656 * continue for a bit first.
658 * All the spin loops have timeouts; when a timeout happens a CPU
659 * typically elects itself to be Monarch.
661 static void mce_reign(void)
664 struct mce *m = NULL;
665 int global_worst = 0;
670 * This CPU is the Monarch and the other CPUs have run
671 * through their handlers.
672 * Grade the severity of the errors of all the CPUs.
674 for_each_possible_cpu(cpu) {
675 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
677 if (severity > global_worst) {
679 global_worst = severity;
680 m = &per_cpu(mces_seen, cpu);
685 * Cannot recover? Panic here then.
686 * This dumps all the mces in the log buffer and stops the
689 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
690 mce_panic("Fatal Machine check", m, msg);
693 * For UC somewhere we let the CPU who detects it handle it.
694 * Also must let continue the others, otherwise the handling
695 * CPU could deadlock on a lock.
699 * No machine check event found. Must be some external
700 * source or one CPU is hung. Panic.
702 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
703 mce_panic("Machine check from unknown source", NULL, NULL);
706 * Now clear all the mces_seen so that they don't reappear on
709 for_each_possible_cpu(cpu)
710 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
713 static atomic_t global_nwo;
716 * Start of Monarch synchronization. This waits until all CPUs have
717 * entered the exception handler and then determines if any of them
718 * saw a fatal event that requires panic. Then it executes them
719 * in the entry order.
720 * TBD double check parallel CPU hotunplug
722 static int mce_start(int *no_way_out)
725 int cpus = num_online_cpus();
726 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
731 atomic_add(*no_way_out, &global_nwo);
733 * global_nwo should be updated before mce_callin
736 order = atomic_inc_return(&mce_callin);
741 while (atomic_read(&mce_callin) != cpus) {
742 if (mce_timed_out(&timeout)) {
743 atomic_set(&global_nwo, 0);
750 * mce_callin should be read before global_nwo
756 * Monarch: Starts executing now, the others wait.
758 atomic_set(&mce_executing, 1);
761 * Subject: Now start the scanning loop one by one in
762 * the original callin order.
763 * This way when there are any shared banks it will be
764 * only seen by one CPU before cleared, avoiding duplicates.
766 while (atomic_read(&mce_executing) < order) {
767 if (mce_timed_out(&timeout)) {
768 atomic_set(&global_nwo, 0);
776 * Cache the global no_way_out state.
778 *no_way_out = atomic_read(&global_nwo);
784 * Synchronize between CPUs after main scanning loop.
785 * This invokes the bulk of the Monarch processing.
787 static int mce_end(int order)
790 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
798 * Allow others to run.
800 atomic_inc(&mce_executing);
803 /* CHECKME: Can this race with a parallel hotplug? */
804 int cpus = num_online_cpus();
807 * Monarch: Wait for everyone to go through their scanning
810 while (atomic_read(&mce_executing) <= cpus) {
811 if (mce_timed_out(&timeout))
821 * Subject: Wait for Monarch to finish.
823 while (atomic_read(&mce_executing) != 0) {
824 if (mce_timed_out(&timeout))
830 * Don't reset anything. That's done by the Monarch.
836 * Reset all global state.
839 atomic_set(&global_nwo, 0);
840 atomic_set(&mce_callin, 0);
844 * Let others run again.
846 atomic_set(&mce_executing, 0);
851 * Check if the address reported by the CPU is in a format we can parse.
852 * It would be possible to add code for most other cases, but all would
853 * be somewhat complicated (e.g. segment offset would require an instruction
854 * parser). So only support physical addresses up to page granuality for now.
856 static int mce_usable_address(struct mce *m)
858 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
860 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
862 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
867 static void mce_clear_state(unsigned long *toclear)
871 for (i = 0; i < banks; i++) {
872 if (test_bit(i, toclear))
873 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
878 * The actual machine check handler. This only handles real
879 * exceptions when something got corrupted coming in through int 18.
881 * This is executed in NMI context not subject to normal locking rules. This
882 * implies that most kernel services cannot be safely used. Don't even
883 * think about putting a printk in there!
885 * On Intel systems this is entered on all CPUs in parallel through
886 * MCE broadcast. However some CPUs might be broken beyond repair,
887 * so be always careful when synchronizing with others.
889 void do_machine_check(struct pt_regs *regs, long error_code)
891 struct mce m, *final;
896 * Establish sequential order between the CPUs entering the machine
901 * If no_way_out gets set, there is no safe way to recover from this
902 * MCE. If tolerant is cranked up, we'll try anyway.
906 * If kill_it gets set, there might be a way to recover from this
910 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
911 char *msg = "Unknown";
913 atomic_inc(&mce_entry);
915 percpu_inc(mce_exception_count);
920 mce_gather_info(&m, regs);
922 final = &__get_cpu_var(mces_seen);
925 no_way_out = mce_no_way_out(&m, &msg);
930 * When no restart IP must always kill or panic.
932 if (!(m.mcgstatus & MCG_STATUS_RIPV))
936 * Go through all the banks in exclusion of the other CPUs.
937 * This way we don't report duplicated events on shared banks
938 * because the first one to see it will clear it.
940 order = mce_start(&no_way_out);
941 for (i = 0; i < banks; i++) {
942 __clear_bit(i, toclear);
943 if (!mce_banks[i].ctl)
950 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
951 if ((m.status & MCI_STATUS_VAL) == 0)
955 * Non uncorrected or non signaled errors are handled by
956 * machine_check_poll. Leave them alone, unless this panics.
958 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
963 * Set taint even when machine check was not enabled.
965 add_taint(TAINT_MACHINE_CHECK);
967 severity = mce_severity(&m, tolerant, NULL);
970 * When machine check was for corrected handler don't touch,
971 * unless we're panicing.
973 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
975 __set_bit(i, toclear);
976 if (severity == MCE_NO_SEVERITY) {
978 * Machine check event was not enabled. Clear, but
985 * Kill on action required.
987 if (severity == MCE_AR_SEVERITY)
990 if (m.status & MCI_STATUS_MISCV)
991 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
992 if (m.status & MCI_STATUS_ADDRV)
993 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
996 * Action optional error. Queue address for later processing.
997 * When the ring overflows we just ignore the AO error.
998 * RED-PEN add some logging mechanism when
999 * usable_address or mce_add_ring fails.
1000 * RED-PEN don't ignore overflow for tolerant == 0
1002 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1003 mce_ring_add(m.addr >> PAGE_SHIFT);
1007 if (severity > worst) {
1014 mce_clear_state(toclear);
1017 * Do most of the synchronization with other CPUs.
1018 * When there's any problem use only local no_way_out state.
1020 if (mce_end(order) < 0)
1021 no_way_out = worst >= MCE_PANIC_SEVERITY;
1024 * If we have decided that we just CAN'T continue, and the user
1025 * has not set tolerant to an insane level, give up and die.
1027 * This is mainly used in the case when the system doesn't
1028 * support MCE broadcasting or it has been disabled.
1030 if (no_way_out && tolerant < 3)
1031 mce_panic("Fatal machine check on current CPU", final, msg);
1034 * If the error seems to be unrecoverable, something should be
1035 * done. Try to kill as little as possible. If we can kill just
1036 * one task, do that. If the user has set the tolerance very
1037 * high, don't try to do anything at all.
1040 if (kill_it && tolerant < 3)
1041 force_sig(SIGBUS, current);
1043 /* notify userspace ASAP */
1044 set_thread_flag(TIF_MCE_NOTIFY);
1047 mce_report_event(regs);
1048 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1050 atomic_dec(&mce_entry);
1053 EXPORT_SYMBOL_GPL(do_machine_check);
1055 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1056 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1058 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1062 * Called after mce notification in process context. This code
1063 * is allowed to sleep. Call the high level VM handler to process
1064 * any corrupted pages.
1065 * Assume that the work queue code only calls this one at a time
1067 * Note we don't disable preemption, so this code might run on the wrong
1068 * CPU. In this case the event is picked up by the scheduled work queue.
1069 * This is merely a fast path to expedite processing in some common
1072 void mce_notify_process(void)
1076 while (mce_ring_get(&pfn))
1077 memory_failure(pfn, MCE_VECTOR);
1080 static void mce_process_work(struct work_struct *dummy)
1082 mce_notify_process();
1085 #ifdef CONFIG_X86_MCE_INTEL
1087 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1088 * @cpu: The CPU on which the event occurred.
1089 * @status: Event status information
1091 * This function should be called by the thermal interrupt after the
1092 * event has been processed and the decision was made to log the event
1095 * The status parameter will be saved to the 'status' field of 'struct mce'
1096 * and historically has been the register value of the
1097 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1099 void mce_log_therm_throt_event(__u64 status)
1104 m.bank = MCE_THERMAL_BANK;
1108 #endif /* CONFIG_X86_MCE_INTEL */
1111 * Periodic polling timer for "silent" machine check errors. If the
1112 * poller finds an MCE, poll 2x faster. When the poller finds no more
1113 * errors, poll 2x slower (up to check_interval seconds).
1115 static int check_interval = 5 * 60; /* 5 minutes */
1117 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1118 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1120 static void mce_start_timer(unsigned long data)
1122 struct timer_list *t = &per_cpu(mce_timer, data);
1125 WARN_ON(smp_processor_id() != data);
1127 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1128 machine_check_poll(MCP_TIMESTAMP,
1129 &__get_cpu_var(mce_poll_banks));
1133 * Alert userspace if needed. If we logged an MCE, reduce the
1134 * polling interval, otherwise increase the polling interval.
1136 n = &__get_cpu_var(mce_next_interval);
1137 if (mce_notify_irq())
1138 *n = max(*n/2, HZ/100);
1140 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1142 t->expires = jiffies + *n;
1143 add_timer_on(t, smp_processor_id());
1146 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1147 static void mce_timer_delete_all(void)
1151 for_each_online_cpu(cpu)
1152 del_timer_sync(&per_cpu(mce_timer, cpu));
1155 static void mce_do_trigger(struct work_struct *work)
1157 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1160 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1163 * Notify the user(s) about new machine check events.
1164 * Can be called from interrupt context, but not from machine check/NMI
1167 int mce_notify_irq(void)
1169 /* Not more than two messages every minute */
1170 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1172 clear_thread_flag(TIF_MCE_NOTIFY);
1174 if (test_and_clear_bit(0, &mce_need_notify)) {
1175 /* wake processes polling /dev/mcelog */
1176 wake_up_interruptible(&mce_chrdev_wait);
1179 * There is no risk of missing notifications because
1180 * work_pending is always cleared before the function is
1183 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1184 schedule_work(&mce_trigger_work);
1186 if (__ratelimit(&ratelimit))
1187 pr_info(HW_ERR "Machine check events logged\n");
1193 EXPORT_SYMBOL_GPL(mce_notify_irq);
1195 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1199 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1202 for (i = 0; i < banks; i++) {
1203 struct mce_bank *b = &mce_banks[i];
1212 * Initialize Machine Checks for a CPU.
1214 static int __cpuinit __mcheck_cpu_cap_init(void)
1219 rdmsrl(MSR_IA32_MCG_CAP, cap);
1221 b = cap & MCG_BANKCNT_MASK;
1223 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1225 if (b > MAX_NR_BANKS) {
1227 "MCE: Using only %u machine check banks out of %u\n",
1232 /* Don't support asymmetric configurations today */
1233 WARN_ON(banks != 0 && b != banks);
1236 int err = __mcheck_cpu_mce_banks_init();
1242 /* Use accurate RIP reporting if available. */
1243 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1244 rip_msr = MSR_IA32_MCG_EIP;
1246 if (cap & MCG_SER_P)
1252 static void __mcheck_cpu_init_generic(void)
1254 mce_banks_t all_banks;
1259 * Log the machine checks left over from the previous reset.
1261 bitmap_fill(all_banks, MAX_NR_BANKS);
1262 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1264 set_in_cr4(X86_CR4_MCE);
1266 rdmsrl(MSR_IA32_MCG_CAP, cap);
1267 if (cap & MCG_CTL_P)
1268 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1270 for (i = 0; i < banks; i++) {
1271 struct mce_bank *b = &mce_banks[i];
1275 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1276 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1280 /* Add per CPU specific workarounds here */
1281 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1283 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1284 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1288 /* This should be disabled by the BIOS, but isn't always */
1289 if (c->x86_vendor == X86_VENDOR_AMD) {
1290 if (c->x86 == 15 && banks > 4) {
1292 * disable GART TBL walk error reporting, which
1293 * trips off incorrectly with the IOMMU & 3ware
1296 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1298 if (c->x86 <= 17 && mce_bootlog < 0) {
1300 * Lots of broken BIOS around that don't clear them
1301 * by default and leave crap in there. Don't log:
1306 * Various K7s with broken bank 0 around. Always disable
1309 if (c->x86 == 6 && banks > 0)
1310 mce_banks[0].ctl = 0;
1313 if (c->x86_vendor == X86_VENDOR_INTEL) {
1315 * SDM documents that on family 6 bank 0 should not be written
1316 * because it aliases to another special BIOS controlled
1318 * But it's not aliased anymore on model 0x1a+
1319 * Don't ignore bank 0 completely because there could be a
1320 * valid event later, merely don't write CTL0.
1323 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1324 mce_banks[0].init = 0;
1327 * All newer Intel systems support MCE broadcasting. Enable
1328 * synchronization with a one second timeout.
1330 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1331 monarch_timeout < 0)
1332 monarch_timeout = USEC_PER_SEC;
1335 * There are also broken BIOSes on some Pentium M and
1338 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1341 if (monarch_timeout < 0)
1342 monarch_timeout = 0;
1343 if (mce_bootlog != 0)
1344 mce_panic_timeout = 30;
1349 static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1354 switch (c->x86_vendor) {
1355 case X86_VENDOR_INTEL:
1356 intel_p5_mcheck_init(c);
1359 case X86_VENDOR_CENTAUR:
1360 winchip_mcheck_init(c);
1368 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1370 switch (c->x86_vendor) {
1371 case X86_VENDOR_INTEL:
1372 mce_intel_feature_init(c);
1374 case X86_VENDOR_AMD:
1375 mce_amd_feature_init(c);
1382 static void __mcheck_cpu_init_timer(void)
1384 struct timer_list *t = &__get_cpu_var(mce_timer);
1385 int *n = &__get_cpu_var(mce_next_interval);
1387 setup_timer(t, mce_start_timer, smp_processor_id());
1392 *n = check_interval * HZ;
1395 t->expires = round_jiffies(jiffies + *n);
1396 add_timer_on(t, smp_processor_id());
1399 /* Handle unconfigured int18 (should never happen) */
1400 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1402 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1403 smp_processor_id());
1406 /* Call the installed machine check handler for this CPU setup. */
1407 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1408 unexpected_machine_check;
1411 * Called for each booted CPU to set up machine checks.
1412 * Must be called with preempt off:
1414 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1419 if (__mcheck_cpu_ancient_init(c))
1422 if (!mce_available(c))
1425 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1430 machine_check_vector = do_machine_check;
1432 __mcheck_cpu_init_generic();
1433 __mcheck_cpu_init_vendor(c);
1434 __mcheck_cpu_init_timer();
1435 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1436 init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
1440 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1443 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1444 static int mce_chrdev_open_count; /* #times opened */
1445 static int mce_chrdev_open_exclu; /* already open exclusive? */
1447 static int mce_chrdev_open(struct inode *inode, struct file *file)
1449 spin_lock(&mce_chrdev_state_lock);
1451 if (mce_chrdev_open_exclu ||
1452 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1453 spin_unlock(&mce_chrdev_state_lock);
1458 if (file->f_flags & O_EXCL)
1459 mce_chrdev_open_exclu = 1;
1460 mce_chrdev_open_count++;
1462 spin_unlock(&mce_chrdev_state_lock);
1464 return nonseekable_open(inode, file);
1467 static int mce_chrdev_release(struct inode *inode, struct file *file)
1469 spin_lock(&mce_chrdev_state_lock);
1471 mce_chrdev_open_count--;
1472 mce_chrdev_open_exclu = 0;
1474 spin_unlock(&mce_chrdev_state_lock);
1479 static void collect_tscs(void *data)
1481 unsigned long *cpu_tsc = (unsigned long *)data;
1483 rdtscll(cpu_tsc[smp_processor_id()]);
1486 static int mce_apei_read_done;
1488 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1489 static int __mce_read_apei(char __user **ubuf, size_t usize)
1495 if (usize < sizeof(struct mce))
1498 rc = apei_read_mce(&m, &record_id);
1499 /* Error or no more MCE record */
1501 mce_apei_read_done = 1;
1505 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1508 * In fact, we should have cleared the record after that has
1509 * been flushed to the disk or sent to network in
1510 * /sbin/mcelog, but we have no interface to support that now,
1511 * so just clear it to avoid duplication.
1513 rc = apei_clear_mce(record_id);
1515 mce_apei_read_done = 1;
1518 *ubuf += sizeof(struct mce);
1523 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1524 size_t usize, loff_t *off)
1526 char __user *buf = ubuf;
1527 unsigned long *cpu_tsc;
1528 unsigned prev, next;
1531 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1535 mutex_lock(&mce_chrdev_read_mutex);
1537 if (!mce_apei_read_done) {
1538 err = __mce_read_apei(&buf, usize);
1539 if (err || buf != ubuf)
1543 next = rcu_dereference_check_mce(mcelog.next);
1545 /* Only supports full reads right now */
1547 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1553 for (i = prev; i < next; i++) {
1554 unsigned long start = jiffies;
1555 struct mce *m = &mcelog.entry[i];
1557 while (!m->finished) {
1558 if (time_after_eq(jiffies, start + 2)) {
1559 memset(m, 0, sizeof(*m));
1565 err |= copy_to_user(buf, m, sizeof(*m));
1571 memset(mcelog.entry + prev, 0,
1572 (next - prev) * sizeof(struct mce));
1574 next = cmpxchg(&mcelog.next, prev, 0);
1575 } while (next != prev);
1577 synchronize_sched();
1580 * Collect entries that were still getting written before the
1583 on_each_cpu(collect_tscs, cpu_tsc, 1);
1585 for (i = next; i < MCE_LOG_LEN; i++) {
1586 struct mce *m = &mcelog.entry[i];
1588 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1589 err |= copy_to_user(buf, m, sizeof(*m));
1592 memset(m, 0, sizeof(*m));
1600 mutex_unlock(&mce_chrdev_read_mutex);
1603 return err ? err : buf - ubuf;
1606 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1608 poll_wait(file, &mce_chrdev_wait, wait);
1609 if (rcu_access_index(mcelog.next))
1610 return POLLIN | POLLRDNORM;
1611 if (!mce_apei_read_done && apei_check_mce())
1612 return POLLIN | POLLRDNORM;
1616 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1619 int __user *p = (int __user *)arg;
1621 if (!capable(CAP_SYS_ADMIN))
1625 case MCE_GET_RECORD_LEN:
1626 return put_user(sizeof(struct mce), p);
1627 case MCE_GET_LOG_LEN:
1628 return put_user(MCE_LOG_LEN, p);
1629 case MCE_GETCLEAR_FLAGS: {
1633 flags = mcelog.flags;
1634 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1636 return put_user(flags, p);
1643 static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
1644 size_t usize, loff_t *off);
1646 void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
1647 const char __user *ubuf,
1648 size_t usize, loff_t *off))
1652 EXPORT_SYMBOL_GPL(register_mce_write_callback);
1654 ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
1655 size_t usize, loff_t *off)
1658 return mce_write(filp, ubuf, usize, off);
1663 static const struct file_operations mce_chrdev_ops = {
1664 .open = mce_chrdev_open,
1665 .release = mce_chrdev_release,
1666 .read = mce_chrdev_read,
1667 .write = mce_chrdev_write,
1668 .poll = mce_chrdev_poll,
1669 .unlocked_ioctl = mce_chrdev_ioctl,
1670 .llseek = no_llseek,
1673 static struct miscdevice mce_chrdev_device = {
1680 * mce=off Disables machine check
1681 * mce=no_cmci Disables CMCI
1682 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1683 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1684 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1685 * monarchtimeout is how long to wait for other CPUs on machine
1686 * check, or 0 to not wait
1687 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1688 * mce=nobootlog Don't log MCEs from before booting.
1690 static int __init mcheck_enable(char *str)
1698 if (!strcmp(str, "off"))
1700 else if (!strcmp(str, "no_cmci"))
1701 mce_cmci_disabled = 1;
1702 else if (!strcmp(str, "dont_log_ce"))
1703 mce_dont_log_ce = 1;
1704 else if (!strcmp(str, "ignore_ce"))
1706 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1707 mce_bootlog = (str[0] == 'b');
1708 else if (isdigit(str[0])) {
1709 get_option(&str, &tolerant);
1712 get_option(&str, &monarch_timeout);
1715 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1721 __setup("mce", mcheck_enable);
1723 int __init mcheck_init(void)
1725 mcheck_intel_therm_init();
1731 * mce_syscore: PM support
1735 * Disable machine checks on suspend and shutdown. We can't really handle
1738 static int mce_disable_error_reporting(void)
1742 for (i = 0; i < banks; i++) {
1743 struct mce_bank *b = &mce_banks[i];
1746 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1751 static int mce_syscore_suspend(void)
1753 return mce_disable_error_reporting();
1756 static void mce_syscore_shutdown(void)
1758 mce_disable_error_reporting();
1762 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1763 * Only one CPU is active at this time, the others get re-added later using
1766 static void mce_syscore_resume(void)
1768 __mcheck_cpu_init_generic();
1769 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1772 static struct syscore_ops mce_syscore_ops = {
1773 .suspend = mce_syscore_suspend,
1774 .shutdown = mce_syscore_shutdown,
1775 .resume = mce_syscore_resume,
1779 * mce_sysdev: Sysfs support
1782 static void mce_cpu_restart(void *data)
1784 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1786 __mcheck_cpu_init_generic();
1787 __mcheck_cpu_init_timer();
1790 /* Reinit MCEs after user configuration changes */
1791 static void mce_restart(void)
1793 mce_timer_delete_all();
1794 on_each_cpu(mce_cpu_restart, NULL, 1);
1797 /* Toggle features for corrected errors */
1798 static void mce_disable_cmci(void *data)
1800 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1805 static void mce_enable_ce(void *all)
1807 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1812 __mcheck_cpu_init_timer();
1815 static struct sysdev_class mce_sysdev_class = {
1816 .name = "machinecheck",
1819 DEFINE_PER_CPU(struct sys_device, mce_sysdev);
1822 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1824 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1826 return container_of(attr, struct mce_bank, attr);
1829 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1832 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1835 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1836 const char *buf, size_t size)
1840 if (strict_strtoull(buf, 0, &new) < 0)
1843 attr_to_bank(attr)->ctl = new;
1850 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1852 strcpy(buf, mce_helper);
1854 return strlen(mce_helper) + 1;
1857 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1858 const char *buf, size_t siz)
1862 strncpy(mce_helper, buf, sizeof(mce_helper));
1863 mce_helper[sizeof(mce_helper)-1] = 0;
1864 p = strchr(mce_helper, '\n');
1869 return strlen(mce_helper) + !!p;
1872 static ssize_t set_ignore_ce(struct sys_device *s,
1873 struct sysdev_attribute *attr,
1874 const char *buf, size_t size)
1878 if (strict_strtoull(buf, 0, &new) < 0)
1881 if (mce_ignore_ce ^ !!new) {
1883 /* disable ce features */
1884 mce_timer_delete_all();
1885 on_each_cpu(mce_disable_cmci, NULL, 1);
1888 /* enable ce features */
1890 on_each_cpu(mce_enable_ce, (void *)1, 1);
1896 static ssize_t set_cmci_disabled(struct sys_device *s,
1897 struct sysdev_attribute *attr,
1898 const char *buf, size_t size)
1902 if (strict_strtoull(buf, 0, &new) < 0)
1905 if (mce_cmci_disabled ^ !!new) {
1908 on_each_cpu(mce_disable_cmci, NULL, 1);
1909 mce_cmci_disabled = 1;
1912 mce_cmci_disabled = 0;
1913 on_each_cpu(mce_enable_ce, NULL, 1);
1919 static ssize_t store_int_with_restart(struct sys_device *s,
1920 struct sysdev_attribute *attr,
1921 const char *buf, size_t size)
1923 ssize_t ret = sysdev_store_int(s, attr, buf, size);
1928 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1929 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1930 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1931 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1933 static struct sysdev_ext_attribute attr_check_interval = {
1934 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1935 store_int_with_restart),
1939 static struct sysdev_ext_attribute attr_ignore_ce = {
1940 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1944 static struct sysdev_ext_attribute attr_cmci_disabled = {
1945 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1949 static struct sysdev_attribute *mce_sysdev_attrs[] = {
1950 &attr_tolerant.attr,
1951 &attr_check_interval.attr,
1953 &attr_monarch_timeout.attr,
1954 &attr_dont_log_ce.attr,
1955 &attr_ignore_ce.attr,
1956 &attr_cmci_disabled.attr,
1960 static cpumask_var_t mce_sysdev_initialized;
1962 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1963 static __cpuinit int mce_sysdev_create(unsigned int cpu)
1965 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
1969 if (!mce_available(&boot_cpu_data))
1972 memset(&sysdev->kobj, 0, sizeof(struct kobject));
1974 sysdev->cls = &mce_sysdev_class;
1976 err = sysdev_register(sysdev);
1980 for (i = 0; mce_sysdev_attrs[i]; i++) {
1981 err = sysdev_create_file(sysdev, mce_sysdev_attrs[i]);
1985 for (j = 0; j < banks; j++) {
1986 err = sysdev_create_file(sysdev, &mce_banks[j].attr);
1990 cpumask_set_cpu(cpu, mce_sysdev_initialized);
1995 sysdev_remove_file(sysdev, &mce_banks[j].attr);
1998 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
2000 sysdev_unregister(sysdev);
2005 static __cpuinit void mce_sysdev_remove(unsigned int cpu)
2007 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
2010 if (!cpumask_test_cpu(cpu, mce_sysdev_initialized))
2013 for (i = 0; mce_sysdev_attrs[i]; i++)
2014 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
2016 for (i = 0; i < banks; i++)
2017 sysdev_remove_file(sysdev, &mce_banks[i].attr);
2019 sysdev_unregister(sysdev);
2020 cpumask_clear_cpu(cpu, mce_sysdev_initialized);
2023 /* Make sure there are no machine checks on offlined CPUs. */
2024 static void __cpuinit mce_disable_cpu(void *h)
2026 unsigned long action = *(unsigned long *)h;
2029 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2032 if (!(action & CPU_TASKS_FROZEN))
2034 for (i = 0; i < banks; i++) {
2035 struct mce_bank *b = &mce_banks[i];
2038 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2042 static void __cpuinit mce_reenable_cpu(void *h)
2044 unsigned long action = *(unsigned long *)h;
2047 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2050 if (!(action & CPU_TASKS_FROZEN))
2052 for (i = 0; i < banks; i++) {
2053 struct mce_bank *b = &mce_banks[i];
2056 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2060 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2061 static int __cpuinit
2062 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2064 unsigned int cpu = (unsigned long)hcpu;
2065 struct timer_list *t = &per_cpu(mce_timer, cpu);
2069 case CPU_ONLINE_FROZEN:
2070 mce_sysdev_create(cpu);
2071 if (threshold_cpu_callback)
2072 threshold_cpu_callback(action, cpu);
2075 case CPU_DEAD_FROZEN:
2076 if (threshold_cpu_callback)
2077 threshold_cpu_callback(action, cpu);
2078 mce_sysdev_remove(cpu);
2080 case CPU_DOWN_PREPARE:
2081 case CPU_DOWN_PREPARE_FROZEN:
2083 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2085 case CPU_DOWN_FAILED:
2086 case CPU_DOWN_FAILED_FROZEN:
2087 if (!mce_ignore_ce && check_interval) {
2088 t->expires = round_jiffies(jiffies +
2089 __get_cpu_var(mce_next_interval));
2090 add_timer_on(t, cpu);
2092 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2095 /* intentionally ignoring frozen here */
2096 cmci_rediscover(cpu);
2102 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2103 .notifier_call = mce_cpu_callback,
2106 static __init void mce_init_banks(void)
2110 for (i = 0; i < banks; i++) {
2111 struct mce_bank *b = &mce_banks[i];
2112 struct sysdev_attribute *a = &b->attr;
2114 sysfs_attr_init(&a->attr);
2115 a->attr.name = b->attrname;
2116 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2118 a->attr.mode = 0644;
2119 a->show = show_bank;
2120 a->store = set_bank;
2124 static __init int mcheck_init_device(void)
2129 if (!mce_available(&boot_cpu_data))
2132 zalloc_cpumask_var(&mce_sysdev_initialized, GFP_KERNEL);
2136 err = sysdev_class_register(&mce_sysdev_class);
2140 for_each_online_cpu(i) {
2141 err = mce_sysdev_create(i);
2146 register_syscore_ops(&mce_syscore_ops);
2147 register_hotcpu_notifier(&mce_cpu_notifier);
2149 /* register character device /dev/mcelog */
2150 misc_register(&mce_chrdev_device);
2154 device_initcall(mcheck_init_device);
2157 * Old style boot options parsing. Only for compatibility.
2159 static int __init mcheck_disable(char *str)
2164 __setup("nomce", mcheck_disable);
2166 #ifdef CONFIG_DEBUG_FS
2167 struct dentry *mce_get_debugfs_dir(void)
2169 static struct dentry *dmce;
2172 dmce = debugfs_create_dir("mce", NULL);
2177 static void mce_reset(void)
2180 atomic_set(&mce_fake_paniced, 0);
2181 atomic_set(&mce_executing, 0);
2182 atomic_set(&mce_callin, 0);
2183 atomic_set(&global_nwo, 0);
2186 static int fake_panic_get(void *data, u64 *val)
2192 static int fake_panic_set(void *data, u64 val)
2199 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2200 fake_panic_set, "%llu\n");
2202 static int __init mcheck_debugfs_init(void)
2204 struct dentry *dmce, *ffake_panic;
2206 dmce = mce_get_debugfs_dir();
2209 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2216 late_initcall(mcheck_debugfs_init);