2 * Machine check handler.
4 * K8 parts Copyright 2002,2003 Andi Kleen, SuSE Labs.
5 * Rest from unknown author(s).
6 * 2004 Andi Kleen. Rewrote most of it.
7 * Copyright 2008 Intel Corporation
10 #include <linux/thread_info.h>
11 #include <linux/capability.h>
12 #include <linux/miscdevice.h>
13 #include <linux/ratelimit.h>
14 #include <linux/kallsyms.h>
15 #include <linux/rcupdate.h>
16 #include <linux/kobject.h>
17 #include <linux/uaccess.h>
18 #include <linux/kdebug.h>
19 #include <linux/kernel.h>
20 #include <linux/percpu.h>
21 #include <linux/string.h>
22 #include <linux/sysdev.h>
23 #include <linux/syscore_ops.h>
24 #include <linux/delay.h>
25 #include <linux/ctype.h>
26 #include <linux/sched.h>
27 #include <linux/sysfs.h>
28 #include <linux/types.h>
29 #include <linux/slab.h>
30 #include <linux/init.h>
31 #include <linux/kmod.h>
32 #include <linux/poll.h>
33 #include <linux/nmi.h>
34 #include <linux/cpu.h>
35 #include <linux/smp.h>
38 #include <linux/debugfs.h>
39 #include <linux/irq_work.h>
40 #include <linux/export.h>
42 #include <asm/processor.h>
46 #include "mce-internal.h"
48 static DEFINE_MUTEX(mce_chrdev_read_mutex);
50 #define rcu_dereference_check_mce(p) \
51 rcu_dereference_index_check((p), \
52 rcu_read_lock_sched_held() || \
53 lockdep_is_held(&mce_chrdev_read_mutex))
55 /* sysfs synchronization */
56 static DEFINE_MUTEX(mce_sysfs_mutex);
58 #define CREATE_TRACE_POINTS
59 #include <trace/events/mce.h>
61 int mce_disabled __read_mostly;
63 #define MISC_MCELOG_MINOR 227
65 #define SPINUNIT 100 /* 100ns */
69 DEFINE_PER_CPU(unsigned, mce_exception_count);
73 * 0: always panic on uncorrected errors, log corrected errors
74 * 1: panic or SIGBUS on uncorrected errors, log corrected errors
75 * 2: SIGBUS or log uncorrected errors (if possible), log corrected errors
76 * 3: never panic or SIGBUS, log all errors (for testing only)
78 static int tolerant __read_mostly = 1;
79 static int banks __read_mostly;
80 static int rip_msr __read_mostly;
81 static int mce_bootlog __read_mostly = -1;
82 static int monarch_timeout __read_mostly = -1;
83 static int mce_panic_timeout __read_mostly;
84 static int mce_dont_log_ce __read_mostly;
85 int mce_cmci_disabled __read_mostly;
86 int mce_ignore_ce __read_mostly;
87 int mce_ser __read_mostly;
89 struct mce_bank *mce_banks __read_mostly;
91 /* User mode helper program triggered by machine check event */
92 static unsigned long mce_need_notify;
93 static char mce_helper[128];
94 static char *mce_helper_argv[2] = { mce_helper, NULL };
96 static DECLARE_WAIT_QUEUE_HEAD(mce_chrdev_wait);
98 static DEFINE_PER_CPU(struct mce, mces_seen);
99 static int cpu_missing;
102 * CPU/chipset specific EDAC code can register a notifier call here to print
103 * MCE errors in a human-readable form.
105 ATOMIC_NOTIFIER_HEAD(x86_mce_decoder_chain);
106 EXPORT_SYMBOL_GPL(x86_mce_decoder_chain);
108 /* MCA banks polled by the period polling timer for corrected events */
109 DEFINE_PER_CPU(mce_banks_t, mce_poll_banks) = {
110 [0 ... BITS_TO_LONGS(MAX_NR_BANKS)-1] = ~0UL
113 static DEFINE_PER_CPU(struct work_struct, mce_work);
115 /* Do initial initialization of a struct mce */
116 void mce_setup(struct mce *m)
118 memset(m, 0, sizeof(struct mce));
119 m->cpu = m->extcpu = smp_processor_id();
121 /* We hope get_seconds stays lockless */
122 m->time = get_seconds();
123 m->cpuvendor = boot_cpu_data.x86_vendor;
124 m->cpuid = cpuid_eax(1);
125 m->socketid = cpu_data(m->extcpu).phys_proc_id;
126 m->apicid = cpu_data(m->extcpu).initial_apicid;
127 rdmsrl(MSR_IA32_MCG_CAP, m->mcgcap);
130 DEFINE_PER_CPU(struct mce, injectm);
131 EXPORT_PER_CPU_SYMBOL_GPL(injectm);
134 * Lockless MCE logging infrastructure.
135 * This avoids deadlocks on printk locks without having to break locks. Also
136 * separate MCEs from kernel messages to avoid bogus bug reports.
139 static struct mce_log mcelog = {
140 .signature = MCE_LOG_SIGNATURE,
142 .recordlen = sizeof(struct mce),
145 void mce_log(struct mce *mce)
147 unsigned next, entry;
150 /* Emit the trace record: */
151 trace_mce_record(mce);
153 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, mce);
154 if (ret == NOTIFY_STOP)
160 entry = rcu_dereference_check_mce(mcelog.next);
164 * When the buffer fills up discard new entries.
165 * Assume that the earlier errors are the more
168 if (entry >= MCE_LOG_LEN) {
169 set_bit(MCE_OVERFLOW,
170 (unsigned long *)&mcelog.flags);
173 /* Old left over entry. Skip: */
174 if (mcelog.entry[entry].finished) {
182 if (cmpxchg(&mcelog.next, entry, next) == entry)
185 memcpy(mcelog.entry + entry, mce, sizeof(struct mce));
187 mcelog.entry[entry].finished = 1;
191 set_bit(0, &mce_need_notify);
194 static void print_mce(struct mce *m)
198 pr_emerg(HW_ERR "CPU %d: Machine Check Exception: %Lx Bank %d: %016Lx\n",
199 m->extcpu, m->mcgstatus, m->bank, m->status);
202 pr_emerg(HW_ERR "RIP%s %02x:<%016Lx> ",
203 !(m->mcgstatus & MCG_STATUS_EIPV) ? " !INEXACT!" : "",
206 if (m->cs == __KERNEL_CS)
207 print_symbol("{%s}", m->ip);
211 pr_emerg(HW_ERR "TSC %llx ", m->tsc);
213 pr_cont("ADDR %llx ", m->addr);
215 pr_cont("MISC %llx ", m->misc);
219 * Note this output is parsed by external tools and old fields
220 * should not be changed.
222 pr_emerg(HW_ERR "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x microcode %x\n",
223 m->cpuvendor, m->cpuid, m->time, m->socketid, m->apicid,
224 cpu_data(m->extcpu).microcode);
227 * Print out human-readable details about the MCE error,
228 * (if the CPU has an implementation for that)
230 ret = atomic_notifier_call_chain(&x86_mce_decoder_chain, 0, m);
231 if (ret == NOTIFY_STOP)
234 pr_emerg_ratelimited(HW_ERR "Run the above through 'mcelog --ascii'\n");
237 #define PANIC_TIMEOUT 5 /* 5 seconds */
239 static atomic_t mce_paniced;
241 static int fake_panic;
242 static atomic_t mce_fake_paniced;
244 /* Panic in progress. Enable interrupts and wait for final IPI */
245 static void wait_for_panic(void)
247 long timeout = PANIC_TIMEOUT*USEC_PER_SEC;
251 while (timeout-- > 0)
253 if (panic_timeout == 0)
254 panic_timeout = mce_panic_timeout;
255 panic("Panicing machine check CPU died");
258 static void mce_panic(char *msg, struct mce *final, char *exp)
264 * Make sure only one CPU runs in machine check panic
266 if (atomic_inc_return(&mce_paniced) > 1)
273 /* Don't log too much for fake panic */
274 if (atomic_inc_return(&mce_fake_paniced) > 1)
277 /* First print corrected ones that are still unlogged */
278 for (i = 0; i < MCE_LOG_LEN; i++) {
279 struct mce *m = &mcelog.entry[i];
280 if (!(m->status & MCI_STATUS_VAL))
282 if (!(m->status & MCI_STATUS_UC)) {
285 apei_err = apei_write_mce(m);
288 /* Now print uncorrected but with the final one last */
289 for (i = 0; i < MCE_LOG_LEN; i++) {
290 struct mce *m = &mcelog.entry[i];
291 if (!(m->status & MCI_STATUS_VAL))
293 if (!(m->status & MCI_STATUS_UC))
295 if (!final || memcmp(m, final, sizeof(struct mce))) {
298 apei_err = apei_write_mce(m);
304 apei_err = apei_write_mce(final);
307 pr_emerg(HW_ERR "Some CPUs didn't answer in synchronization\n");
309 pr_emerg(HW_ERR "Machine check: %s\n", exp);
311 if (panic_timeout == 0)
312 panic_timeout = mce_panic_timeout;
315 pr_emerg(HW_ERR "Fake kernel panic: %s\n", msg);
318 /* Support code for software error injection */
320 static int msr_to_offset(u32 msr)
322 unsigned bank = __this_cpu_read(injectm.bank);
325 return offsetof(struct mce, ip);
326 if (msr == MSR_IA32_MCx_STATUS(bank))
327 return offsetof(struct mce, status);
328 if (msr == MSR_IA32_MCx_ADDR(bank))
329 return offsetof(struct mce, addr);
330 if (msr == MSR_IA32_MCx_MISC(bank))
331 return offsetof(struct mce, misc);
332 if (msr == MSR_IA32_MCG_STATUS)
333 return offsetof(struct mce, mcgstatus);
337 /* MSR access wrappers used for error injection */
338 static u64 mce_rdmsrl(u32 msr)
342 if (__this_cpu_read(injectm.finished)) {
343 int offset = msr_to_offset(msr);
347 return *(u64 *)((char *)&__get_cpu_var(injectm) + offset);
350 if (rdmsrl_safe(msr, &v)) {
351 WARN_ONCE(1, "mce: Unable to read msr %d!\n", msr);
353 * Return zero in case the access faulted. This should
354 * not happen normally but can happen if the CPU does
355 * something weird, or if the code is buggy.
363 static void mce_wrmsrl(u32 msr, u64 v)
365 if (__this_cpu_read(injectm.finished)) {
366 int offset = msr_to_offset(msr);
369 *(u64 *)((char *)&__get_cpu_var(injectm) + offset) = v;
376 * Collect all global (w.r.t. this processor) status about this machine
377 * check into our "mce" struct so that we can use it later to assess
378 * the severity of the problem as we read per-bank specific details.
380 static inline void mce_gather_info(struct mce *m, struct pt_regs *regs)
384 m->mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
387 * Get the address of the instruction at the time of
388 * the machine check error.
390 if (m->mcgstatus & (MCG_STATUS_RIPV|MCG_STATUS_EIPV)) {
395 * When in VM86 mode make the cs look like ring 3
396 * always. This is a lie, but it's better than passing
397 * the additional vm86 bit around everywhere.
399 if (v8086_mode(regs))
402 /* Use accurate RIP reporting if available. */
404 m->ip = mce_rdmsrl(rip_msr);
409 * Simple lockless ring to communicate PFNs from the exception handler with the
410 * process context work function. This is vastly simplified because there's
411 * only a single reader and a single writer.
413 #define MCE_RING_SIZE 16 /* we use one entry less */
416 unsigned short start;
418 unsigned long ring[MCE_RING_SIZE];
420 static DEFINE_PER_CPU(struct mce_ring, mce_ring);
422 /* Runs with CPU affinity in workqueue */
423 static int mce_ring_empty(void)
425 struct mce_ring *r = &__get_cpu_var(mce_ring);
427 return r->start == r->end;
430 static int mce_ring_get(unsigned long *pfn)
437 r = &__get_cpu_var(mce_ring);
438 if (r->start == r->end)
440 *pfn = r->ring[r->start];
441 r->start = (r->start + 1) % MCE_RING_SIZE;
448 /* Always runs in MCE context with preempt off */
449 static int mce_ring_add(unsigned long pfn)
451 struct mce_ring *r = &__get_cpu_var(mce_ring);
454 next = (r->end + 1) % MCE_RING_SIZE;
455 if (next == r->start)
457 r->ring[r->end] = pfn;
463 int mce_available(struct cpuinfo_x86 *c)
467 return cpu_has(c, X86_FEATURE_MCE) && cpu_has(c, X86_FEATURE_MCA);
470 static void mce_schedule_work(void)
472 if (!mce_ring_empty()) {
473 struct work_struct *work = &__get_cpu_var(mce_work);
474 if (!work_pending(work))
479 DEFINE_PER_CPU(struct irq_work, mce_irq_work);
481 static void mce_irq_work_cb(struct irq_work *entry)
487 static void mce_report_event(struct pt_regs *regs)
489 if (regs->flags & (X86_VM_MASK|X86_EFLAGS_IF)) {
492 * Triggering the work queue here is just an insurance
493 * policy in case the syscall exit notify handler
494 * doesn't run soon enough or ends up running on the
495 * wrong CPU (can happen when audit sleeps)
501 irq_work_queue(&__get_cpu_var(mce_irq_work));
504 DEFINE_PER_CPU(unsigned, mce_poll_count);
507 * Poll for corrected events or events that happened before reset.
508 * Those are just logged through /dev/mcelog.
510 * This is executed in standard interrupt context.
512 * Note: spec recommends to panic for fatal unsignalled
513 * errors here. However this would be quite problematic --
514 * we would need to reimplement the Monarch handling and
515 * it would mess up the exclusion between exception handler
516 * and poll hander -- * so we skip this for now.
517 * These cases should not happen anyways, or only when the CPU
518 * is already totally * confused. In this case it's likely it will
519 * not fully execute the machine check handler either.
521 void machine_check_poll(enum mcp_flags flags, mce_banks_t *b)
526 percpu_inc(mce_poll_count);
528 mce_gather_info(&m, NULL);
530 for (i = 0; i < banks; i++) {
531 if (!mce_banks[i].ctl || !test_bit(i, *b))
540 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
541 if (!(m.status & MCI_STATUS_VAL))
545 * Uncorrected or signalled events are handled by the exception
546 * handler when it is enabled, so don't process those here.
548 * TBD do the same check for MCI_STATUS_EN here?
550 if (!(flags & MCP_UC) &&
551 (m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)))
554 if (m.status & MCI_STATUS_MISCV)
555 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
556 if (m.status & MCI_STATUS_ADDRV)
557 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
559 if (!(flags & MCP_TIMESTAMP))
562 * Don't get the IP here because it's unlikely to
563 * have anything to do with the actual error location.
565 if (!(flags & MCP_DONTLOG) && !mce_dont_log_ce)
569 * Clear state for this bank.
571 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
575 * Don't clear MCG_STATUS here because it's only defined for
581 EXPORT_SYMBOL_GPL(machine_check_poll);
584 * Do a quick check if any of the events requires a panic.
585 * This decides if we keep the events around or clear them.
587 static int mce_no_way_out(struct mce *m, char **msg)
591 for (i = 0; i < banks; i++) {
592 m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
593 if (mce_severity(m, tolerant, msg) >= MCE_PANIC_SEVERITY)
600 * Variable to establish order between CPUs while scanning.
601 * Each CPU spins initially until executing is equal its number.
603 static atomic_t mce_executing;
606 * Defines order of CPUs on entry. First CPU becomes Monarch.
608 static atomic_t mce_callin;
611 * Check if a timeout waiting for other CPUs happened.
613 static int mce_timed_out(u64 *t)
616 * The others already did panic for some reason.
617 * Bail out like in a timeout.
618 * rmb() to tell the compiler that system_state
619 * might have been modified by someone else.
622 if (atomic_read(&mce_paniced))
624 if (!monarch_timeout)
626 if ((s64)*t < SPINUNIT) {
627 /* CHECKME: Make panic default for 1 too? */
629 mce_panic("Timeout synchronizing machine check over CPUs",
636 touch_nmi_watchdog();
641 * The Monarch's reign. The Monarch is the CPU who entered
642 * the machine check handler first. It waits for the others to
643 * raise the exception too and then grades them. When any
644 * error is fatal panic. Only then let the others continue.
646 * The other CPUs entering the MCE handler will be controlled by the
647 * Monarch. They are called Subjects.
649 * This way we prevent any potential data corruption in a unrecoverable case
650 * and also makes sure always all CPU's errors are examined.
652 * Also this detects the case of a machine check event coming from outer
653 * space (not detected by any CPUs) In this case some external agent wants
654 * us to shut down, so panic too.
656 * The other CPUs might still decide to panic if the handler happens
657 * in a unrecoverable place, but in this case the system is in a semi-stable
658 * state and won't corrupt anything by itself. It's ok to let the others
659 * continue for a bit first.
661 * All the spin loops have timeouts; when a timeout happens a CPU
662 * typically elects itself to be Monarch.
664 static void mce_reign(void)
667 struct mce *m = NULL;
668 int global_worst = 0;
673 * This CPU is the Monarch and the other CPUs have run
674 * through their handlers.
675 * Grade the severity of the errors of all the CPUs.
677 for_each_possible_cpu(cpu) {
678 int severity = mce_severity(&per_cpu(mces_seen, cpu), tolerant,
680 if (severity > global_worst) {
682 global_worst = severity;
683 m = &per_cpu(mces_seen, cpu);
688 * Cannot recover? Panic here then.
689 * This dumps all the mces in the log buffer and stops the
692 if (m && global_worst >= MCE_PANIC_SEVERITY && tolerant < 3)
693 mce_panic("Fatal Machine check", m, msg);
696 * For UC somewhere we let the CPU who detects it handle it.
697 * Also must let continue the others, otherwise the handling
698 * CPU could deadlock on a lock.
702 * No machine check event found. Must be some external
703 * source or one CPU is hung. Panic.
705 if (global_worst <= MCE_KEEP_SEVERITY && tolerant < 3)
706 mce_panic("Machine check from unknown source", NULL, NULL);
709 * Now clear all the mces_seen so that they don't reappear on
712 for_each_possible_cpu(cpu)
713 memset(&per_cpu(mces_seen, cpu), 0, sizeof(struct mce));
716 static atomic_t global_nwo;
719 * Start of Monarch synchronization. This waits until all CPUs have
720 * entered the exception handler and then determines if any of them
721 * saw a fatal event that requires panic. Then it executes them
722 * in the entry order.
723 * TBD double check parallel CPU hotunplug
725 static int mce_start(int *no_way_out)
728 int cpus = num_online_cpus();
729 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
734 atomic_add(*no_way_out, &global_nwo);
736 * global_nwo should be updated before mce_callin
739 order = atomic_inc_return(&mce_callin);
744 while (atomic_read(&mce_callin) != cpus) {
745 if (mce_timed_out(&timeout)) {
746 atomic_set(&global_nwo, 0);
753 * mce_callin should be read before global_nwo
759 * Monarch: Starts executing now, the others wait.
761 atomic_set(&mce_executing, 1);
764 * Subject: Now start the scanning loop one by one in
765 * the original callin order.
766 * This way when there are any shared banks it will be
767 * only seen by one CPU before cleared, avoiding duplicates.
769 while (atomic_read(&mce_executing) < order) {
770 if (mce_timed_out(&timeout)) {
771 atomic_set(&global_nwo, 0);
779 * Cache the global no_way_out state.
781 *no_way_out = atomic_read(&global_nwo);
787 * Synchronize between CPUs after main scanning loop.
788 * This invokes the bulk of the Monarch processing.
790 static int mce_end(int order)
793 u64 timeout = (u64)monarch_timeout * NSEC_PER_USEC;
801 * Allow others to run.
803 atomic_inc(&mce_executing);
806 /* CHECKME: Can this race with a parallel hotplug? */
807 int cpus = num_online_cpus();
810 * Monarch: Wait for everyone to go through their scanning
813 while (atomic_read(&mce_executing) <= cpus) {
814 if (mce_timed_out(&timeout))
824 * Subject: Wait for Monarch to finish.
826 while (atomic_read(&mce_executing) != 0) {
827 if (mce_timed_out(&timeout))
833 * Don't reset anything. That's done by the Monarch.
839 * Reset all global state.
842 atomic_set(&global_nwo, 0);
843 atomic_set(&mce_callin, 0);
847 * Let others run again.
849 atomic_set(&mce_executing, 0);
854 * Check if the address reported by the CPU is in a format we can parse.
855 * It would be possible to add code for most other cases, but all would
856 * be somewhat complicated (e.g. segment offset would require an instruction
857 * parser). So only support physical addresses up to page granuality for now.
859 static int mce_usable_address(struct mce *m)
861 if (!(m->status & MCI_STATUS_MISCV) || !(m->status & MCI_STATUS_ADDRV))
863 if (MCI_MISC_ADDR_LSB(m->misc) > PAGE_SHIFT)
865 if (MCI_MISC_ADDR_MODE(m->misc) != MCI_MISC_ADDR_PHYS)
870 static void mce_clear_state(unsigned long *toclear)
874 for (i = 0; i < banks; i++) {
875 if (test_bit(i, toclear))
876 mce_wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
881 * The actual machine check handler. This only handles real
882 * exceptions when something got corrupted coming in through int 18.
884 * This is executed in NMI context not subject to normal locking rules. This
885 * implies that most kernel services cannot be safely used. Don't even
886 * think about putting a printk in there!
888 * On Intel systems this is entered on all CPUs in parallel through
889 * MCE broadcast. However some CPUs might be broken beyond repair,
890 * so be always careful when synchronizing with others.
892 void do_machine_check(struct pt_regs *regs, long error_code)
894 struct mce m, *final;
899 * Establish sequential order between the CPUs entering the machine
904 * If no_way_out gets set, there is no safe way to recover from this
905 * MCE. If tolerant is cranked up, we'll try anyway.
909 * If kill_it gets set, there might be a way to recover from this
913 DECLARE_BITMAP(toclear, MAX_NR_BANKS);
914 char *msg = "Unknown";
916 atomic_inc(&mce_entry);
918 percpu_inc(mce_exception_count);
923 mce_gather_info(&m, regs);
925 final = &__get_cpu_var(mces_seen);
928 no_way_out = mce_no_way_out(&m, &msg);
933 * When no restart IP must always kill or panic.
935 if (!(m.mcgstatus & MCG_STATUS_RIPV))
939 * Go through all the banks in exclusion of the other CPUs.
940 * This way we don't report duplicated events on shared banks
941 * because the first one to see it will clear it.
943 order = mce_start(&no_way_out);
944 for (i = 0; i < banks; i++) {
945 __clear_bit(i, toclear);
946 if (!mce_banks[i].ctl)
953 m.status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));
954 if ((m.status & MCI_STATUS_VAL) == 0)
958 * Non uncorrected or non signaled errors are handled by
959 * machine_check_poll. Leave them alone, unless this panics.
961 if (!(m.status & (mce_ser ? MCI_STATUS_S : MCI_STATUS_UC)) &&
966 * Set taint even when machine check was not enabled.
968 add_taint(TAINT_MACHINE_CHECK);
970 severity = mce_severity(&m, tolerant, NULL);
973 * When machine check was for corrected handler don't touch,
974 * unless we're panicing.
976 if (severity == MCE_KEEP_SEVERITY && !no_way_out)
978 __set_bit(i, toclear);
979 if (severity == MCE_NO_SEVERITY) {
981 * Machine check event was not enabled. Clear, but
988 * Kill on action required.
990 if (severity == MCE_AR_SEVERITY)
993 if (m.status & MCI_STATUS_MISCV)
994 m.misc = mce_rdmsrl(MSR_IA32_MCx_MISC(i));
995 if (m.status & MCI_STATUS_ADDRV)
996 m.addr = mce_rdmsrl(MSR_IA32_MCx_ADDR(i));
999 * Action optional error. Queue address for later processing.
1000 * When the ring overflows we just ignore the AO error.
1001 * RED-PEN add some logging mechanism when
1002 * usable_address or mce_add_ring fails.
1003 * RED-PEN don't ignore overflow for tolerant == 0
1005 if (severity == MCE_AO_SEVERITY && mce_usable_address(&m))
1006 mce_ring_add(m.addr >> PAGE_SHIFT);
1010 if (severity > worst) {
1017 mce_clear_state(toclear);
1020 * Do most of the synchronization with other CPUs.
1021 * When there's any problem use only local no_way_out state.
1023 if (mce_end(order) < 0)
1024 no_way_out = worst >= MCE_PANIC_SEVERITY;
1027 * If we have decided that we just CAN'T continue, and the user
1028 * has not set tolerant to an insane level, give up and die.
1030 * This is mainly used in the case when the system doesn't
1031 * support MCE broadcasting or it has been disabled.
1033 if (no_way_out && tolerant < 3)
1034 mce_panic("Fatal machine check on current CPU", final, msg);
1037 * If the error seems to be unrecoverable, something should be
1038 * done. Try to kill as little as possible. If we can kill just
1039 * one task, do that. If the user has set the tolerance very
1040 * high, don't try to do anything at all.
1043 if (kill_it && tolerant < 3)
1044 force_sig(SIGBUS, current);
1046 /* notify userspace ASAP */
1047 set_thread_flag(TIF_MCE_NOTIFY);
1050 mce_report_event(regs);
1051 mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
1053 atomic_dec(&mce_entry);
1056 EXPORT_SYMBOL_GPL(do_machine_check);
1058 /* dummy to break dependency. actual code is in mm/memory-failure.c */
1059 void __attribute__((weak)) memory_failure(unsigned long pfn, int vector)
1061 printk(KERN_ERR "Action optional memory failure at %lx ignored\n", pfn);
1065 * Called after mce notification in process context. This code
1066 * is allowed to sleep. Call the high level VM handler to process
1067 * any corrupted pages.
1068 * Assume that the work queue code only calls this one at a time
1070 * Note we don't disable preemption, so this code might run on the wrong
1071 * CPU. In this case the event is picked up by the scheduled work queue.
1072 * This is merely a fast path to expedite processing in some common
1075 void mce_notify_process(void)
1079 while (mce_ring_get(&pfn))
1080 memory_failure(pfn, MCE_VECTOR);
1083 static void mce_process_work(struct work_struct *dummy)
1085 mce_notify_process();
1088 #ifdef CONFIG_X86_MCE_INTEL
1090 * mce_log_therm_throt_event - Logs the thermal throttling event to mcelog
1091 * @cpu: The CPU on which the event occurred.
1092 * @status: Event status information
1094 * This function should be called by the thermal interrupt after the
1095 * event has been processed and the decision was made to log the event
1098 * The status parameter will be saved to the 'status' field of 'struct mce'
1099 * and historically has been the register value of the
1100 * MSR_IA32_THERMAL_STATUS (Intel) msr.
1102 void mce_log_therm_throt_event(__u64 status)
1107 m.bank = MCE_THERMAL_BANK;
1111 #endif /* CONFIG_X86_MCE_INTEL */
1114 * Periodic polling timer for "silent" machine check errors. If the
1115 * poller finds an MCE, poll 2x faster. When the poller finds no more
1116 * errors, poll 2x slower (up to check_interval seconds).
1118 static int check_interval = 5 * 60; /* 5 minutes */
1120 static DEFINE_PER_CPU(int, mce_next_interval); /* in jiffies */
1121 static DEFINE_PER_CPU(struct timer_list, mce_timer);
1123 static void mce_start_timer(unsigned long data)
1125 struct timer_list *t = &per_cpu(mce_timer, data);
1128 WARN_ON(smp_processor_id() != data);
1130 if (mce_available(__this_cpu_ptr(&cpu_info))) {
1131 machine_check_poll(MCP_TIMESTAMP,
1132 &__get_cpu_var(mce_poll_banks));
1136 * Alert userspace if needed. If we logged an MCE, reduce the
1137 * polling interval, otherwise increase the polling interval.
1139 n = &__get_cpu_var(mce_next_interval);
1140 if (mce_notify_irq())
1141 *n = max(*n/2, HZ/100);
1143 *n = min(*n*2, (int)round_jiffies_relative(check_interval*HZ));
1145 t->expires = jiffies + *n;
1146 add_timer_on(t, smp_processor_id());
1149 /* Must not be called in IRQ context where del_timer_sync() can deadlock */
1150 static void mce_timer_delete_all(void)
1154 for_each_online_cpu(cpu)
1155 del_timer_sync(&per_cpu(mce_timer, cpu));
1158 static void mce_do_trigger(struct work_struct *work)
1160 call_usermodehelper(mce_helper, mce_helper_argv, NULL, UMH_NO_WAIT);
1163 static DECLARE_WORK(mce_trigger_work, mce_do_trigger);
1166 * Notify the user(s) about new machine check events.
1167 * Can be called from interrupt context, but not from machine check/NMI
1170 int mce_notify_irq(void)
1172 /* Not more than two messages every minute */
1173 static DEFINE_RATELIMIT_STATE(ratelimit, 60*HZ, 2);
1175 clear_thread_flag(TIF_MCE_NOTIFY);
1177 if (test_and_clear_bit(0, &mce_need_notify)) {
1178 /* wake processes polling /dev/mcelog */
1179 wake_up_interruptible(&mce_chrdev_wait);
1182 * There is no risk of missing notifications because
1183 * work_pending is always cleared before the function is
1186 if (mce_helper[0] && !work_pending(&mce_trigger_work))
1187 schedule_work(&mce_trigger_work);
1189 if (__ratelimit(&ratelimit))
1190 pr_info(HW_ERR "Machine check events logged\n");
1196 EXPORT_SYMBOL_GPL(mce_notify_irq);
1198 static int __cpuinit __mcheck_cpu_mce_banks_init(void)
1202 mce_banks = kzalloc(banks * sizeof(struct mce_bank), GFP_KERNEL);
1205 for (i = 0; i < banks; i++) {
1206 struct mce_bank *b = &mce_banks[i];
1215 * Initialize Machine Checks for a CPU.
1217 static int __cpuinit __mcheck_cpu_cap_init(void)
1222 rdmsrl(MSR_IA32_MCG_CAP, cap);
1224 b = cap & MCG_BANKCNT_MASK;
1226 printk(KERN_INFO "mce: CPU supports %d MCE banks\n", b);
1228 if (b > MAX_NR_BANKS) {
1230 "MCE: Using only %u machine check banks out of %u\n",
1235 /* Don't support asymmetric configurations today */
1236 WARN_ON(banks != 0 && b != banks);
1239 int err = __mcheck_cpu_mce_banks_init();
1245 /* Use accurate RIP reporting if available. */
1246 if ((cap & MCG_EXT_P) && MCG_EXT_CNT(cap) >= 9)
1247 rip_msr = MSR_IA32_MCG_EIP;
1249 if (cap & MCG_SER_P)
1255 static void __mcheck_cpu_init_generic(void)
1257 mce_banks_t all_banks;
1262 * Log the machine checks left over from the previous reset.
1264 bitmap_fill(all_banks, MAX_NR_BANKS);
1265 machine_check_poll(MCP_UC|(!mce_bootlog ? MCP_DONTLOG : 0), &all_banks);
1267 set_in_cr4(X86_CR4_MCE);
1269 rdmsrl(MSR_IA32_MCG_CAP, cap);
1270 if (cap & MCG_CTL_P)
1271 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
1273 for (i = 0; i < banks; i++) {
1274 struct mce_bank *b = &mce_banks[i];
1278 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
1279 wrmsrl(MSR_IA32_MCx_STATUS(i), 0);
1283 /* Add per CPU specific workarounds here */
1284 static int __cpuinit __mcheck_cpu_apply_quirks(struct cpuinfo_x86 *c)
1286 if (c->x86_vendor == X86_VENDOR_UNKNOWN) {
1287 pr_info("MCE: unknown CPU type - not enabling MCE support.\n");
1291 /* This should be disabled by the BIOS, but isn't always */
1292 if (c->x86_vendor == X86_VENDOR_AMD) {
1293 if (c->x86 == 15 && banks > 4) {
1295 * disable GART TBL walk error reporting, which
1296 * trips off incorrectly with the IOMMU & 3ware
1299 clear_bit(10, (unsigned long *)&mce_banks[4].ctl);
1301 if (c->x86 <= 17 && mce_bootlog < 0) {
1303 * Lots of broken BIOS around that don't clear them
1304 * by default and leave crap in there. Don't log:
1309 * Various K7s with broken bank 0 around. Always disable
1312 if (c->x86 == 6 && banks > 0)
1313 mce_banks[0].ctl = 0;
1316 if (c->x86_vendor == X86_VENDOR_INTEL) {
1318 * SDM documents that on family 6 bank 0 should not be written
1319 * because it aliases to another special BIOS controlled
1321 * But it's not aliased anymore on model 0x1a+
1322 * Don't ignore bank 0 completely because there could be a
1323 * valid event later, merely don't write CTL0.
1326 if (c->x86 == 6 && c->x86_model < 0x1A && banks > 0)
1327 mce_banks[0].init = 0;
1330 * All newer Intel systems support MCE broadcasting. Enable
1331 * synchronization with a one second timeout.
1333 if ((c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xe)) &&
1334 monarch_timeout < 0)
1335 monarch_timeout = USEC_PER_SEC;
1338 * There are also broken BIOSes on some Pentium M and
1341 if (c->x86 == 6 && c->x86_model <= 13 && mce_bootlog < 0)
1344 if (monarch_timeout < 0)
1345 monarch_timeout = 0;
1346 if (mce_bootlog != 0)
1347 mce_panic_timeout = 30;
1352 static int __cpuinit __mcheck_cpu_ancient_init(struct cpuinfo_x86 *c)
1357 switch (c->x86_vendor) {
1358 case X86_VENDOR_INTEL:
1359 intel_p5_mcheck_init(c);
1362 case X86_VENDOR_CENTAUR:
1363 winchip_mcheck_init(c);
1371 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
1373 switch (c->x86_vendor) {
1374 case X86_VENDOR_INTEL:
1375 mce_intel_feature_init(c);
1377 case X86_VENDOR_AMD:
1378 mce_amd_feature_init(c);
1385 static void __mcheck_cpu_init_timer(void)
1387 struct timer_list *t = &__get_cpu_var(mce_timer);
1388 int *n = &__get_cpu_var(mce_next_interval);
1390 setup_timer(t, mce_start_timer, smp_processor_id());
1395 *n = check_interval * HZ;
1398 t->expires = round_jiffies(jiffies + *n);
1399 add_timer_on(t, smp_processor_id());
1402 /* Handle unconfigured int18 (should never happen) */
1403 static void unexpected_machine_check(struct pt_regs *regs, long error_code)
1405 printk(KERN_ERR "CPU#%d: Unexpected int18 (Machine Check).\n",
1406 smp_processor_id());
1409 /* Call the installed machine check handler for this CPU setup. */
1410 void (*machine_check_vector)(struct pt_regs *, long error_code) =
1411 unexpected_machine_check;
1413 void do_mce(struct pt_regs *regs, long error_code)
1415 machine_check_vector(regs, error_code);
1419 * Called for each booted CPU to set up machine checks.
1420 * Must be called with preempt off:
1422 void __cpuinit mcheck_cpu_init(struct cpuinfo_x86 *c)
1427 if (__mcheck_cpu_ancient_init(c))
1430 if (!mce_available(c))
1433 if (__mcheck_cpu_cap_init() < 0 || __mcheck_cpu_apply_quirks(c) < 0) {
1438 machine_check_vector = do_machine_check;
1440 __mcheck_cpu_init_generic();
1441 __mcheck_cpu_init_vendor(c);
1442 __mcheck_cpu_init_timer();
1443 INIT_WORK(&__get_cpu_var(mce_work), mce_process_work);
1444 init_irq_work(&__get_cpu_var(mce_irq_work), &mce_irq_work_cb);
1448 * mce_chrdev: Character device /dev/mcelog to read and clear the MCE log.
1451 static DEFINE_SPINLOCK(mce_chrdev_state_lock);
1452 static int mce_chrdev_open_count; /* #times opened */
1453 static int mce_chrdev_open_exclu; /* already open exclusive? */
1455 static int mce_chrdev_open(struct inode *inode, struct file *file)
1457 spin_lock(&mce_chrdev_state_lock);
1459 if (mce_chrdev_open_exclu ||
1460 (mce_chrdev_open_count && (file->f_flags & O_EXCL))) {
1461 spin_unlock(&mce_chrdev_state_lock);
1466 if (file->f_flags & O_EXCL)
1467 mce_chrdev_open_exclu = 1;
1468 mce_chrdev_open_count++;
1470 spin_unlock(&mce_chrdev_state_lock);
1472 return nonseekable_open(inode, file);
1475 static int mce_chrdev_release(struct inode *inode, struct file *file)
1477 spin_lock(&mce_chrdev_state_lock);
1479 mce_chrdev_open_count--;
1480 mce_chrdev_open_exclu = 0;
1482 spin_unlock(&mce_chrdev_state_lock);
1487 static void collect_tscs(void *data)
1489 unsigned long *cpu_tsc = (unsigned long *)data;
1491 rdtscll(cpu_tsc[smp_processor_id()]);
1494 static int mce_apei_read_done;
1496 /* Collect MCE record of previous boot in persistent storage via APEI ERST. */
1497 static int __mce_read_apei(char __user **ubuf, size_t usize)
1503 if (usize < sizeof(struct mce))
1506 rc = apei_read_mce(&m, &record_id);
1507 /* Error or no more MCE record */
1509 mce_apei_read_done = 1;
1513 if (copy_to_user(*ubuf, &m, sizeof(struct mce)))
1516 * In fact, we should have cleared the record after that has
1517 * been flushed to the disk or sent to network in
1518 * /sbin/mcelog, but we have no interface to support that now,
1519 * so just clear it to avoid duplication.
1521 rc = apei_clear_mce(record_id);
1523 mce_apei_read_done = 1;
1526 *ubuf += sizeof(struct mce);
1531 static ssize_t mce_chrdev_read(struct file *filp, char __user *ubuf,
1532 size_t usize, loff_t *off)
1534 char __user *buf = ubuf;
1535 unsigned long *cpu_tsc;
1536 unsigned prev, next;
1539 cpu_tsc = kmalloc(nr_cpu_ids * sizeof(long), GFP_KERNEL);
1543 mutex_lock(&mce_chrdev_read_mutex);
1545 if (!mce_apei_read_done) {
1546 err = __mce_read_apei(&buf, usize);
1547 if (err || buf != ubuf)
1551 next = rcu_dereference_check_mce(mcelog.next);
1553 /* Only supports full reads right now */
1555 if (*off != 0 || usize < MCE_LOG_LEN*sizeof(struct mce))
1561 for (i = prev; i < next; i++) {
1562 unsigned long start = jiffies;
1563 struct mce *m = &mcelog.entry[i];
1565 while (!m->finished) {
1566 if (time_after_eq(jiffies, start + 2)) {
1567 memset(m, 0, sizeof(*m));
1573 err |= copy_to_user(buf, m, sizeof(*m));
1579 memset(mcelog.entry + prev, 0,
1580 (next - prev) * sizeof(struct mce));
1582 next = cmpxchg(&mcelog.next, prev, 0);
1583 } while (next != prev);
1585 synchronize_sched();
1588 * Collect entries that were still getting written before the
1591 on_each_cpu(collect_tscs, cpu_tsc, 1);
1593 for (i = next; i < MCE_LOG_LEN; i++) {
1594 struct mce *m = &mcelog.entry[i];
1596 if (m->finished && m->tsc < cpu_tsc[m->cpu]) {
1597 err |= copy_to_user(buf, m, sizeof(*m));
1600 memset(m, 0, sizeof(*m));
1608 mutex_unlock(&mce_chrdev_read_mutex);
1611 return err ? err : buf - ubuf;
1614 static unsigned int mce_chrdev_poll(struct file *file, poll_table *wait)
1616 poll_wait(file, &mce_chrdev_wait, wait);
1617 if (rcu_access_index(mcelog.next))
1618 return POLLIN | POLLRDNORM;
1619 if (!mce_apei_read_done && apei_check_mce())
1620 return POLLIN | POLLRDNORM;
1624 static long mce_chrdev_ioctl(struct file *f, unsigned int cmd,
1627 int __user *p = (int __user *)arg;
1629 if (!capable(CAP_SYS_ADMIN))
1633 case MCE_GET_RECORD_LEN:
1634 return put_user(sizeof(struct mce), p);
1635 case MCE_GET_LOG_LEN:
1636 return put_user(MCE_LOG_LEN, p);
1637 case MCE_GETCLEAR_FLAGS: {
1641 flags = mcelog.flags;
1642 } while (cmpxchg(&mcelog.flags, flags, 0) != flags);
1644 return put_user(flags, p);
1651 static ssize_t (*mce_write)(struct file *filp, const char __user *ubuf,
1652 size_t usize, loff_t *off);
1654 void register_mce_write_callback(ssize_t (*fn)(struct file *filp,
1655 const char __user *ubuf,
1656 size_t usize, loff_t *off))
1660 EXPORT_SYMBOL_GPL(register_mce_write_callback);
1662 ssize_t mce_chrdev_write(struct file *filp, const char __user *ubuf,
1663 size_t usize, loff_t *off)
1666 return mce_write(filp, ubuf, usize, off);
1671 static const struct file_operations mce_chrdev_ops = {
1672 .open = mce_chrdev_open,
1673 .release = mce_chrdev_release,
1674 .read = mce_chrdev_read,
1675 .write = mce_chrdev_write,
1676 .poll = mce_chrdev_poll,
1677 .unlocked_ioctl = mce_chrdev_ioctl,
1678 .llseek = no_llseek,
1681 static struct miscdevice mce_chrdev_device = {
1688 * mce=off Disables machine check
1689 * mce=no_cmci Disables CMCI
1690 * mce=dont_log_ce Clears corrected events silently, no log created for CEs.
1691 * mce=ignore_ce Disables polling and CMCI, corrected events are not cleared.
1692 * mce=TOLERANCELEVEL[,monarchtimeout] (number, see above)
1693 * monarchtimeout is how long to wait for other CPUs on machine
1694 * check, or 0 to not wait
1695 * mce=bootlog Log MCEs from before booting. Disabled by default on AMD.
1696 * mce=nobootlog Don't log MCEs from before booting.
1698 static int __init mcheck_enable(char *str)
1706 if (!strcmp(str, "off"))
1708 else if (!strcmp(str, "no_cmci"))
1709 mce_cmci_disabled = 1;
1710 else if (!strcmp(str, "dont_log_ce"))
1711 mce_dont_log_ce = 1;
1712 else if (!strcmp(str, "ignore_ce"))
1714 else if (!strcmp(str, "bootlog") || !strcmp(str, "nobootlog"))
1715 mce_bootlog = (str[0] == 'b');
1716 else if (isdigit(str[0])) {
1717 get_option(&str, &tolerant);
1720 get_option(&str, &monarch_timeout);
1723 printk(KERN_INFO "mce argument %s ignored. Please use /sys\n",
1729 __setup("mce", mcheck_enable);
1731 int __init mcheck_init(void)
1733 mcheck_intel_therm_init();
1739 * mce_syscore: PM support
1743 * Disable machine checks on suspend and shutdown. We can't really handle
1746 static int mce_disable_error_reporting(void)
1750 for (i = 0; i < banks; i++) {
1751 struct mce_bank *b = &mce_banks[i];
1754 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
1759 static int mce_syscore_suspend(void)
1761 return mce_disable_error_reporting();
1764 static void mce_syscore_shutdown(void)
1766 mce_disable_error_reporting();
1770 * On resume clear all MCE state. Don't want to see leftovers from the BIOS.
1771 * Only one CPU is active at this time, the others get re-added later using
1774 static void mce_syscore_resume(void)
1776 __mcheck_cpu_init_generic();
1777 __mcheck_cpu_init_vendor(__this_cpu_ptr(&cpu_info));
1780 static struct syscore_ops mce_syscore_ops = {
1781 .suspend = mce_syscore_suspend,
1782 .shutdown = mce_syscore_shutdown,
1783 .resume = mce_syscore_resume,
1787 * mce_sysdev: Sysfs support
1790 static void mce_cpu_restart(void *data)
1792 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1794 __mcheck_cpu_init_generic();
1795 __mcheck_cpu_init_timer();
1798 /* Reinit MCEs after user configuration changes */
1799 static void mce_restart(void)
1801 mce_timer_delete_all();
1802 on_each_cpu(mce_cpu_restart, NULL, 1);
1805 /* Toggle features for corrected errors */
1806 static void mce_disable_cmci(void *data)
1808 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1813 static void mce_enable_ce(void *all)
1815 if (!mce_available(__this_cpu_ptr(&cpu_info)))
1820 __mcheck_cpu_init_timer();
1823 static struct sysdev_class mce_sysdev_class = {
1824 .name = "machinecheck",
1827 DEFINE_PER_CPU(struct sys_device, mce_sysdev);
1830 void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
1832 static inline struct mce_bank *attr_to_bank(struct sysdev_attribute *attr)
1834 return container_of(attr, struct mce_bank, attr);
1837 static ssize_t show_bank(struct sys_device *s, struct sysdev_attribute *attr,
1840 return sprintf(buf, "%llx\n", attr_to_bank(attr)->ctl);
1843 static ssize_t set_bank(struct sys_device *s, struct sysdev_attribute *attr,
1844 const char *buf, size_t size)
1848 if (strict_strtoull(buf, 0, &new) < 0)
1851 attr_to_bank(attr)->ctl = new;
1858 show_trigger(struct sys_device *s, struct sysdev_attribute *attr, char *buf)
1860 strcpy(buf, mce_helper);
1862 return strlen(mce_helper) + 1;
1865 static ssize_t set_trigger(struct sys_device *s, struct sysdev_attribute *attr,
1866 const char *buf, size_t siz)
1870 strncpy(mce_helper, buf, sizeof(mce_helper));
1871 mce_helper[sizeof(mce_helper)-1] = 0;
1872 p = strchr(mce_helper, '\n');
1877 return strlen(mce_helper) + !!p;
1880 static ssize_t set_ignore_ce(struct sys_device *s,
1881 struct sysdev_attribute *attr,
1882 const char *buf, size_t size)
1886 if (strict_strtoull(buf, 0, &new) < 0)
1889 mutex_lock(&mce_sysfs_mutex);
1890 if (mce_ignore_ce ^ !!new) {
1892 /* disable ce features */
1893 mce_timer_delete_all();
1894 on_each_cpu(mce_disable_cmci, NULL, 1);
1897 /* enable ce features */
1899 on_each_cpu(mce_enable_ce, (void *)1, 1);
1902 mutex_unlock(&mce_sysfs_mutex);
1907 static ssize_t set_cmci_disabled(struct sys_device *s,
1908 struct sysdev_attribute *attr,
1909 const char *buf, size_t size)
1913 if (strict_strtoull(buf, 0, &new) < 0)
1916 mutex_lock(&mce_sysfs_mutex);
1917 if (mce_cmci_disabled ^ !!new) {
1920 on_each_cpu(mce_disable_cmci, NULL, 1);
1921 mce_cmci_disabled = 1;
1924 mce_cmci_disabled = 0;
1925 on_each_cpu(mce_enable_ce, NULL, 1);
1928 mutex_unlock(&mce_sysfs_mutex);
1933 static ssize_t store_int_with_restart(struct sys_device *s,
1934 struct sysdev_attribute *attr,
1935 const char *buf, size_t size)
1937 unsigned long old_check_interval = check_interval;
1938 ssize_t ret = sysdev_store_ulong(s, attr, buf, size);
1940 if (check_interval == old_check_interval)
1943 if (check_interval < 1)
1946 mutex_lock(&mce_sysfs_mutex);
1948 mutex_unlock(&mce_sysfs_mutex);
1953 static SYSDEV_ATTR(trigger, 0644, show_trigger, set_trigger);
1954 static SYSDEV_INT_ATTR(tolerant, 0644, tolerant);
1955 static SYSDEV_INT_ATTR(monarch_timeout, 0644, monarch_timeout);
1956 static SYSDEV_INT_ATTR(dont_log_ce, 0644, mce_dont_log_ce);
1958 static struct sysdev_ext_attribute attr_check_interval = {
1959 _SYSDEV_ATTR(check_interval, 0644, sysdev_show_int,
1960 store_int_with_restart),
1964 static struct sysdev_ext_attribute attr_ignore_ce = {
1965 _SYSDEV_ATTR(ignore_ce, 0644, sysdev_show_int, set_ignore_ce),
1969 static struct sysdev_ext_attribute attr_cmci_disabled = {
1970 _SYSDEV_ATTR(cmci_disabled, 0644, sysdev_show_int, set_cmci_disabled),
1974 static struct sysdev_attribute *mce_sysdev_attrs[] = {
1975 &attr_tolerant.attr,
1976 &attr_check_interval.attr,
1978 &attr_monarch_timeout.attr,
1979 &attr_dont_log_ce.attr,
1980 &attr_ignore_ce.attr,
1981 &attr_cmci_disabled.attr,
1985 static cpumask_var_t mce_sysdev_initialized;
1987 /* Per cpu sysdev init. All of the cpus still share the same ctrl bank: */
1988 static __cpuinit int mce_sysdev_create(unsigned int cpu)
1990 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
1994 if (!mce_available(&boot_cpu_data))
1997 memset(&sysdev->kobj, 0, sizeof(struct kobject));
1999 sysdev->cls = &mce_sysdev_class;
2001 err = sysdev_register(sysdev);
2005 for (i = 0; mce_sysdev_attrs[i]; i++) {
2006 err = sysdev_create_file(sysdev, mce_sysdev_attrs[i]);
2010 for (j = 0; j < banks; j++) {
2011 err = sysdev_create_file(sysdev, &mce_banks[j].attr);
2015 cpumask_set_cpu(cpu, mce_sysdev_initialized);
2020 sysdev_remove_file(sysdev, &mce_banks[j].attr);
2023 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
2025 sysdev_unregister(sysdev);
2030 static __cpuinit void mce_sysdev_remove(unsigned int cpu)
2032 struct sys_device *sysdev = &per_cpu(mce_sysdev, cpu);
2035 if (!cpumask_test_cpu(cpu, mce_sysdev_initialized))
2038 for (i = 0; mce_sysdev_attrs[i]; i++)
2039 sysdev_remove_file(sysdev, mce_sysdev_attrs[i]);
2041 for (i = 0; i < banks; i++)
2042 sysdev_remove_file(sysdev, &mce_banks[i].attr);
2044 sysdev_unregister(sysdev);
2045 cpumask_clear_cpu(cpu, mce_sysdev_initialized);
2048 /* Make sure there are no machine checks on offlined CPUs. */
2049 static void __cpuinit mce_disable_cpu(void *h)
2051 unsigned long action = *(unsigned long *)h;
2054 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2057 if (!(action & CPU_TASKS_FROZEN))
2059 for (i = 0; i < banks; i++) {
2060 struct mce_bank *b = &mce_banks[i];
2063 wrmsrl(MSR_IA32_MCx_CTL(i), 0);
2067 static void __cpuinit mce_reenable_cpu(void *h)
2069 unsigned long action = *(unsigned long *)h;
2072 if (!mce_available(__this_cpu_ptr(&cpu_info)))
2075 if (!(action & CPU_TASKS_FROZEN))
2077 for (i = 0; i < banks; i++) {
2078 struct mce_bank *b = &mce_banks[i];
2081 wrmsrl(MSR_IA32_MCx_CTL(i), b->ctl);
2085 /* Get notified when a cpu comes on/off. Be hotplug friendly. */
2086 static int __cpuinit
2087 mce_cpu_callback(struct notifier_block *nfb, unsigned long action, void *hcpu)
2089 unsigned int cpu = (unsigned long)hcpu;
2090 struct timer_list *t = &per_cpu(mce_timer, cpu);
2094 case CPU_ONLINE_FROZEN:
2095 mce_sysdev_create(cpu);
2096 if (threshold_cpu_callback)
2097 threshold_cpu_callback(action, cpu);
2100 case CPU_DEAD_FROZEN:
2101 if (threshold_cpu_callback)
2102 threshold_cpu_callback(action, cpu);
2103 mce_sysdev_remove(cpu);
2105 case CPU_DOWN_PREPARE:
2106 case CPU_DOWN_PREPARE_FROZEN:
2108 smp_call_function_single(cpu, mce_disable_cpu, &action, 1);
2110 case CPU_DOWN_FAILED:
2111 case CPU_DOWN_FAILED_FROZEN:
2112 if (!mce_ignore_ce && check_interval) {
2113 t->expires = round_jiffies(jiffies +
2114 __get_cpu_var(mce_next_interval));
2115 add_timer_on(t, cpu);
2117 smp_call_function_single(cpu, mce_reenable_cpu, &action, 1);
2120 /* intentionally ignoring frozen here */
2121 cmci_rediscover(cpu);
2127 static struct notifier_block mce_cpu_notifier __cpuinitdata = {
2128 .notifier_call = mce_cpu_callback,
2131 static __init void mce_init_banks(void)
2135 for (i = 0; i < banks; i++) {
2136 struct mce_bank *b = &mce_banks[i];
2137 struct sysdev_attribute *a = &b->attr;
2139 sysfs_attr_init(&a->attr);
2140 a->attr.name = b->attrname;
2141 snprintf(b->attrname, ATTR_LEN, "bank%d", i);
2143 a->attr.mode = 0644;
2144 a->show = show_bank;
2145 a->store = set_bank;
2149 static __init int mcheck_init_device(void)
2154 if (!mce_available(&boot_cpu_data))
2157 zalloc_cpumask_var(&mce_sysdev_initialized, GFP_KERNEL);
2161 err = sysdev_class_register(&mce_sysdev_class);
2165 for_each_online_cpu(i) {
2166 err = mce_sysdev_create(i);
2171 register_syscore_ops(&mce_syscore_ops);
2172 register_hotcpu_notifier(&mce_cpu_notifier);
2174 /* register character device /dev/mcelog */
2175 misc_register(&mce_chrdev_device);
2179 device_initcall(mcheck_init_device);
2182 * Old style boot options parsing. Only for compatibility.
2184 static int __init mcheck_disable(char *str)
2189 __setup("nomce", mcheck_disable);
2191 #ifdef CONFIG_DEBUG_FS
2192 struct dentry *mce_get_debugfs_dir(void)
2194 static struct dentry *dmce;
2197 dmce = debugfs_create_dir("mce", NULL);
2202 static void mce_reset(void)
2205 atomic_set(&mce_fake_paniced, 0);
2206 atomic_set(&mce_executing, 0);
2207 atomic_set(&mce_callin, 0);
2208 atomic_set(&global_nwo, 0);
2211 static int fake_panic_get(void *data, u64 *val)
2217 static int fake_panic_set(void *data, u64 val)
2224 DEFINE_SIMPLE_ATTRIBUTE(fake_panic_fops, fake_panic_get,
2225 fake_panic_set, "%llu\n");
2227 static int __init mcheck_debugfs_init(void)
2229 struct dentry *dmce, *ffake_panic;
2231 dmce = mce_get_debugfs_dir();
2234 ffake_panic = debugfs_create_file("fake_panic", 0444, dmce, NULL,
2241 late_initcall(mcheck_debugfs_init);