arch/x86/kernel/cpu/cpufreq/longhaul.c

   1 /*
   2  *  (C) 2001-2004  Dave Jones. <davej@redhat.com>
   3  *  (C) 2002  Padraig Brady. <padraig@antefacto.com>
   4  *
   5  *  Licensed under the terms of the GNU GPL License version 2.
   6  *  Based upon datasheets & sample CPUs kindly provided by VIA.
   7  *
   8  *  VIA have currently 3 different versions of Longhaul.
   9  *  Version 1 (Longhaul) uses the BCR2 MSR at 0x1147.
  10  *   It is present only in Samuel 1 (C5A), Samuel 2 (C5B) stepping 0.
  11  *  Version 2 of longhaul is backward compatible with v1, but adds
  12  *   LONGHAUL MSR for purpose of both frequency and voltage scaling.
  13  *   Present in Samuel 2 (steppings 1-7 only) (C5B), and Ezra (C5C).
  14  *  Version 3 of longhaul got renamed to Powersaver and redesigned
  15  *   to use only the POWERSAVER MSR at 0x110a.
  16  *   It is present in Ezra-T (C5M), Nehemiah (C5X) and above.
  17  *   It's pretty much the same feature wise to longhaul v2, though
  18  *   there is provision for scaling FSB too, but this doesn't work
  19  *   too well in practice so we don't even try to use this.
  20  *
  21  *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/moduleparam.h>
  27 #include <linux/init.h>
  28 #include <linux/cpufreq.h>
  29 #include <linux/pci.h>
  30 #include <linux/slab.h>
  31 #include <linux/string.h>
  32 #include <linux/delay.h>
  33
  34 #include <asm/msr.h>
  35 #include <asm/timex.h>
  36 #include <asm/io.h>
  37 #include <asm/acpi.h>
  38 #include <linux/acpi.h>
  39 #include <acpi/processor.h>
  40
  41 #include "longhaul.h"
  42
  43 #define PFX "longhaul: "
  44
  45 #define TYPE_LONGHAUL_V1        1
  46 #define TYPE_LONGHAUL_V2        2
  47 #define TYPE_POWERSAVER         3
  48
  49 #define CPU_SAMUEL      1
  50 #define CPU_SAMUEL2     2
  51 #define CPU_EZRA        3
  52 #define CPU_EZRA_T      4
  53 #define CPU_NEHEMIAH    5
  54 #define CPU_NEHEMIAH_C  6
  55
  56 /* Flags */
  57 #define USE_ACPI_C3             (1 << 1)
  58 #define USE_NORTHBRIDGE         (1 << 2)
  59
  60 static int cpu_model;
  61 static unsigned int numscales=16;
  62 static unsigned int fsb;
  63
  64 static const struct mV_pos *vrm_mV_table;
  65 static const unsigned char *mV_vrm_table;
  66
  67 static unsigned int highest_speed, lowest_speed; /* kHz */
  68 static unsigned int minmult, maxmult;
  69 static int can_scale_voltage;
  70 static struct acpi_processor *pr = NULL;
  71 static struct acpi_processor_cx *cx = NULL;
  72 static u32 acpi_regs_addr;
  73 static u8 longhaul_flags;
  74 static unsigned int longhaul_index;
  75
  76 /* Module parameters */
  77 static int scale_voltage;
  78 static int disable_acpi_c3;
  79 static int revid_errata;
  80
  81 #define dprintk(msg...) cpufreq_debug_printk(CPUFREQ_DEBUG_DRIVER, "longhaul", msg)
  82
  83
  84 /* Clock ratios multiplied by 10 */
  85 static int clock_ratio[32];
  86 static int eblcr_table[32];
  87 static int longhaul_version;
  88 static struct cpufreq_frequency_table *longhaul_table;
  89
  90 #ifdef CONFIG_CPU_FREQ_DEBUG
  91 static char speedbuffer[8];
  92
  93 static char *print_speed(int speed)
  94 {
  95         if (speed < 1000) {
  96                 snprintf(speedbuffer, sizeof(speedbuffer),"%dMHz", speed);
  97                 return speedbuffer;
  98         }
  99
 100         if (speed%1000 == 0)
 101                 snprintf(speedbuffer, sizeof(speedbuffer),
 102                         "%dGHz", speed/1000);
 103         else
 104                 snprintf(speedbuffer, sizeof(speedbuffer),
 105                         "%d.%dGHz", speed/1000, (speed%1000)/100);
 106
 107         return speedbuffer;
 108 }
 109 #endif
 110
 111
 112 static unsigned int calc_speed(int mult)
 113 {
 114         int khz;
 115         khz = (mult/10)*fsb;
 116         if (mult%10)
 117                 khz += fsb/2;
 118         khz *= 1000;
 119         return khz;
 120 }
 121
 122
 123 static int longhaul_get_cpu_mult(void)
 124 {
 125         unsigned long invalue=0,lo, hi;
 126
 127         rdmsr (MSR_IA32_EBL_CR_POWERON, lo, hi);
 128         invalue = (lo & (1<<22|1<<23|1<<24|1<<25)) >>22;
 129         if (longhaul_version==TYPE_LONGHAUL_V2 || longhaul_version==TYPE_POWERSAVER) {
 130                 if (lo & (1<<27))
 131                         invalue+=16;
 132         }
 133         return eblcr_table[invalue];
 134 }
 135
 136 /* For processor with BCR2 MSR */
 137
 138 static void do_longhaul1(unsigned int clock_ratio_index)
 139 {
 140         union msr_bcr2 bcr2;
 141
 142         rdmsrl(MSR_VIA_BCR2, bcr2.val);
 143         /* Enable software clock multiplier */
 144         bcr2.bits.ESOFTBF = 1;
 145         bcr2.bits.CLOCKMUL = clock_ratio_index & 0xff;
 146
 147         /* Sync to timer tick */
 148         safe_halt();
 149         /* Change frequency on next halt or sleep */
 150         wrmsrl(MSR_VIA_BCR2, bcr2.val);
 151         /* Invoke transition */
 152         ACPI_FLUSH_CPU_CACHE();
 153         halt();
 154
 155         /* Disable software clock multiplier */
 156         local_irq_disable();
 157         rdmsrl(MSR_VIA_BCR2, bcr2.val);
 158         bcr2.bits.ESOFTBF = 0;
 159         wrmsrl(MSR_VIA_BCR2, bcr2.val);
 160 }
 161
 162 /* For processor with Longhaul MSR */
 163
 164 static void do_powersaver(int cx_address, unsigned int clock_ratio_index,
 165                           unsigned int dir)
 166 {
 167         union msr_longhaul longhaul;
 168         u32 t;
 169
 170         rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 171         /* Setup new frequency */
 172         if (!revid_errata)
 173                 longhaul.bits.RevisionKey = longhaul.bits.RevisionID;
 174         else
 175                 longhaul.bits.RevisionKey = 0;
 176         longhaul.bits.SoftBusRatio = clock_ratio_index & 0xf;
 177         longhaul.bits.SoftBusRatio4 = (clock_ratio_index & 0x10) >> 4;
 178         /* Setup new voltage */
 179         if (can_scale_voltage)
 180                 longhaul.bits.SoftVID = (clock_ratio_index >> 8) & 0x1f;
 181         /* Sync to timer tick */
 182         safe_halt();
 183         /* Raise voltage if necessary */
 184         if (can_scale_voltage && dir) {
 185                 longhaul.bits.EnableSoftVID = 1;
 186                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 187                 /* Change voltage */
 188                 if (!cx_address) {
 189                         ACPI_FLUSH_CPU_CACHE();
 190                         halt();
 191                 } else {
 192                         ACPI_FLUSH_CPU_CACHE();
 193                         /* Invoke C3 */
 194                         inb(cx_address);
 195                         /* Dummy op - must do something useless after P_LVL3
 196                          * read */
 197                         t = inl(acpi_gbl_FADT.xpm_timer_block.address);
 198                 }
 199                 longhaul.bits.EnableSoftVID = 0;
 200                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 201         }
 202
 203         /* Change frequency on next halt or sleep */
 204         longhaul.bits.EnableSoftBusRatio = 1;
 205         wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 206         if (!cx_address) {
 207                 ACPI_FLUSH_CPU_CACHE();
 208                 halt();
 209         } else {
 210                 ACPI_FLUSH_CPU_CACHE();
 211                 /* Invoke C3 */
 212                 inb(cx_address);
 213                 /* Dummy op - must do something useless after P_LVL3 read */
 214                 t = inl(acpi_gbl_FADT.xpm_timer_block.address);
 215         }
 216         /* Disable bus ratio bit */
 217         longhaul.bits.EnableSoftBusRatio = 0;
 218         wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 219
 220         /* Reduce voltage if necessary */
 221         if (can_scale_voltage && !dir) {
 222                 longhaul.bits.EnableSoftVID = 1;
 223                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 224                 /* Change voltage */
 225                 if (!cx_address) {
 226                         ACPI_FLUSH_CPU_CACHE();
 227                         halt();
 228                 } else {
 229                         ACPI_FLUSH_CPU_CACHE();
 230                         /* Invoke C3 */
 231                         inb(cx_address);
 232                         /* Dummy op - must do something useless after P_LVL3
 233                          * read */
 234                         t = inl(acpi_gbl_FADT.xpm_timer_block.address);
 235                 }
 236                 longhaul.bits.EnableSoftVID = 0;
 237                 wrmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 238         }
 239 }
 240
 241 /**
 242  * longhaul_set_cpu_frequency()
 243  * @clock_ratio_index : bitpattern of the new multiplier.
 244  *
 245  * Sets a new clock ratio.
 246  */
 247
 248 static void longhaul_setstate(unsigned int table_index)
 249 {
 250         unsigned int clock_ratio_index;
 251         int speed, mult;
 252         struct cpufreq_freqs freqs;
 253         unsigned long flags;
 254         unsigned int pic1_mask, pic2_mask;
 255         u16 bm_status = 0;
 256         u32 bm_timeout = 1000;
 257         unsigned int dir = 0;
 258
 259         clock_ratio_index = longhaul_table[table_index].index;
 260         /* Safety precautions */
 261         mult = clock_ratio[clock_ratio_index & 0x1f];
 262         if (mult == -1)
 263                 return;
 264         speed = calc_speed(mult);
 265         if ((speed > highest_speed) || (speed < lowest_speed))
 266                 return;
 267         /* Voltage transition before frequency transition? */
 268         if (can_scale_voltage && longhaul_index < table_index)
 269                 dir = 1;
 270
 271         freqs.old = calc_speed(longhaul_get_cpu_mult());
 272         freqs.new = speed;
 273         freqs.cpu = 0; /* longhaul.c is UP only driver */
 274
 275         cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
 276
 277         dprintk ("Setting to FSB:%dMHz Mult:%d.%dx (%s)\n",
 278                         fsb, mult/10, mult%10, print_speed(speed/1000));
 279 retry_loop:
 280         preempt_disable();
 281         local_irq_save(flags);
 282
 283         pic2_mask = inb(0xA1);
 284         pic1_mask = inb(0x21);  /* works on C3. save mask. */
 285         outb(0xFF,0xA1);        /* Overkill */
 286         outb(0xFE,0x21);        /* TMR0 only */
 287
 288         /* Wait while PCI bus is busy. */
 289         if (acpi_regs_addr && (longhaul_flags & USE_NORTHBRIDGE
 290             || ((pr != NULL) && pr->flags.bm_control))) {
 291                 bm_status = inw(acpi_regs_addr);
 292                 bm_status &= 1 << 4;
 293                 while (bm_status && bm_timeout) {
 294                         outw(1 << 4, acpi_regs_addr);
 295                         bm_timeout--;
 296                         bm_status = inw(acpi_regs_addr);
 297                         bm_status &= 1 << 4;
 298                 }
 299         }
 300
 301         if (longhaul_flags & USE_NORTHBRIDGE) {
 302                 /* Disable AGP and PCI arbiters */
 303                 outb(3, 0x22);
 304         } else if ((pr != NULL) && pr->flags.bm_control) {
 305                 /* Disable bus master arbitration */
 306                 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1);
 307         }
 308         switch (longhaul_version) {
 309
 310         /*
 311          * Longhaul v1. (Samuel[C5A] and Samuel2 stepping 0[C5B])
 312          * Software controlled multipliers only.
 313          */
 314         case TYPE_LONGHAUL_V1:
 315                 do_longhaul1(clock_ratio_index);
 316                 break;
 317
 318         /*
 319          * Longhaul v2 appears in Samuel2 Steppings 1->7 [C5B] and Ezra [C5C]
 320          *
 321          * Longhaul v3 (aka Powersaver). (Ezra-T [C5M] & Nehemiah [C5N])
 322          * Nehemiah can do FSB scaling too, but this has never been proven
 323          * to work in practice.
 324          */
 325         case TYPE_LONGHAUL_V2:
 326         case TYPE_POWERSAVER:
 327                 if (longhaul_flags & USE_ACPI_C3) {
 328                         /* Don't allow wakeup */
 329                         acpi_write_bit_register(ACPI_BITREG_BUS_MASTER_RLD, 0);
 330                         do_powersaver(cx->address, clock_ratio_index, dir);
 331                 } else {
 332                         do_powersaver(0, clock_ratio_index, dir);
 333                 }
 334                 break;
 335         }
 336
 337         if (longhaul_flags & USE_NORTHBRIDGE) {
 338                 /* Enable arbiters */
 339                 outb(0, 0x22);
 340         } else if ((pr != NULL) && pr->flags.bm_control) {
 341                 /* Enable bus master arbitration */
 342                 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0);
 343         }
 344         outb(pic2_mask,0xA1);   /* restore mask */
 345         outb(pic1_mask,0x21);
 346
 347         local_irq_restore(flags);
 348         preempt_enable();
 349
 350         freqs.new = calc_speed(longhaul_get_cpu_mult());
 351         /* Check if requested frequency is set. */
 352         if (unlikely(freqs.new != speed)) {
 353                 printk(KERN_INFO PFX "Failed to set requested frequency!\n");
 354                 /* Revision ID = 1 but processor is expecting revision key
 355                  * equal to 0. Jumpers at the bottom of processor will change
 356                  * multiplier and FSB, but will not change bits in Longhaul
 357                  * MSR nor enable voltage scaling. */
 358                 if (!revid_errata) {
 359                         printk(KERN_INFO PFX "Enabling \"Ignore Revision ID\" "
 360                                                 "option.\n");
 361                         revid_errata = 1;
 362                         msleep(200);
 363                         goto retry_loop;
 364                 }
 365                 /* Why ACPI C3 sometimes doesn't work is a mystery for me.
 366                  * But it does happen. Processor is entering ACPI C3 state,
 367                  * but it doesn't change frequency. I tried poking various
 368                  * bits in northbridge registers, but without success. */
 369                 if (longhaul_flags & USE_ACPI_C3) {
 370                         printk(KERN_INFO PFX "Disabling ACPI C3 support.\n");
 371                         longhaul_flags &= ~USE_ACPI_C3;
 372                         if (revid_errata) {
 373                                 printk(KERN_INFO PFX "Disabling \"Ignore "
 374                                                 "Revision ID\" option.\n");
 375                                 revid_errata = 0;
 376                         }
 377                         msleep(200);
 378                         goto retry_loop;
 379                 }
 380                 /* This shouldn't happen. Longhaul ver. 2 was reported not
 381                  * working on processors without voltage scaling, but with
 382                  * RevID = 1. RevID errata will make things right. Just
 383                  * to be 100% sure. */
 384                 if (longhaul_version == TYPE_LONGHAUL_V2) {
 385                         printk(KERN_INFO PFX "Switching to Longhaul ver. 1\n");
 386                         longhaul_version = TYPE_LONGHAUL_V1;
 387                         msleep(200);
 388                         goto retry_loop;
 389                 }
 390         }
 391         /* Report true CPU frequency */
 392         cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
 393
 394         if (!bm_timeout)
 395                 printk(KERN_INFO PFX "Warning: Timeout while waiting for idle PCI bus.\n");
 396 }
 397
 398 /*
 399  * Centaur decided to make life a little more tricky.
 400  * Only longhaul v1 is allowed to read EBLCR BSEL[0:1].
 401  * Samuel2 and above have to try and guess what the FSB is.
 402  * We do this by assuming we booted at maximum multiplier, and interpolate
 403  * between that value multiplied by possible FSBs and cpu_mhz which
 404  * was calculated at boot time. Really ugly, but no other way to do this.
 405  */
 406
 407 #define ROUNDING        0xf
 408
 409 static int guess_fsb(int mult)
 410 {
 411         int speed = cpu_khz / 1000;
 412         int i;
 413         int speeds[] = { 666, 1000, 1333, 2000 };
 414         int f_max, f_min;
 415
 416         for (i = 0; i < 4; i++) {
 417                 f_max = ((speeds[i] * mult) + 50) / 100;
 418                 f_max += (ROUNDING / 2);
 419                 f_min = f_max - ROUNDING;
 420                 if ((speed <= f_max) && (speed >= f_min))
 421                         return speeds[i] / 10;
 422         }
 423         return 0;
 424 }
 425
 426
 427 static int __init longhaul_get_ranges(void)
 428 {
 429         unsigned int i, j, k = 0;
 430         unsigned int ratio;
 431         int mult;
 432
 433         /* Get current frequency */
 434         mult = longhaul_get_cpu_mult();
 435         if (mult == -1) {
 436                 printk(KERN_INFO PFX "Invalid (reserved) multiplier!\n");
 437                 return -EINVAL;
 438         }
 439         fsb = guess_fsb(mult);
 440         if (fsb == 0) {
 441                 printk(KERN_INFO PFX "Invalid (reserved) FSB!\n");
 442                 return -EINVAL;
 443         }
 444         /* Get max multiplier - as we always did.
 445          * Longhaul MSR is usefull only when voltage scaling is enabled.
 446          * C3 is booting at max anyway. */
 447         maxmult = mult;
 448         /* Get min multiplier */
 449         switch (cpu_model) {
 450         case CPU_NEHEMIAH:
 451                 minmult = 50;
 452                 break;
 453         case CPU_NEHEMIAH_C:
 454                 minmult = 40;
 455                 break;
 456         default:
 457                 minmult = 30;
 458                 break;
 459         }
 460
 461         dprintk ("MinMult:%d.%dx MaxMult:%d.%dx\n",
 462                  minmult/10, minmult%10, maxmult/10, maxmult%10);
 463
 464         highest_speed = calc_speed(maxmult);
 465         lowest_speed = calc_speed(minmult);
 466         dprintk ("FSB:%dMHz  Lowest speed: %s   Highest speed:%s\n", fsb,
 467                  print_speed(lowest_speed/1000),
 468                  print_speed(highest_speed/1000));
 469
 470         if (lowest_speed == highest_speed) {
 471                 printk (KERN_INFO PFX "highestspeed == lowest, aborting.\n");
 472                 return -EINVAL;
 473         }
 474         if (lowest_speed > highest_speed) {
 475                 printk (KERN_INFO PFX "nonsense! lowest (%d > %d) !\n",
 476                         lowest_speed, highest_speed);
 477                 return -EINVAL;
 478         }
 479
 480         longhaul_table = kmalloc((numscales + 1) * sizeof(struct cpufreq_frequency_table), GFP_KERNEL);
 481         if(!longhaul_table)
 482                 return -ENOMEM;
 483
 484         for (j = 0; j < numscales; j++) {
 485                 ratio = clock_ratio[j];
 486                 if (ratio == -1)
 487                         continue;
 488                 if (ratio > maxmult || ratio < minmult)
 489                         continue;
 490                 longhaul_table[k].frequency = calc_speed(ratio);
 491                 longhaul_table[k].index = j;
 492                 k++;
 493         }
 494         if (k <= 1) {
 495                 kfree(longhaul_table);
 496                 return -ENODEV;
 497         }
 498         /* Sort */
 499         for (j = 0; j < k - 1; j++) {
 500                 unsigned int min_f, min_i;
 501                 min_f = longhaul_table[j].frequency;
 502                 min_i = j;
 503                 for (i = j + 1; i < k; i++) {
 504                         if (longhaul_table[i].frequency < min_f) {
 505                                 min_f = longhaul_table[i].frequency;
 506                                 min_i = i;
 507                         }
 508                 }
 509                 if (min_i != j) {
 510                         unsigned int temp;
 511                         temp = longhaul_table[j].frequency;
 512                         longhaul_table[j].frequency = longhaul_table[min_i].frequency;
 513                         longhaul_table[min_i].frequency = temp;
 514                         temp = longhaul_table[j].index;
 515                         longhaul_table[j].index = longhaul_table[min_i].index;
 516                         longhaul_table[min_i].index = temp;
 517                 }
 518         }
 519
 520         longhaul_table[k].frequency = CPUFREQ_TABLE_END;
 521
 522         /* Find index we are running on */
 523         for (j = 0; j < k; j++) {
 524                 if (clock_ratio[longhaul_table[j].index & 0x1f] == mult) {
 525                         longhaul_index = j;
 526                         break;
 527                 }
 528         }
 529         return 0;
 530 }
 531
 532
 533 static void __init longhaul_setup_voltagescaling(void)
 534 {
 535         union msr_longhaul longhaul;
 536         struct mV_pos minvid, maxvid, vid;
 537         unsigned int j, speed, pos, kHz_step, numvscales;
 538         int min_vid_speed;
 539
 540         rdmsrl(MSR_VIA_LONGHAUL, longhaul.val);
 541         if (!(longhaul.bits.RevisionID & 1)) {
 542                 printk(KERN_INFO PFX "Voltage scaling not supported by CPU.\n");
 543                 return;
 544         }
 545
 546         if (!longhaul.bits.VRMRev) {
 547                 printk(KERN_INFO PFX "VRM 8.5\n");
 548                 vrm_mV_table = &vrm85_mV[0];
 549                 mV_vrm_table = &mV_vrm85[0];
 550         } else {
 551                 printk(KERN_INFO PFX "Mobile VRM\n");
 552                 if (cpu_model < CPU_NEHEMIAH)
 553                         return;
 554                 vrm_mV_table = &mobilevrm_mV[0];
 555                 mV_vrm_table = &mV_mobilevrm[0];
 556         }
 557
 558         minvid = vrm_mV_table[longhaul.bits.MinimumVID];
 559         maxvid = vrm_mV_table[longhaul.bits.MaximumVID];
 560
 561         if (minvid.mV == 0 || maxvid.mV == 0 || minvid.mV > maxvid.mV) {
 562                 printk (KERN_INFO PFX "Bogus values Min:%d.%03d Max:%d.%03d. "
 563                                         "Voltage scaling disabled.\n",
 564                                         minvid.mV/1000, minvid.mV%1000, maxvid.mV/1000, maxvid.mV%1000);
 565                 return;
 566         }
 567
 568         if (minvid.mV == maxvid.mV) {
 569                 printk (KERN_INFO PFX "Claims to support voltage scaling but min & max are "
 570                                 "both %d.%03d. Voltage scaling disabled\n",
 571                                 maxvid.mV/1000, maxvid.mV%1000);
 572                 return;
 573         }
 574
 575         /* How many voltage steps */
 576         numvscales = maxvid.pos - minvid.pos + 1;
 577         printk(KERN_INFO PFX
 578                 "Max VID=%d.%03d  "
 579                 "Min VID=%d.%03d, "
 580                 "%d possible voltage scales\n",
 581                 maxvid.mV/1000, maxvid.mV%1000,
 582                 minvid.mV/1000, minvid.mV%1000,
 583                 numvscales);
 584
 585         /* Calculate max frequency at min voltage */
 586         j = longhaul.bits.MinMHzBR;
 587         if (longhaul.bits.MinMHzBR4)
 588                 j += 16;
 589         min_vid_speed = eblcr_table[j];
 590         if (min_vid_speed == -1)
 591                 return;
 592         switch (longhaul.bits.MinMHzFSB) {
 593         case 0:
 594                 min_vid_speed *= 13333;
 595                 break;
 596         case 1:
 597                 min_vid_speed *= 10000;
 598                 break;
 599         case 3:
 600                 min_vid_speed *= 6666;
 601                 break;
 602         default:
 603                 return;
 604                 break;
 605         }
 606         if (min_vid_speed >= highest_speed)
 607                 return;
 608         /* Calculate kHz for one voltage step */
 609         kHz_step = (highest_speed - min_vid_speed) / numvscales;
 610
 611         j = 0;
 612         while (longhaul_table[j].frequency != CPUFREQ_TABLE_END) {
 613                 speed = longhaul_table[j].frequency;
 614                 if (speed > min_vid_speed)
 615                         pos = (speed - min_vid_speed) / kHz_step + minvid.pos;
 616                 else
 617                         pos = minvid.pos;
 618                 longhaul_table[j].index |= mV_vrm_table[pos] << 8;
 619                 vid = vrm_mV_table[mV_vrm_table[pos]];
 620                 printk(KERN_INFO PFX "f: %d kHz, index: %d, vid: %d mV\n", speed, j, vid.mV);
 621                 j++;
 622         }
 623
 624         can_scale_voltage = 1;
 625         printk(KERN_INFO PFX "Voltage scaling enabled.\n");
 626 }
 627
 628
 629 static int longhaul_verify(struct cpufreq_policy *policy)
 630 {
 631         return cpufreq_frequency_table_verify(policy, longhaul_table);
 632 }
 633
 634
 635 static int longhaul_target(struct cpufreq_policy *policy,
 636                             unsigned int target_freq, unsigned int relation)
 637 {
 638         unsigned int table_index = 0;
 639         unsigned int i;
 640         unsigned int dir = 0;
 641         u8 vid, current_vid;
 642
 643         if (cpufreq_frequency_table_target(policy, longhaul_table, target_freq, relation, &table_index))
 644                 return -EINVAL;
 645
 646         /* Don't set same frequency again */
 647         if (longhaul_index == table_index)
 648                 return 0;
 649
 650         if (!can_scale_voltage)
 651                 longhaul_setstate(table_index);
 652         else {
 653                 /* On test system voltage transitions exceeding single
 654                  * step up or down were turning motherboard off. Both
 655                  * "ondemand" and "userspace" are unsafe. C7 is doing
 656                  * this in hardware, C3 is old and we need to do this
 657                  * in software. */
 658                 i = longhaul_index;
 659                 current_vid = (longhaul_table[longhaul_index].index >> 8) & 0x1f;
 660                 if (table_index > longhaul_index)
 661                         dir = 1;
 662                 while (i != table_index) {
 663                         vid = (longhaul_table[i].index >> 8) & 0x1f;
 664                         if (vid != current_vid) {
 665                                 longhaul_setstate(i);
 666                                 current_vid = vid;
 667                                 msleep(200);
 668                         }
 669                         if (dir)
 670                                 i++;
 671                         else
 672                                 i--;
 673                 }
 674                 longhaul_setstate(table_index);
 675         }
 676         longhaul_index = table_index;
 677         return 0;
 678 }
 679
 680
 681 static unsigned int longhaul_get(unsigned int cpu)
 682 {
 683         if (cpu)
 684                 return 0;
 685         return calc_speed(longhaul_get_cpu_mult());
 686 }
 687
 688 static acpi_status longhaul_walk_callback(acpi_handle obj_handle,
 689                                           u32 nesting_level,
 690                                           void *context, void **return_value)
 691 {
 692         struct acpi_device *d;
 693
 694         if ( acpi_bus_get_device(obj_handle, &d) ) {
 695                 return 0;
 696         }
 697         *return_value = acpi_driver_data(d);
 698         return 1;
 699 }
 700
 701 /* VIA don't support PM2 reg, but have something similar */
 702 static int enable_arbiter_disable(void)
 703 {
 704         struct pci_dev *dev;
 705         int status = 1;
 706         int reg;
 707         u8 pci_cmd;
 708
 709         /* Find PLE133 host bridge */
 710         reg = 0x78;
 711         dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8601_0,
 712                              NULL);
 713         /* Find PM133/VT8605 host bridge */
 714         if (dev == NULL)
 715                 dev = pci_get_device(PCI_VENDOR_ID_VIA,
 716                                      PCI_DEVICE_ID_VIA_8605_0, NULL);
 717         /* Find CLE266 host bridge */
 718         if (dev == NULL) {
 719                 reg = 0x76;
 720                 dev = pci_get_device(PCI_VENDOR_ID_VIA,
 721                                      PCI_DEVICE_ID_VIA_862X_0, NULL);
 722                 /* Find CN400 V-Link host bridge */
 723                 if (dev == NULL)
 724                         dev = pci_get_device(PCI_VENDOR_ID_VIA, 0x7259, NULL);
 725         }
 726         if (dev != NULL) {
 727                 /* Enable access to port 0x22 */
 728                 pci_read_config_byte(dev, reg, &pci_cmd);
 729                 if (!(pci_cmd & 1<<7)) {
 730                         pci_cmd |= 1<<7;
 731                         pci_write_config_byte(dev, reg, pci_cmd);
 732                         pci_read_config_byte(dev, reg, &pci_cmd);
 733                         if (!(pci_cmd & 1<<7)) {
 734                                 printk(KERN_ERR PFX
 735                                         "Can't enable access to port 0x22.\n");
 736                                 status = 0;
 737                         }
 738                 }
 739                 pci_dev_put(dev);
 740                 return status;
 741         }
 742         return 0;
 743 }
 744
 745 static int longhaul_setup_southbridge(void)
 746 {
 747         struct pci_dev *dev;
 748         u8 pci_cmd;
 749
 750         /* Find VT8235 southbridge */
 751         dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, NULL);
 752         if (dev == NULL)
 753         /* Find VT8237 southbridge */
 754                 dev = pci_get_device(PCI_VENDOR_ID_VIA,
 755                                      PCI_DEVICE_ID_VIA_8237, NULL);
 756         if (dev != NULL) {
 757                 /* Set transition time to max */
 758                 pci_read_config_byte(dev, 0xec, &pci_cmd);
 759                 pci_cmd &= ~(1 << 2);
 760                 pci_write_config_byte(dev, 0xec, pci_cmd);
 761                 pci_read_config_byte(dev, 0xe4, &pci_cmd);
 762                 pci_cmd &= ~(1 << 7);
 763                 pci_write_config_byte(dev, 0xe4, pci_cmd);
 764                 pci_read_config_byte(dev, 0xe5, &pci_cmd);
 765                 pci_cmd |= 1 << 7;
 766                 pci_write_config_byte(dev, 0xe5, pci_cmd);
 767                 /* Get address of ACPI registers block*/
 768                 pci_read_config_byte(dev, 0x81, &pci_cmd);
 769                 if (pci_cmd & 1 << 7) {
 770                         pci_read_config_dword(dev, 0x88, &acpi_regs_addr);
 771                         acpi_regs_addr &= 0xff00;
 772                         printk(KERN_INFO PFX "ACPI I/O at 0x%x\n", acpi_regs_addr);
 773                 }
 774
 775                 pci_dev_put(dev);
 776                 return 1;
 777         }
 778         return 0;
 779 }
 780
 781 static int __init longhaul_cpu_init(struct cpufreq_policy *policy)
 782 {
 783         struct cpuinfo_x86 *c = &cpu_data(0);
 784         char *cpuname=NULL;
 785         int ret;
 786         u32 lo, hi;
 787
 788         /* Check what we have on this motherboard */
 789         switch (c->x86_model) {
 790         case 6:
 791                 cpu_model = CPU_SAMUEL;
 792                 cpuname = "C3 'Samuel' [C5A]";
 793                 longhaul_version = TYPE_LONGHAUL_V1;
 794                 memcpy (clock_ratio, samuel1_clock_ratio, sizeof(samuel1_clock_ratio));
 795                 memcpy (eblcr_table, samuel1_eblcr, sizeof(samuel1_eblcr));
 796                 break;
 797
 798         case 7:
 799                 switch (c->x86_mask) {
 800                 case 0:
 801                         longhaul_version = TYPE_LONGHAUL_V1;
 802                         cpu_model = CPU_SAMUEL2;
 803                         cpuname = "C3 'Samuel 2' [C5B]";
 804                         /* Note, this is not a typo, early Samuel2's had
 805                          * Samuel1 ratios. */
 806                         memcpy(clock_ratio, samuel1_clock_ratio,
 807                                 sizeof(samuel1_clock_ratio));
 808                         memcpy(eblcr_table, samuel2_eblcr,
 809                                 sizeof(samuel2_eblcr));
 810                         break;
 811                 case 1 ... 15:
 812                         longhaul_version = TYPE_LONGHAUL_V1;
 813                         if (c->x86_mask < 8) {
 814                                 cpu_model = CPU_SAMUEL2;
 815                                 cpuname = "C3 'Samuel 2' [C5B]";
 816                         } else {
 817                                 cpu_model = CPU_EZRA;
 818                                 cpuname = "C3 'Ezra' [C5C]";
 819                         }
 820                         memcpy(clock_ratio, ezra_clock_ratio,
 821                                 sizeof(ezra_clock_ratio));
 822                         memcpy(eblcr_table, ezra_eblcr,
 823                                 sizeof(ezra_eblcr));
 824                         break;
 825                 }
 826                 break;
 827
 828         case 8:
 829                 cpu_model = CPU_EZRA_T;
 830                 cpuname = "C3 'Ezra-T' [C5M]";
 831                 longhaul_version = TYPE_POWERSAVER;
 832                 numscales=32;
 833                 memcpy (clock_ratio, ezrat_clock_ratio, sizeof(ezrat_clock_ratio));
 834                 memcpy (eblcr_table, ezrat_eblcr, sizeof(ezrat_eblcr));
 835                 break;
 836
 837         case 9:
 838                 longhaul_version = TYPE_POWERSAVER;
 839                 numscales = 32;
 840                 memcpy(clock_ratio,
 841                        nehemiah_clock_ratio,
 842                        sizeof(nehemiah_clock_ratio));
 843                 memcpy(eblcr_table, nehemiah_eblcr, sizeof(nehemiah_eblcr));
 844                 switch (c->x86_mask) {
 845                 case 0 ... 1:
 846                         cpu_model = CPU_NEHEMIAH;
 847                         cpuname = "C3 'Nehemiah A' [C5XLOE]";
 848                         break;
 849                 case 2 ... 4:
 850                         cpu_model = CPU_NEHEMIAH;
 851                         cpuname = "C3 'Nehemiah B' [C5XLOH]";
 852                         break;
 853                 case 5 ... 15:
 854                         cpu_model = CPU_NEHEMIAH_C;
 855                         cpuname = "C3 'Nehemiah C' [C5P]";
 856                         break;
 857                 }
 858                 break;
 859
 860         default:
 861                 cpuname = "Unknown";
 862                 break;
 863         }
 864         /* Check Longhaul ver. 2 */
 865         if (longhaul_version == TYPE_LONGHAUL_V2) {
 866                 rdmsr(MSR_VIA_LONGHAUL, lo, hi);
 867                 if (lo == 0 && hi == 0)
 868                         /* Looks like MSR isn't present */
 869                         longhaul_version = TYPE_LONGHAUL_V1;
 870         }
 871
 872         printk (KERN_INFO PFX "VIA %s CPU detected.  ", cpuname);
 873         switch (longhaul_version) {
 874         case TYPE_LONGHAUL_V1:
 875         case TYPE_LONGHAUL_V2:
 876                 printk ("Longhaul v%d supported.\n", longhaul_version);
 877                 break;
 878         case TYPE_POWERSAVER:
 879                 printk ("Powersaver supported.\n");
 880                 break;
 881         };
 882
 883         /* Doesn't hurt */
 884         longhaul_setup_southbridge();
 885
 886         /* Find ACPI data for processor */
 887         acpi_walk_namespace(ACPI_TYPE_PROCESSOR, ACPI_ROOT_OBJECT,
 888                                 ACPI_UINT32_MAX, &longhaul_walk_callback,
 889                                 NULL, (void *)&pr);
 890
 891         /* Check ACPI support for C3 state */
 892         if (pr != NULL && longhaul_version == TYPE_POWERSAVER) {
 893                 cx = &pr->power.states[ACPI_STATE_C3];
 894                 if (cx->address > 0 && cx->latency <= 1000)
 895                         longhaul_flags |= USE_ACPI_C3;
 896         }
 897         /* Disable if it isn't working */
 898         if (disable_acpi_c3)
 899                 longhaul_flags &= ~USE_ACPI_C3;
 900         /* Check if northbridge is friendly */
 901         if (enable_arbiter_disable())
 902                 longhaul_flags |= USE_NORTHBRIDGE;
 903
 904         /* Check ACPI support for bus master arbiter disable */
 905         if (!(longhaul_flags & USE_ACPI_C3
 906              || longhaul_flags & USE_NORTHBRIDGE)
 907             && ((pr == NULL) || !(pr->flags.bm_control))) {
 908                 printk(KERN_ERR PFX
 909                         "No ACPI support. Unsupported northbridge.\n");
 910                 return -ENODEV;
 911         }
 912
 913         if (longhaul_flags & USE_NORTHBRIDGE)
 914                 printk(KERN_INFO PFX "Using northbridge support.\n");
 915         if (longhaul_flags & USE_ACPI_C3)
 916                 printk(KERN_INFO PFX "Using ACPI support.\n");
 917
 918         ret = longhaul_get_ranges();
 919         if (ret != 0)
 920                 return ret;
 921
 922         if ((longhaul_version != TYPE_LONGHAUL_V1) && (scale_voltage != 0))
 923                 longhaul_setup_voltagescaling();
 924
 925         policy->cpuinfo.transition_latency = 200000;    /* nsec */
 926         policy->cur = calc_speed(longhaul_get_cpu_mult());
 927
 928         ret = cpufreq_frequency_table_cpuinfo(policy, longhaul_table);
 929         if (ret)
 930                 return ret;
 931
 932         cpufreq_frequency_table_get_attr(longhaul_table, policy->cpu);
 933
 934         return 0;
 935 }
 936
 937 static int __devexit longhaul_cpu_exit(struct cpufreq_policy *policy)
 938 {
 939         cpufreq_frequency_table_put_attr(policy->cpu);
 940         return 0;
 941 }
 942
 943 static struct freq_attr* longhaul_attr[] = {
 944         &cpufreq_freq_attr_scaling_available_freqs,
 945         NULL,
 946 };
 947
 948 static struct cpufreq_driver longhaul_driver = {
 949         .verify = longhaul_verify,
 950         .target = longhaul_target,
 951         .get    = longhaul_get,
 952         .init   = longhaul_cpu_init,
 953         .exit   = __devexit_p(longhaul_cpu_exit),
 954         .name   = "longhaul",
 955         .owner  = THIS_MODULE,
 956         .attr   = longhaul_attr,
 957 };
 958
 959
 960 static int __init longhaul_init(void)
 961 {
 962         struct cpuinfo_x86 *c = &cpu_data(0);
 963
 964         if (c->x86_vendor != X86_VENDOR_CENTAUR || c->x86 != 6)
 965                 return -ENODEV;
 966
 967 #ifdef CONFIG_SMP
 968         if (num_online_cpus() > 1) {
 969                 printk(KERN_ERR PFX "More than 1 CPU detected, longhaul disabled.\n");
 970                 return -ENODEV;
 971         }
 972 #endif
 973 #ifdef CONFIG_X86_IO_APIC
 974         if (cpu_has_apic) {
 975                 printk(KERN_ERR PFX "APIC detected. Longhaul is currently broken in this configuration.\n");
 976                 return -ENODEV;
 977         }
 978 #endif
 979         switch (c->x86_model) {
 980         case 6 ... 9:
 981                 return cpufreq_register_driver(&longhaul_driver);
 982         case 10:
 983                 printk(KERN_ERR PFX "Use acpi-cpufreq driver for VIA C7\n");
 984         default:
 985                 ;
 986         }
 987
 988         return -ENODEV;
 989 }
 990
 991
 992 static void __exit longhaul_exit(void)
 993 {
 994         int i;
 995
 996         for (i=0; i < numscales; i++) {
 997                 if (clock_ratio[i] == maxmult) {
 998                         longhaul_setstate(i);
 999                         break;
1000                 }
1001         }
1002
1003         cpufreq_unregister_driver(&longhaul_driver);
1004         kfree(longhaul_table);
1005 }
1006
1007 /* Even if BIOS is exporting ACPI C3 state, and it is used
1008  * with success when CPU is idle, this state doesn't
1009  * trigger frequency transition in some cases. */
1010 module_param (disable_acpi_c3, int, 0644);
1011 MODULE_PARM_DESC(disable_acpi_c3, "Don't use ACPI C3 support");
1012 /* Change CPU voltage with frequency. Very usefull to save
1013  * power, but most VIA C3 processors aren't supporting it. */
1014 module_param (scale_voltage, int, 0644);
1015 MODULE_PARM_DESC(scale_voltage, "Scale voltage of processor");
1016 /* Force revision key to 0 for processors which doesn't
1017  * support voltage scaling, but are introducing itself as
1018  * such. */
1019 module_param(revid_errata, int, 0644);
1020 MODULE_PARM_DESC(revid_errata, "Ignore CPU Revision ID");
1021
1022 MODULE_AUTHOR ("Dave Jones <davej@redhat.com>");
1023 MODULE_DESCRIPTION ("Longhaul driver for VIA Cyrix processors.");
1024 MODULE_LICENSE ("GPL");
1025
1026 late_initcall(longhaul_init);
1027 module_exit(longhaul_exit);