arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2009 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/cpu.h>
  21 #include <linux/init.h>
  22 #include <linux/io.h>
  23 #include <linux/pci.h>
  24 #include <linux/kdebug.h>
  25
  26 #include <asm/uv/uv_mmrs.h>
  27 #include <asm/uv/uv_hub.h>
  28 #include <asm/current.h>
  29 #include <asm/pgtable.h>
  30 #include <asm/uv/bios.h>
  31 #include <asm/uv/uv.h>
  32 #include <asm/apic.h>
  33 #include <asm/ipi.h>
  34 #include <asm/smp.h>
  35 #include <asm/x86_init.h>
  36
  37 DEFINE_PER_CPU(int, x2apic_extra_bits);
  38
  39 #define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
  40
  41 static enum uv_system_type uv_system_type;
  42 static u64 gru_start_paddr, gru_end_paddr;
  43 int uv_min_hub_revision_id;
  44 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  45 static DEFINE_SPINLOCK(uv_nmi_lock);
  46
  47 static inline bool is_GRU_range(u64 start, u64 end)
  48 {
  49         return start >= gru_start_paddr && end <= gru_end_paddr;
  50 }
  51
  52 static bool uv_is_untracked_pat_range(u64 start, u64 end)
  53 {
  54         return is_ISA_range(start, end) || is_GRU_range(start, end);
  55 }
  56
  57 static int early_get_nodeid(void)
  58 {
  59         union uvh_node_id_u node_id;
  60         unsigned long *mmr;
  61
  62         mmr = early_ioremap(UV_LOCAL_MMR_BASE | UVH_NODE_ID, sizeof(*mmr));
  63         node_id.v = *mmr;
  64         early_iounmap(mmr, sizeof(*mmr));
  65
  66         /* Currently, all blades have same revision number */
  67         uv_min_hub_revision_id = node_id.s.revision;
  68
  69         return node_id.s.node_id;
  70 }
  71
  72 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
  73 {
  74         int nodeid;
  75
  76         if (!strcmp(oem_id, "SGI")) {
  77                 nodeid = early_get_nodeid();
  78                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
  79                 x86_platform.nmi_init = uv_nmi_init;
  80                 if (!strcmp(oem_table_id, "UVL"))
  81                         uv_system_type = UV_LEGACY_APIC;
  82                 else if (!strcmp(oem_table_id, "UVX"))
  83                         uv_system_type = UV_X2APIC;
  84                 else if (!strcmp(oem_table_id, "UVH")) {
  85                         __get_cpu_var(x2apic_extra_bits) =
  86                                 nodeid << (UV_APIC_PNODE_SHIFT - 1);
  87                         uv_system_type = UV_NON_UNIQUE_APIC;
  88                         return 1;
  89                 }
  90         }
  91         return 0;
  92 }
  93
  94 enum uv_system_type get_uv_system_type(void)
  95 {
  96         return uv_system_type;
  97 }
  98
  99 int is_uv_system(void)
 100 {
 101         return uv_system_type != UV_NONE;
 102 }
 103 EXPORT_SYMBOL_GPL(is_uv_system);
 104
 105 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 106 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
 107
 108 struct uv_blade_info *uv_blade_info;
 109 EXPORT_SYMBOL_GPL(uv_blade_info);
 110
 111 short *uv_node_to_blade;
 112 EXPORT_SYMBOL_GPL(uv_node_to_blade);
 113
 114 short *uv_cpu_to_blade;
 115 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
 116
 117 short uv_possible_blades;
 118 EXPORT_SYMBOL_GPL(uv_possible_blades);
 119
 120 unsigned long sn_rtc_cycles_per_second;
 121 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 122
 123 static const struct cpumask *uv_target_cpus(void)
 124 {
 125         return cpu_online_mask;
 126 }
 127
 128 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
 129 {
 130         cpumask_clear(retmask);
 131         cpumask_set_cpu(cpu, retmask);
 132 }
 133
 134 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 135 {
 136 #ifdef CONFIG_SMP
 137         unsigned long val;
 138         int pnode;
 139
 140         pnode = uv_apicid_to_pnode(phys_apicid);
 141         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 142             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 143             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 144             APIC_DM_INIT;
 145         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 146         mdelay(10);
 147
 148         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 149             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 150             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 151             APIC_DM_STARTUP;
 152         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 153
 154         atomic_set(&init_deasserted, 1);
 155 #endif
 156         return 0;
 157 }
 158
 159 static void uv_send_IPI_one(int cpu, int vector)
 160 {
 161         unsigned long apicid;
 162         int pnode;
 163
 164         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 165         pnode = uv_apicid_to_pnode(apicid);
 166         uv_hub_send_ipi(pnode, apicid, vector);
 167 }
 168
 169 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 170 {
 171         unsigned int cpu;
 172
 173         for_each_cpu(cpu, mask)
 174                 uv_send_IPI_one(cpu, vector);
 175 }
 176
 177 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 178 {
 179         unsigned int this_cpu = smp_processor_id();
 180         unsigned int cpu;
 181
 182         for_each_cpu(cpu, mask) {
 183                 if (cpu != this_cpu)
 184                         uv_send_IPI_one(cpu, vector);
 185         }
 186 }
 187
 188 static void uv_send_IPI_allbutself(int vector)
 189 {
 190         unsigned int this_cpu = smp_processor_id();
 191         unsigned int cpu;
 192
 193         for_each_online_cpu(cpu) {
 194                 if (cpu != this_cpu)
 195                         uv_send_IPI_one(cpu, vector);
 196         }
 197 }
 198
 199 static void uv_send_IPI_all(int vector)
 200 {
 201         uv_send_IPI_mask(cpu_online_mask, vector);
 202 }
 203
 204 static int uv_apic_id_registered(void)
 205 {
 206         return 1;
 207 }
 208
 209 static void uv_init_apic_ldr(void)
 210 {
 211 }
 212
 213 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 214 {
 215         /*
 216          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 217          * May as well be the first.
 218          */
 219         int cpu = cpumask_first(cpumask);
 220
 221         if ((unsigned)cpu < nr_cpu_ids)
 222                 return per_cpu(x86_cpu_to_apicid, cpu);
 223         else
 224                 return BAD_APICID;
 225 }
 226
 227 static unsigned int
 228 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 229                           const struct cpumask *andmask)
 230 {
 231         int cpu;
 232
 233         /*
 234          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 235          * May as well be the first.
 236          */
 237         for_each_cpu_and(cpu, cpumask, andmask) {
 238                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 239                         break;
 240         }
 241         return per_cpu(x86_cpu_to_apicid, cpu);
 242 }
 243
 244 static unsigned int x2apic_get_apic_id(unsigned long x)
 245 {
 246         unsigned int id;
 247
 248         WARN_ON(preemptible() && num_online_cpus() > 1);
 249         id = x | __get_cpu_var(x2apic_extra_bits);
 250
 251         return id;
 252 }
 253
 254 static unsigned long set_apic_id(unsigned int id)
 255 {
 256         unsigned long x;
 257
 258         /* maskout x2apic_extra_bits ? */
 259         x = id;
 260         return x;
 261 }
 262
 263 static unsigned int uv_read_apic_id(void)
 264 {
 265
 266         return x2apic_get_apic_id(apic_read(APIC_ID));
 267 }
 268
 269 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 270 {
 271         return uv_read_apic_id() >> index_msb;
 272 }
 273
 274 static void uv_send_IPI_self(int vector)
 275 {
 276         apic_write(APIC_SELF_IPI, vector);
 277 }
 278
 279 struct apic __refdata apic_x2apic_uv_x = {
 280
 281         .name                           = "UV large system",
 282         .probe                          = NULL,
 283         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 284         .apic_id_registered             = uv_apic_id_registered,
 285
 286         .irq_delivery_mode              = dest_Fixed,
 287         .irq_dest_mode                  = 0, /* physical */
 288
 289         .target_cpus                    = uv_target_cpus,
 290         .disable_esr                    = 0,
 291         .dest_logical                   = APIC_DEST_LOGICAL,
 292         .check_apicid_used              = NULL,
 293         .check_apicid_present           = NULL,
 294
 295         .vector_allocation_domain       = uv_vector_allocation_domain,
 296         .init_apic_ldr                  = uv_init_apic_ldr,
 297
 298         .ioapic_phys_id_map             = NULL,
 299         .setup_apic_routing             = NULL,
 300         .multi_timer_check              = NULL,
 301         .apicid_to_node                 = NULL,
 302         .cpu_to_logical_apicid          = NULL,
 303         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 304         .apicid_to_cpu_present          = NULL,
 305         .setup_portio_remap             = NULL,
 306         .check_phys_apicid_present      = default_check_phys_apicid_present,
 307         .enable_apic_mode               = NULL,
 308         .phys_pkg_id                    = uv_phys_pkg_id,
 309         .mps_oem_check                  = NULL,
 310
 311         .get_apic_id                    = x2apic_get_apic_id,
 312         .set_apic_id                    = set_apic_id,
 313         .apic_id_mask                   = 0xFFFFFFFFu,
 314
 315         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
 316         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 317
 318         .send_IPI_mask                  = uv_send_IPI_mask,
 319         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 320         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 321         .send_IPI_all                   = uv_send_IPI_all,
 322         .send_IPI_self                  = uv_send_IPI_self,
 323
 324         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 325         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 326         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 327         .wait_for_init_deassert         = NULL,
 328         .smp_callin_clear_local_apic    = NULL,
 329         .inquire_remote_apic            = NULL,
 330
 331         .read                           = native_apic_msr_read,
 332         .write                          = native_apic_msr_write,
 333         .icr_read                       = native_x2apic_icr_read,
 334         .icr_write                      = native_x2apic_icr_write,
 335         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 336         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 337 };
 338
 339 static __cpuinit void set_x2apic_extra_bits(int pnode)
 340 {
 341         __get_cpu_var(x2apic_extra_bits) = (pnode << 6);
 342 }
 343
 344 /*
 345  * Called on boot cpu.
 346  */
 347 static __init int boot_pnode_to_blade(int pnode)
 348 {
 349         int blade;
 350
 351         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 352                 if (pnode == uv_blade_info[blade].pnode)
 353                         return blade;
 354         BUG();
 355 }
 356
 357 struct redir_addr {
 358         unsigned long redirect;
 359         unsigned long alias;
 360 };
 361
 362 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 363
 364 static __initdata struct redir_addr redir_addrs[] = {
 365         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_SI_ALIAS0_OVERLAY_CONFIG},
 366         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_SI_ALIAS1_OVERLAY_CONFIG},
 367         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_SI_ALIAS2_OVERLAY_CONFIG},
 368 };
 369
 370 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 371 {
 372         union uvh_si_alias0_overlay_config_u alias;
 373         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 374         int i;
 375
 376         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 377                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 378                 if (alias.s.enable && alias.s.base == 0) {
 379                         *size = (1UL << alias.s.m_alias);
 380                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 381                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 382                         return;
 383                 }
 384         }
 385         *base = *size = 0;
 386 }
 387
 388 enum map_type {map_wb, map_uc};
 389
 390 static __init void map_high(char *id, unsigned long base, int pshift,
 391                         int bshift, int max_pnode, enum map_type map_type)
 392 {
 393         unsigned long bytes, paddr;
 394
 395         paddr = base << pshift;
 396         bytes = (1UL << bshift) * (max_pnode + 1);
 397         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 398                                                 paddr + bytes);
 399         if (map_type == map_uc)
 400                 init_extra_mapping_uc(paddr, bytes);
 401         else
 402                 init_extra_mapping_wb(paddr, bytes);
 403
 404 }
 405 static __init void map_gru_high(int max_pnode)
 406 {
 407         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 408         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 409
 410         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 411         if (gru.s.enable) {
 412                 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
 413                 gru_start_paddr = ((u64)gru.s.base << shift);
 414                 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 415
 416         }
 417 }
 418
 419 static __init void map_mmr_high(int max_pnode)
 420 {
 421         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 422         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 423
 424         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 425         if (mmr.s.enable)
 426                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 427 }
 428
 429 static __init void map_mmioh_high(int max_pnode)
 430 {
 431         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 432         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 433
 434         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 435         if (mmioh.s.enable)
 436                 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
 437                         max_pnode, map_uc);
 438 }
 439
 440 static __init void map_low_mmrs(void)
 441 {
 442         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 443         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 444 }
 445
 446 static __init void uv_rtc_init(void)
 447 {
 448         long status;
 449         u64 ticks_per_sec;
 450
 451         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 452                                         &ticks_per_sec);
 453         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 454                 printk(KERN_WARNING
 455                         "unable to determine platform RTC clock frequency, "
 456                         "guessing.\n");
 457                 /* BIOS gives wrong value for clock freq. so guess */
 458                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 459         } else
 460                 sn_rtc_cycles_per_second = ticks_per_sec;
 461 }
 462
 463 /*
 464  * percpu heartbeat timer
 465  */
 466 static void uv_heartbeat(unsigned long ignored)
 467 {
 468         struct timer_list *timer = &uv_hub_info->scir.timer;
 469         unsigned char bits = uv_hub_info->scir.state;
 470
 471         /* flip heartbeat bit */
 472         bits ^= SCIR_CPU_HEARTBEAT;
 473
 474         /* is this cpu idle? */
 475         if (idle_cpu(raw_smp_processor_id()))
 476                 bits &= ~SCIR_CPU_ACTIVITY;
 477         else
 478                 bits |= SCIR_CPU_ACTIVITY;
 479
 480         /* update system controller interface reg */
 481         uv_set_scir_bits(bits);
 482
 483         /* enable next timer period */
 484         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 485 }
 486
 487 static void __cpuinit uv_heartbeat_enable(int cpu)
 488 {
 489         while (!uv_cpu_hub_info(cpu)->scir.enabled) {
 490                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 491
 492                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 493                 setup_timer(timer, uv_heartbeat, cpu);
 494                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 495                 add_timer_on(timer, cpu);
 496                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 497
 498                 /* also ensure that boot cpu is enabled */
 499                 cpu = 0;
 500         }
 501 }
 502
 503 #ifdef CONFIG_HOTPLUG_CPU
 504 static void __cpuinit uv_heartbeat_disable(int cpu)
 505 {
 506         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 507                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 508                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 509         }
 510         uv_set_cpu_scir_bits(cpu, 0xff);
 511 }
 512
 513 /*
 514  * cpu hotplug notifier
 515  */
 516 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 517                                        unsigned long action, void *hcpu)
 518 {
 519         long cpu = (long)hcpu;
 520
 521         switch (action) {
 522         case CPU_ONLINE:
 523                 uv_heartbeat_enable(cpu);
 524                 break;
 525         case CPU_DOWN_PREPARE:
 526                 uv_heartbeat_disable(cpu);
 527                 break;
 528         default:
 529                 break;
 530         }
 531         return NOTIFY_OK;
 532 }
 533
 534 static __init void uv_scir_register_cpu_notifier(void)
 535 {
 536         hotcpu_notifier(uv_scir_cpu_notify, 0);
 537 }
 538
 539 #else /* !CONFIG_HOTPLUG_CPU */
 540
 541 static __init void uv_scir_register_cpu_notifier(void)
 542 {
 543 }
 544
 545 static __init int uv_init_heartbeat(void)
 546 {
 547         int cpu;
 548
 549         if (is_uv_system())
 550                 for_each_online_cpu(cpu)
 551                         uv_heartbeat_enable(cpu);
 552         return 0;
 553 }
 554
 555 late_initcall(uv_init_heartbeat);
 556
 557 #endif /* !CONFIG_HOTPLUG_CPU */
 558
 559 /* Direct Legacy VGA I/O traffic to designated IOH */
 560 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
 561                       unsigned int command_bits, bool change_bridge)
 562 {
 563         int domain, bus, rc;
 564
 565         PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n",
 566                         pdev->devfn, decode, command_bits, change_bridge);
 567
 568         if (!change_bridge)
 569                 return 0;
 570
 571         if ((command_bits & PCI_COMMAND_IO) == 0)
 572                 return 0;
 573
 574         domain = pci_domain_nr(pdev->bus);
 575         bus = pdev->bus->number;
 576
 577         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
 578         PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
 579
 580         return rc;
 581 }
 582
 583 /*
 584  * Called on each cpu to initialize the per_cpu UV data area.
 585  * FIXME: hotplug not supported yet
 586  */
 587 void __cpuinit uv_cpu_init(void)
 588 {
 589         /* CPU 0 initilization will be done via uv_system_init. */
 590         if (!uv_blade_info)
 591                 return;
 592
 593         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 594
 595         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 596                 set_x2apic_extra_bits(uv_hub_info->pnode);
 597 }
 598
 599 /*
 600  * When NMI is received, print a stack trace.
 601  */
 602 int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
 603 {
 604         if (reason != DIE_NMI_IPI)
 605                 return NOTIFY_OK;
 606         /*
 607          * Use a lock so only one cpu prints at a time
 608          * to prevent intermixed output.
 609          */
 610         spin_lock(&uv_nmi_lock);
 611         pr_info("NMI stack dump cpu %u:\n", smp_processor_id());
 612         dump_stack();
 613         spin_unlock(&uv_nmi_lock);
 614
 615         return NOTIFY_STOP;
 616 }
 617
 618 static struct notifier_block uv_dump_stack_nmi_nb = {
 619         .notifier_call  = uv_handle_nmi
 620 };
 621
 622 void uv_register_nmi_notifier(void)
 623 {
 624         if (register_die_notifier(&uv_dump_stack_nmi_nb))
 625                 printk(KERN_WARNING "UV NMI handler failed to register\n");
 626 }
 627
 628 void uv_nmi_init(void)
 629 {
 630         unsigned int value;
 631
 632         /*
 633          * Unmask NMI on all cpus
 634          */
 635         value = apic_read(APIC_LVT1) | APIC_DM_NMI;
 636         value &= ~APIC_LVT_MASKED;
 637         apic_write(APIC_LVT1, value);
 638 }
 639
 640 void __init uv_system_init(void)
 641 {
 642         union uvh_si_addr_map_config_u m_n_config;
 643         union uvh_node_id_u node_id;
 644         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 645         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
 646         int gnode_extra, max_pnode = 0;
 647         unsigned long mmr_base, present, paddr;
 648         unsigned short pnode_mask;
 649
 650         map_low_mmrs();
 651
 652         m_n_config.v = uv_read_local_mmr(UVH_SI_ADDR_MAP_CONFIG);
 653         m_val = m_n_config.s.m_skt;
 654         n_val = m_n_config.s.n_skt;
 655         mmr_base =
 656             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 657             ~UV_MMR_ENABLE;
 658         pnode_mask = (1 << n_val) - 1;
 659         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 660         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
 661         gnode_upper = ((unsigned long)gnode_extra  << m_val);
 662         printk(KERN_DEBUG "UV: N %d, M %d, gnode_upper 0x%lx, gnode_extra 0x%x\n",
 663                         n_val, m_val, gnode_upper, gnode_extra);
 664
 665         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 666
 667         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 668                 uv_possible_blades +=
 669                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 670         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 671
 672         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 673         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 674         BUG_ON(!uv_blade_info);
 675         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 676                 uv_blade_info[blade].memory_nid = -1;
 677
 678         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 679
 680         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 681         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 682         BUG_ON(!uv_node_to_blade);
 683         memset(uv_node_to_blade, 255, bytes);
 684
 685         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 686         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 687         BUG_ON(!uv_cpu_to_blade);
 688         memset(uv_cpu_to_blade, 255, bytes);
 689
 690         blade = 0;
 691         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 692                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 693                 for (j = 0; j < 64; j++) {
 694                         if (!test_bit(j, &present))
 695                                 continue;
 696                         uv_blade_info[blade].pnode = (i * 64 + j);
 697                         uv_blade_info[blade].nr_possible_cpus = 0;
 698                         uv_blade_info[blade].nr_online_cpus = 0;
 699                         blade++;
 700                 }
 701         }
 702
 703         uv_bios_init();
 704         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
 705                             &sn_region_size, &system_serial_number);
 706         uv_rtc_init();
 707
 708         for_each_present_cpu(cpu) {
 709                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
 710
 711                 nid = cpu_to_node(cpu);
 712                 pnode = uv_apicid_to_pnode(apicid);
 713                 blade = boot_pnode_to_blade(pnode);
 714                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 715                 uv_blade_info[blade].nr_possible_cpus++;
 716
 717                 /* Any node on the blade, else will contain -1. */
 718                 uv_blade_info[blade].memory_nid = nid;
 719
 720                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 721                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 722                 uv_cpu_hub_info(cpu)->m_val = m_val;
 723                 uv_cpu_hub_info(cpu)->n_val = n_val;
 724                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 725                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 726                 uv_cpu_hub_info(cpu)->pnode = pnode;
 727                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
 728                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
 729                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 730                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
 731                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 732                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 733                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
 734                 uv_node_to_blade[nid] = blade;
 735                 uv_cpu_to_blade[cpu] = blade;
 736                 max_pnode = max(pnode, max_pnode);
 737
 738                 printk(KERN_DEBUG "UV: cpu %d, apicid 0x%x, pnode %d, nid %d, lcpu %d, blade %d\n",
 739                         cpu, apicid, pnode, nid, lcpu, blade);
 740         }
 741
 742         /* Add blade/pnode info for nodes without cpus */
 743         for_each_online_node(nid) {
 744                 if (uv_node_to_blade[nid] >= 0)
 745                         continue;
 746                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
 747                 paddr = uv_soc_phys_ram_to_gpa(paddr);
 748                 pnode = (paddr >> m_val) & pnode_mask;
 749                 blade = boot_pnode_to_blade(pnode);
 750                 uv_node_to_blade[nid] = blade;
 751                 max_pnode = max(pnode, max_pnode);
 752         }
 753
 754         map_gru_high(max_pnode);
 755         map_mmr_high(max_pnode);
 756         map_mmioh_high(max_pnode);
 757
 758         uv_cpu_init();
 759         uv_scir_register_cpu_notifier();
 760         uv_register_nmi_notifier();
 761         proc_mkdir("sgi_uv", NULL);
 762
 763         /* register Legacy VGA I/O redirection handler */
 764         pci_register_set_vga_state(uv_set_vga_state);
 765 }