arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/slab.h>
  21 #include <linux/cpu.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdebug.h>
  26
  27 #include <asm/uv/uv_mmrs.h>
  28 #include <asm/uv/uv_hub.h>
  29 #include <asm/current.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/uv/bios.h>
  32 #include <asm/uv/uv.h>
  33 #include <asm/apic.h>
  34 #include <asm/ipi.h>
  35 #include <asm/smp.h>
  36 #include <asm/x86_init.h>
  37
  38 DEFINE_PER_CPU(int, x2apic_extra_bits);
  39
  40 #define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
  41
  42 static enum uv_system_type uv_system_type;
  43 static u64 gru_start_paddr, gru_end_paddr;
  44 static union uvh_apicid uvh_apicid;
  45 int uv_min_hub_revision_id;
  46 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  47 unsigned int uv_apicid_hibits;
  48 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
  49 static DEFINE_SPINLOCK(uv_nmi_lock);
  50
  51 static unsigned long __init uv_early_read_mmr(unsigned long addr)
  52 {
  53         unsigned long val, *mmr;
  54
  55         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
  56         val = *mmr;
  57         early_iounmap(mmr, sizeof(*mmr));
  58         return val;
  59 }
  60
  61 static inline bool is_GRU_range(u64 start, u64 end)
  62 {
  63         return start >= gru_start_paddr && end <= gru_end_paddr;
  64 }
  65
  66 static bool uv_is_untracked_pat_range(u64 start, u64 end)
  67 {
  68         return is_ISA_range(start, end) || is_GRU_range(start, end);
  69 }
  70
  71 static int __init early_get_pnodeid(void)
  72 {
  73         union uvh_node_id_u node_id;
  74         union uvh_rh_gam_config_mmr_u  m_n_config;
  75         int pnode;
  76
  77         /* Currently, all blades have same revision number */
  78         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
  79         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
  80         uv_min_hub_revision_id = node_id.s.revision;
  81
  82         pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
  83         return pnode;
  84 }
  85
  86 static void __init early_get_apic_pnode_shift(void)
  87 {
  88         uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
  89         if (!uvh_apicid.v)
  90                 /*
  91                  * Old bios, use default value
  92                  */
  93                 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
  94 }
  95
  96 /*
  97  * Add an extra bit as dictated by bios to the destination apicid of
  98  * interrupts potentially passing through the UV HUB.  This prevents
  99  * a deadlock between interrupts and IO port operations.
 100  */
 101 static void __init uv_set_apicid_hibit(void)
 102 {
 103         union uvh_lb_target_physical_apic_id_mask_u apicid_mask;
 104
 105         apicid_mask.v = uv_early_read_mmr(UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK);
 106         uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK;
 107 }
 108
 109 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 110 {
 111         int pnodeid;
 112
 113         if (!strcmp(oem_id, "SGI")) {
 114                 pnodeid = early_get_pnodeid();
 115                 early_get_apic_pnode_shift();
 116                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
 117                 x86_platform.nmi_init = uv_nmi_init;
 118                 if (!strcmp(oem_table_id, "UVL"))
 119                         uv_system_type = UV_LEGACY_APIC;
 120                 else if (!strcmp(oem_table_id, "UVX"))
 121                         uv_system_type = UV_X2APIC;
 122                 else if (!strcmp(oem_table_id, "UVH")) {
 123                         __this_cpu_write(x2apic_extra_bits,
 124                                 pnodeid << uvh_apicid.s.pnode_shift);
 125                         uv_system_type = UV_NON_UNIQUE_APIC;
 126                         uv_set_apicid_hibit();
 127                         return 1;
 128                 }
 129         }
 130         return 0;
 131 }
 132
 133 enum uv_system_type get_uv_system_type(void)
 134 {
 135         return uv_system_type;
 136 }
 137
 138 int is_uv_system(void)
 139 {
 140         return uv_system_type != UV_NONE;
 141 }
 142 EXPORT_SYMBOL_GPL(is_uv_system);
 143
 144 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 145 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
 146
 147 struct uv_blade_info *uv_blade_info;
 148 EXPORT_SYMBOL_GPL(uv_blade_info);
 149
 150 short *uv_node_to_blade;
 151 EXPORT_SYMBOL_GPL(uv_node_to_blade);
 152
 153 short *uv_cpu_to_blade;
 154 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
 155
 156 short uv_possible_blades;
 157 EXPORT_SYMBOL_GPL(uv_possible_blades);
 158
 159 unsigned long sn_rtc_cycles_per_second;
 160 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 161
 162 static const struct cpumask *uv_target_cpus(void)
 163 {
 164         return cpu_online_mask;
 165 }
 166
 167 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
 168 {
 169         cpumask_clear(retmask);
 170         cpumask_set_cpu(cpu, retmask);
 171 }
 172
 173 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 174 {
 175 #ifdef CONFIG_SMP
 176         unsigned long val;
 177         int pnode;
 178
 179         pnode = uv_apicid_to_pnode(phys_apicid);
 180         phys_apicid |= uv_apicid_hibits;
 181         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 182             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 183             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 184             APIC_DM_INIT;
 185         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 186         mdelay(10);
 187
 188         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 189             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 190             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 191             APIC_DM_STARTUP;
 192         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 193
 194         atomic_set(&init_deasserted, 1);
 195 #endif
 196         return 0;
 197 }
 198
 199 static void uv_send_IPI_one(int cpu, int vector)
 200 {
 201         unsigned long apicid;
 202         int pnode;
 203
 204         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 205         pnode = uv_apicid_to_pnode(apicid);
 206         uv_hub_send_ipi(pnode, apicid, vector);
 207 }
 208
 209 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 210 {
 211         unsigned int cpu;
 212
 213         for_each_cpu(cpu, mask)
 214                 uv_send_IPI_one(cpu, vector);
 215 }
 216
 217 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 218 {
 219         unsigned int this_cpu = smp_processor_id();
 220         unsigned int cpu;
 221
 222         for_each_cpu(cpu, mask) {
 223                 if (cpu != this_cpu)
 224                         uv_send_IPI_one(cpu, vector);
 225         }
 226 }
 227
 228 static void uv_send_IPI_allbutself(int vector)
 229 {
 230         unsigned int this_cpu = smp_processor_id();
 231         unsigned int cpu;
 232
 233         for_each_online_cpu(cpu) {
 234                 if (cpu != this_cpu)
 235                         uv_send_IPI_one(cpu, vector);
 236         }
 237 }
 238
 239 static void uv_send_IPI_all(int vector)
 240 {
 241         uv_send_IPI_mask(cpu_online_mask, vector);
 242 }
 243
 244 static int uv_apic_id_registered(void)
 245 {
 246         return 1;
 247 }
 248
 249 static void uv_init_apic_ldr(void)
 250 {
 251 }
 252
 253 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 254 {
 255         /*
 256          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 257          * May as well be the first.
 258          */
 259         int cpu = cpumask_first(cpumask);
 260
 261         if ((unsigned)cpu < nr_cpu_ids)
 262                 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
 263         else
 264                 return BAD_APICID;
 265 }
 266
 267 static unsigned int
 268 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 269                           const struct cpumask *andmask)
 270 {
 271         int cpu;
 272
 273         /*
 274          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 275          * May as well be the first.
 276          */
 277         for_each_cpu_and(cpu, cpumask, andmask) {
 278                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 279                         break;
 280         }
 281         return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
 282 }
 283
 284 static unsigned int x2apic_get_apic_id(unsigned long x)
 285 {
 286         unsigned int id;
 287
 288         WARN_ON(preemptible() && num_online_cpus() > 1);
 289         id = x | __this_cpu_read(x2apic_extra_bits);
 290
 291         return id;
 292 }
 293
 294 static unsigned long set_apic_id(unsigned int id)
 295 {
 296         unsigned long x;
 297
 298         /* maskout x2apic_extra_bits ? */
 299         x = id;
 300         return x;
 301 }
 302
 303 static unsigned int uv_read_apic_id(void)
 304 {
 305
 306         return x2apic_get_apic_id(apic_read(APIC_ID));
 307 }
 308
 309 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 310 {
 311         return uv_read_apic_id() >> index_msb;
 312 }
 313
 314 static void uv_send_IPI_self(int vector)
 315 {
 316         apic_write(APIC_SELF_IPI, vector);
 317 }
 318
 319 struct apic __refdata apic_x2apic_uv_x = {
 320
 321         .name                           = "UV large system",
 322         .probe                          = NULL,
 323         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 324         .apic_id_registered             = uv_apic_id_registered,
 325
 326         .irq_delivery_mode              = dest_Fixed,
 327         .irq_dest_mode                  = 0, /* physical */
 328
 329         .target_cpus                    = uv_target_cpus,
 330         .disable_esr                    = 0,
 331         .dest_logical                   = APIC_DEST_LOGICAL,
 332         .check_apicid_used              = NULL,
 333         .check_apicid_present           = NULL,
 334
 335         .vector_allocation_domain       = uv_vector_allocation_domain,
 336         .init_apic_ldr                  = uv_init_apic_ldr,
 337
 338         .ioapic_phys_id_map             = NULL,
 339         .setup_apic_routing             = NULL,
 340         .multi_timer_check              = NULL,
 341         .apicid_to_node                 = NULL,
 342         .cpu_to_logical_apicid          = NULL,
 343         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 344         .apicid_to_cpu_present          = NULL,
 345         .setup_portio_remap             = NULL,
 346         .check_phys_apicid_present      = default_check_phys_apicid_present,
 347         .enable_apic_mode               = NULL,
 348         .phys_pkg_id                    = uv_phys_pkg_id,
 349         .mps_oem_check                  = NULL,
 350
 351         .get_apic_id                    = x2apic_get_apic_id,
 352         .set_apic_id                    = set_apic_id,
 353         .apic_id_mask                   = 0xFFFFFFFFu,
 354
 355         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
 356         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 357
 358         .send_IPI_mask                  = uv_send_IPI_mask,
 359         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 360         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 361         .send_IPI_all                   = uv_send_IPI_all,
 362         .send_IPI_self                  = uv_send_IPI_self,
 363
 364         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 365         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 366         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 367         .wait_for_init_deassert         = NULL,
 368         .smp_callin_clear_local_apic    = NULL,
 369         .inquire_remote_apic            = NULL,
 370
 371         .read                           = native_apic_msr_read,
 372         .write                          = native_apic_msr_write,
 373         .icr_read                       = native_x2apic_icr_read,
 374         .icr_write                      = native_x2apic_icr_write,
 375         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 376         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 377 };
 378
 379 static __cpuinit void set_x2apic_extra_bits(int pnode)
 380 {
 381         __this_cpu_write(x2apic_extra_bits, (pnode << 6));
 382 }
 383
 384 /*
 385  * Called on boot cpu.
 386  */
 387 static __init int boot_pnode_to_blade(int pnode)
 388 {
 389         int blade;
 390
 391         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 392                 if (pnode == uv_blade_info[blade].pnode)
 393                         return blade;
 394         BUG();
 395 }
 396
 397 struct redir_addr {
 398         unsigned long redirect;
 399         unsigned long alias;
 400 };
 401
 402 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 403
 404 static __initdata struct redir_addr redir_addrs[] = {
 405         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
 406         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
 407         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
 408 };
 409
 410 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 411 {
 412         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
 413         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 414         int i;
 415
 416         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 417                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 418                 if (alias.s.enable && alias.s.base == 0) {
 419                         *size = (1UL << alias.s.m_alias);
 420                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 421                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 422                         return;
 423                 }
 424         }
 425         *base = *size = 0;
 426 }
 427
 428 enum map_type {map_wb, map_uc};
 429
 430 static __init void map_high(char *id, unsigned long base, int pshift,
 431                         int bshift, int max_pnode, enum map_type map_type)
 432 {
 433         unsigned long bytes, paddr;
 434
 435         paddr = base << pshift;
 436         bytes = (1UL << bshift) * (max_pnode + 1);
 437         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 438                                                 paddr + bytes);
 439         if (map_type == map_uc)
 440                 init_extra_mapping_uc(paddr, bytes);
 441         else
 442                 init_extra_mapping_wb(paddr, bytes);
 443
 444 }
 445 static __init void map_gru_high(int max_pnode)
 446 {
 447         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 448         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 449
 450         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 451         if (gru.s.enable) {
 452                 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
 453                 gru_start_paddr = ((u64)gru.s.base << shift);
 454                 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 455
 456         }
 457 }
 458
 459 static __init void map_mmr_high(int max_pnode)
 460 {
 461         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 462         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 463
 464         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 465         if (mmr.s.enable)
 466                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 467 }
 468
 469 static __init void map_mmioh_high(int max_pnode)
 470 {
 471         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 472         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 473
 474         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 475         if (mmioh.s.enable)
 476                 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
 477                         max_pnode, map_uc);
 478 }
 479
 480 static __init void map_low_mmrs(void)
 481 {
 482         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 483         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 484 }
 485
 486 static __init void uv_rtc_init(void)
 487 {
 488         long status;
 489         u64 ticks_per_sec;
 490
 491         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 492                                         &ticks_per_sec);
 493         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 494                 printk(KERN_WARNING
 495                         "unable to determine platform RTC clock frequency, "
 496                         "guessing.\n");
 497                 /* BIOS gives wrong value for clock freq. so guess */
 498                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 499         } else
 500                 sn_rtc_cycles_per_second = ticks_per_sec;
 501 }
 502
 503 /*
 504  * percpu heartbeat timer
 505  */
 506 static void uv_heartbeat(unsigned long ignored)
 507 {
 508         struct timer_list *timer = &uv_hub_info->scir.timer;
 509         unsigned char bits = uv_hub_info->scir.state;
 510
 511         /* flip heartbeat bit */
 512         bits ^= SCIR_CPU_HEARTBEAT;
 513
 514         /* is this cpu idle? */
 515         if (idle_cpu(raw_smp_processor_id()))
 516                 bits &= ~SCIR_CPU_ACTIVITY;
 517         else
 518                 bits |= SCIR_CPU_ACTIVITY;
 519
 520         /* update system controller interface reg */
 521         uv_set_scir_bits(bits);
 522
 523         /* enable next timer period */
 524         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 525 }
 526
 527 static void __cpuinit uv_heartbeat_enable(int cpu)
 528 {
 529         while (!uv_cpu_hub_info(cpu)->scir.enabled) {
 530                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 531
 532                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 533                 setup_timer(timer, uv_heartbeat, cpu);
 534                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 535                 add_timer_on(timer, cpu);
 536                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 537
 538                 /* also ensure that boot cpu is enabled */
 539                 cpu = 0;
 540         }
 541 }
 542
 543 #ifdef CONFIG_HOTPLUG_CPU
 544 static void __cpuinit uv_heartbeat_disable(int cpu)
 545 {
 546         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 547                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 548                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 549         }
 550         uv_set_cpu_scir_bits(cpu, 0xff);
 551 }
 552
 553 /*
 554  * cpu hotplug notifier
 555  */
 556 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 557                                        unsigned long action, void *hcpu)
 558 {
 559         long cpu = (long)hcpu;
 560
 561         switch (action) {
 562         case CPU_ONLINE:
 563                 uv_heartbeat_enable(cpu);
 564                 break;
 565         case CPU_DOWN_PREPARE:
 566                 uv_heartbeat_disable(cpu);
 567                 break;
 568         default:
 569                 break;
 570         }
 571         return NOTIFY_OK;
 572 }
 573
 574 static __init void uv_scir_register_cpu_notifier(void)
 575 {
 576         hotcpu_notifier(uv_scir_cpu_notify, 0);
 577 }
 578
 579 #else /* !CONFIG_HOTPLUG_CPU */
 580
 581 static __init void uv_scir_register_cpu_notifier(void)
 582 {
 583 }
 584
 585 static __init int uv_init_heartbeat(void)
 586 {
 587         int cpu;
 588
 589         if (is_uv_system())
 590                 for_each_online_cpu(cpu)
 591                         uv_heartbeat_enable(cpu);
 592         return 0;
 593 }
 594
 595 late_initcall(uv_init_heartbeat);
 596
 597 #endif /* !CONFIG_HOTPLUG_CPU */
 598
 599 /* Direct Legacy VGA I/O traffic to designated IOH */
 600 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
 601                       unsigned int command_bits, bool change_bridge)
 602 {
 603         int domain, bus, rc;
 604
 605         PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n",
 606                         pdev->devfn, decode, command_bits, change_bridge);
 607
 608         if (!change_bridge)
 609                 return 0;
 610
 611         if ((command_bits & PCI_COMMAND_IO) == 0)
 612                 return 0;
 613
 614         domain = pci_domain_nr(pdev->bus);
 615         bus = pdev->bus->number;
 616
 617         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
 618         PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
 619
 620         return rc;
 621 }
 622
 623 /*
 624  * Called on each cpu to initialize the per_cpu UV data area.
 625  * FIXME: hotplug not supported yet
 626  */
 627 void __cpuinit uv_cpu_init(void)
 628 {
 629         /* CPU 0 initilization will be done via uv_system_init. */
 630         if (!uv_blade_info)
 631                 return;
 632
 633         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 634
 635         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 636                 set_x2apic_extra_bits(uv_hub_info->pnode);
 637 }
 638
 639 /*
 640  * When NMI is received, print a stack trace.
 641  */
 642 int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
 643 {
 644         if (reason != DIE_NMI_IPI)
 645                 return NOTIFY_OK;
 646
 647         if (in_crash_kexec)
 648                 /* do nothing if entering the crash kernel */
 649                 return NOTIFY_OK;
 650         /*
 651          * Use a lock so only one cpu prints at a time
 652          * to prevent intermixed output.
 653          */
 654         spin_lock(&uv_nmi_lock);
 655         pr_info("NMI stack dump cpu %u:\n", smp_processor_id());
 656         dump_stack();
 657         spin_unlock(&uv_nmi_lock);
 658
 659         return NOTIFY_STOP;
 660 }
 661
 662 static struct notifier_block uv_dump_stack_nmi_nb = {
 663         .notifier_call  = uv_handle_nmi
 664 };
 665
 666 void uv_register_nmi_notifier(void)
 667 {
 668         if (register_die_notifier(&uv_dump_stack_nmi_nb))
 669                 printk(KERN_WARNING "UV NMI handler failed to register\n");
 670 }
 671
 672 void uv_nmi_init(void)
 673 {
 674         unsigned int value;
 675
 676         /*
 677          * Unmask NMI on all cpus
 678          */
 679         value = apic_read(APIC_LVT1) | APIC_DM_NMI;
 680         value &= ~APIC_LVT_MASKED;
 681         apic_write(APIC_LVT1, value);
 682 }
 683
 684 void __init uv_system_init(void)
 685 {
 686         union uvh_rh_gam_config_mmr_u  m_n_config;
 687         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 688         union uvh_node_id_u node_id;
 689         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 690         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io;
 691         int gnode_extra, max_pnode = 0;
 692         unsigned long mmr_base, present, paddr;
 693         unsigned short pnode_mask, pnode_io_mask;
 694
 695         map_low_mmrs();
 696
 697         m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
 698         m_val = m_n_config.s.m_skt;
 699         n_val = m_n_config.s.n_skt;
 700         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 701         n_io = mmioh.s.n_io;
 702         mmr_base =
 703             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 704             ~UV_MMR_ENABLE;
 705         pnode_mask = (1 << n_val) - 1;
 706         pnode_io_mask = (1 << n_io) - 1;
 707
 708         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 709         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
 710         gnode_upper = ((unsigned long)gnode_extra  << m_val);
 711         printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n",
 712                         n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask);
 713
 714         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 715
 716         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 717                 uv_possible_blades +=
 718                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 719         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 720
 721         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 722         uv_blade_info = kmalloc(bytes, GFP_KERNEL);
 723         BUG_ON(!uv_blade_info);
 724         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 725                 uv_blade_info[blade].memory_nid = -1;
 726
 727         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 728
 729         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 730         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 731         BUG_ON(!uv_node_to_blade);
 732         memset(uv_node_to_blade, 255, bytes);
 733
 734         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 735         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 736         BUG_ON(!uv_cpu_to_blade);
 737         memset(uv_cpu_to_blade, 255, bytes);
 738
 739         blade = 0;
 740         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 741                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 742                 for (j = 0; j < 64; j++) {
 743                         if (!test_bit(j, &present))
 744                                 continue;
 745                         pnode = (i * 64 + j) & pnode_mask;
 746                         uv_blade_info[blade].pnode = pnode;
 747                         uv_blade_info[blade].nr_possible_cpus = 0;
 748                         uv_blade_info[blade].nr_online_cpus = 0;
 749                         max_pnode = max(pnode, max_pnode);
 750                         blade++;
 751                 }
 752         }
 753
 754         uv_bios_init();
 755         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
 756                             &sn_region_size, &system_serial_number);
 757         uv_rtc_init();
 758
 759         for_each_present_cpu(cpu) {
 760                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
 761
 762                 nid = cpu_to_node(cpu);
 763                 /*
 764                  * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
 765                  */
 766                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
 767                 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
 768                 pnode = uv_apicid_to_pnode(apicid);
 769                 blade = boot_pnode_to_blade(pnode);
 770                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 771                 uv_blade_info[blade].nr_possible_cpus++;
 772
 773                 /* Any node on the blade, else will contain -1. */
 774                 uv_blade_info[blade].memory_nid = nid;
 775
 776                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 777                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 778                 uv_cpu_hub_info(cpu)->m_val = m_val;
 779                 uv_cpu_hub_info(cpu)->n_val = n_val;
 780                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 781                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 782                 uv_cpu_hub_info(cpu)->pnode = pnode;
 783                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
 784                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 785                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
 786                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 787                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 788                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
 789                 uv_node_to_blade[nid] = blade;
 790                 uv_cpu_to_blade[cpu] = blade;
 791         }
 792
 793         /* Add blade/pnode info for nodes without cpus */
 794         for_each_online_node(nid) {
 795                 if (uv_node_to_blade[nid] >= 0)
 796                         continue;
 797                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
 798                 paddr = uv_soc_phys_ram_to_gpa(paddr);
 799                 pnode = (paddr >> m_val) & pnode_mask;
 800                 blade = boot_pnode_to_blade(pnode);
 801                 uv_node_to_blade[nid] = blade;
 802         }
 803
 804         map_gru_high(max_pnode);
 805         map_mmr_high(max_pnode);
 806         map_mmioh_high(max_pnode & pnode_io_mask);
 807
 808         uv_cpu_init();
 809         uv_scir_register_cpu_notifier();
 810         uv_register_nmi_notifier();
 811         proc_mkdir("sgi_uv", NULL);
 812
 813         /* register Legacy VGA I/O redirection handler */
 814         pci_register_set_vga_state(uv_set_vga_state);
 815 }