arch/x86/kernel/apic/x2apic_uv_x.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * SGI UV APIC functions (note: not an Intel compatible APIC)
   7  *
   8  * Copyright (C) 2007-2010 Silicon Graphics, Inc. All rights reserved.
   9  */
  10 #include <linux/cpumask.h>
  11 #include <linux/hardirq.h>
  12 #include <linux/proc_fs.h>
  13 #include <linux/threads.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/string.h>
  17 #include <linux/ctype.h>
  18 #include <linux/sched.h>
  19 #include <linux/timer.h>
  20 #include <linux/slab.h>
  21 #include <linux/cpu.h>
  22 #include <linux/init.h>
  23 #include <linux/io.h>
  24 #include <linux/pci.h>
  25 #include <linux/kdebug.h>
  26 #include <linux/delay.h>
  27 #include <linux/crash_dump.h>
  28
  29 #include <asm/uv/uv_mmrs.h>
  30 #include <asm/uv/uv_hub.h>
  31 #include <asm/current.h>
  32 #include <asm/pgtable.h>
  33 #include <asm/uv/bios.h>
  34 #include <asm/uv/uv.h>
  35 #include <asm/apic.h>
  36 #include <asm/ipi.h>
  37 #include <asm/smp.h>
  38 #include <asm/x86_init.h>
  39 #include <asm/emergency-restart.h>
  40 #include <asm/nmi.h>
  41
  42 /* BMC sets a bit this MMR non-zero before sending an NMI */
  43 #define UVH_NMI_MMR                             UVH_SCRATCH5
  44 #define UVH_NMI_MMR_CLEAR                       (UVH_NMI_MMR + 8)
  45 #define UV_NMI_PENDING_MASK                     (1UL << 63)
  46 DEFINE_PER_CPU(unsigned long, cpu_last_nmi_count);
  47
  48 DEFINE_PER_CPU(int, x2apic_extra_bits);
  49
  50 #define PR_DEVEL(fmt, args...)  pr_devel("%s: " fmt, __func__, args)
  51
  52 static enum uv_system_type uv_system_type;
  53 static u64 gru_start_paddr, gru_end_paddr;
  54 static union uvh_apicid uvh_apicid;
  55 int uv_min_hub_revision_id;
  56 EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
  57 unsigned int uv_apicid_hibits;
  58 EXPORT_SYMBOL_GPL(uv_apicid_hibits);
  59 static DEFINE_SPINLOCK(uv_nmi_lock);
  60
  61 static unsigned long __init uv_early_read_mmr(unsigned long addr)
  62 {
  63         unsigned long val, *mmr;
  64
  65         mmr = early_ioremap(UV_LOCAL_MMR_BASE | addr, sizeof(*mmr));
  66         val = *mmr;
  67         early_iounmap(mmr, sizeof(*mmr));
  68         return val;
  69 }
  70
  71 static inline bool is_GRU_range(u64 start, u64 end)
  72 {
  73         return start >= gru_start_paddr && end <= gru_end_paddr;
  74 }
  75
  76 static bool uv_is_untracked_pat_range(u64 start, u64 end)
  77 {
  78         return is_ISA_range(start, end) || is_GRU_range(start, end);
  79 }
  80
  81 static int __init early_get_pnodeid(void)
  82 {
  83         union uvh_node_id_u node_id;
  84         union uvh_rh_gam_config_mmr_u  m_n_config;
  85         int pnode;
  86
  87         /* Currently, all blades have same revision number */
  88         node_id.v = uv_early_read_mmr(UVH_NODE_ID);
  89         m_n_config.v = uv_early_read_mmr(UVH_RH_GAM_CONFIG_MMR);
  90         uv_min_hub_revision_id = node_id.s.revision;
  91
  92         pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1);
  93         return pnode;
  94 }
  95
  96 static void __init early_get_apic_pnode_shift(void)
  97 {
  98         uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
  99         if (!uvh_apicid.v)
 100                 /*
 101                  * Old bios, use default value
 102                  */
 103                 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT;
 104 }
 105
 106 /*
 107  * Add an extra bit as dictated by bios to the destination apicid of
 108  * interrupts potentially passing through the UV HUB.  This prevents
 109  * a deadlock between interrupts and IO port operations.
 110  */
 111 static void __init uv_set_apicid_hibit(void)
 112 {
 113         union uvh_lb_target_physical_apic_id_mask_u apicid_mask;
 114
 115         apicid_mask.v = uv_early_read_mmr(UVH_LB_TARGET_PHYSICAL_APIC_ID_MASK);
 116         uv_apicid_hibits = apicid_mask.s.bit_enables & UV_APICID_HIBIT_MASK;
 117 }
 118
 119 static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 120 {
 121         int pnodeid;
 122
 123         if (!strcmp(oem_id, "SGI")) {
 124                 pnodeid = early_get_pnodeid();
 125                 early_get_apic_pnode_shift();
 126                 x86_platform.is_untracked_pat_range =  uv_is_untracked_pat_range;
 127                 x86_platform.nmi_init = uv_nmi_init;
 128                 if (!strcmp(oem_table_id, "UVL"))
 129                         uv_system_type = UV_LEGACY_APIC;
 130                 else if (!strcmp(oem_table_id, "UVX"))
 131                         uv_system_type = UV_X2APIC;
 132                 else if (!strcmp(oem_table_id, "UVH")) {
 133                         __this_cpu_write(x2apic_extra_bits,
 134                                 pnodeid << uvh_apicid.s.pnode_shift);
 135                         uv_system_type = UV_NON_UNIQUE_APIC;
 136                         uv_set_apicid_hibit();
 137                         return 1;
 138                 }
 139         }
 140         return 0;
 141 }
 142
 143 enum uv_system_type get_uv_system_type(void)
 144 {
 145         return uv_system_type;
 146 }
 147
 148 int is_uv_system(void)
 149 {
 150         return uv_system_type != UV_NONE;
 151 }
 152 EXPORT_SYMBOL_GPL(is_uv_system);
 153
 154 DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info);
 155 EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info);
 156
 157 struct uv_blade_info *uv_blade_info;
 158 EXPORT_SYMBOL_GPL(uv_blade_info);
 159
 160 short *uv_node_to_blade;
 161 EXPORT_SYMBOL_GPL(uv_node_to_blade);
 162
 163 short *uv_cpu_to_blade;
 164 EXPORT_SYMBOL_GPL(uv_cpu_to_blade);
 165
 166 short uv_possible_blades;
 167 EXPORT_SYMBOL_GPL(uv_possible_blades);
 168
 169 unsigned long sn_rtc_cycles_per_second;
 170 EXPORT_SYMBOL(sn_rtc_cycles_per_second);
 171
 172 static const struct cpumask *uv_target_cpus(void)
 173 {
 174         return cpu_online_mask;
 175 }
 176
 177 static void uv_vector_allocation_domain(int cpu, struct cpumask *retmask)
 178 {
 179         cpumask_clear(retmask);
 180         cpumask_set_cpu(cpu, retmask);
 181 }
 182
 183 static int __cpuinit uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
 184 {
 185 #ifdef CONFIG_SMP
 186         unsigned long val;
 187         int pnode;
 188
 189         pnode = uv_apicid_to_pnode(phys_apicid);
 190         phys_apicid |= uv_apicid_hibits;
 191         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 192             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 193             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 194             APIC_DM_INIT;
 195         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 196         mdelay(10);
 197
 198         val = (1UL << UVH_IPI_INT_SEND_SHFT) |
 199             (phys_apicid << UVH_IPI_INT_APIC_ID_SHFT) |
 200             ((start_rip << UVH_IPI_INT_VECTOR_SHFT) >> 12) |
 201             APIC_DM_STARTUP;
 202         uv_write_global_mmr64(pnode, UVH_IPI_INT, val);
 203
 204         atomic_set(&init_deasserted, 1);
 205 #endif
 206         return 0;
 207 }
 208
 209 static void uv_send_IPI_one(int cpu, int vector)
 210 {
 211         unsigned long apicid;
 212         int pnode;
 213
 214         apicid = per_cpu(x86_cpu_to_apicid, cpu);
 215         pnode = uv_apicid_to_pnode(apicid);
 216         uv_hub_send_ipi(pnode, apicid, vector);
 217 }
 218
 219 static void uv_send_IPI_mask(const struct cpumask *mask, int vector)
 220 {
 221         unsigned int cpu;
 222
 223         for_each_cpu(cpu, mask)
 224                 uv_send_IPI_one(cpu, vector);
 225 }
 226
 227 static void uv_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
 228 {
 229         unsigned int this_cpu = smp_processor_id();
 230         unsigned int cpu;
 231
 232         for_each_cpu(cpu, mask) {
 233                 if (cpu != this_cpu)
 234                         uv_send_IPI_one(cpu, vector);
 235         }
 236 }
 237
 238 static void uv_send_IPI_allbutself(int vector)
 239 {
 240         unsigned int this_cpu = smp_processor_id();
 241         unsigned int cpu;
 242
 243         for_each_online_cpu(cpu) {
 244                 if (cpu != this_cpu)
 245                         uv_send_IPI_one(cpu, vector);
 246         }
 247 }
 248
 249 static void uv_send_IPI_all(int vector)
 250 {
 251         uv_send_IPI_mask(cpu_online_mask, vector);
 252 }
 253
 254 static int uv_apic_id_registered(void)
 255 {
 256         return 1;
 257 }
 258
 259 static void uv_init_apic_ldr(void)
 260 {
 261 }
 262
 263 static unsigned int uv_cpu_mask_to_apicid(const struct cpumask *cpumask)
 264 {
 265         /*
 266          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 267          * May as well be the first.
 268          */
 269         int cpu = cpumask_first(cpumask);
 270
 271         if ((unsigned)cpu < nr_cpu_ids)
 272                 return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
 273         else
 274                 return BAD_APICID;
 275 }
 276
 277 static unsigned int
 278 uv_cpu_mask_to_apicid_and(const struct cpumask *cpumask,
 279                           const struct cpumask *andmask)
 280 {
 281         int cpu;
 282
 283         /*
 284          * We're using fixed IRQ delivery, can only return one phys APIC ID.
 285          * May as well be the first.
 286          */
 287         for_each_cpu_and(cpu, cpumask, andmask) {
 288                 if (cpumask_test_cpu(cpu, cpu_online_mask))
 289                         break;
 290         }
 291         return per_cpu(x86_cpu_to_apicid, cpu) | uv_apicid_hibits;
 292 }
 293
 294 static unsigned int x2apic_get_apic_id(unsigned long x)
 295 {
 296         unsigned int id;
 297
 298         WARN_ON(preemptible() && num_online_cpus() > 1);
 299         id = x | __this_cpu_read(x2apic_extra_bits);
 300
 301         return id;
 302 }
 303
 304 static unsigned long set_apic_id(unsigned int id)
 305 {
 306         unsigned long x;
 307
 308         /* maskout x2apic_extra_bits ? */
 309         x = id;
 310         return x;
 311 }
 312
 313 static unsigned int uv_read_apic_id(void)
 314 {
 315
 316         return x2apic_get_apic_id(apic_read(APIC_ID));
 317 }
 318
 319 static int uv_phys_pkg_id(int initial_apicid, int index_msb)
 320 {
 321         return uv_read_apic_id() >> index_msb;
 322 }
 323
 324 static void uv_send_IPI_self(int vector)
 325 {
 326         apic_write(APIC_SELF_IPI, vector);
 327 }
 328
 329 struct apic __refdata apic_x2apic_uv_x = {
 330
 331         .name                           = "UV large system",
 332         .probe                          = NULL,
 333         .acpi_madt_oem_check            = uv_acpi_madt_oem_check,
 334         .apic_id_registered             = uv_apic_id_registered,
 335
 336         .irq_delivery_mode              = dest_Fixed,
 337         .irq_dest_mode                  = 0, /* physical */
 338
 339         .target_cpus                    = uv_target_cpus,
 340         .disable_esr                    = 0,
 341         .dest_logical                   = APIC_DEST_LOGICAL,
 342         .check_apicid_used              = NULL,
 343         .check_apicid_present           = NULL,
 344
 345         .vector_allocation_domain       = uv_vector_allocation_domain,
 346         .init_apic_ldr                  = uv_init_apic_ldr,
 347
 348         .ioapic_phys_id_map             = NULL,
 349         .setup_apic_routing             = NULL,
 350         .multi_timer_check              = NULL,
 351         .cpu_present_to_apicid          = default_cpu_present_to_apicid,
 352         .apicid_to_cpu_present          = NULL,
 353         .setup_portio_remap             = NULL,
 354         .check_phys_apicid_present      = default_check_phys_apicid_present,
 355         .enable_apic_mode               = NULL,
 356         .phys_pkg_id                    = uv_phys_pkg_id,
 357         .mps_oem_check                  = NULL,
 358
 359         .get_apic_id                    = x2apic_get_apic_id,
 360         .set_apic_id                    = set_apic_id,
 361         .apic_id_mask                   = 0xFFFFFFFFu,
 362
 363         .cpu_mask_to_apicid             = uv_cpu_mask_to_apicid,
 364         .cpu_mask_to_apicid_and         = uv_cpu_mask_to_apicid_and,
 365
 366         .send_IPI_mask                  = uv_send_IPI_mask,
 367         .send_IPI_mask_allbutself       = uv_send_IPI_mask_allbutself,
 368         .send_IPI_allbutself            = uv_send_IPI_allbutself,
 369         .send_IPI_all                   = uv_send_IPI_all,
 370         .send_IPI_self                  = uv_send_IPI_self,
 371
 372         .wakeup_secondary_cpu           = uv_wakeup_secondary,
 373         .trampoline_phys_low            = DEFAULT_TRAMPOLINE_PHYS_LOW,
 374         .trampoline_phys_high           = DEFAULT_TRAMPOLINE_PHYS_HIGH,
 375         .wait_for_init_deassert         = NULL,
 376         .smp_callin_clear_local_apic    = NULL,
 377         .inquire_remote_apic            = NULL,
 378
 379         .read                           = native_apic_msr_read,
 380         .write                          = native_apic_msr_write,
 381         .icr_read                       = native_x2apic_icr_read,
 382         .icr_write                      = native_x2apic_icr_write,
 383         .wait_icr_idle                  = native_x2apic_wait_icr_idle,
 384         .safe_wait_icr_idle             = native_safe_x2apic_wait_icr_idle,
 385 };
 386
 387 static __cpuinit void set_x2apic_extra_bits(int pnode)
 388 {
 389         __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
 390 }
 391
 392 /*
 393  * Called on boot cpu.
 394  */
 395 static __init int boot_pnode_to_blade(int pnode)
 396 {
 397         int blade;
 398
 399         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 400                 if (pnode == uv_blade_info[blade].pnode)
 401                         return blade;
 402         BUG();
 403 }
 404
 405 struct redir_addr {
 406         unsigned long redirect;
 407         unsigned long alias;
 408 };
 409
 410 #define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
 411
 412 static __initdata struct redir_addr redir_addrs[] = {
 413         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
 414         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
 415         {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
 416 };
 417
 418 static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
 419 {
 420         union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
 421         union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
 422         int i;
 423
 424         for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) {
 425                 alias.v = uv_read_local_mmr(redir_addrs[i].alias);
 426                 if (alias.s.enable && alias.s.base == 0) {
 427                         *size = (1UL << alias.s.m_alias);
 428                         redirect.v = uv_read_local_mmr(redir_addrs[i].redirect);
 429                         *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT;
 430                         return;
 431                 }
 432         }
 433         *base = *size = 0;
 434 }
 435
 436 enum map_type {map_wb, map_uc};
 437
 438 static __init void map_high(char *id, unsigned long base, int pshift,
 439                         int bshift, int max_pnode, enum map_type map_type)
 440 {
 441         unsigned long bytes, paddr;
 442
 443         paddr = base << pshift;
 444         bytes = (1UL << bshift) * (max_pnode + 1);
 445         printk(KERN_INFO "UV: Map %s_HI 0x%lx - 0x%lx\n", id, paddr,
 446                                                 paddr + bytes);
 447         if (map_type == map_uc)
 448                 init_extra_mapping_uc(paddr, bytes);
 449         else
 450                 init_extra_mapping_wb(paddr, bytes);
 451
 452 }
 453 static __init void map_gru_high(int max_pnode)
 454 {
 455         union uvh_rh_gam_gru_overlay_config_mmr_u gru;
 456         int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
 457
 458         gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
 459         if (gru.s.enable) {
 460                 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb);
 461                 gru_start_paddr = ((u64)gru.s.base << shift);
 462                 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
 463
 464         }
 465 }
 466
 467 static __init void map_mmr_high(int max_pnode)
 468 {
 469         union uvh_rh_gam_mmr_overlay_config_mmr_u mmr;
 470         int shift = UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT;
 471
 472         mmr.v = uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR);
 473         if (mmr.s.enable)
 474                 map_high("MMR", mmr.s.base, shift, shift, max_pnode, map_uc);
 475 }
 476
 477 static __init void map_mmioh_high(int max_pnode)
 478 {
 479         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 480         int shift = UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT;
 481
 482         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 483         if (mmioh.s.enable)
 484                 map_high("MMIOH", mmioh.s.base, shift, mmioh.s.m_io,
 485                         max_pnode, map_uc);
 486 }
 487
 488 static __init void map_low_mmrs(void)
 489 {
 490         init_extra_mapping_uc(UV_GLOBAL_MMR32_BASE, UV_GLOBAL_MMR32_SIZE);
 491         init_extra_mapping_uc(UV_LOCAL_MMR_BASE, UV_LOCAL_MMR_SIZE);
 492 }
 493
 494 static __init void uv_rtc_init(void)
 495 {
 496         long status;
 497         u64 ticks_per_sec;
 498
 499         status = uv_bios_freq_base(BIOS_FREQ_BASE_REALTIME_CLOCK,
 500                                         &ticks_per_sec);
 501         if (status != BIOS_STATUS_SUCCESS || ticks_per_sec < 100000) {
 502                 printk(KERN_WARNING
 503                         "unable to determine platform RTC clock frequency, "
 504                         "guessing.\n");
 505                 /* BIOS gives wrong value for clock freq. so guess */
 506                 sn_rtc_cycles_per_second = 1000000000000UL / 30000UL;
 507         } else
 508                 sn_rtc_cycles_per_second = ticks_per_sec;
 509 }
 510
 511 /*
 512  * percpu heartbeat timer
 513  */
 514 static void uv_heartbeat(unsigned long ignored)
 515 {
 516         struct timer_list *timer = &uv_hub_info->scir.timer;
 517         unsigned char bits = uv_hub_info->scir.state;
 518
 519         /* flip heartbeat bit */
 520         bits ^= SCIR_CPU_HEARTBEAT;
 521
 522         /* is this cpu idle? */
 523         if (idle_cpu(raw_smp_processor_id()))
 524                 bits &= ~SCIR_CPU_ACTIVITY;
 525         else
 526                 bits |= SCIR_CPU_ACTIVITY;
 527
 528         /* update system controller interface reg */
 529         uv_set_scir_bits(bits);
 530
 531         /* enable next timer period */
 532         mod_timer_pinned(timer, jiffies + SCIR_CPU_HB_INTERVAL);
 533 }
 534
 535 static void __cpuinit uv_heartbeat_enable(int cpu)
 536 {
 537         while (!uv_cpu_hub_info(cpu)->scir.enabled) {
 538                 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer;
 539
 540                 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
 541                 setup_timer(timer, uv_heartbeat, cpu);
 542                 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
 543                 add_timer_on(timer, cpu);
 544                 uv_cpu_hub_info(cpu)->scir.enabled = 1;
 545
 546                 /* also ensure that boot cpu is enabled */
 547                 cpu = 0;
 548         }
 549 }
 550
 551 #ifdef CONFIG_HOTPLUG_CPU
 552 static void __cpuinit uv_heartbeat_disable(int cpu)
 553 {
 554         if (uv_cpu_hub_info(cpu)->scir.enabled) {
 555                 uv_cpu_hub_info(cpu)->scir.enabled = 0;
 556                 del_timer(&uv_cpu_hub_info(cpu)->scir.timer);
 557         }
 558         uv_set_cpu_scir_bits(cpu, 0xff);
 559 }
 560
 561 /*
 562  * cpu hotplug notifier
 563  */
 564 static __cpuinit int uv_scir_cpu_notify(struct notifier_block *self,
 565                                        unsigned long action, void *hcpu)
 566 {
 567         long cpu = (long)hcpu;
 568
 569         switch (action) {
 570         case CPU_ONLINE:
 571                 uv_heartbeat_enable(cpu);
 572                 break;
 573         case CPU_DOWN_PREPARE:
 574                 uv_heartbeat_disable(cpu);
 575                 break;
 576         default:
 577                 break;
 578         }
 579         return NOTIFY_OK;
 580 }
 581
 582 static __init void uv_scir_register_cpu_notifier(void)
 583 {
 584         hotcpu_notifier(uv_scir_cpu_notify, 0);
 585 }
 586
 587 #else /* !CONFIG_HOTPLUG_CPU */
 588
 589 static __init void uv_scir_register_cpu_notifier(void)
 590 {
 591 }
 592
 593 static __init int uv_init_heartbeat(void)
 594 {
 595         int cpu;
 596
 597         if (is_uv_system())
 598                 for_each_online_cpu(cpu)
 599                         uv_heartbeat_enable(cpu);
 600         return 0;
 601 }
 602
 603 late_initcall(uv_init_heartbeat);
 604
 605 #endif /* !CONFIG_HOTPLUG_CPU */
 606
 607 /* Direct Legacy VGA I/O traffic to designated IOH */
 608 int uv_set_vga_state(struct pci_dev *pdev, bool decode,
 609                       unsigned int command_bits, bool change_bridge)
 610 {
 611         int domain, bus, rc;
 612
 613         PR_DEVEL("devfn %x decode %d cmd %x chg_brdg %d\n",
 614                         pdev->devfn, decode, command_bits, change_bridge);
 615
 616         if (!change_bridge)
 617                 return 0;
 618
 619         if ((command_bits & PCI_COMMAND_IO) == 0)
 620                 return 0;
 621
 622         domain = pci_domain_nr(pdev->bus);
 623         bus = pdev->bus->number;
 624
 625         rc = uv_bios_set_legacy_vga_target(decode, domain, bus);
 626         PR_DEVEL("vga decode %d %x:%x, rc: %d\n", decode, domain, bus, rc);
 627
 628         return rc;
 629 }
 630
 631 /*
 632  * Called on each cpu to initialize the per_cpu UV data area.
 633  * FIXME: hotplug not supported yet
 634  */
 635 void __cpuinit uv_cpu_init(void)
 636 {
 637         /* CPU 0 initilization will be done via uv_system_init. */
 638         if (!uv_blade_info)
 639                 return;
 640
 641         uv_blade_info[uv_numa_blade_id()].nr_online_cpus++;
 642
 643         if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
 644                 set_x2apic_extra_bits(uv_hub_info->pnode);
 645 }
 646
 647 /*
 648  * When NMI is received, print a stack trace.
 649  */
 650 int uv_handle_nmi(struct notifier_block *self, unsigned long reason, void *data)
 651 {
 652         unsigned long real_uv_nmi;
 653         int bid;
 654
 655         if (reason != DIE_NMIUNKNOWN)
 656                 return NOTIFY_OK;
 657
 658         if (in_crash_kexec)
 659                 /* do nothing if entering the crash kernel */
 660                 return NOTIFY_OK;
 661
 662         /*
 663          * Each blade has an MMR that indicates when an NMI has been sent
 664          * to cpus on the blade. If an NMI is detected, atomically
 665          * clear the MMR and update a per-blade NMI count used to
 666          * cause each cpu on the blade to notice a new NMI.
 667          */
 668         bid = uv_numa_blade_id();
 669         real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
 670
 671         if (unlikely(real_uv_nmi)) {
 672                 spin_lock(&uv_blade_info[bid].nmi_lock);
 673                 real_uv_nmi = (uv_read_local_mmr(UVH_NMI_MMR) & UV_NMI_PENDING_MASK);
 674                 if (real_uv_nmi) {
 675                         uv_blade_info[bid].nmi_count++;
 676                         uv_write_local_mmr(UVH_NMI_MMR_CLEAR, UV_NMI_PENDING_MASK);
 677                 }
 678                 spin_unlock(&uv_blade_info[bid].nmi_lock);
 679         }
 680
 681         if (likely(__get_cpu_var(cpu_last_nmi_count) == uv_blade_info[bid].nmi_count))
 682                 return NOTIFY_DONE;
 683
 684         __get_cpu_var(cpu_last_nmi_count) = uv_blade_info[bid].nmi_count;
 685
 686         /*
 687          * Use a lock so only one cpu prints at a time.
 688          * This prevents intermixed output.
 689          */
 690         spin_lock(&uv_nmi_lock);
 691         pr_info("UV NMI stack dump cpu %u:\n", smp_processor_id());
 692         dump_stack();
 693         spin_unlock(&uv_nmi_lock);
 694
 695         return NOTIFY_STOP;
 696 }
 697
 698 static struct notifier_block uv_dump_stack_nmi_nb = {
 699         .notifier_call  = uv_handle_nmi,
 700         .priority = NMI_LOCAL_LOW_PRIOR - 1,
 701 };
 702
 703 void uv_register_nmi_notifier(void)
 704 {
 705         if (register_die_notifier(&uv_dump_stack_nmi_nb))
 706                 printk(KERN_WARNING "UV NMI handler failed to register\n");
 707 }
 708
 709 void uv_nmi_init(void)
 710 {
 711         unsigned int value;
 712
 713         /*
 714          * Unmask NMI on all cpus
 715          */
 716         value = apic_read(APIC_LVT1) | APIC_DM_NMI;
 717         value &= ~APIC_LVT_MASKED;
 718         apic_write(APIC_LVT1, value);
 719 }
 720
 721 void __init uv_system_init(void)
 722 {
 723         union uvh_rh_gam_config_mmr_u  m_n_config;
 724         union uvh_rh_gam_mmioh_overlay_config_mmr_u mmioh;
 725         union uvh_node_id_u node_id;
 726         unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
 727         int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val, n_io;
 728         int gnode_extra, max_pnode = 0;
 729         unsigned long mmr_base, present, paddr;
 730         unsigned short pnode_mask, pnode_io_mask;
 731
 732         map_low_mmrs();
 733
 734         m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR );
 735         m_val = m_n_config.s.m_skt;
 736         n_val = m_n_config.s.n_skt;
 737         mmioh.v = uv_read_local_mmr(UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR);
 738         n_io = mmioh.s.n_io;
 739         mmr_base =
 740             uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
 741             ~UV_MMR_ENABLE;
 742         pnode_mask = (1 << n_val) - 1;
 743         pnode_io_mask = (1 << n_io) - 1;
 744
 745         node_id.v = uv_read_local_mmr(UVH_NODE_ID);
 746         gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1;
 747         gnode_upper = ((unsigned long)gnode_extra  << m_val);
 748         printk(KERN_INFO "UV: N %d, M %d, N_IO: %d, gnode_upper 0x%lx, gnode_extra 0x%x, pnode_mask 0x%x, pnode_io_mask 0x%x\n",
 749                         n_val, m_val, n_io, gnode_upper, gnode_extra, pnode_mask, pnode_io_mask);
 750
 751         printk(KERN_DEBUG "UV: global MMR base 0x%lx\n", mmr_base);
 752
 753         for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++)
 754                 uv_possible_blades +=
 755                   hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
 756         printk(KERN_DEBUG "UV: Found %d blades\n", uv_num_possible_blades());
 757
 758         bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades();
 759         uv_blade_info = kzalloc(bytes, GFP_KERNEL);
 760         BUG_ON(!uv_blade_info);
 761
 762         for (blade = 0; blade < uv_num_possible_blades(); blade++)
 763                 uv_blade_info[blade].memory_nid = -1;
 764
 765         get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size);
 766
 767         bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes();
 768         uv_node_to_blade = kmalloc(bytes, GFP_KERNEL);
 769         BUG_ON(!uv_node_to_blade);
 770         memset(uv_node_to_blade, 255, bytes);
 771
 772         bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus();
 773         uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL);
 774         BUG_ON(!uv_cpu_to_blade);
 775         memset(uv_cpu_to_blade, 255, bytes);
 776
 777         blade = 0;
 778         for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
 779                 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
 780                 for (j = 0; j < 64; j++) {
 781                         if (!test_bit(j, &present))
 782                                 continue;
 783                         pnode = (i * 64 + j) & pnode_mask;
 784                         uv_blade_info[blade].pnode = pnode;
 785                         uv_blade_info[blade].nr_possible_cpus = 0;
 786                         uv_blade_info[blade].nr_online_cpus = 0;
 787                         spin_lock_init(&uv_blade_info[blade].nmi_lock);
 788                         max_pnode = max(pnode, max_pnode);
 789                         blade++;
 790                 }
 791         }
 792
 793         uv_bios_init();
 794         uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
 795                             &sn_region_size, &system_serial_number);
 796         uv_rtc_init();
 797
 798         for_each_present_cpu(cpu) {
 799                 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
 800
 801                 nid = cpu_to_node(cpu);
 802                 /*
 803                  * apic_pnode_shift must be set before calling uv_apicid_to_pnode();
 804                  */
 805                 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
 806                 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
 807                 pnode = uv_apicid_to_pnode(apicid);
 808                 blade = boot_pnode_to_blade(pnode);
 809                 lcpu = uv_blade_info[blade].nr_possible_cpus;
 810                 uv_blade_info[blade].nr_possible_cpus++;
 811
 812                 /* Any node on the blade, else will contain -1. */
 813                 uv_blade_info[blade].memory_nid = nid;
 814
 815                 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base;
 816                 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size;
 817                 uv_cpu_hub_info(cpu)->m_val = m_val;
 818                 uv_cpu_hub_info(cpu)->n_val = n_val;
 819                 uv_cpu_hub_info(cpu)->numa_blade_id = blade;
 820                 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
 821                 uv_cpu_hub_info(cpu)->pnode = pnode;
 822                 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
 823                 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
 824                 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
 825                 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
 826                 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
 827                 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
 828                 uv_node_to_blade[nid] = blade;
 829                 uv_cpu_to_blade[cpu] = blade;
 830         }
 831
 832         /* Add blade/pnode info for nodes without cpus */
 833         for_each_online_node(nid) {
 834                 if (uv_node_to_blade[nid] >= 0)
 835                         continue;
 836                 paddr = node_start_pfn(nid) << PAGE_SHIFT;
 837                 paddr = uv_soc_phys_ram_to_gpa(paddr);
 838                 pnode = (paddr >> m_val) & pnode_mask;
 839                 blade = boot_pnode_to_blade(pnode);
 840                 uv_node_to_blade[nid] = blade;
 841         }
 842
 843         map_gru_high(max_pnode);
 844         map_mmr_high(max_pnode);
 845         map_mmioh_high(max_pnode & pnode_io_mask);
 846
 847         uv_cpu_init();
 848         uv_scir_register_cpu_notifier();
 849         uv_register_nmi_notifier();
 850         proc_mkdir("sgi_uv", NULL);
 851
 852         /* register Legacy VGA I/O redirection handler */
 853         pci_register_set_vga_state(uv_set_vga_state);
 854
 855         /*
 856          * For a kdump kernel the reset must be BOOT_ACPI, not BOOT_EFI, as
 857          * EFI is not enabled in the kdump kernel.
 858          */
 859         if (is_kdump_kernel())
 860                 reboot_type = BOOT_ACPI;
 861 }