arch/x86/kernel/apic/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/init.h>
  26 #include <linux/delay.h>
  27 #include <linux/sched.h>
  28 #include <linux/pci.h>
  29 #include <linux/mc146818rtc.h>
  30 #include <linux/compiler.h>
  31 #include <linux/acpi.h>
  32 #include <linux/module.h>
  33 #include <linux/sysdev.h>
  34 #include <linux/msi.h>
  35 #include <linux/htirq.h>
  36 #include <linux/freezer.h>
  37 #include <linux/kthread.h>
  38 #include <linux/jiffies.h>      /* time_after() */
  39 #ifdef CONFIG_ACPI
  40 #include <acpi/acpi_bus.h>
  41 #endif
  42 #include <linux/bootmem.h>
  43 #include <linux/dmar.h>
  44 #include <linux/hpet.h>
  45
  46 #include <asm/idle.h>
  47 #include <asm/io.h>
  48 #include <asm/smp.h>
  49 #include <asm/cpu.h>
  50 #include <asm/desc.h>
  51 #include <asm/proto.h>
  52 #include <asm/acpi.h>
  53 #include <asm/dma.h>
  54 #include <asm/timer.h>
  55 #include <asm/i8259.h>
  56 #include <asm/nmi.h>
  57 #include <asm/msidef.h>
  58 #include <asm/hypertransport.h>
  59 #include <asm/setup.h>
  60 #include <asm/irq_remapping.h>
  61 #include <asm/hpet.h>
  62 #include <asm/uv/uv_hub.h>
  63 #include <asm/uv/uv_irq.h>
  64
  65 #include <asm/apic.h>
  66
  67 #define __apicdebuginit(type) static type __init
  68
  69 /*
  70  *      Is the SiS APIC rmw bug present ?
  71  *      -1 = don't know, 0 = no, 1 = yes
  72  */
  73 int sis_apic_bug = -1;
  74
  75 static DEFINE_SPINLOCK(ioapic_lock);
  76 static DEFINE_SPINLOCK(vector_lock);
  77
  78 /*
  79  * # of IRQ routing registers
  80  */
  81 int nr_ioapic_registers[MAX_IO_APICS];
  82
  83 /* I/O APIC entries */
  84 struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
  85 int nr_ioapics;
  86
  87 /* MP IRQ source entries */
  88 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
  89
  90 /* # of MP IRQ source entries */
  91 int mp_irq_entries;
  92
  93 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
  94 int mp_bus_id_to_type[MAX_MP_BUSSES];
  95 #endif
  96
  97 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  98
  99 int skip_ioapic_setup;
 100
 101 void arch_disable_smp_support(void)
 102 {
 103 #ifdef CONFIG_PCI
 104         noioapicquirk = 1;
 105         noioapicreroute = -1;
 106 #endif
 107         skip_ioapic_setup = 1;
 108 }
 109
 110 static int __init parse_noapic(char *str)
 111 {
 112         /* disable IO-APIC */
 113         arch_disable_smp_support();
 114         return 0;
 115 }
 116 early_param("noapic", parse_noapic);
 117
 118 struct irq_pin_list;
 119
 120 /*
 121  * This is performance-critical, we want to do it O(1)
 122  *
 123  * the indexing order of this array favors 1:1 mappings
 124  * between pins and IRQs.
 125  */
 126
 127 struct irq_pin_list {
 128         int apic, pin;
 129         struct irq_pin_list *next;
 130 };
 131
 132 static struct irq_pin_list *get_one_free_irq_2_pin(int cpu)
 133 {
 134         struct irq_pin_list *pin;
 135         int node;
 136
 137         node = cpu_to_node(cpu);
 138
 139         pin = kzalloc_node(sizeof(*pin), GFP_ATOMIC, node);
 140
 141         return pin;
 142 }
 143
 144 struct irq_cfg {
 145         struct irq_pin_list *irq_2_pin;
 146         cpumask_var_t domain;
 147         cpumask_var_t old_domain;
 148         unsigned move_cleanup_count;
 149         u8 vector;
 150         u8 move_in_progress : 1;
 151 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 152         u8 move_desc_pending : 1;
 153 #endif
 154 };
 155
 156 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
 157 #ifdef CONFIG_SPARSE_IRQ
 158 static struct irq_cfg irq_cfgx[] = {
 159 #else
 160 static struct irq_cfg irq_cfgx[NR_IRQS] = {
 161 #endif
 162         [0]  = { .vector = IRQ0_VECTOR,  },
 163         [1]  = { .vector = IRQ1_VECTOR,  },
 164         [2]  = { .vector = IRQ2_VECTOR,  },
 165         [3]  = { .vector = IRQ3_VECTOR,  },
 166         [4]  = { .vector = IRQ4_VECTOR,  },
 167         [5]  = { .vector = IRQ5_VECTOR,  },
 168         [6]  = { .vector = IRQ6_VECTOR,  },
 169         [7]  = { .vector = IRQ7_VECTOR,  },
 170         [8]  = { .vector = IRQ8_VECTOR,  },
 171         [9]  = { .vector = IRQ9_VECTOR,  },
 172         [10] = { .vector = IRQ10_VECTOR, },
 173         [11] = { .vector = IRQ11_VECTOR, },
 174         [12] = { .vector = IRQ12_VECTOR, },
 175         [13] = { .vector = IRQ13_VECTOR, },
 176         [14] = { .vector = IRQ14_VECTOR, },
 177         [15] = { .vector = IRQ15_VECTOR, },
 178 };
 179
 180 int __init arch_early_irq_init(void)
 181 {
 182         struct irq_cfg *cfg;
 183         struct irq_desc *desc;
 184         int count;
 185         int i;
 186
 187         cfg = irq_cfgx;
 188         count = ARRAY_SIZE(irq_cfgx);
 189
 190         for (i = 0; i < count; i++) {
 191                 desc = irq_to_desc(i);
 192                 desc->chip_data = &cfg[i];
 193                 alloc_bootmem_cpumask_var(&cfg[i].domain);
 194                 alloc_bootmem_cpumask_var(&cfg[i].old_domain);
 195                 if (i < NR_IRQS_LEGACY)
 196                         cpumask_setall(cfg[i].domain);
 197         }
 198
 199         return 0;
 200 }
 201
 202 #ifdef CONFIG_SPARSE_IRQ
 203 static struct irq_cfg *irq_cfg(unsigned int irq)
 204 {
 205         struct irq_cfg *cfg = NULL;
 206         struct irq_desc *desc;
 207
 208         desc = irq_to_desc(irq);
 209         if (desc)
 210                 cfg = desc->chip_data;
 211
 212         return cfg;
 213 }
 214
 215 static struct irq_cfg *get_one_free_irq_cfg(int cpu)
 216 {
 217         struct irq_cfg *cfg;
 218         int node;
 219
 220         node = cpu_to_node(cpu);
 221
 222         cfg = kzalloc_node(sizeof(*cfg), GFP_ATOMIC, node);
 223         if (cfg) {
 224                 if (!alloc_cpumask_var_node(&cfg->domain, GFP_ATOMIC, node)) {
 225                         kfree(cfg);
 226                         cfg = NULL;
 227                 } else if (!alloc_cpumask_var_node(&cfg->old_domain,
 228                                                           GFP_ATOMIC, node)) {
 229                         free_cpumask_var(cfg->domain);
 230                         kfree(cfg);
 231                         cfg = NULL;
 232                 } else {
 233                         cpumask_clear(cfg->domain);
 234                         cpumask_clear(cfg->old_domain);
 235                 }
 236         }
 237
 238         return cfg;
 239 }
 240
 241 int arch_init_chip_data(struct irq_desc *desc, int cpu)
 242 {
 243         struct irq_cfg *cfg;
 244
 245         cfg = desc->chip_data;
 246         if (!cfg) {
 247                 desc->chip_data = get_one_free_irq_cfg(cpu);
 248                 if (!desc->chip_data) {
 249                         printk(KERN_ERR "can not alloc irq_cfg\n");
 250                         BUG_ON(1);
 251                 }
 252         }
 253
 254         return 0;
 255 }
 256
 257 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
 258
 259 static void
 260 init_copy_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg, int cpu)
 261 {
 262         struct irq_pin_list *old_entry, *head, *tail, *entry;
 263
 264         cfg->irq_2_pin = NULL;
 265         old_entry = old_cfg->irq_2_pin;
 266         if (!old_entry)
 267                 return;
 268
 269         entry = get_one_free_irq_2_pin(cpu);
 270         if (!entry)
 271                 return;
 272
 273         entry->apic     = old_entry->apic;
 274         entry->pin      = old_entry->pin;
 275         head            = entry;
 276         tail            = entry;
 277         old_entry       = old_entry->next;
 278         while (old_entry) {
 279                 entry = get_one_free_irq_2_pin(cpu);
 280                 if (!entry) {
 281                         entry = head;
 282                         while (entry) {
 283                                 head = entry->next;
 284                                 kfree(entry);
 285                                 entry = head;
 286                         }
 287                         /* still use the old one */
 288                         return;
 289                 }
 290                 entry->apic     = old_entry->apic;
 291                 entry->pin      = old_entry->pin;
 292                 tail->next      = entry;
 293                 tail            = entry;
 294                 old_entry       = old_entry->next;
 295         }
 296
 297         tail->next = NULL;
 298         cfg->irq_2_pin = head;
 299 }
 300
 301 static void free_irq_2_pin(struct irq_cfg *old_cfg, struct irq_cfg *cfg)
 302 {
 303         struct irq_pin_list *entry, *next;
 304
 305         if (old_cfg->irq_2_pin == cfg->irq_2_pin)
 306                 return;
 307
 308         entry = old_cfg->irq_2_pin;
 309
 310         while (entry) {
 311                 next = entry->next;
 312                 kfree(entry);
 313                 entry = next;
 314         }
 315         old_cfg->irq_2_pin = NULL;
 316 }
 317
 318 void arch_init_copy_chip_data(struct irq_desc *old_desc,
 319                                  struct irq_desc *desc, int cpu)
 320 {
 321         struct irq_cfg *cfg;
 322         struct irq_cfg *old_cfg;
 323
 324         cfg = get_one_free_irq_cfg(cpu);
 325
 326         if (!cfg)
 327                 return;
 328
 329         desc->chip_data = cfg;
 330
 331         old_cfg = old_desc->chip_data;
 332
 333         memcpy(cfg, old_cfg, sizeof(struct irq_cfg));
 334
 335         init_copy_irq_2_pin(old_cfg, cfg, cpu);
 336 }
 337
 338 static void free_irq_cfg(struct irq_cfg *old_cfg)
 339 {
 340         kfree(old_cfg);
 341 }
 342
 343 void arch_free_chip_data(struct irq_desc *old_desc, struct irq_desc *desc)
 344 {
 345         struct irq_cfg *old_cfg, *cfg;
 346
 347         old_cfg = old_desc->chip_data;
 348         cfg = desc->chip_data;
 349
 350         if (old_cfg == cfg)
 351                 return;
 352
 353         if (old_cfg) {
 354                 free_irq_2_pin(old_cfg, cfg);
 355                 free_irq_cfg(old_cfg);
 356                 old_desc->chip_data = NULL;
 357         }
 358 }
 359
 360 static void
 361 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 362 {
 363         struct irq_cfg *cfg = desc->chip_data;
 364
 365         if (!cfg->move_in_progress) {
 366                 /* it means that domain is not changed */
 367                 if (!cpumask_intersects(desc->affinity, mask))
 368                         cfg->move_desc_pending = 1;
 369         }
 370 }
 371 #endif
 372
 373 #else
 374 static struct irq_cfg *irq_cfg(unsigned int irq)
 375 {
 376         return irq < nr_irqs ? irq_cfgx + irq : NULL;
 377 }
 378
 379 #endif
 380
 381 #ifndef CONFIG_NUMA_MIGRATE_IRQ_DESC
 382 static inline void
 383 set_extra_move_desc(struct irq_desc *desc, const struct cpumask *mask)
 384 {
 385 }
 386 #endif
 387
 388 struct io_apic {
 389         unsigned int index;
 390         unsigned int unused[3];
 391         unsigned int data;
 392         unsigned int unused2[11];
 393         unsigned int eoi;
 394 };
 395
 396 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
 397 {
 398         return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
 399                 + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
 400 }
 401
 402 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
 403 {
 404         struct io_apic __iomem *io_apic = io_apic_base(apic);
 405         writel(vector, &io_apic->eoi);
 406 }
 407
 408 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
 409 {
 410         struct io_apic __iomem *io_apic = io_apic_base(apic);
 411         writel(reg, &io_apic->index);
 412         return readl(&io_apic->data);
 413 }
 414
 415 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
 416 {
 417         struct io_apic __iomem *io_apic = io_apic_base(apic);
 418         writel(reg, &io_apic->index);
 419         writel(value, &io_apic->data);
 420 }
 421
 422 /*
 423  * Re-write a value: to be used for read-modify-write
 424  * cycles where the read already set up the index register.
 425  *
 426  * Older SiS APIC requires we rewrite the index register
 427  */
 428 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
 429 {
 430         struct io_apic __iomem *io_apic = io_apic_base(apic);
 431
 432         if (sis_apic_bug)
 433                 writel(reg, &io_apic->index);
 434         writel(value, &io_apic->data);
 435 }
 436
 437 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
 438 {
 439         struct irq_pin_list *entry;
 440         unsigned long flags;
 441
 442         spin_lock_irqsave(&ioapic_lock, flags);
 443         entry = cfg->irq_2_pin;
 444         for (;;) {
 445                 unsigned int reg;
 446                 int pin;
 447
 448                 if (!entry)
 449                         break;
 450                 pin = entry->pin;
 451                 reg = io_apic_read(entry->apic, 0x10 + pin*2);
 452                 /* Is the remote IRR bit set? */
 453                 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
 454                         spin_unlock_irqrestore(&ioapic_lock, flags);
 455                         return true;
 456                 }
 457                 if (!entry->next)
 458                         break;
 459                 entry = entry->next;
 460         }
 461         spin_unlock_irqrestore(&ioapic_lock, flags);
 462
 463         return false;
 464 }
 465
 466 union entry_union {
 467         struct { u32 w1, w2; };
 468         struct IO_APIC_route_entry entry;
 469 };
 470
 471 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
 472 {
 473         union entry_union eu;
 474         unsigned long flags;
 475         spin_lock_irqsave(&ioapic_lock, flags);
 476         eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
 477         eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
 478         spin_unlock_irqrestore(&ioapic_lock, flags);
 479         return eu.entry;
 480 }
 481
 482 /*
 483  * When we write a new IO APIC routing entry, we need to write the high
 484  * word first! If the mask bit in the low word is clear, we will enable
 485  * the interrupt, and we need to make sure the entry is fully populated
 486  * before that happens.
 487  */
 488 static void
 489 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 490 {
 491         union entry_union eu;
 492         eu.entry = e;
 493         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 494         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 495 }
 496
 497 void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
 498 {
 499         unsigned long flags;
 500         spin_lock_irqsave(&ioapic_lock, flags);
 501         __ioapic_write_entry(apic, pin, e);
 502         spin_unlock_irqrestore(&ioapic_lock, flags);
 503 }
 504
 505 /*
 506  * When we mask an IO APIC routing entry, we need to write the low
 507  * word first, in order to set the mask bit before we change the
 508  * high bits!
 509  */
 510 static void ioapic_mask_entry(int apic, int pin)
 511 {
 512         unsigned long flags;
 513         union entry_union eu = { .entry.mask = 1 };
 514
 515         spin_lock_irqsave(&ioapic_lock, flags);
 516         io_apic_write(apic, 0x10 + 2*pin, eu.w1);
 517         io_apic_write(apic, 0x11 + 2*pin, eu.w2);
 518         spin_unlock_irqrestore(&ioapic_lock, flags);
 519 }
 520
 521 #ifdef CONFIG_SMP
 522 static void send_cleanup_vector(struct irq_cfg *cfg)
 523 {
 524         cpumask_var_t cleanup_mask;
 525
 526         if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
 527                 unsigned int i;
 528                 cfg->move_cleanup_count = 0;
 529                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 530                         cfg->move_cleanup_count++;
 531                 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
 532                         apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
 533         } else {
 534                 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
 535                 cfg->move_cleanup_count = cpumask_weight(cleanup_mask);
 536                 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
 537                 free_cpumask_var(cleanup_mask);
 538         }
 539         cfg->move_in_progress = 0;
 540 }
 541
 542 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
 543 {
 544         int apic, pin;
 545         struct irq_pin_list *entry;
 546         u8 vector = cfg->vector;
 547
 548         entry = cfg->irq_2_pin;
 549         for (;;) {
 550                 unsigned int reg;
 551
 552                 if (!entry)
 553                         break;
 554
 555                 apic = entry->apic;
 556                 pin = entry->pin;
 557                 /*
 558                  * With interrupt-remapping, destination information comes
 559                  * from interrupt-remapping table entry.
 560                  */
 561                 if (!irq_remapped(irq))
 562                         io_apic_write(apic, 0x11 + pin*2, dest);
 563                 reg = io_apic_read(apic, 0x10 + pin*2);
 564                 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
 565                 reg |= vector;
 566                 io_apic_modify(apic, 0x10 + pin*2, reg);
 567                 if (!entry->next)
 568                         break;
 569                 entry = entry->next;
 570         }
 571 }
 572
 573 static int
 574 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask);
 575
 576 /*
 577  * Either sets desc->affinity to a valid value, and returns
 578  * ->cpu_mask_to_apicid of that, or returns BAD_APICID and
 579  * leaves desc->affinity untouched.
 580  */
 581 static unsigned int
 582 set_desc_affinity(struct irq_desc *desc, const struct cpumask *mask)
 583 {
 584         struct irq_cfg *cfg;
 585         unsigned int irq;
 586
 587         if (!cpumask_intersects(mask, cpu_online_mask))
 588                 return BAD_APICID;
 589
 590         irq = desc->irq;
 591         cfg = desc->chip_data;
 592         if (assign_irq_vector(irq, cfg, mask))
 593                 return BAD_APICID;
 594
 595         /* check that before desc->addinity get updated */
 596         set_extra_move_desc(desc, mask);
 597
 598         cpumask_copy(desc->affinity, mask);
 599
 600         return apic->cpu_mask_to_apicid_and(desc->affinity, cfg->domain);
 601 }
 602
 603 static void
 604 set_ioapic_affinity_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
 605 {
 606         struct irq_cfg *cfg;
 607         unsigned long flags;
 608         unsigned int dest;
 609         unsigned int irq;
 610
 611         irq = desc->irq;
 612         cfg = desc->chip_data;
 613
 614         spin_lock_irqsave(&ioapic_lock, flags);
 615         dest = set_desc_affinity(desc, mask);
 616         if (dest != BAD_APICID) {
 617                 /* Only the high 8 bits are valid. */
 618                 dest = SET_APIC_LOGICAL_ID(dest);
 619                 __target_IO_APIC_irq(irq, dest, cfg);
 620         }
 621         spin_unlock_irqrestore(&ioapic_lock, flags);
 622 }
 623
 624 static void
 625 set_ioapic_affinity_irq(unsigned int irq, const struct cpumask *mask)
 626 {
 627         struct irq_desc *desc;
 628
 629         desc = irq_to_desc(irq);
 630
 631         set_ioapic_affinity_irq_desc(desc, mask);
 632 }
 633 #endif /* CONFIG_SMP */
 634
 635 /*
 636  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
 637  * shared ISA-space IRQs, so we have to support them. We are super
 638  * fast in the common case, and fast for shared ISA-space IRQs.
 639  */
 640 static void add_pin_to_irq_cpu(struct irq_cfg *cfg, int cpu, int apic, int pin)
 641 {
 642         struct irq_pin_list *entry;
 643
 644         entry = cfg->irq_2_pin;
 645         if (!entry) {
 646                 entry = get_one_free_irq_2_pin(cpu);
 647                 if (!entry) {
 648                         printk(KERN_ERR "can not alloc irq_2_pin to add %d - %d\n",
 649                                         apic, pin);
 650                         return;
 651                 }
 652                 cfg->irq_2_pin = entry;
 653                 entry->apic = apic;
 654                 entry->pin = pin;
 655                 return;
 656         }
 657
 658         while (entry->next) {
 659                 /* not again, please */
 660                 if (entry->apic == apic && entry->pin == pin)
 661                         return;
 662
 663                 entry = entry->next;
 664         }
 665
 666         entry->next = get_one_free_irq_2_pin(cpu);
 667         entry = entry->next;
 668         entry->apic = apic;
 669         entry->pin = pin;
 670 }
 671
 672 /*
 673  * Reroute an IRQ to a different pin.
 674  */
 675 static void __init replace_pin_at_irq_cpu(struct irq_cfg *cfg, int cpu,
 676                                       int oldapic, int oldpin,
 677                                       int newapic, int newpin)
 678 {
 679         struct irq_pin_list *entry = cfg->irq_2_pin;
 680         int replaced = 0;
 681
 682         while (entry) {
 683                 if (entry->apic == oldapic && entry->pin == oldpin) {
 684                         entry->apic = newapic;
 685                         entry->pin = newpin;
 686                         replaced = 1;
 687                         /* every one is different, right? */
 688                         break;
 689                 }
 690                 entry = entry->next;
 691         }
 692
 693         /* why? call replace before add? */
 694         if (!replaced)
 695                 add_pin_to_irq_cpu(cfg, cpu, newapic, newpin);
 696 }
 697
 698 static inline void io_apic_modify_irq(struct irq_cfg *cfg,
 699                                 int mask_and, int mask_or,
 700                                 void (*final)(struct irq_pin_list *entry))
 701 {
 702         int pin;
 703         struct irq_pin_list *entry;
 704
 705         for (entry = cfg->irq_2_pin; entry != NULL; entry = entry->next) {
 706                 unsigned int reg;
 707                 pin = entry->pin;
 708                 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
 709                 reg &= mask_and;
 710                 reg |= mask_or;
 711                 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
 712                 if (final)
 713                         final(entry);
 714         }
 715 }
 716
 717 static void __unmask_IO_APIC_irq(struct irq_cfg *cfg)
 718 {
 719         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
 720 }
 721
 722 #ifdef CONFIG_X86_64
 723 static void io_apic_sync(struct irq_pin_list *entry)
 724 {
 725         /*
 726          * Synchronize the IO-APIC and the CPU by doing
 727          * a dummy read from the IO-APIC
 728          */
 729         struct io_apic __iomem *io_apic;
 730         io_apic = io_apic_base(entry->apic);
 731         readl(&io_apic->data);
 732 }
 733
 734 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 735 {
 736         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
 737 }
 738 #else /* CONFIG_X86_32 */
 739 static void __mask_IO_APIC_irq(struct irq_cfg *cfg)
 740 {
 741         io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, NULL);
 742 }
 743
 744 static void __mask_and_edge_IO_APIC_irq(struct irq_cfg *cfg)
 745 {
 746         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_LEVEL_TRIGGER,
 747                         IO_APIC_REDIR_MASKED, NULL);
 748 }
 749
 750 static void __unmask_and_level_IO_APIC_irq(struct irq_cfg *cfg)
 751 {
 752         io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED,
 753                         IO_APIC_REDIR_LEVEL_TRIGGER, NULL);
 754 }
 755 #endif /* CONFIG_X86_32 */
 756
 757 static void mask_IO_APIC_irq_desc(struct irq_desc *desc)
 758 {
 759         struct irq_cfg *cfg = desc->chip_data;
 760         unsigned long flags;
 761
 762         BUG_ON(!cfg);
 763
 764         spin_lock_irqsave(&ioapic_lock, flags);
 765         __mask_IO_APIC_irq(cfg);
 766         spin_unlock_irqrestore(&ioapic_lock, flags);
 767 }
 768
 769 static void unmask_IO_APIC_irq_desc(struct irq_desc *desc)
 770 {
 771         struct irq_cfg *cfg = desc->chip_data;
 772         unsigned long flags;
 773
 774         spin_lock_irqsave(&ioapic_lock, flags);
 775         __unmask_IO_APIC_irq(cfg);
 776         spin_unlock_irqrestore(&ioapic_lock, flags);
 777 }
 778
 779 static void mask_IO_APIC_irq(unsigned int irq)
 780 {
 781         struct irq_desc *desc = irq_to_desc(irq);
 782
 783         mask_IO_APIC_irq_desc(desc);
 784 }
 785 static void unmask_IO_APIC_irq(unsigned int irq)
 786 {
 787         struct irq_desc *desc = irq_to_desc(irq);
 788
 789         unmask_IO_APIC_irq_desc(desc);
 790 }
 791
 792 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 793 {
 794         struct IO_APIC_route_entry entry;
 795
 796         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 797         entry = ioapic_read_entry(apic, pin);
 798         if (entry.delivery_mode == dest_SMI)
 799                 return;
 800         /*
 801          * Disable it in the IO-APIC irq-routing table:
 802          */
 803         ioapic_mask_entry(apic, pin);
 804 }
 805
 806 static void clear_IO_APIC (void)
 807 {
 808         int apic, pin;
 809
 810         for (apic = 0; apic < nr_ioapics; apic++)
 811                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 812                         clear_IO_APIC_pin(apic, pin);
 813 }
 814
 815 #ifdef CONFIG_X86_32
 816 /*
 817  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 818  * specific CPU-side IRQs.
 819  */
 820
 821 #define MAX_PIRQS 8
 822 static int pirq_entries[MAX_PIRQS] = {
 823         [0 ... MAX_PIRQS - 1] = -1
 824 };
 825
 826 static int __init ioapic_pirq_setup(char *str)
 827 {
 828         int i, max;
 829         int ints[MAX_PIRQS+1];
 830
 831         get_options(str, ARRAY_SIZE(ints), ints);
 832
 833         apic_printk(APIC_VERBOSE, KERN_INFO
 834                         "PIRQ redirection, working around broken MP-BIOS.\n");
 835         max = MAX_PIRQS;
 836         if (ints[0] < MAX_PIRQS)
 837                 max = ints[0];
 838
 839         for (i = 0; i < max; i++) {
 840                 apic_printk(APIC_VERBOSE, KERN_DEBUG
 841                                 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 842                 /*
 843                  * PIRQs are mapped upside down, usually.
 844                  */
 845                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 846         }
 847         return 1;
 848 }
 849
 850 __setup("pirq=", ioapic_pirq_setup);
 851 #endif /* CONFIG_X86_32 */
 852
 853 #ifdef CONFIG_INTR_REMAP
 854 /* I/O APIC RTE contents at the OS boot up */
 855 static struct IO_APIC_route_entry *early_ioapic_entries[MAX_IO_APICS];
 856
 857 /*
 858  * Saves all the IO-APIC RTE's
 859  */
 860 int save_IO_APIC_setup(void)
 861 {
 862         union IO_APIC_reg_01 reg_01;
 863         unsigned long flags;
 864         int apic, pin;
 865
 866         /*
 867          * The number of IO-APIC IRQ registers (== #pins):
 868          */
 869         for (apic = 0; apic < nr_ioapics; apic++) {
 870                 spin_lock_irqsave(&ioapic_lock, flags);
 871                 reg_01.raw = io_apic_read(apic, 1);
 872                 spin_unlock_irqrestore(&ioapic_lock, flags);
 873                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
 874         }
 875
 876         for (apic = 0; apic < nr_ioapics; apic++) {
 877                 early_ioapic_entries[apic] =
 878                         kzalloc(sizeof(struct IO_APIC_route_entry) *
 879                                 nr_ioapic_registers[apic], GFP_KERNEL);
 880                 if (!early_ioapic_entries[apic])
 881                         goto nomem;
 882         }
 883
 884         for (apic = 0; apic < nr_ioapics; apic++)
 885                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 886                         early_ioapic_entries[apic][pin] =
 887                                 ioapic_read_entry(apic, pin);
 888
 889         return 0;
 890
 891 nomem:
 892         while (apic >= 0)
 893                 kfree(early_ioapic_entries[apic--]);
 894         memset(early_ioapic_entries, 0,
 895                 ARRAY_SIZE(early_ioapic_entries));
 896
 897         return -ENOMEM;
 898 }
 899
 900 void mask_IO_APIC_setup(void)
 901 {
 902         int apic, pin;
 903
 904         for (apic = 0; apic < nr_ioapics; apic++) {
 905                 if (!early_ioapic_entries[apic])
 906                         break;
 907                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 908                         struct IO_APIC_route_entry entry;
 909
 910                         entry = early_ioapic_entries[apic][pin];
 911                         if (!entry.mask) {
 912                                 entry.mask = 1;
 913                                 ioapic_write_entry(apic, pin, entry);
 914                         }
 915                 }
 916         }
 917 }
 918
 919 void restore_IO_APIC_setup(void)
 920 {
 921         int apic, pin;
 922
 923         for (apic = 0; apic < nr_ioapics; apic++) {
 924                 if (!early_ioapic_entries[apic])
 925                         break;
 926                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 927                         ioapic_write_entry(apic, pin,
 928                                            early_ioapic_entries[apic][pin]);
 929                 kfree(early_ioapic_entries[apic]);
 930                 early_ioapic_entries[apic] = NULL;
 931         }
 932 }
 933
 934 void reinit_intr_remapped_IO_APIC(int intr_remapping)
 935 {
 936         /*
 937          * for now plain restore of previous settings.
 938          * TBD: In the case of OS enabling interrupt-remapping,
 939          * IO-APIC RTE's need to be setup to point to interrupt-remapping
 940          * table entries. for now, do a plain restore, and wait for
 941          * the setup_IO_APIC_irqs() to do proper initialization.
 942          */
 943         restore_IO_APIC_setup();
 944 }
 945 #endif
 946
 947 /*
 948  * Find the IRQ entry number of a certain pin.
 949  */
 950 static int find_irq_entry(int apic, int pin, int type)
 951 {
 952         int i;
 953
 954         for (i = 0; i < mp_irq_entries; i++)
 955                 if (mp_irqs[i].irqtype == type &&
 956                     (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
 957                      mp_irqs[i].dstapic == MP_APIC_ALL) &&
 958                     mp_irqs[i].dstirq == pin)
 959                         return i;
 960
 961         return -1;
 962 }
 963
 964 /*
 965  * Find the pin to which IRQ[irq] (ISA) is connected
 966  */
 967 static int __init find_isa_irq_pin(int irq, int type)
 968 {
 969         int i;
 970
 971         for (i = 0; i < mp_irq_entries; i++) {
 972                 int lbus = mp_irqs[i].srcbus;
 973
 974                 if (test_bit(lbus, mp_bus_not_pci) &&
 975                     (mp_irqs[i].irqtype == type) &&
 976                     (mp_irqs[i].srcbusirq == irq))
 977
 978                         return mp_irqs[i].dstirq;
 979         }
 980         return -1;
 981 }
 982
 983 static int __init find_isa_irq_apic(int irq, int type)
 984 {
 985         int i;
 986
 987         for (i = 0; i < mp_irq_entries; i++) {
 988                 int lbus = mp_irqs[i].srcbus;
 989
 990                 if (test_bit(lbus, mp_bus_not_pci) &&
 991                     (mp_irqs[i].irqtype == type) &&
 992                     (mp_irqs[i].srcbusirq == irq))
 993                         break;
 994         }
 995         if (i < mp_irq_entries) {
 996                 int apic;
 997                 for(apic = 0; apic < nr_ioapics; apic++) {
 998                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
 999                                 return apic;
1000                 }
1001         }
1002
1003         return -1;
1004 }
1005
1006 /*
1007  * Find a specific PCI IRQ entry.
1008  * Not an __init, possibly needed by modules
1009  */
1010 static int pin_2_irq(int idx, int apic, int pin);
1011
1012 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
1013 {
1014         int apic, i, best_guess = -1;
1015
1016         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1017                 bus, slot, pin);
1018         if (test_bit(bus, mp_bus_not_pci)) {
1019                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1020                 return -1;
1021         }
1022         for (i = 0; i < mp_irq_entries; i++) {
1023                 int lbus = mp_irqs[i].srcbus;
1024
1025                 for (apic = 0; apic < nr_ioapics; apic++)
1026                         if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
1027                             mp_irqs[i].dstapic == MP_APIC_ALL)
1028                                 break;
1029
1030                 if (!test_bit(lbus, mp_bus_not_pci) &&
1031                     !mp_irqs[i].irqtype &&
1032                     (bus == lbus) &&
1033                     (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1034                         int irq = pin_2_irq(i, apic, mp_irqs[i].dstirq);
1035
1036                         if (!(apic || IO_APIC_IRQ(irq)))
1037                                 continue;
1038
1039                         if (pin == (mp_irqs[i].srcbusirq & 3))
1040                                 return irq;
1041                         /*
1042                          * Use the first all-but-pin matching entry as a
1043                          * best-guess fuzzy result for broken mptables.
1044                          */
1045                         if (best_guess < 0)
1046                                 best_guess = irq;
1047                 }
1048         }
1049         return best_guess;
1050 }
1051
1052 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1053
1054 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1055 /*
1056  * EISA Edge/Level control register, ELCR
1057  */
1058 static int EISA_ELCR(unsigned int irq)
1059 {
1060         if (irq < NR_IRQS_LEGACY) {
1061                 unsigned int port = 0x4d0 + (irq >> 3);
1062                 return (inb(port) >> (irq & 7)) & 1;
1063         }
1064         apic_printk(APIC_VERBOSE, KERN_INFO
1065                         "Broken MPtable reports ISA irq %d\n", irq);
1066         return 0;
1067 }
1068
1069 #endif
1070
1071 /* ISA interrupts are always polarity zero edge triggered,
1072  * when listed as conforming in the MP table. */
1073
1074 #define default_ISA_trigger(idx)        (0)
1075 #define default_ISA_polarity(idx)       (0)
1076
1077 /* EISA interrupts are always polarity zero and can be edge or level
1078  * trigger depending on the ELCR value.  If an interrupt is listed as
1079  * EISA conforming in the MP table, that means its trigger type must
1080  * be read in from the ELCR */
1081
1082 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].srcbusirq))
1083 #define default_EISA_polarity(idx)      default_ISA_polarity(idx)
1084
1085 /* PCI interrupts are always polarity one level triggered,
1086  * when listed as conforming in the MP table. */
1087
1088 #define default_PCI_trigger(idx)        (1)
1089 #define default_PCI_polarity(idx)       (1)
1090
1091 /* MCA interrupts are always polarity zero level triggered,
1092  * when listed as conforming in the MP table. */
1093
1094 #define default_MCA_trigger(idx)        (1)
1095 #define default_MCA_polarity(idx)       default_ISA_polarity(idx)
1096
1097 static int MPBIOS_polarity(int idx)
1098 {
1099         int bus = mp_irqs[idx].srcbus;
1100         int polarity;
1101
1102         /*
1103          * Determine IRQ line polarity (high active or low active):
1104          */
1105         switch (mp_irqs[idx].irqflag & 3)
1106         {
1107                 case 0: /* conforms, ie. bus-type dependent polarity */
1108                         if (test_bit(bus, mp_bus_not_pci))
1109                                 polarity = default_ISA_polarity(idx);
1110                         else
1111                                 polarity = default_PCI_polarity(idx);
1112                         break;
1113                 case 1: /* high active */
1114                 {
1115                         polarity = 0;
1116                         break;
1117                 }
1118                 case 2: /* reserved */
1119                 {
1120                         printk(KERN_WARNING "broken BIOS!!\n");
1121                         polarity = 1;
1122                         break;
1123                 }
1124                 case 3: /* low active */
1125                 {
1126                         polarity = 1;
1127                         break;
1128                 }
1129                 default: /* invalid */
1130                 {
1131                         printk(KERN_WARNING "broken BIOS!!\n");
1132                         polarity = 1;
1133                         break;
1134                 }
1135         }
1136         return polarity;
1137 }
1138
1139 static int MPBIOS_trigger(int idx)
1140 {
1141         int bus = mp_irqs[idx].srcbus;
1142         int trigger;
1143
1144         /*
1145          * Determine IRQ trigger mode (edge or level sensitive):
1146          */
1147         switch ((mp_irqs[idx].irqflag>>2) & 3)
1148         {
1149                 case 0: /* conforms, ie. bus-type dependent */
1150                         if (test_bit(bus, mp_bus_not_pci))
1151                                 trigger = default_ISA_trigger(idx);
1152                         else
1153                                 trigger = default_PCI_trigger(idx);
1154 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
1155                         switch (mp_bus_id_to_type[bus]) {
1156                                 case MP_BUS_ISA: /* ISA pin */
1157                                 {
1158                                         /* set before the switch */
1159                                         break;
1160                                 }
1161                                 case MP_BUS_EISA: /* EISA pin */
1162                                 {
1163                                         trigger = default_EISA_trigger(idx);
1164                                         break;
1165                                 }
1166                                 case MP_BUS_PCI: /* PCI pin */
1167                                 {
1168                                         /* set before the switch */
1169                                         break;
1170                                 }
1171                                 case MP_BUS_MCA: /* MCA pin */
1172                                 {
1173                                         trigger = default_MCA_trigger(idx);
1174                                         break;
1175                                 }
1176                                 default:
1177                                 {
1178                                         printk(KERN_WARNING "broken BIOS!!\n");
1179                                         trigger = 1;
1180                                         break;
1181                                 }
1182                         }
1183 #endif
1184                         break;
1185                 case 1: /* edge */
1186                 {
1187                         trigger = 0;
1188                         break;
1189                 }
1190                 case 2: /* reserved */
1191                 {
1192                         printk(KERN_WARNING "broken BIOS!!\n");
1193                         trigger = 1;
1194                         break;
1195                 }
1196                 case 3: /* level */
1197                 {
1198                         trigger = 1;
1199                         break;
1200                 }
1201                 default: /* invalid */
1202                 {
1203                         printk(KERN_WARNING "broken BIOS!!\n");
1204                         trigger = 0;
1205                         break;
1206                 }
1207         }
1208         return trigger;
1209 }
1210
1211 static inline int irq_polarity(int idx)
1212 {
1213         return MPBIOS_polarity(idx);
1214 }
1215
1216 static inline int irq_trigger(int idx)
1217 {
1218         return MPBIOS_trigger(idx);
1219 }
1220
1221 int (*ioapic_renumber_irq)(int ioapic, int irq);
1222 static int pin_2_irq(int idx, int apic, int pin)
1223 {
1224         int irq, i;
1225         int bus = mp_irqs[idx].srcbus;
1226
1227         /*
1228          * Debugging check, we are in big trouble if this message pops up!
1229          */
1230         if (mp_irqs[idx].dstirq != pin)
1231                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1232
1233         if (test_bit(bus, mp_bus_not_pci)) {
1234                 irq = mp_irqs[idx].srcbusirq;
1235         } else {
1236                 /*
1237                  * PCI IRQs are mapped in order
1238                  */
1239                 i = irq = 0;
1240                 while (i < apic)
1241                         irq += nr_ioapic_registers[i++];
1242                 irq += pin;
1243                 /*
1244                  * For MPS mode, so far only needed by ES7000 platform
1245                  */
1246                 if (ioapic_renumber_irq)
1247                         irq = ioapic_renumber_irq(apic, irq);
1248         }
1249
1250 #ifdef CONFIG_X86_32
1251         /*
1252          * PCI IRQ command line redirection. Yes, limits are hardcoded.
1253          */
1254         if ((pin >= 16) && (pin <= 23)) {
1255                 if (pirq_entries[pin-16] != -1) {
1256                         if (!pirq_entries[pin-16]) {
1257                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1258                                                 "disabling PIRQ%d\n", pin-16);
1259                         } else {
1260                                 irq = pirq_entries[pin-16];
1261                                 apic_printk(APIC_VERBOSE, KERN_DEBUG
1262                                                 "using PIRQ%d -> IRQ %d\n",
1263                                                 pin-16, irq);
1264                         }
1265                 }
1266         }
1267 #endif
1268
1269         return irq;
1270 }
1271
1272 void lock_vector_lock(void)
1273 {
1274         /* Used to the online set of cpus does not change
1275          * during assign_irq_vector.
1276          */
1277         spin_lock(&vector_lock);
1278 }
1279
1280 void unlock_vector_lock(void)
1281 {
1282         spin_unlock(&vector_lock);
1283 }
1284
1285 static int
1286 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1287 {
1288         /*
1289          * NOTE! The local APIC isn't very good at handling
1290          * multiple interrupts at the same interrupt level.
1291          * As the interrupt level is determined by taking the
1292          * vector number and shifting that right by 4, we
1293          * want to spread these out a bit so that they don't
1294          * all fall in the same interrupt level.
1295          *
1296          * Also, we've got to be careful not to trash gate
1297          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1298          */
1299         static int current_vector = FIRST_DEVICE_VECTOR, current_offset = 0;
1300         unsigned int old_vector;
1301         int cpu, err;
1302         cpumask_var_t tmp_mask;
1303
1304         if ((cfg->move_in_progress) || cfg->move_cleanup_count)
1305                 return -EBUSY;
1306
1307         if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1308                 return -ENOMEM;
1309
1310         old_vector = cfg->vector;
1311         if (old_vector) {
1312                 cpumask_and(tmp_mask, mask, cpu_online_mask);
1313                 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1314                 if (!cpumask_empty(tmp_mask)) {
1315                         free_cpumask_var(tmp_mask);
1316                         return 0;
1317                 }
1318         }
1319
1320         /* Only try and allocate irqs on cpus that are present */
1321         err = -ENOSPC;
1322         for_each_cpu_and(cpu, mask, cpu_online_mask) {
1323                 int new_cpu;
1324                 int vector, offset;
1325
1326                 apic->vector_allocation_domain(cpu, tmp_mask);
1327
1328                 vector = current_vector;
1329                 offset = current_offset;
1330 next:
1331                 vector += 8;
1332                 if (vector >= first_system_vector) {
1333                         /* If out of vectors on large boxen, must share them. */
1334                         offset = (offset + 1) % 8;
1335                         vector = FIRST_DEVICE_VECTOR + offset;
1336                 }
1337                 if (unlikely(current_vector == vector))
1338                         continue;
1339
1340                 if (test_bit(vector, used_vectors))
1341                         goto next;
1342
1343                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1344                         if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1345                                 goto next;
1346                 /* Found one! */
1347                 current_vector = vector;
1348                 current_offset = offset;
1349                 if (old_vector) {
1350                         cfg->move_in_progress = 1;
1351                         cpumask_copy(cfg->old_domain, cfg->domain);
1352                 }
1353                 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1354                         per_cpu(vector_irq, new_cpu)[vector] = irq;
1355                 cfg->vector = vector;
1356                 cpumask_copy(cfg->domain, tmp_mask);
1357                 err = 0;
1358                 break;
1359         }
1360         free_cpumask_var(tmp_mask);
1361         return err;
1362 }
1363
1364 static int
1365 assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1366 {
1367         int err;
1368         unsigned long flags;
1369
1370         spin_lock_irqsave(&vector_lock, flags);
1371         err = __assign_irq_vector(irq, cfg, mask);
1372         spin_unlock_irqrestore(&vector_lock, flags);
1373         return err;
1374 }
1375
1376 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1377 {
1378         int cpu, vector;
1379
1380         BUG_ON(!cfg->vector);
1381
1382         vector = cfg->vector;
1383         for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1384                 per_cpu(vector_irq, cpu)[vector] = -1;
1385
1386         cfg->vector = 0;
1387         cpumask_clear(cfg->domain);
1388
1389         if (likely(!cfg->move_in_progress))
1390                 return;
1391         for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1392                 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1393                                                                 vector++) {
1394                         if (per_cpu(vector_irq, cpu)[vector] != irq)
1395                                 continue;
1396                         per_cpu(vector_irq, cpu)[vector] = -1;
1397                         break;
1398                 }
1399         }
1400         cfg->move_in_progress = 0;
1401 }
1402
1403 void __setup_vector_irq(int cpu)
1404 {
1405         /* Initialize vector_irq on a new cpu */
1406         /* This function must be called with vector_lock held */
1407         int irq, vector;
1408         struct irq_cfg *cfg;
1409         struct irq_desc *desc;
1410
1411         /* Mark the inuse vectors */
1412         for_each_irq_desc(irq, desc) {
1413                 cfg = desc->chip_data;
1414                 if (!cpumask_test_cpu(cpu, cfg->domain))
1415                         continue;
1416                 vector = cfg->vector;
1417                 per_cpu(vector_irq, cpu)[vector] = irq;
1418         }
1419         /* Mark the free vectors */
1420         for (vector = 0; vector < NR_VECTORS; ++vector) {
1421                 irq = per_cpu(vector_irq, cpu)[vector];
1422                 if (irq < 0)
1423                         continue;
1424
1425                 cfg = irq_cfg(irq);
1426                 if (!cpumask_test_cpu(cpu, cfg->domain))
1427                         per_cpu(vector_irq, cpu)[vector] = -1;
1428         }
1429 }
1430
1431 static struct irq_chip ioapic_chip;
1432 static struct irq_chip ir_ioapic_chip;
1433
1434 #define IOAPIC_AUTO     -1
1435 #define IOAPIC_EDGE     0
1436 #define IOAPIC_LEVEL    1
1437
1438 #ifdef CONFIG_X86_32
1439 static inline int IO_APIC_irq_trigger(int irq)
1440 {
1441         int apic, idx, pin;
1442
1443         for (apic = 0; apic < nr_ioapics; apic++) {
1444                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
1445                         idx = find_irq_entry(apic, pin, mp_INT);
1446                         if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1447                                 return irq_trigger(idx);
1448                 }
1449         }
1450         /*
1451          * nonexistent IRQs are edge default
1452          */
1453         return 0;
1454 }
1455 #else
1456 static inline int IO_APIC_irq_trigger(int irq)
1457 {
1458         return 1;
1459 }
1460 #endif
1461
1462 static void ioapic_register_intr(int irq, struct irq_desc *desc, unsigned long trigger)
1463 {
1464
1465         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1466             trigger == IOAPIC_LEVEL)
1467                 desc->status |= IRQ_LEVEL;
1468         else
1469                 desc->status &= ~IRQ_LEVEL;
1470
1471         if (irq_remapped(irq)) {
1472                 desc->status |= IRQ_MOVE_PCNTXT;
1473                 if (trigger)
1474                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1475                                                       handle_fasteoi_irq,
1476                                                      "fasteoi");
1477                 else
1478                         set_irq_chip_and_handler_name(irq, &ir_ioapic_chip,
1479                                                       handle_edge_irq, "edge");
1480                 return;
1481         }
1482
1483         if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1484             trigger == IOAPIC_LEVEL)
1485                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1486                                               handle_fasteoi_irq,
1487                                               "fasteoi");
1488         else
1489                 set_irq_chip_and_handler_name(irq, &ioapic_chip,
1490                                               handle_edge_irq, "edge");
1491 }
1492
1493 int setup_ioapic_entry(int apic_id, int irq,
1494                        struct IO_APIC_route_entry *entry,
1495                        unsigned int destination, int trigger,
1496                        int polarity, int vector, int pin)
1497 {
1498         /*
1499          * add it to the IO-APIC irq-routing table:
1500          */
1501         memset(entry,0,sizeof(*entry));
1502
1503         if (intr_remapping_enabled) {
1504                 struct intel_iommu *iommu = map_ioapic_to_ir(apic_id);
1505                 struct irte irte;
1506                 struct IR_IO_APIC_route_entry *ir_entry =
1507                         (struct IR_IO_APIC_route_entry *) entry;
1508                 int index;
1509
1510                 if (!iommu)
1511                         panic("No mapping iommu for ioapic %d\n", apic_id);
1512
1513                 index = alloc_irte(iommu, irq, 1);
1514                 if (index < 0)
1515                         panic("Failed to allocate IRTE for ioapic %d\n", apic_id);
1516
1517                 memset(&irte, 0, sizeof(irte));
1518
1519                 irte.present = 1;
1520                 irte.dst_mode = apic->irq_dest_mode;
1521                 /*
1522                  * Trigger mode in the IRTE will always be edge, and the
1523                  * actual level or edge trigger will be setup in the IO-APIC
1524                  * RTE. This will help simplify level triggered irq migration.
1525                  * For more details, see the comments above explainig IO-APIC
1526                  * irq migration in the presence of interrupt-remapping.
1527                  */
1528                 irte.trigger_mode = 0;
1529                 irte.dlvry_mode = apic->irq_delivery_mode;
1530                 irte.vector = vector;
1531                 irte.dest_id = IRTE_DEST(destination);
1532
1533                 modify_irte(irq, &irte);
1534
1535                 ir_entry->index2 = (index >> 15) & 0x1;
1536                 ir_entry->zero = 0;
1537                 ir_entry->format = 1;
1538                 ir_entry->index = (index & 0x7fff);
1539                 /*
1540                  * IO-APIC RTE will be configured with virtual vector.
1541                  * irq handler will do the explicit EOI to the io-apic.
1542                  */
1543                 ir_entry->vector = pin;
1544         } else {
1545                 entry->delivery_mode = apic->irq_delivery_mode;
1546                 entry->dest_mode = apic->irq_dest_mode;
1547                 entry->dest = destination;
1548                 entry->vector = vector;
1549         }
1550
1551         entry->mask = 0;                                /* enable IRQ */
1552         entry->trigger = trigger;
1553         entry->polarity = polarity;
1554
1555         /* Mask level triggered irqs.
1556          * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1557          */
1558         if (trigger)
1559                 entry->mask = 1;
1560         return 0;
1561 }
1562
1563 static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq_desc *desc,
1564                               int trigger, int polarity)
1565 {
1566         struct irq_cfg *cfg;
1567         struct IO_APIC_route_entry entry;
1568         unsigned int dest;
1569
1570         if (!IO_APIC_IRQ(irq))
1571                 return;
1572
1573         cfg = desc->chip_data;
1574
1575         if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1576                 return;
1577
1578         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1579
1580         apic_printk(APIC_VERBOSE,KERN_DEBUG
1581                     "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1582                     "IRQ %d Mode:%i Active:%i)\n",
1583                     apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
1584                     irq, trigger, polarity);
1585
1586
1587         if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
1588                                dest, trigger, polarity, cfg->vector, pin)) {
1589                 printk("Failed to setup ioapic entry for ioapic  %d, pin %d\n",
1590                        mp_ioapics[apic_id].apicid, pin);
1591                 __clear_irq_vector(irq, cfg);
1592                 return;
1593         }
1594
1595         ioapic_register_intr(irq, desc, trigger);
1596         if (irq < NR_IRQS_LEGACY)
1597                 disable_8259A_irq(irq);
1598
1599         ioapic_write_entry(apic_id, pin, entry);
1600 }
1601
1602 static void __init setup_IO_APIC_irqs(void)
1603 {
1604         int apic_id, pin, idx, irq;
1605         int notcon = 0;
1606         struct irq_desc *desc;
1607         struct irq_cfg *cfg;
1608         int cpu = boot_cpu_id;
1609
1610         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1611
1612         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
1613                 for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
1614
1615                         idx = find_irq_entry(apic_id, pin, mp_INT);
1616                         if (idx == -1) {
1617                                 if (!notcon) {
1618                                         notcon = 1;
1619                                         apic_printk(APIC_VERBOSE,
1620                                                 KERN_DEBUG " %d-%d",
1621                                                 mp_ioapics[apic_id].apicid, pin);
1622                                 } else
1623                                         apic_printk(APIC_VERBOSE, " %d-%d",
1624                                                 mp_ioapics[apic_id].apicid, pin);
1625                                 continue;
1626                         }
1627                         if (notcon) {
1628                                 apic_printk(APIC_VERBOSE,
1629                                         " (apicid-pin) not connected\n");
1630                                 notcon = 0;
1631                         }
1632
1633                         irq = pin_2_irq(idx, apic_id, pin);
1634
1635                         /*
1636                          * Skip the timer IRQ if there's a quirk handler
1637                          * installed and if it returns 1:
1638                          */
1639                         if (apic->multi_timer_check &&
1640                                         apic->multi_timer_check(apic_id, irq))
1641                                 continue;
1642
1643                         desc = irq_to_desc_alloc_cpu(irq, cpu);
1644                         if (!desc) {
1645                                 printk(KERN_INFO "can not get irq_desc for %d\n", irq);
1646                                 continue;
1647                         }
1648                         cfg = desc->chip_data;
1649                         add_pin_to_irq_cpu(cfg, cpu, apic_id, pin);
1650
1651                         setup_IO_APIC_irq(apic_id, pin, irq, desc,
1652                                         irq_trigger(idx), irq_polarity(idx));
1653                 }
1654         }
1655
1656         if (notcon)
1657                 apic_printk(APIC_VERBOSE,
1658                         " (apicid-pin) not connected\n");
1659 }
1660
1661 /*
1662  * Set up the timer pin, possibly with the 8259A-master behind.
1663  */
1664 static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin,
1665                                         int vector)
1666 {
1667         struct IO_APIC_route_entry entry;
1668
1669         if (intr_remapping_enabled)
1670                 return;
1671
1672         memset(&entry, 0, sizeof(entry));
1673
1674         /*
1675          * We use logical delivery to get the timer IRQ
1676          * to the first CPU.
1677          */
1678         entry.dest_mode = apic->irq_dest_mode;
1679         entry.mask = 0;                 /* don't mask IRQ for edge */
1680         entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1681         entry.delivery_mode = apic->irq_delivery_mode;
1682         entry.polarity = 0;
1683         entry.trigger = 0;
1684         entry.vector = vector;
1685
1686         /*
1687          * The timer IRQ doesn't have to know that behind the
1688          * scene we may have a 8259A-master in AEOI mode ...
1689          */
1690         set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
1691
1692         /*
1693          * Add it to the IO-APIC irq-routing table:
1694          */
1695         ioapic_write_entry(apic_id, pin, entry);
1696 }
1697
1698
1699 __apicdebuginit(void) print_IO_APIC(void)
1700 {
1701         int apic, i;
1702         union IO_APIC_reg_00 reg_00;
1703         union IO_APIC_reg_01 reg_01;
1704         union IO_APIC_reg_02 reg_02;
1705         union IO_APIC_reg_03 reg_03;
1706         unsigned long flags;
1707         struct irq_cfg *cfg;
1708         struct irq_desc *desc;
1709         unsigned int irq;
1710
1711         if (apic_verbosity == APIC_QUIET)
1712                 return;
1713
1714         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1715         for (i = 0; i < nr_ioapics; i++)
1716                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1717                        mp_ioapics[i].apicid, nr_ioapic_registers[i]);
1718
1719         /*
1720          * We are a bit conservative about what we expect.  We have to
1721          * know about every hardware change ASAP.
1722          */
1723         printk(KERN_INFO "testing the IO APIC.......................\n");
1724
1725         for (apic = 0; apic < nr_ioapics; apic++) {
1726
1727         spin_lock_irqsave(&ioapic_lock, flags);
1728         reg_00.raw = io_apic_read(apic, 0);
1729         reg_01.raw = io_apic_read(apic, 1);
1730         if (reg_01.bits.version >= 0x10)
1731                 reg_02.raw = io_apic_read(apic, 2);
1732         if (reg_01.bits.version >= 0x20)
1733                 reg_03.raw = io_apic_read(apic, 3);
1734         spin_unlock_irqrestore(&ioapic_lock, flags);
1735
1736         printk("\n");
1737         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
1738         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1739         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
1740         printk(KERN_DEBUG ".......    : Delivery Type: %X\n", reg_00.bits.delivery_type);
1741         printk(KERN_DEBUG ".......    : LTS          : %X\n", reg_00.bits.LTS);
1742
1743         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
1744         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
1745
1746         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
1747         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
1748
1749         /*
1750          * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1751          * but the value of reg_02 is read as the previous read register
1752          * value, so ignore it if reg_02 == reg_01.
1753          */
1754         if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1755                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1756                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
1757         }
1758
1759         /*
1760          * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1761          * or reg_03, but the value of reg_0[23] is read as the previous read
1762          * register value, so ignore it if reg_03 == reg_0[12].
1763          */
1764         if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1765             reg_03.raw != reg_01.raw) {
1766                 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1767                 printk(KERN_DEBUG ".......     : Boot DT    : %X\n", reg_03.bits.boot_DT);
1768         }
1769
1770         printk(KERN_DEBUG ".... IRQ redirection table:\n");
1771
1772         printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1773                           " Stat Dmod Deli Vect:   \n");
1774
1775         for (i = 0; i <= reg_01.bits.entries; i++) {
1776                 struct IO_APIC_route_entry entry;
1777
1778                 entry = ioapic_read_entry(apic, i);
1779
1780                 printk(KERN_DEBUG " %02x %03X ",
1781                         i,
1782                         entry.dest
1783                 );
1784
1785                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
1786                         entry.mask,
1787                         entry.trigger,
1788                         entry.irr,
1789                         entry.polarity,
1790                         entry.delivery_status,
1791                         entry.dest_mode,
1792                         entry.delivery_mode,
1793                         entry.vector
1794                 );
1795         }
1796         }
1797         printk(KERN_DEBUG "IRQ to pin mappings:\n");
1798         for_each_irq_desc(irq, desc) {
1799                 struct irq_pin_list *entry;
1800
1801                 cfg = desc->chip_data;
1802                 entry = cfg->irq_2_pin;
1803                 if (!entry)
1804                         continue;
1805                 printk(KERN_DEBUG "IRQ%d ", irq);
1806                 for (;;) {
1807                         printk("-> %d:%d", entry->apic, entry->pin);
1808                         if (!entry->next)
1809                                 break;
1810                         entry = entry->next;
1811                 }
1812                 printk("\n");
1813         }
1814
1815         printk(KERN_INFO ".................................... done.\n");
1816
1817         return;
1818 }
1819
1820 __apicdebuginit(void) print_APIC_bitfield(int base)
1821 {
1822         unsigned int v;
1823         int i, j;
1824
1825         if (apic_verbosity == APIC_QUIET)
1826                 return;
1827
1828         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
1829         for (i = 0; i < 8; i++) {
1830                 v = apic_read(base + i*0x10);
1831                 for (j = 0; j < 32; j++) {
1832                         if (v & (1<<j))
1833                                 printk("1");
1834                         else
1835                                 printk("0");
1836                 }
1837                 printk("\n");
1838         }
1839 }
1840
1841 __apicdebuginit(void) print_local_APIC(void *dummy)
1842 {
1843         unsigned int v, ver, maxlvt;
1844         u64 icr;
1845
1846         if (apic_verbosity == APIC_QUIET)
1847                 return;
1848
1849         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1850                 smp_processor_id(), hard_smp_processor_id());
1851         v = apic_read(APIC_ID);
1852         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, read_apic_id());
1853         v = apic_read(APIC_LVR);
1854         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1855         ver = GET_APIC_VERSION(v);
1856         maxlvt = lapic_get_maxlvt();
1857
1858         v = apic_read(APIC_TASKPRI);
1859         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1860
1861         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
1862                 if (!APIC_XAPIC(ver)) {
1863                         v = apic_read(APIC_ARBPRI);
1864                         printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1865                                v & APIC_ARBPRI_MASK);
1866                 }
1867                 v = apic_read(APIC_PROCPRI);
1868                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1869         }
1870
1871         /*
1872          * Remote read supported only in the 82489DX and local APIC for
1873          * Pentium processors.
1874          */
1875         if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1876                 v = apic_read(APIC_RRR);
1877                 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1878         }
1879
1880         v = apic_read(APIC_LDR);
1881         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1882         if (!x2apic_enabled()) {
1883                 v = apic_read(APIC_DFR);
1884                 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1885         }
1886         v = apic_read(APIC_SPIV);
1887         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1888
1889         printk(KERN_DEBUG "... APIC ISR field:\n");
1890         print_APIC_bitfield(APIC_ISR);
1891         printk(KERN_DEBUG "... APIC TMR field:\n");
1892         print_APIC_bitfield(APIC_TMR);
1893         printk(KERN_DEBUG "... APIC IRR field:\n");
1894         print_APIC_bitfield(APIC_IRR);
1895
1896         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1897                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1898                         apic_write(APIC_ESR, 0);
1899
1900                 v = apic_read(APIC_ESR);
1901                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1902         }
1903
1904         icr = apic_icr_read();
1905         printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1906         printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1907
1908         v = apic_read(APIC_LVTT);
1909         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1910
1911         if (maxlvt > 3) {                       /* PC is LVT#4. */
1912                 v = apic_read(APIC_LVTPC);
1913                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1914         }
1915         v = apic_read(APIC_LVT0);
1916         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1917         v = apic_read(APIC_LVT1);
1918         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1919
1920         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1921                 v = apic_read(APIC_LVTERR);
1922                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1923         }
1924
1925         v = apic_read(APIC_TMICT);
1926         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1927         v = apic_read(APIC_TMCCT);
1928         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1929         v = apic_read(APIC_TDCR);
1930         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1931         printk("\n");
1932 }
1933
1934 __apicdebuginit(void) print_all_local_APICs(void)
1935 {
1936         int cpu;
1937
1938         preempt_disable();
1939         for_each_online_cpu(cpu)
1940                 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1941         preempt_enable();
1942 }
1943
1944 __apicdebuginit(void) print_PIC(void)
1945 {
1946         unsigned int v;
1947         unsigned long flags;
1948
1949         if (apic_verbosity == APIC_QUIET)
1950                 return;
1951
1952         printk(KERN_DEBUG "\nprinting PIC contents\n");
1953
1954         spin_lock_irqsave(&i8259A_lock, flags);
1955
1956         v = inb(0xa1) << 8 | inb(0x21);
1957         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1958
1959         v = inb(0xa0) << 8 | inb(0x20);
1960         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1961
1962         outb(0x0b,0xa0);
1963         outb(0x0b,0x20);
1964         v = inb(0xa0) << 8 | inb(0x20);
1965         outb(0x0a,0xa0);
1966         outb(0x0a,0x20);
1967
1968         spin_unlock_irqrestore(&i8259A_lock, flags);
1969
1970         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1971
1972         v = inb(0x4d1) << 8 | inb(0x4d0);
1973         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1974 }
1975
1976 __apicdebuginit(int) print_all_ICs(void)
1977 {
1978         print_PIC();
1979         print_all_local_APICs();
1980         print_IO_APIC();
1981
1982         return 0;
1983 }
1984
1985 fs_initcall(print_all_ICs);
1986
1987
1988 /* Where if anywhere is the i8259 connect in external int mode */
1989 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1990
1991 void __init enable_IO_APIC(void)
1992 {
1993         union IO_APIC_reg_01 reg_01;
1994         int i8259_apic, i8259_pin;
1995         int apic;
1996         unsigned long flags;
1997
1998         /*
1999          * The number of IO-APIC IRQ registers (== #pins):
2000          */
2001         for (apic = 0; apic < nr_ioapics; apic++) {
2002                 spin_lock_irqsave(&ioapic_lock, flags);
2003                 reg_01.raw = io_apic_read(apic, 1);
2004                 spin_unlock_irqrestore(&ioapic_lock, flags);
2005                 nr_ioapic_registers[apic] = reg_01.bits.entries+1;
2006         }
2007         for(apic = 0; apic < nr_ioapics; apic++) {
2008                 int pin;
2009                 /* See if any of the pins is in ExtINT mode */
2010                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
2011                         struct IO_APIC_route_entry entry;
2012                         entry = ioapic_read_entry(apic, pin);
2013
2014                         /* If the interrupt line is enabled and in ExtInt mode
2015                          * I have found the pin where the i8259 is connected.
2016                          */
2017                         if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
2018                                 ioapic_i8259.apic = apic;
2019                                 ioapic_i8259.pin  = pin;
2020                                 goto found_i8259;
2021                         }
2022                 }
2023         }
2024  found_i8259:
2025         /* Look to see what if the MP table has reported the ExtINT */
2026         /* If we could not find the appropriate pin by looking at the ioapic
2027          * the i8259 probably is not connected the ioapic but give the
2028          * mptable a chance anyway.
2029          */
2030         i8259_pin  = find_isa_irq_pin(0, mp_ExtINT);
2031         i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
2032         /* Trust the MP table if nothing is setup in the hardware */
2033         if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
2034                 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
2035                 ioapic_i8259.pin  = i8259_pin;
2036                 ioapic_i8259.apic = i8259_apic;
2037         }
2038         /* Complain if the MP table and the hardware disagree */
2039         if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
2040                 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
2041         {
2042                 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
2043         }
2044
2045         /*
2046          * Do not trust the IO-APIC being empty at bootup
2047          */
2048         clear_IO_APIC();
2049 }
2050
2051 /*
2052  * Not an __init, needed by the reboot code
2053  */
2054 void disable_IO_APIC(void)
2055 {
2056         /*
2057          * Clear the IO-APIC before rebooting:
2058          */
2059         clear_IO_APIC();
2060
2061         /*
2062          * If the i8259 is routed through an IOAPIC
2063          * Put that IOAPIC in virtual wire mode
2064          * so legacy interrupts can be delivered.
2065          *
2066          * With interrupt-remapping, for now we will use virtual wire A mode,
2067          * as virtual wire B is little complex (need to configure both
2068          * IOAPIC RTE aswell as interrupt-remapping table entry).
2069          * As this gets called during crash dump, keep this simple for now.
2070          */
2071         if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2072                 struct IO_APIC_route_entry entry;
2073
2074                 memset(&entry, 0, sizeof(entry));
2075                 entry.mask            = 0; /* Enabled */
2076                 entry.trigger         = 0; /* Edge */
2077                 entry.irr             = 0;
2078                 entry.polarity        = 0; /* High */
2079                 entry.delivery_status = 0;
2080                 entry.dest_mode       = 0; /* Physical */
2081                 entry.delivery_mode   = dest_ExtINT; /* ExtInt */
2082                 entry.vector          = 0;
2083                 entry.dest            = read_apic_id();
2084
2085                 /*
2086                  * Add it to the IO-APIC irq-routing table:
2087                  */
2088                 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2089         }
2090
2091         /*
2092          * Use virtual wire A mode when interrupt remapping is enabled.
2093          */
2094         disconnect_bsp_APIC(!intr_remapping_enabled && ioapic_i8259.pin != -1);
2095 }
2096
2097 #ifdef CONFIG_X86_32
2098 /*
2099  * function to set the IO-APIC physical IDs based on the
2100  * values stored in the MPC table.
2101  *
2102  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
2103  */
2104
2105 static void __init setup_ioapic_ids_from_mpc(void)
2106 {
2107         union IO_APIC_reg_00 reg_00;
2108         physid_mask_t phys_id_present_map;
2109         int apic_id;
2110         int i;
2111         unsigned char old_id;
2112         unsigned long flags;
2113
2114         if (x86_quirks->setup_ioapic_ids && x86_quirks->setup_ioapic_ids())
2115                 return;
2116
2117         /*
2118          * Don't check I/O APIC IDs for xAPIC systems.  They have
2119          * no meaning without the serial APIC bus.
2120          */
2121         if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2122                 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2123                 return;
2124         /*
2125          * This is broken; anything with a real cpu count has to
2126          * circumvent this idiocy regardless.
2127          */
2128         phys_id_present_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
2129
2130         /*
2131          * Set the IOAPIC ID to the value stored in the MPC table.
2132          */
2133         for (apic_id = 0; apic_id < nr_ioapics; apic_id++) {
2134
2135                 /* Read the register 0 value */
2136                 spin_lock_irqsave(&ioapic_lock, flags);
2137                 reg_00.raw = io_apic_read(apic_id, 0);
2138                 spin_unlock_irqrestore(&ioapic_lock, flags);
2139
2140                 old_id = mp_ioapics[apic_id].apicid;
2141
2142                 if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
2143                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2144                                 apic_id, mp_ioapics[apic_id].apicid);
2145                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2146                                 reg_00.bits.ID);
2147                         mp_ioapics[apic_id].apicid = reg_00.bits.ID;
2148                 }
2149
2150                 /*
2151                  * Sanity check, is the ID really free? Every APIC in a
2152                  * system must have a unique ID or we get lots of nice
2153                  * 'stuck on smp_invalidate_needed IPI wait' messages.
2154                  */
2155                 if (apic->check_apicid_used(phys_id_present_map,
2156                                         mp_ioapics[apic_id].apicid)) {
2157                         printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2158                                 apic_id, mp_ioapics[apic_id].apicid);
2159                         for (i = 0; i < get_physical_broadcast(); i++)
2160                                 if (!physid_isset(i, phys_id_present_map))
2161                                         break;
2162                         if (i >= get_physical_broadcast())
2163                                 panic("Max APIC ID exceeded!\n");
2164                         printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2165                                 i);
2166                         physid_set(i, phys_id_present_map);
2167                         mp_ioapics[apic_id].apicid = i;
2168                 } else {
2169                         physid_mask_t tmp;
2170                         tmp = apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid);
2171                         apic_printk(APIC_VERBOSE, "Setting %d in the "
2172                                         "phys_id_present_map\n",
2173                                         mp_ioapics[apic_id].apicid);
2174                         physids_or(phys_id_present_map, phys_id_present_map, tmp);
2175                 }
2176
2177
2178                 /*
2179                  * We need to adjust the IRQ routing table
2180                  * if the ID changed.
2181                  */
2182                 if (old_id != mp_ioapics[apic_id].apicid)
2183                         for (i = 0; i < mp_irq_entries; i++)
2184                                 if (mp_irqs[i].dstapic == old_id)
2185                                         mp_irqs[i].dstapic
2186                                                 = mp_ioapics[apic_id].apicid;
2187
2188                 /*
2189                  * Read the right value from the MPC table and
2190                  * write it into the ID register.
2191                  */
2192                 apic_printk(APIC_VERBOSE, KERN_INFO
2193                         "...changing IO-APIC physical APIC ID to %d ...",
2194                         mp_ioapics[apic_id].apicid);
2195
2196                 reg_00.bits.ID = mp_ioapics[apic_id].apicid;
2197                 spin_lock_irqsave(&ioapic_lock, flags);
2198                 io_apic_write(apic_id, 0, reg_00.raw);
2199                 spin_unlock_irqrestore(&ioapic_lock, flags);
2200
2201                 /*
2202                  * Sanity check
2203                  */
2204                 spin_lock_irqsave(&ioapic_lock, flags);
2205                 reg_00.raw = io_apic_read(apic_id, 0);
2206                 spin_unlock_irqrestore(&ioapic_lock, flags);
2207                 if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
2208                         printk("could not set ID!\n");
2209                 else
2210                         apic_printk(APIC_VERBOSE, " ok.\n");
2211         }
2212 }
2213 #endif
2214
2215 int no_timer_check __initdata;
2216
2217 static int __init notimercheck(char *s)
2218 {
2219         no_timer_check = 1;
2220         return 1;
2221 }
2222 __setup("no_timer_check", notimercheck);
2223
2224 /*
2225  * There is a nasty bug in some older SMP boards, their mptable lies
2226  * about the timer IRQ. We do the following to work around the situation:
2227  *
2228  *      - timer IRQ defaults to IO-APIC IRQ
2229  *      - if this function detects that timer IRQs are defunct, then we fall
2230  *        back to ISA timer IRQs
2231  */
2232 static int __init timer_irq_works(void)
2233 {
2234         unsigned long t1 = jiffies;
2235         unsigned long flags;
2236
2237         if (no_timer_check)
2238                 return 1;
2239
2240         local_save_flags(flags);
2241         local_irq_enable();
2242         /* Let ten ticks pass... */
2243         mdelay((10 * 1000) / HZ);
2244         local_irq_restore(flags);
2245
2246         /*
2247          * Expect a few ticks at least, to be sure some possible
2248          * glue logic does not lock up after one or two first
2249          * ticks in a non-ExtINT mode.  Also the local APIC
2250          * might have cached one ExtINT interrupt.  Finally, at
2251          * least one tick may be lost due to delays.
2252          */
2253
2254         /* jiffies wrap? */
2255         if (time_after(jiffies, t1 + 4))
2256                 return 1;
2257         return 0;
2258 }
2259
2260 /*
2261  * In the SMP+IOAPIC case it might happen that there are an unspecified
2262  * number of pending IRQ events unhandled. These cases are very rare,
2263  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2264  * better to do it this way as thus we do not have to be aware of
2265  * 'pending' interrupts in the IRQ path, except at this point.
2266  */
2267 /*
2268  * Edge triggered needs to resend any interrupt
2269  * that was delayed but this is now handled in the device
2270  * independent code.
2271  */
2272
2273 /*
2274  * Starting up a edge-triggered IO-APIC interrupt is
2275  * nasty - we need to make sure that we get the edge.
2276  * If it is already asserted for some reason, we need
2277  * return 1 to indicate that is was pending.
2278  *
2279  * This is not complete - we should be able to fake
2280  * an edge even if it isn't on the 8259A...
2281  */
2282
2283 static unsigned int startup_ioapic_irq(unsigned int irq)
2284 {
2285         int was_pending = 0;
2286         unsigned long flags;
2287         struct irq_cfg *cfg;
2288
2289         spin_lock_irqsave(&ioapic_lock, flags);
2290         if (irq < NR_IRQS_LEGACY) {
2291                 disable_8259A_irq(irq);
2292                 if (i8259A_irq_pending(irq))
2293                         was_pending = 1;
2294         }
2295         cfg = irq_cfg(irq);
2296         __unmask_IO_APIC_irq(cfg);
2297         spin_unlock_irqrestore(&ioapic_lock, flags);
2298
2299         return was_pending;
2300 }
2301
2302 #ifdef CONFIG_X86_64
2303 static int ioapic_retrigger_irq(unsigned int irq)
2304 {
2305
2306         struct irq_cfg *cfg = irq_cfg(irq);
2307         unsigned long flags;
2308
2309         spin_lock_irqsave(&vector_lock, flags);
2310         apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2311         spin_unlock_irqrestore(&vector_lock, flags);
2312
2313         return 1;
2314 }
2315 #else
2316 static int ioapic_retrigger_irq(unsigned int irq)
2317 {
2318         apic->send_IPI_self(irq_cfg(irq)->vector);
2319
2320         return 1;
2321 }
2322 #endif
2323
2324 /*
2325  * Level and edge triggered IO-APIC interrupts need different handling,
2326  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2327  * handled with the level-triggered descriptor, but that one has slightly
2328  * more overhead. Level-triggered interrupts cannot be handled with the
2329  * edge-triggered handler, without risking IRQ storms and other ugly
2330  * races.
2331  */
2332
2333 #ifdef CONFIG_SMP
2334
2335 #ifdef CONFIG_INTR_REMAP
2336
2337 /*
2338  * Migrate the IO-APIC irq in the presence of intr-remapping.
2339  *
2340  * For both level and edge triggered, irq migration is a simple atomic
2341  * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2342  *
2343  * For level triggered, we eliminate the io-apic RTE modification (with the
2344  * updated vector information), by using a virtual vector (io-apic pin number).
2345  * Real vector that is used for interrupting cpu will be coming from
2346  * the interrupt-remapping table entry.
2347  */
2348 static void
2349 migrate_ioapic_irq_desc(struct irq_desc *desc, const struct cpumask *mask)
2350 {
2351         struct irq_cfg *cfg;
2352         struct irte irte;
2353         unsigned int dest;
2354         unsigned int irq;
2355
2356         if (!cpumask_intersects(mask, cpu_online_mask))
2357                 return;
2358
2359         irq = desc->irq;
2360         if (get_irte(irq, &irte))
2361                 return;
2362
2363         cfg = desc->chip_data;
2364         if (assign_irq_vector(irq, cfg, mask))
2365                 return;
2366
2367         set_extra_move_desc(desc, mask);
2368
2369         dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2370
2371         irte.vector = cfg->vector;
2372         irte.dest_id = IRTE_DEST(dest);
2373
2374         /*
2375          * Modified the IRTE and flushes the Interrupt entry cache.
2376          */
2377         modify_irte(irq, &irte);
2378
2379         if (cfg->move_in_progress)
2380                 send_cleanup_vector(cfg);
2381
2382         cpumask_copy(desc->affinity, mask);
2383 }
2384
2385 /*
2386  * Migrates the IRQ destination in the process context.
2387  */
2388 static void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2389                                             const struct cpumask *mask)
2390 {
2391         migrate_ioapic_irq_desc(desc, mask);
2392 }
2393 static void set_ir_ioapic_affinity_irq(unsigned int irq,
2394                                        const struct cpumask *mask)
2395 {
2396         struct irq_desc *desc = irq_to_desc(irq);
2397
2398         set_ir_ioapic_affinity_irq_desc(desc, mask);
2399 }
2400 #else
2401 static inline void set_ir_ioapic_affinity_irq_desc(struct irq_desc *desc,
2402                                                    const struct cpumask *mask)
2403 {
2404 }
2405 #endif
2406
2407 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2408 {
2409         unsigned vector, me;
2410
2411         ack_APIC_irq();
2412         exit_idle();
2413         irq_enter();
2414
2415         me = smp_processor_id();
2416         for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2417                 unsigned int irq;
2418                 unsigned int irr;
2419                 struct irq_desc *desc;
2420                 struct irq_cfg *cfg;
2421                 irq = __get_cpu_var(vector_irq)[vector];
2422
2423                 if (irq == -1)
2424                         continue;
2425
2426                 desc = irq_to_desc(irq);
2427                 if (!desc)
2428                         continue;
2429
2430                 cfg = irq_cfg(irq);
2431                 spin_lock(&desc->lock);
2432                 if (!cfg->move_cleanup_count)
2433                         goto unlock;
2434
2435                 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2436                         goto unlock;
2437
2438                 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2439                 /*
2440                  * Check if the vector that needs to be cleanedup is
2441                  * registered at the cpu's IRR. If so, then this is not
2442                  * the best time to clean it up. Lets clean it up in the
2443                  * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2444                  * to myself.
2445                  */
2446                 if (irr  & (1 << (vector % 32))) {
2447                         apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2448                         goto unlock;
2449                 }
2450                 __get_cpu_var(vector_irq)[vector] = -1;
2451                 cfg->move_cleanup_count--;
2452 unlock:
2453                 spin_unlock(&desc->lock);
2454         }
2455
2456         irq_exit();
2457 }
2458
2459 static void irq_complete_move(struct irq_desc **descp)
2460 {
2461         struct irq_desc *desc = *descp;
2462         struct irq_cfg *cfg = desc->chip_data;
2463         unsigned vector, me;
2464
2465         if (likely(!cfg->move_in_progress)) {
2466 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2467                 if (likely(!cfg->move_desc_pending))
2468                         return;
2469
2470                 /* domain has not changed, but affinity did */
2471                 me = smp_processor_id();
2472                 if (cpumask_test_cpu(me, desc->affinity)) {
2473                         *descp = desc = move_irq_desc(desc, me);
2474                         /* get the new one */
2475                         cfg = desc->chip_data;
2476                         cfg->move_desc_pending = 0;
2477                 }
2478 #endif
2479                 return;
2480         }
2481
2482         vector = ~get_irq_regs()->orig_ax;
2483         me = smp_processor_id();
2484
2485         if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain)) {
2486 #ifdef CONFIG_NUMA_MIGRATE_IRQ_DESC
2487                 *descp = desc = move_irq_desc(desc, me);
2488                 /* get the new one */
2489                 cfg = desc->chip_data;
2490 #endif
2491                 send_cleanup_vector(cfg);
2492         }
2493 }
2494 #else
2495 static inline void irq_complete_move(struct irq_desc **descp) {}
2496 #endif
2497
2498 #ifdef CONFIG_INTR_REMAP
2499 static void __eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
2500 {
2501         int apic, pin;
2502         struct irq_pin_list *entry;
2503
2504         entry = cfg->irq_2_pin;
2505         for (;;) {
2506
2507                 if (!entry)
2508                         break;
2509
2510                 apic = entry->apic;
2511                 pin = entry->pin;
2512                 io_apic_eoi(apic, pin);
2513                 entry = entry->next;
2514         }
2515 }
2516
2517 static void
2518 eoi_ioapic_irq(struct irq_desc *desc)
2519 {
2520         struct irq_cfg *cfg;
2521         unsigned long flags;
2522         unsigned int irq;
2523
2524         irq = desc->irq;
2525         cfg = desc->chip_data;
2526
2527         spin_lock_irqsave(&ioapic_lock, flags);
2528         __eoi_ioapic_irq(irq, cfg);
2529         spin_unlock_irqrestore(&ioapic_lock, flags);
2530 }
2531
2532 static void ack_x2apic_level(unsigned int irq)
2533 {
2534         struct irq_desc *desc = irq_to_desc(irq);
2535         ack_x2APIC_irq();
2536         eoi_ioapic_irq(desc);
2537 }
2538
2539 static void ack_x2apic_edge(unsigned int irq)
2540 {
2541         ack_x2APIC_irq();
2542 }
2543
2544 #endif
2545
2546 static void ack_apic_edge(unsigned int irq)
2547 {
2548         struct irq_desc *desc = irq_to_desc(irq);
2549
2550         irq_complete_move(&desc);
2551         move_native_irq(irq);
2552         ack_APIC_irq();
2553 }
2554
2555 atomic_t irq_mis_count;
2556
2557 static void ack_apic_level(unsigned int irq)
2558 {
2559         struct irq_desc *desc = irq_to_desc(irq);
2560
2561 #ifdef CONFIG_X86_32
2562         unsigned long v;
2563         int i;
2564 #endif
2565         struct irq_cfg *cfg;
2566         int do_unmask_irq = 0;
2567
2568         irq_complete_move(&desc);
2569 #ifdef CONFIG_GENERIC_PENDING_IRQ
2570         /* If we are moving the irq we need to mask it */
2571         if (unlikely(desc->status & IRQ_MOVE_PENDING)) {
2572                 do_unmask_irq = 1;
2573                 mask_IO_APIC_irq_desc(desc);
2574         }
2575 #endif
2576
2577 #ifdef CONFIG_X86_32
2578         /*
2579         * It appears there is an erratum which affects at least version 0x11
2580         * of I/O APIC (that's the 82093AA and cores integrated into various
2581         * chipsets).  Under certain conditions a level-triggered interrupt is
2582         * erroneously delivered as edge-triggered one but the respective IRR
2583         * bit gets set nevertheless.  As a result the I/O unit expects an EOI
2584         * message but it will never arrive and further interrupts are blocked
2585         * from the source.  The exact reason is so far unknown, but the
2586         * phenomenon was observed when two consecutive interrupt requests
2587         * from a given source get delivered to the same CPU and the source is
2588         * temporarily disabled in between.
2589         *
2590         * A workaround is to simulate an EOI message manually.  We achieve it
2591         * by setting the trigger mode to edge and then to level when the edge
2592         * trigger mode gets detected in the TMR of a local APIC for a
2593         * level-triggered interrupt.  We mask the source for the time of the
2594         * operation to prevent an edge-triggered interrupt escaping meanwhile.
2595         * The idea is from Manfred Spraul.  --macro
2596         */
2597         cfg = desc->chip_data;
2598         i = cfg->vector;
2599
2600         v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2601 #endif
2602
2603         /*
2604          * We must acknowledge the irq before we move it or the acknowledge will
2605          * not propagate properly.
2606          */
2607         ack_APIC_irq();
2608
2609         /* Now we can move and renable the irq */
2610         if (unlikely(do_unmask_irq)) {
2611                 /* Only migrate the irq if the ack has been received.
2612                  *
2613                  * On rare occasions the broadcast level triggered ack gets
2614                  * delayed going to ioapics, and if we reprogram the
2615                  * vector while Remote IRR is still set the irq will never
2616                  * fire again.
2617                  *
2618                  * To prevent this scenario we read the Remote IRR bit
2619                  * of the ioapic.  This has two effects.
2620                  * - On any sane system the read of the ioapic will
2621                  *   flush writes (and acks) going to the ioapic from
2622                  *   this cpu.
2623                  * - We get to see if the ACK has actually been delivered.
2624                  *
2625                  * Based on failed experiments of reprogramming the
2626                  * ioapic entry from outside of irq context starting
2627                  * with masking the ioapic entry and then polling until
2628                  * Remote IRR was clear before reprogramming the
2629                  * ioapic I don't trust the Remote IRR bit to be
2630                  * completey accurate.
2631                  *
2632                  * However there appears to be no other way to plug
2633                  * this race, so if the Remote IRR bit is not
2634                  * accurate and is causing problems then it is a hardware bug
2635                  * and you can go talk to the chipset vendor about it.
2636                  */
2637                 cfg = desc->chip_data;
2638                 if (!io_apic_level_ack_pending(cfg))
2639                         move_masked_irq(irq);
2640                 unmask_IO_APIC_irq_desc(desc);
2641         }
2642
2643 #ifdef CONFIG_X86_32
2644         if (!(v & (1 << (i & 0x1f)))) {
2645                 atomic_inc(&irq_mis_count);
2646                 spin_lock(&ioapic_lock);
2647                 __mask_and_edge_IO_APIC_irq(cfg);
2648                 __unmask_and_level_IO_APIC_irq(cfg);
2649                 spin_unlock(&ioapic_lock);
2650         }
2651 #endif
2652 }
2653
2654 static struct irq_chip ioapic_chip __read_mostly = {
2655         .name           = "IO-APIC",
2656         .startup        = startup_ioapic_irq,
2657         .mask           = mask_IO_APIC_irq,
2658         .unmask         = unmask_IO_APIC_irq,
2659         .ack            = ack_apic_edge,
2660         .eoi            = ack_apic_level,
2661 #ifdef CONFIG_SMP
2662         .set_affinity   = set_ioapic_affinity_irq,
2663 #endif
2664         .retrigger      = ioapic_retrigger_irq,
2665 };
2666
2667 static struct irq_chip ir_ioapic_chip __read_mostly = {
2668         .name           = "IR-IO-APIC",
2669         .startup        = startup_ioapic_irq,
2670         .mask           = mask_IO_APIC_irq,
2671         .unmask         = unmask_IO_APIC_irq,
2672 #ifdef CONFIG_INTR_REMAP
2673         .ack            = ack_x2apic_edge,
2674         .eoi            = ack_x2apic_level,
2675 #ifdef CONFIG_SMP
2676         .set_affinity   = set_ir_ioapic_affinity_irq,
2677 #endif
2678 #endif
2679         .retrigger      = ioapic_retrigger_irq,
2680 };
2681
2682 static inline void init_IO_APIC_traps(void)
2683 {
2684         int irq;
2685         struct irq_desc *desc;
2686         struct irq_cfg *cfg;
2687
2688         /*
2689          * NOTE! The local APIC isn't very good at handling
2690          * multiple interrupts at the same interrupt level.
2691          * As the interrupt level is determined by taking the
2692          * vector number and shifting that right by 4, we
2693          * want to spread these out a bit so that they don't
2694          * all fall in the same interrupt level.
2695          *
2696          * Also, we've got to be careful not to trash gate
2697          * 0x80, because int 0x80 is hm, kind of importantish. ;)
2698          */
2699         for_each_irq_desc(irq, desc) {
2700                 cfg = desc->chip_data;
2701                 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2702                         /*
2703                          * Hmm.. We don't have an entry for this,
2704                          * so default to an old-fashioned 8259
2705                          * interrupt if we can..
2706                          */
2707                         if (irq < NR_IRQS_LEGACY)
2708                                 make_8259A_irq(irq);
2709                         else
2710                                 /* Strange. Oh, well.. */
2711                                 desc->chip = &no_irq_chip;
2712                 }
2713         }
2714 }
2715
2716 /*
2717  * The local APIC irq-chip implementation:
2718  */
2719
2720 static void mask_lapic_irq(unsigned int irq)
2721 {
2722         unsigned long v;
2723
2724         v = apic_read(APIC_LVT0);
2725         apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2726 }
2727
2728 static void unmask_lapic_irq(unsigned int irq)
2729 {
2730         unsigned long v;
2731
2732         v = apic_read(APIC_LVT0);
2733         apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2734 }
2735
2736 static void ack_lapic_irq(unsigned int irq)
2737 {
2738         ack_APIC_irq();
2739 }
2740
2741 static struct irq_chip lapic_chip __read_mostly = {
2742         .name           = "local-APIC",
2743         .mask           = mask_lapic_irq,
2744         .unmask         = unmask_lapic_irq,
2745         .ack            = ack_lapic_irq,
2746 };
2747
2748 static void lapic_register_intr(int irq, struct irq_desc *desc)
2749 {
2750         desc->status &= ~IRQ_LEVEL;
2751         set_irq_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2752                                       "edge");
2753 }
2754
2755 static void __init setup_nmi(void)
2756 {
2757         /*
2758          * Dirty trick to enable the NMI watchdog ...
2759          * We put the 8259A master into AEOI mode and
2760          * unmask on all local APICs LVT0 as NMI.
2761          *
2762          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
2763          * is from Maciej W. Rozycki - so we do not have to EOI from
2764          * the NMI handler or the timer interrupt.
2765          */
2766         apic_printk(APIC_VERBOSE, KERN_INFO "activating NMI Watchdog ...");
2767
2768         enable_NMI_through_LVT0();
2769
2770         apic_printk(APIC_VERBOSE, " done.\n");
2771 }
2772
2773 /*
2774  * This looks a bit hackish but it's about the only one way of sending
2775  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
2776  * not support the ExtINT mode, unfortunately.  We need to send these
2777  * cycles as some i82489DX-based boards have glue logic that keeps the
2778  * 8259A interrupt line asserted until INTA.  --macro
2779  */
2780 static inline void __init unlock_ExtINT_logic(void)
2781 {
2782         int apic, pin, i;
2783         struct IO_APIC_route_entry entry0, entry1;
2784         unsigned char save_control, save_freq_select;
2785
2786         pin  = find_isa_irq_pin(8, mp_INT);
2787         if (pin == -1) {
2788                 WARN_ON_ONCE(1);
2789                 return;
2790         }
2791         apic = find_isa_irq_apic(8, mp_INT);
2792         if (apic == -1) {
2793                 WARN_ON_ONCE(1);
2794                 return;
2795         }
2796
2797         entry0 = ioapic_read_entry(apic, pin);
2798         clear_IO_APIC_pin(apic, pin);
2799
2800         memset(&entry1, 0, sizeof(entry1));
2801
2802         entry1.dest_mode = 0;                   /* physical delivery */
2803         entry1.mask = 0;                        /* unmask IRQ now */
2804         entry1.dest = hard_smp_processor_id();
2805         entry1.delivery_mode = dest_ExtINT;
2806         entry1.polarity = entry0.polarity;
2807         entry1.trigger = 0;
2808         entry1.vector = 0;
2809
2810         ioapic_write_entry(apic, pin, entry1);
2811
2812         save_control = CMOS_READ(RTC_CONTROL);
2813         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2814         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2815                    RTC_FREQ_SELECT);
2816         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2817
2818         i = 100;
2819         while (i-- > 0) {
2820                 mdelay(10);
2821                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2822                         i -= 10;
2823         }
2824
2825         CMOS_WRITE(save_control, RTC_CONTROL);
2826         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2827         clear_IO_APIC_pin(apic, pin);
2828
2829         ioapic_write_entry(apic, pin, entry0);
2830 }
2831
2832 static int disable_timer_pin_1 __initdata;
2833 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2834 static int __init disable_timer_pin_setup(char *arg)
2835 {
2836         disable_timer_pin_1 = 1;
2837         return 0;
2838 }
2839 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2840
2841 int timer_through_8259 __initdata;
2842
2843 /*
2844  * This code may look a bit paranoid, but it's supposed to cooperate with
2845  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
2846  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
2847  * fanatically on his truly buggy board.
2848  *
2849  * FIXME: really need to revamp this for all platforms.
2850  */
2851 static inline void __init check_timer(void)
2852 {
2853         struct irq_desc *desc = irq_to_desc(0);
2854         struct irq_cfg *cfg = desc->chip_data;
2855         int cpu = boot_cpu_id;
2856         int apic1, pin1, apic2, pin2;
2857         unsigned long flags;
2858         int no_pin1 = 0;
2859
2860         local_irq_save(flags);
2861
2862         /*
2863          * get/set the timer IRQ vector:
2864          */
2865         disable_8259A_irq(0);
2866         assign_irq_vector(0, cfg, apic->target_cpus());
2867
2868         /*
2869          * As IRQ0 is to be enabled in the 8259A, the virtual
2870          * wire has to be disabled in the local APIC.  Also
2871          * timer interrupts need to be acknowledged manually in
2872          * the 8259A for the i82489DX when using the NMI
2873          * watchdog as that APIC treats NMIs as level-triggered.
2874          * The AEOI mode will finish them in the 8259A
2875          * automatically.
2876          */
2877         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2878         init_8259A(1);
2879 #ifdef CONFIG_X86_32
2880         {
2881                 unsigned int ver;
2882
2883                 ver = apic_read(APIC_LVR);
2884                 ver = GET_APIC_VERSION(ver);
2885                 timer_ack = (nmi_watchdog == NMI_IO_APIC && !APIC_INTEGRATED(ver));
2886         }
2887 #endif
2888
2889         pin1  = find_isa_irq_pin(0, mp_INT);
2890         apic1 = find_isa_irq_apic(0, mp_INT);
2891         pin2  = ioapic_i8259.pin;
2892         apic2 = ioapic_i8259.apic;
2893
2894         apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2895                     "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2896                     cfg->vector, apic1, pin1, apic2, pin2);
2897
2898         /*
2899          * Some BIOS writers are clueless and report the ExtINTA
2900          * I/O APIC input from the cascaded 8259A as the timer
2901          * interrupt input.  So just in case, if only one pin
2902          * was found above, try it both directly and through the
2903          * 8259A.
2904          */
2905         if (pin1 == -1) {
2906                 if (intr_remapping_enabled)
2907                         panic("BIOS bug: timer not connected to IO-APIC");
2908                 pin1 = pin2;
2909                 apic1 = apic2;
2910                 no_pin1 = 1;
2911         } else if (pin2 == -1) {
2912                 pin2 = pin1;
2913                 apic2 = apic1;
2914         }
2915
2916         if (pin1 != -1) {
2917                 /*
2918                  * Ok, does IRQ0 through the IOAPIC work?
2919                  */
2920                 if (no_pin1) {
2921                         add_pin_to_irq_cpu(cfg, cpu, apic1, pin1);
2922                         setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2923                 } else {
2924                         /* for edge trigger, setup_IO_APIC_irq already
2925                          * leave it unmasked.
2926                          * so only need to unmask if it is level-trigger
2927                          * do we really have level trigger timer?
2928                          */
2929                         int idx;
2930                         idx = find_irq_entry(apic1, pin1, mp_INT);
2931                         if (idx != -1 && irq_trigger(idx))
2932                                 unmask_IO_APIC_irq_desc(desc);
2933                 }
2934                 if (timer_irq_works()) {
2935                         if (nmi_watchdog == NMI_IO_APIC) {
2936                                 setup_nmi();
2937                                 enable_8259A_irq(0);
2938                         }
2939                         if (disable_timer_pin_1 > 0)
2940                                 clear_IO_APIC_pin(0, pin1);
2941                         goto out;
2942                 }
2943                 if (intr_remapping_enabled)
2944                         panic("timer doesn't work through Interrupt-remapped IO-APIC");
2945                 local_irq_disable();
2946                 clear_IO_APIC_pin(apic1, pin1);
2947                 if (!no_pin1)
2948                         apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2949                                     "8254 timer not connected to IO-APIC\n");
2950
2951                 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2952                             "(IRQ0) through the 8259A ...\n");
2953                 apic_printk(APIC_QUIET, KERN_INFO
2954                             "..... (found apic %d pin %d) ...\n", apic2, pin2);
2955                 /*
2956                  * legacy devices should be connected to IO APIC #0
2957                  */
2958                 replace_pin_at_irq_cpu(cfg, cpu, apic1, pin1, apic2, pin2);
2959                 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2960                 enable_8259A_irq(0);
2961                 if (timer_irq_works()) {
2962                         apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2963                         timer_through_8259 = 1;
2964                         if (nmi_watchdog == NMI_IO_APIC) {
2965                                 disable_8259A_irq(0);
2966                                 setup_nmi();
2967                                 enable_8259A_irq(0);
2968                         }
2969                         goto out;
2970                 }
2971                 /*
2972                  * Cleanup, just in case ...
2973                  */
2974                 local_irq_disable();
2975                 disable_8259A_irq(0);
2976                 clear_IO_APIC_pin(apic2, pin2);
2977                 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2978         }
2979
2980         if (nmi_watchdog == NMI_IO_APIC) {
2981                 apic_printk(APIC_QUIET, KERN_WARNING "timer doesn't work "
2982                             "through the IO-APIC - disabling NMI Watchdog!\n");
2983                 nmi_watchdog = NMI_NONE;
2984         }
2985 #ifdef CONFIG_X86_32
2986         timer_ack = 0;
2987 #endif
2988
2989         apic_printk(APIC_QUIET, KERN_INFO
2990                     "...trying to set up timer as Virtual Wire IRQ...\n");
2991
2992         lapic_register_intr(0, desc);
2993         apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector);     /* Fixed mode */
2994         enable_8259A_irq(0);
2995
2996         if (timer_irq_works()) {
2997                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2998                 goto out;
2999         }
3000         local_irq_disable();
3001         disable_8259A_irq(0);
3002         apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
3003         apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
3004
3005         apic_printk(APIC_QUIET, KERN_INFO
3006                     "...trying to set up timer as ExtINT IRQ...\n");
3007
3008         init_8259A(0);
3009         make_8259A_irq(0);
3010         apic_write(APIC_LVT0, APIC_DM_EXTINT);
3011
3012         unlock_ExtINT_logic();
3013
3014         if (timer_irq_works()) {
3015                 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
3016                 goto out;
3017         }
3018         local_irq_disable();
3019         apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
3020         panic("IO-APIC + timer doesn't work!  Boot with apic=debug and send a "
3021                 "report.  Then try booting with the 'noapic' option.\n");
3022 out:
3023         local_irq_restore(flags);
3024 }
3025
3026 /*
3027  * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
3028  * to devices.  However there may be an I/O APIC pin available for
3029  * this interrupt regardless.  The pin may be left unconnected, but
3030  * typically it will be reused as an ExtINT cascade interrupt for
3031  * the master 8259A.  In the MPS case such a pin will normally be
3032  * reported as an ExtINT interrupt in the MP table.  With ACPI
3033  * there is no provision for ExtINT interrupts, and in the absence
3034  * of an override it would be treated as an ordinary ISA I/O APIC
3035  * interrupt, that is edge-triggered and unmasked by default.  We
3036  * used to do this, but it caused problems on some systems because
3037  * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
3038  * the same ExtINT cascade interrupt to drive the local APIC of the
3039  * bootstrap processor.  Therefore we refrain from routing IRQ2 to
3040  * the I/O APIC in all cases now.  No actual device should request
3041  * it anyway.  --macro
3042  */
3043 #define PIC_IRQS        (1 << PIC_CASCADE_IR)
3044
3045 void __init setup_IO_APIC(void)
3046 {
3047
3048         /*
3049          * calling enable_IO_APIC() is moved to setup_local_APIC for BP
3050          */
3051
3052         io_apic_irqs = ~PIC_IRQS;
3053
3054         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
3055         /*
3056          * Set up IO-APIC IRQ routing.
3057          */
3058 #ifdef CONFIG_X86_32
3059         if (!acpi_ioapic)
3060                 setup_ioapic_ids_from_mpc();
3061 #endif
3062         sync_Arb_IDs();
3063         setup_IO_APIC_irqs();
3064         init_IO_APIC_traps();
3065         check_timer();
3066 }
3067
3068 /*
3069  *      Called after all the initialization is done. If we didnt find any
3070  *      APIC bugs then we can allow the modify fast path
3071  */
3072
3073 static int __init io_apic_bug_finalize(void)
3074 {
3075         if (sis_apic_bug == -1)
3076                 sis_apic_bug = 0;
3077         return 0;
3078 }
3079
3080 late_initcall(io_apic_bug_finalize);
3081
3082 struct sysfs_ioapic_data {
3083         struct sys_device dev;
3084         struct IO_APIC_route_entry entry[0];
3085 };
3086 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
3087
3088 static int ioapic_suspend(struct sys_device *dev, pm_message_t state)
3089 {
3090         struct IO_APIC_route_entry *entry;
3091         struct sysfs_ioapic_data *data;
3092         int i;
3093
3094         data = container_of(dev, struct sysfs_ioapic_data, dev);
3095         entry = data->entry;
3096         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ )
3097                 *entry = ioapic_read_entry(dev->id, i);
3098
3099         return 0;
3100 }
3101
3102 static int ioapic_resume(struct sys_device *dev)
3103 {
3104         struct IO_APIC_route_entry *entry;
3105         struct sysfs_ioapic_data *data;
3106         unsigned long flags;
3107         union IO_APIC_reg_00 reg_00;
3108         int i;
3109
3110         data = container_of(dev, struct sysfs_ioapic_data, dev);
3111         entry = data->entry;
3112
3113         spin_lock_irqsave(&ioapic_lock, flags);
3114         reg_00.raw = io_apic_read(dev->id, 0);
3115         if (reg_00.bits.ID != mp_ioapics[dev->id].apicid) {
3116                 reg_00.bits.ID = mp_ioapics[dev->id].apicid;
3117                 io_apic_write(dev->id, 0, reg_00.raw);
3118         }
3119         spin_unlock_irqrestore(&ioapic_lock, flags);
3120         for (i = 0; i < nr_ioapic_registers[dev->id]; i++)
3121                 ioapic_write_entry(dev->id, i, entry[i]);
3122
3123         return 0;
3124 }
3125
3126 static struct sysdev_class ioapic_sysdev_class = {
3127         .name = "ioapic",
3128         .suspend = ioapic_suspend,
3129         .resume = ioapic_resume,
3130 };
3131
3132 static int __init ioapic_init_sysfs(void)
3133 {
3134         struct sys_device * dev;
3135         int i, size, error;
3136
3137         error = sysdev_class_register(&ioapic_sysdev_class);
3138         if (error)
3139                 return error;
3140
3141         for (i = 0; i < nr_ioapics; i++ ) {
3142                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
3143                         * sizeof(struct IO_APIC_route_entry);
3144                 mp_ioapic_data[i] = kzalloc(size, GFP_KERNEL);
3145                 if (!mp_ioapic_data[i]) {
3146                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3147                         continue;
3148                 }
3149                 dev = &mp_ioapic_data[i]->dev;
3150                 dev->id = i;
3151                 dev->cls = &ioapic_sysdev_class;
3152                 error = sysdev_register(dev);
3153                 if (error) {
3154                         kfree(mp_ioapic_data[i]);
3155                         mp_ioapic_data[i] = NULL;
3156                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
3157                         continue;
3158                 }
3159         }
3160
3161         return 0;
3162 }
3163
3164 device_initcall(ioapic_init_sysfs);
3165
3166 static int nr_irqs_gsi = NR_IRQS_LEGACY;
3167 /*
3168  * Dynamic irq allocate and deallocation
3169  */
3170 unsigned int create_irq_nr(unsigned int irq_want)
3171 {
3172         /* Allocate an unused irq */
3173         unsigned int irq;
3174         unsigned int new;
3175         unsigned long flags;
3176         struct irq_cfg *cfg_new = NULL;
3177         int cpu = boot_cpu_id;
3178         struct irq_desc *desc_new = NULL;
3179
3180         irq = 0;
3181         if (irq_want < nr_irqs_gsi)
3182                 irq_want = nr_irqs_gsi;
3183
3184         spin_lock_irqsave(&vector_lock, flags);
3185         for (new = irq_want; new < nr_irqs; new++) {
3186                 desc_new = irq_to_desc_alloc_cpu(new, cpu);
3187                 if (!desc_new) {
3188                         printk(KERN_INFO "can not get irq_desc for %d\n", new);
3189                         continue;
3190                 }
3191                 cfg_new = desc_new->chip_data;
3192
3193                 if (cfg_new->vector != 0)
3194                         continue;
3195                 if (__assign_irq_vector(new, cfg_new, apic->target_cpus()) == 0)
3196                         irq = new;
3197                 break;
3198         }
3199         spin_unlock_irqrestore(&vector_lock, flags);
3200
3201         if (irq > 0) {
3202                 dynamic_irq_init(irq);
3203                 /* restore it, in case dynamic_irq_init clear it */
3204                 if (desc_new)
3205                         desc_new->chip_data = cfg_new;
3206         }
3207         return irq;
3208 }
3209
3210 int create_irq(void)
3211 {
3212         unsigned int irq_want;
3213         int irq;
3214
3215         irq_want = nr_irqs_gsi;
3216         irq = create_irq_nr(irq_want);
3217
3218         if (irq == 0)
3219                 irq = -1;
3220
3221         return irq;
3222 }
3223
3224 void destroy_irq(unsigned int irq)
3225 {
3226         unsigned long flags;
3227         struct irq_cfg *cfg;
3228         struct irq_desc *desc;
3229
3230         /* store it, in case dynamic_irq_cleanup clear it */
3231         desc = irq_to_desc(irq);
3232         cfg = desc->chip_data;
3233         dynamic_irq_cleanup(irq);
3234         /* connect back irq_cfg */
3235         if (desc)
3236                 desc->chip_data = cfg;
3237
3238         free_irte(irq);
3239         spin_lock_irqsave(&vector_lock, flags);
3240         __clear_irq_vector(irq, cfg);
3241         spin_unlock_irqrestore(&vector_lock, flags);
3242 }
3243
3244 /*
3245  * MSI message composition
3246  */
3247 #ifdef CONFIG_PCI_MSI
3248 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_msg *msg)
3249 {
3250         struct irq_cfg *cfg;
3251         int err;
3252         unsigned dest;
3253
3254         if (disable_apic)
3255                 return -ENXIO;
3256
3257         cfg = irq_cfg(irq);
3258         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3259         if (err)
3260                 return err;
3261
3262         dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3263
3264         if (irq_remapped(irq)) {
3265                 struct irte irte;
3266                 int ir_index;
3267                 u16 sub_handle;
3268
3269                 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3270                 BUG_ON(ir_index == -1);
3271
3272                 memset (&irte, 0, sizeof(irte));
3273
3274                 irte.present = 1;
3275                 irte.dst_mode = apic->irq_dest_mode;
3276                 irte.trigger_mode = 0; /* edge */
3277                 irte.dlvry_mode = apic->irq_delivery_mode;
3278                 irte.vector = cfg->vector;
3279                 irte.dest_id = IRTE_DEST(dest);
3280
3281                 modify_irte(irq, &irte);
3282
3283                 msg->address_hi = MSI_ADDR_BASE_HI;
3284                 msg->data = sub_handle;
3285                 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3286                                   MSI_ADDR_IR_SHV |
3287                                   MSI_ADDR_IR_INDEX1(ir_index) |
3288                                   MSI_ADDR_IR_INDEX2(ir_index);
3289         } else {
3290                 if (x2apic_enabled())
3291                         msg->address_hi = MSI_ADDR_BASE_HI |
3292                                           MSI_ADDR_EXT_DEST_ID(dest);
3293                 else
3294                         msg->address_hi = MSI_ADDR_BASE_HI;
3295
3296                 msg->address_lo =
3297                         MSI_ADDR_BASE_LO |
3298                         ((apic->irq_dest_mode == 0) ?
3299                                 MSI_ADDR_DEST_MODE_PHYSICAL:
3300                                 MSI_ADDR_DEST_MODE_LOGICAL) |
3301                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3302                                 MSI_ADDR_REDIRECTION_CPU:
3303                                 MSI_ADDR_REDIRECTION_LOWPRI) |
3304                         MSI_ADDR_DEST_ID(dest);
3305
3306                 msg->data =
3307                         MSI_DATA_TRIGGER_EDGE |
3308                         MSI_DATA_LEVEL_ASSERT |
3309                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3310                                 MSI_DATA_DELIVERY_FIXED:
3311                                 MSI_DATA_DELIVERY_LOWPRI) |
3312                         MSI_DATA_VECTOR(cfg->vector);
3313         }
3314         return err;
3315 }
3316
3317 #ifdef CONFIG_SMP
3318 static void set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3319 {
3320         struct irq_desc *desc = irq_to_desc(irq);
3321         struct irq_cfg *cfg;
3322         struct msi_msg msg;
3323         unsigned int dest;
3324
3325         dest = set_desc_affinity(desc, mask);
3326         if (dest == BAD_APICID)
3327                 return;
3328
3329         cfg = desc->chip_data;
3330
3331         read_msi_msg_desc(desc, &msg);
3332
3333         msg.data &= ~MSI_DATA_VECTOR_MASK;
3334         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3335         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3336         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3337
3338         write_msi_msg_desc(desc, &msg);
3339 }
3340 #ifdef CONFIG_INTR_REMAP
3341 /*
3342  * Migrate the MSI irq to another cpumask. This migration is
3343  * done in the process context using interrupt-remapping hardware.
3344  */
3345 static void
3346 ir_set_msi_irq_affinity(unsigned int irq, const struct cpumask *mask)
3347 {
3348         struct irq_desc *desc = irq_to_desc(irq);
3349         struct irq_cfg *cfg = desc->chip_data;
3350         unsigned int dest;
3351         struct irte irte;
3352
3353         if (get_irte(irq, &irte))
3354                 return;
3355
3356         dest = set_desc_affinity(desc, mask);
3357         if (dest == BAD_APICID)
3358                 return;
3359
3360         irte.vector = cfg->vector;
3361         irte.dest_id = IRTE_DEST(dest);
3362
3363         /*
3364          * atomically update the IRTE with the new destination and vector.
3365          */
3366         modify_irte(irq, &irte);
3367
3368         /*
3369          * After this point, all the interrupts will start arriving
3370          * at the new destination. So, time to cleanup the previous
3371          * vector allocation.
3372          */
3373         if (cfg->move_in_progress)
3374                 send_cleanup_vector(cfg);
3375 }
3376
3377 #endif
3378 #endif /* CONFIG_SMP */
3379
3380 /*
3381  * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3382  * which implement the MSI or MSI-X Capability Structure.
3383  */
3384 static struct irq_chip msi_chip = {
3385         .name           = "PCI-MSI",
3386         .unmask         = unmask_msi_irq,
3387         .mask           = mask_msi_irq,
3388         .ack            = ack_apic_edge,
3389 #ifdef CONFIG_SMP
3390         .set_affinity   = set_msi_irq_affinity,
3391 #endif
3392         .retrigger      = ioapic_retrigger_irq,
3393 };
3394
3395 static struct irq_chip msi_ir_chip = {
3396         .name           = "IR-PCI-MSI",
3397         .unmask         = unmask_msi_irq,
3398         .mask           = mask_msi_irq,
3399 #ifdef CONFIG_INTR_REMAP
3400         .ack            = ack_x2apic_edge,
3401 #ifdef CONFIG_SMP
3402         .set_affinity   = ir_set_msi_irq_affinity,
3403 #endif
3404 #endif
3405         .retrigger      = ioapic_retrigger_irq,
3406 };
3407
3408 /*
3409  * Map the PCI dev to the corresponding remapping hardware unit
3410  * and allocate 'nvec' consecutive interrupt-remapping table entries
3411  * in it.
3412  */
3413 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3414 {
3415         struct intel_iommu *iommu;
3416         int index;
3417
3418         iommu = map_dev_to_ir(dev);
3419         if (!iommu) {
3420                 printk(KERN_ERR
3421                        "Unable to map PCI %s to iommu\n", pci_name(dev));
3422                 return -ENOENT;
3423         }
3424
3425         index = alloc_irte(iommu, irq, nvec);
3426         if (index < 0) {
3427                 printk(KERN_ERR
3428                        "Unable to allocate %d IRTE for PCI %s\n", nvec,
3429                        pci_name(dev));
3430                 return -ENOSPC;
3431         }
3432         return index;
3433 }
3434
3435 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3436 {
3437         int ret;
3438         struct msi_msg msg;
3439
3440         ret = msi_compose_msg(dev, irq, &msg);
3441         if (ret < 0)
3442                 return ret;
3443
3444         set_irq_msi(irq, msidesc);
3445         write_msi_msg(irq, &msg);
3446
3447         if (irq_remapped(irq)) {
3448                 struct irq_desc *desc = irq_to_desc(irq);
3449                 /*
3450                  * irq migration in process context
3451                  */
3452                 desc->status |= IRQ_MOVE_PCNTXT;
3453                 set_irq_chip_and_handler_name(irq, &msi_ir_chip, handle_edge_irq, "edge");
3454         } else
3455                 set_irq_chip_and_handler_name(irq, &msi_chip, handle_edge_irq, "edge");
3456
3457         dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3458
3459         return 0;
3460 }
3461
3462 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3463 {
3464         unsigned int irq;
3465         int ret, sub_handle;
3466         struct msi_desc *msidesc;
3467         unsigned int irq_want;
3468         struct intel_iommu *iommu = NULL;
3469         int index = 0;
3470
3471         irq_want = nr_irqs_gsi;
3472         sub_handle = 0;
3473         list_for_each_entry(msidesc, &dev->msi_list, list) {
3474                 irq = create_irq_nr(irq_want);
3475                 if (irq == 0)
3476                         return -1;
3477                 irq_want = irq + 1;
3478                 if (!intr_remapping_enabled)
3479                         goto no_ir;
3480
3481                 if (!sub_handle) {
3482                         /*
3483                          * allocate the consecutive block of IRTE's
3484                          * for 'nvec'
3485                          */
3486                         index = msi_alloc_irte(dev, irq, nvec);
3487                         if (index < 0) {
3488                                 ret = index;
3489                                 goto error;
3490                         }
3491                 } else {
3492                         iommu = map_dev_to_ir(dev);
3493                         if (!iommu) {
3494                                 ret = -ENOENT;
3495                                 goto error;
3496                         }
3497                         /*
3498                          * setup the mapping between the irq and the IRTE
3499                          * base index, the sub_handle pointing to the
3500                          * appropriate interrupt remap table entry.
3501                          */
3502                         set_irte_irq(irq, iommu, index, sub_handle);
3503                 }
3504 no_ir:
3505                 ret = setup_msi_irq(dev, msidesc, irq);
3506                 if (ret < 0)
3507                         goto error;
3508                 sub_handle++;
3509         }
3510         return 0;
3511
3512 error:
3513         destroy_irq(irq);
3514         return ret;
3515 }
3516
3517 void arch_teardown_msi_irq(unsigned int irq)
3518 {
3519         destroy_irq(irq);
3520 }
3521
3522 #if defined (CONFIG_DMAR) || defined (CONFIG_INTR_REMAP)
3523 #ifdef CONFIG_SMP
3524 static void dmar_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3525 {
3526         struct irq_desc *desc = irq_to_desc(irq);
3527         struct irq_cfg *cfg;
3528         struct msi_msg msg;
3529         unsigned int dest;
3530
3531         dest = set_desc_affinity(desc, mask);
3532         if (dest == BAD_APICID)
3533                 return;
3534
3535         cfg = desc->chip_data;
3536
3537         dmar_msi_read(irq, &msg);
3538
3539         msg.data &= ~MSI_DATA_VECTOR_MASK;
3540         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3541         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3542         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3543
3544         dmar_msi_write(irq, &msg);
3545 }
3546
3547 #endif /* CONFIG_SMP */
3548
3549 struct irq_chip dmar_msi_type = {
3550         .name = "DMAR_MSI",
3551         .unmask = dmar_msi_unmask,
3552         .mask = dmar_msi_mask,
3553         .ack = ack_apic_edge,
3554 #ifdef CONFIG_SMP
3555         .set_affinity = dmar_msi_set_affinity,
3556 #endif
3557         .retrigger = ioapic_retrigger_irq,
3558 };
3559
3560 int arch_setup_dmar_msi(unsigned int irq)
3561 {
3562         int ret;
3563         struct msi_msg msg;
3564
3565         ret = msi_compose_msg(NULL, irq, &msg);
3566         if (ret < 0)
3567                 return ret;
3568         dmar_msi_write(irq, &msg);
3569         set_irq_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3570                 "edge");
3571         return 0;
3572 }
3573 #endif
3574
3575 #ifdef CONFIG_HPET_TIMER
3576
3577 #ifdef CONFIG_SMP
3578 static void hpet_msi_set_affinity(unsigned int irq, const struct cpumask *mask)
3579 {
3580         struct irq_desc *desc = irq_to_desc(irq);
3581         struct irq_cfg *cfg;
3582         struct msi_msg msg;
3583         unsigned int dest;
3584
3585         dest = set_desc_affinity(desc, mask);
3586         if (dest == BAD_APICID)
3587                 return;
3588
3589         cfg = desc->chip_data;
3590
3591         hpet_msi_read(irq, &msg);
3592
3593         msg.data &= ~MSI_DATA_VECTOR_MASK;
3594         msg.data |= MSI_DATA_VECTOR(cfg->vector);
3595         msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3596         msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3597
3598         hpet_msi_write(irq, &msg);
3599 }
3600
3601 #endif /* CONFIG_SMP */
3602
3603 static struct irq_chip hpet_msi_type = {
3604         .name = "HPET_MSI",
3605         .unmask = hpet_msi_unmask,
3606         .mask = hpet_msi_mask,
3607         .ack = ack_apic_edge,
3608 #ifdef CONFIG_SMP
3609         .set_affinity = hpet_msi_set_affinity,
3610 #endif
3611         .retrigger = ioapic_retrigger_irq,
3612 };
3613
3614 int arch_setup_hpet_msi(unsigned int irq)
3615 {
3616         int ret;
3617         struct msi_msg msg;
3618
3619         ret = msi_compose_msg(NULL, irq, &msg);
3620         if (ret < 0)
3621                 return ret;
3622
3623         hpet_msi_write(irq, &msg);
3624         set_irq_chip_and_handler_name(irq, &hpet_msi_type, handle_edge_irq,
3625                 "edge");
3626
3627         return 0;
3628 }
3629 #endif
3630
3631 #endif /* CONFIG_PCI_MSI */
3632 /*
3633  * Hypertransport interrupt support
3634  */
3635 #ifdef CONFIG_HT_IRQ
3636
3637 #ifdef CONFIG_SMP
3638
3639 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3640 {
3641         struct ht_irq_msg msg;
3642         fetch_ht_irq_msg(irq, &msg);
3643
3644         msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3645         msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3646
3647         msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3648         msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3649
3650         write_ht_irq_msg(irq, &msg);
3651 }
3652
3653 static void set_ht_irq_affinity(unsigned int irq, const struct cpumask *mask)
3654 {
3655         struct irq_desc *desc = irq_to_desc(irq);
3656         struct irq_cfg *cfg;
3657         unsigned int dest;
3658
3659         dest = set_desc_affinity(desc, mask);
3660         if (dest == BAD_APICID)
3661                 return;
3662
3663         cfg = desc->chip_data;
3664
3665         target_ht_irq(irq, dest, cfg->vector);
3666 }
3667
3668 #endif
3669
3670 static struct irq_chip ht_irq_chip = {
3671         .name           = "PCI-HT",
3672         .mask           = mask_ht_irq,
3673         .unmask         = unmask_ht_irq,
3674         .ack            = ack_apic_edge,
3675 #ifdef CONFIG_SMP
3676         .set_affinity   = set_ht_irq_affinity,
3677 #endif
3678         .retrigger      = ioapic_retrigger_irq,
3679 };
3680
3681 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3682 {
3683         struct irq_cfg *cfg;
3684         int err;
3685
3686         if (disable_apic)
3687                 return -ENXIO;
3688
3689         cfg = irq_cfg(irq);
3690         err = assign_irq_vector(irq, cfg, apic->target_cpus());
3691         if (!err) {
3692                 struct ht_irq_msg msg;
3693                 unsigned dest;
3694
3695                 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3696                                                     apic->target_cpus());
3697
3698                 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3699
3700                 msg.address_lo =
3701                         HT_IRQ_LOW_BASE |
3702                         HT_IRQ_LOW_DEST_ID(dest) |
3703                         HT_IRQ_LOW_VECTOR(cfg->vector) |
3704                         ((apic->irq_dest_mode == 0) ?
3705                                 HT_IRQ_LOW_DM_PHYSICAL :
3706                                 HT_IRQ_LOW_DM_LOGICAL) |
3707                         HT_IRQ_LOW_RQEOI_EDGE |
3708                         ((apic->irq_delivery_mode != dest_LowestPrio) ?
3709                                 HT_IRQ_LOW_MT_FIXED :
3710                                 HT_IRQ_LOW_MT_ARBITRATED) |
3711                         HT_IRQ_LOW_IRQ_MASKED;
3712
3713                 write_ht_irq_msg(irq, &msg);
3714
3715                 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
3716                                               handle_edge_irq, "edge");
3717
3718                 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3719         }
3720         return err;
3721 }
3722 #endif /* CONFIG_HT_IRQ */
3723
3724 #ifdef CONFIG_X86_UV
3725 /*
3726  * Re-target the irq to the specified CPU and enable the specified MMR located
3727  * on the specified blade to allow the sending of MSIs to the specified CPU.
3728  */
3729 int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
3730                        unsigned long mmr_offset)
3731 {
3732         const struct cpumask *eligible_cpu = cpumask_of(cpu);
3733         struct irq_cfg *cfg;
3734         int mmr_pnode;
3735         unsigned long mmr_value;
3736         struct uv_IO_APIC_route_entry *entry;
3737         unsigned long flags;
3738         int err;
3739
3740         cfg = irq_cfg(irq);
3741
3742         err = assign_irq_vector(irq, cfg, eligible_cpu);
3743         if (err != 0)
3744                 return err;
3745
3746         spin_lock_irqsave(&vector_lock, flags);
3747         set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
3748                                       irq_name);
3749         spin_unlock_irqrestore(&vector_lock, flags);
3750
3751         mmr_value = 0;
3752         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3753         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3754
3755         entry->vector = cfg->vector;
3756         entry->delivery_mode = apic->irq_delivery_mode;
3757         entry->dest_mode = apic->irq_dest_mode;
3758         entry->polarity = 0;
3759         entry->trigger = 0;
3760         entry->mask = 0;
3761         entry->dest = apic->cpu_mask_to_apicid(eligible_cpu);
3762
3763         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3764         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3765
3766         return irq;
3767 }
3768
3769 /*
3770  * Disable the specified MMR located on the specified blade so that MSIs are
3771  * longer allowed to be sent.
3772  */
3773 void arch_disable_uv_irq(int mmr_blade, unsigned long mmr_offset)
3774 {
3775         unsigned long mmr_value;
3776         struct uv_IO_APIC_route_entry *entry;
3777         int mmr_pnode;
3778
3779         mmr_value = 0;
3780         entry = (struct uv_IO_APIC_route_entry *)&mmr_value;
3781         BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long));
3782
3783         entry->mask = 1;
3784
3785         mmr_pnode = uv_blade_to_pnode(mmr_blade);
3786         uv_write_global_mmr64(mmr_pnode, mmr_offset, mmr_value);
3787 }
3788 #endif /* CONFIG_X86_64 */
3789
3790 int __init io_apic_get_redir_entries (int ioapic)
3791 {
3792         union IO_APIC_reg_01    reg_01;
3793         unsigned long flags;
3794
3795         spin_lock_irqsave(&ioapic_lock, flags);
3796         reg_01.raw = io_apic_read(ioapic, 1);
3797         spin_unlock_irqrestore(&ioapic_lock, flags);
3798
3799         return reg_01.bits.entries;
3800 }
3801
3802 void __init probe_nr_irqs_gsi(void)
3803 {
3804         int nr = 0;
3805
3806         nr = acpi_probe_gsi();
3807         if (nr > nr_irqs_gsi) {
3808                 nr_irqs_gsi = nr;
3809         } else {
3810                 /* for acpi=off or acpi is not compiled in */
3811                 int idx;
3812
3813                 nr = 0;
3814                 for (idx = 0; idx < nr_ioapics; idx++)
3815                         nr += io_apic_get_redir_entries(idx) + 1;
3816
3817                 if (nr > nr_irqs_gsi)
3818                         nr_irqs_gsi = nr;
3819         }
3820
3821         printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3822 }
3823
3824 #ifdef CONFIG_SPARSE_IRQ
3825 int __init arch_probe_nr_irqs(void)
3826 {
3827         int nr;
3828
3829         if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3830                 nr_irqs = NR_VECTORS * nr_cpu_ids;
3831
3832         nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3833 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3834         /*
3835          * for MSI and HT dyn irq
3836          */
3837         nr += nr_irqs_gsi * 16;
3838 #endif
3839         if (nr < nr_irqs)
3840                 nr_irqs = nr;
3841
3842         return 0;
3843 }
3844 #endif
3845
3846 /* --------------------------------------------------------------------------
3847                           ACPI-based IOAPIC Configuration
3848    -------------------------------------------------------------------------- */
3849
3850 #ifdef CONFIG_ACPI
3851
3852 #ifdef CONFIG_X86_32
3853 int __init io_apic_get_unique_id(int ioapic, int apic_id)
3854 {
3855         union IO_APIC_reg_00 reg_00;
3856         static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3857         physid_mask_t tmp;
3858         unsigned long flags;
3859         int i = 0;
3860
3861         /*
3862          * The P4 platform supports up to 256 APIC IDs on two separate APIC
3863          * buses (one for LAPICs, one for IOAPICs), where predecessors only
3864          * supports up to 16 on one shared APIC bus.
3865          *
3866          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3867          *      advantage of new APIC bus architecture.
3868          */
3869
3870         if (physids_empty(apic_id_map))
3871                 apic_id_map = apic->ioapic_phys_id_map(phys_cpu_present_map);
3872
3873         spin_lock_irqsave(&ioapic_lock, flags);
3874         reg_00.raw = io_apic_read(ioapic, 0);
3875         spin_unlock_irqrestore(&ioapic_lock, flags);
3876
3877         if (apic_id >= get_physical_broadcast()) {
3878                 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3879                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
3880                 apic_id = reg_00.bits.ID;
3881         }
3882
3883         /*
3884          * Every APIC in a system must have a unique ID or we get lots of nice
3885          * 'stuck on smp_invalidate_needed IPI wait' messages.
3886          */
3887         if (apic->check_apicid_used(apic_id_map, apic_id)) {
3888
3889                 for (i = 0; i < get_physical_broadcast(); i++) {
3890                         if (!apic->check_apicid_used(apic_id_map, i))
3891                                 break;
3892                 }
3893
3894                 if (i == get_physical_broadcast())
3895                         panic("Max apic_id exceeded!\n");
3896
3897                 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3898                         "trying %d\n", ioapic, apic_id, i);
3899
3900                 apic_id = i;
3901         }
3902
3903         tmp = apic->apicid_to_cpu_present(apic_id);
3904         physids_or(apic_id_map, apic_id_map, tmp);
3905
3906         if (reg_00.bits.ID != apic_id) {
3907                 reg_00.bits.ID = apic_id;
3908
3909                 spin_lock_irqsave(&ioapic_lock, flags);
3910                 io_apic_write(ioapic, 0, reg_00.raw);
3911                 reg_00.raw = io_apic_read(ioapic, 0);
3912                 spin_unlock_irqrestore(&ioapic_lock, flags);
3913
3914                 /* Sanity check */
3915                 if (reg_00.bits.ID != apic_id) {
3916                         printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3917                         return -1;
3918                 }
3919         }
3920
3921         apic_printk(APIC_VERBOSE, KERN_INFO
3922                         "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3923
3924         return apic_id;
3925 }
3926
3927 int __init io_apic_get_version(int ioapic)
3928 {
3929         union IO_APIC_reg_01    reg_01;
3930         unsigned long flags;
3931
3932         spin_lock_irqsave(&ioapic_lock, flags);
3933         reg_01.raw = io_apic_read(ioapic, 1);
3934         spin_unlock_irqrestore(&ioapic_lock, flags);
3935
3936         return reg_01.bits.version;
3937 }
3938 #endif
3939
3940 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int triggering, int polarity)
3941 {
3942         struct irq_desc *desc;
3943         struct irq_cfg *cfg;
3944         int cpu = boot_cpu_id;
3945
3946         if (!IO_APIC_IRQ(irq)) {
3947                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3948                         ioapic);
3949                 return -EINVAL;
3950         }
3951
3952         desc = irq_to_desc_alloc_cpu(irq, cpu);
3953         if (!desc) {
3954                 printk(KERN_INFO "can not get irq_desc %d\n", irq);
3955                 return 0;
3956         }
3957
3958         /*
3959          * IRQs < 16 are already in the irq_2_pin[] map
3960          */
3961         if (irq >= NR_IRQS_LEGACY) {
3962                 cfg = desc->chip_data;
3963                 add_pin_to_irq_cpu(cfg, cpu, ioapic, pin);
3964         }
3965
3966         setup_IO_APIC_irq(ioapic, pin, irq, desc, triggering, polarity);
3967
3968         return 0;
3969 }
3970
3971
3972 int acpi_get_override_irq(int bus_irq, int *trigger, int *polarity)
3973 {
3974         int i;
3975
3976         if (skip_ioapic_setup)
3977                 return -1;
3978
3979         for (i = 0; i < mp_irq_entries; i++)
3980                 if (mp_irqs[i].irqtype == mp_INT &&
3981                     mp_irqs[i].srcbusirq == bus_irq)
3982                         break;
3983         if (i >= mp_irq_entries)
3984                 return -1;
3985
3986         *trigger = irq_trigger(i);
3987         *polarity = irq_polarity(i);
3988         return 0;
3989 }
3990
3991 #endif /* CONFIG_ACPI */
3992
3993 /*
3994  * This function currently is only a helper for the i386 smp boot process where
3995  * we need to reprogram the ioredtbls to cater for the cpus which have come online
3996  * so mask in all cases should simply be apic->target_cpus()
3997  */
3998 #ifdef CONFIG_SMP
3999 void __init setup_ioapic_dest(void)
4000 {
4001         int pin, ioapic, irq, irq_entry;
4002         struct irq_desc *desc;
4003         struct irq_cfg *cfg;
4004         const struct cpumask *mask;
4005
4006         if (skip_ioapic_setup == 1)
4007                 return;
4008
4009         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
4010                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
4011                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
4012                         if (irq_entry == -1)
4013                                 continue;
4014                         irq = pin_2_irq(irq_entry, ioapic, pin);
4015
4016                         /* setup_IO_APIC_irqs could fail to get vector for some device
4017                          * when you have too many devices, because at that time only boot
4018                          * cpu is online.
4019                          */
4020                         desc = irq_to_desc(irq);
4021                         cfg = desc->chip_data;
4022                         if (!cfg->vector) {
4023                                 setup_IO_APIC_irq(ioapic, pin, irq, desc,
4024                                                   irq_trigger(irq_entry),
4025                                                   irq_polarity(irq_entry));
4026                                 continue;
4027
4028                         }
4029
4030                         /*
4031                          * Honour affinities which have been set in early boot
4032                          */
4033                         if (desc->status &
4034                             (IRQ_NO_BALANCING | IRQ_AFFINITY_SET))
4035                                 mask = desc->affinity;
4036                         else
4037                                 mask = apic->target_cpus();
4038
4039                         if (intr_remapping_enabled)
4040                                 set_ir_ioapic_affinity_irq_desc(desc, mask);
4041                         else
4042                                 set_ioapic_affinity_irq_desc(desc, mask);
4043                 }
4044
4045         }
4046 }
4047 #endif
4048
4049 #define IOAPIC_RESOURCE_NAME_SIZE 11
4050
4051 static struct resource *ioapic_resources;
4052
4053 static struct resource * __init ioapic_setup_resources(void)
4054 {
4055         unsigned long n;
4056         struct resource *res;
4057         char *mem;
4058         int i;
4059
4060         if (nr_ioapics <= 0)
4061                 return NULL;
4062
4063         n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
4064         n *= nr_ioapics;
4065
4066         mem = alloc_bootmem(n);
4067         res = (void *)mem;
4068
4069         if (mem != NULL) {
4070                 mem += sizeof(struct resource) * nr_ioapics;
4071
4072                 for (i = 0; i < nr_ioapics; i++) {
4073                         res[i].name = mem;
4074                         res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
4075                         sprintf(mem,  "IOAPIC %u", i);
4076                         mem += IOAPIC_RESOURCE_NAME_SIZE;
4077                 }
4078         }
4079
4080         ioapic_resources = res;
4081
4082         return res;
4083 }
4084
4085 void __init ioapic_init_mappings(void)
4086 {
4087         unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
4088         struct resource *ioapic_res;
4089         int i;
4090
4091         ioapic_res = ioapic_setup_resources();
4092         for (i = 0; i < nr_ioapics; i++) {
4093                 if (smp_found_config) {
4094                         ioapic_phys = mp_ioapics[i].apicaddr;
4095 #ifdef CONFIG_X86_32
4096                         if (!ioapic_phys) {
4097                                 printk(KERN_ERR
4098                                        "WARNING: bogus zero IO-APIC "
4099                                        "address found in MPTABLE, "
4100                                        "disabling IO/APIC support!\n");
4101                                 smp_found_config = 0;
4102                                 skip_ioapic_setup = 1;
4103                                 goto fake_ioapic_page;
4104                         }
4105 #endif
4106                 } else {
4107 #ifdef CONFIG_X86_32
4108 fake_ioapic_page:
4109 #endif
4110                         ioapic_phys = (unsigned long)
4111                                 alloc_bootmem_pages(PAGE_SIZE);
4112                         ioapic_phys = __pa(ioapic_phys);
4113                 }
4114                 set_fixmap_nocache(idx, ioapic_phys);
4115                 apic_printk(APIC_VERBOSE,
4116                             "mapped IOAPIC to %08lx (%08lx)\n",
4117                             __fix_to_virt(idx), ioapic_phys);
4118                 idx++;
4119
4120                 if (ioapic_res != NULL) {
4121                         ioapic_res->start = ioapic_phys;
4122                         ioapic_res->end = ioapic_phys + (4 * 1024) - 1;
4123                         ioapic_res++;
4124                 }
4125         }
4126 }
4127
4128 static int __init ioapic_insert_resources(void)
4129 {
4130         int i;
4131         struct resource *r = ioapic_resources;
4132
4133         if (!r) {
4134                 if (nr_ioapics > 0) {
4135                         printk(KERN_ERR
4136                                 "IO APIC resources couldn't be allocated.\n");
4137                         return -1;
4138                 }
4139                 return 0;
4140         }
4141
4142         for (i = 0; i < nr_ioapics; i++) {
4143                 insert_resource(&iomem_resource, r);
4144                 r++;
4145         }
4146
4147         return 0;
4148 }
4149
4150 /* Insert the IO APIC resources after PCI initialization has occured to handle
4151  * IO APICS that are mapped in on a BAR in PCI space. */
4152 late_initcall(ioapic_insert_resources);