2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000, 2009 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/delay.h>
27 #include <linux/sched.h>
28 #include <linux/pci.h>
29 #include <linux/mc146818rtc.h>
30 #include <linux/compiler.h>
31 #include <linux/acpi.h>
32 #include <linux/module.h>
33 #include <linux/syscore_ops.h>
34 #include <linux/msi.h>
35 #include <linux/htirq.h>
36 #include <linux/freezer.h>
37 #include <linux/kthread.h>
38 #include <linux/jiffies.h> /* time_after() */
39 #include <linux/slab.h>
41 #include <acpi/acpi_bus.h>
43 #include <linux/bootmem.h>
44 #include <linux/dmar.h>
45 #include <linux/hpet.h>
52 #include <asm/proto.h>
55 #include <asm/timer.h>
56 #include <asm/i8259.h>
57 #include <asm/msidef.h>
58 #include <asm/hypertransport.h>
59 #include <asm/setup.h>
60 #include <asm/irq_remapping.h>
62 #include <asm/hw_irq.h>
66 #define __apicdebuginit(type) static type __init
67 #define for_each_irq_pin(entry, head) \
68 for (entry = head; entry; entry = entry->next)
71 * Is the SiS APIC rmw bug present ?
72 * -1 = don't know, 0 = no, 1 = yes
74 int sis_apic_bug = -1;
76 static DEFINE_RAW_SPINLOCK(ioapic_lock);
77 static DEFINE_RAW_SPINLOCK(vector_lock);
79 static struct ioapic {
81 * # of IRQ routing registers
85 * Saved state during suspend/resume, or while enabling intr-remap.
87 struct IO_APIC_route_entry *saved_registers;
89 struct mpc_ioapic mp_config;
90 /* IO APIC gsi routing info */
91 struct mp_ioapic_gsi gsi_config;
92 DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
93 } ioapics[MAX_IO_APICS];
95 #define mpc_ioapic_ver(ioapic_idx) ioapics[ioapic_idx].mp_config.apicver
97 int mpc_ioapic_id(int ioapic_idx)
99 return ioapics[ioapic_idx].mp_config.apicid;
102 unsigned int mpc_ioapic_addr(int ioapic_idx)
104 return ioapics[ioapic_idx].mp_config.apicaddr;
107 struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic_idx)
109 return &ioapics[ioapic_idx].gsi_config;
114 /* The one past the highest gsi number used */
117 /* MP IRQ source entries */
118 struct mpc_intsrc mp_irqs[MAX_IRQ_SOURCES];
120 /* # of MP IRQ source entries */
124 static int nr_irqs_gsi = NR_IRQS_LEGACY;
126 #if defined (CONFIG_MCA) || defined (CONFIG_EISA)
127 int mp_bus_id_to_type[MAX_MP_BUSSES];
130 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
132 int skip_ioapic_setup;
135 * disable_ioapic_support() - disables ioapic support at runtime
137 void disable_ioapic_support(void)
141 noioapicreroute = -1;
143 skip_ioapic_setup = 1;
146 static int __init parse_noapic(char *str)
148 /* disable IO-APIC */
149 disable_ioapic_support();
152 early_param("noapic", parse_noapic);
154 static int io_apic_setup_irq_pin(unsigned int irq, int node,
155 struct io_apic_irq_attr *attr);
157 /* Will be called in mpparse/acpi/sfi codes for saving IRQ info */
158 void mp_save_irq(struct mpc_intsrc *m)
162 apic_printk(APIC_VERBOSE, "Int: type %d, pol %d, trig %d, bus %02x,"
163 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
164 m->irqtype, m->irqflag & 3, (m->irqflag >> 2) & 3, m->srcbus,
165 m->srcbusirq, m->dstapic, m->dstirq);
167 for (i = 0; i < mp_irq_entries; i++) {
168 if (!memcmp(&mp_irqs[i], m, sizeof(*m)))
172 memcpy(&mp_irqs[mp_irq_entries], m, sizeof(*m));
173 if (++mp_irq_entries == MAX_IRQ_SOURCES)
174 panic("Max # of irq sources exceeded!!\n");
177 struct irq_pin_list {
179 struct irq_pin_list *next;
182 static struct irq_pin_list *alloc_irq_pin_list(int node)
184 return kzalloc_node(sizeof(struct irq_pin_list), GFP_KERNEL, node);
188 /* irq_cfg is indexed by the sum of all RTEs in all I/O APICs. */
189 static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
191 int __init arch_early_irq_init(void)
196 if (!legacy_pic->nr_legacy_irqs)
199 for (i = 0; i < nr_ioapics; i++) {
200 ioapics[i].saved_registers =
201 kzalloc(sizeof(struct IO_APIC_route_entry) *
202 ioapics[i].nr_registers, GFP_KERNEL);
203 if (!ioapics[i].saved_registers)
204 pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
208 count = ARRAY_SIZE(irq_cfgx);
209 node = cpu_to_node(0);
211 /* Make sure the legacy interrupts are marked in the bitmap */
212 irq_reserve_irqs(0, legacy_pic->nr_legacy_irqs);
214 for (i = 0; i < count; i++) {
215 irq_set_chip_data(i, &cfg[i]);
216 zalloc_cpumask_var_node(&cfg[i].domain, GFP_KERNEL, node);
217 zalloc_cpumask_var_node(&cfg[i].old_domain, GFP_KERNEL, node);
219 * For legacy IRQ's, start with assigning irq0 to irq15 to
220 * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
222 if (i < legacy_pic->nr_legacy_irqs) {
223 cfg[i].vector = IRQ0_VECTOR + i;
224 cpumask_set_cpu(0, cfg[i].domain);
231 static struct irq_cfg *irq_cfg(unsigned int irq)
233 return irq_get_chip_data(irq);
236 static struct irq_cfg *alloc_irq_cfg(unsigned int irq, int node)
240 cfg = kzalloc_node(sizeof(*cfg), GFP_KERNEL, node);
243 if (!zalloc_cpumask_var_node(&cfg->domain, GFP_KERNEL, node))
245 if (!zalloc_cpumask_var_node(&cfg->old_domain, GFP_KERNEL, node))
249 free_cpumask_var(cfg->domain);
255 static void free_irq_cfg(unsigned int at, struct irq_cfg *cfg)
259 irq_set_chip_data(at, NULL);
260 free_cpumask_var(cfg->domain);
261 free_cpumask_var(cfg->old_domain);
265 static struct irq_cfg *alloc_irq_and_cfg_at(unsigned int at, int node)
267 int res = irq_alloc_desc_at(at, node);
273 cfg = irq_get_chip_data(at);
278 cfg = alloc_irq_cfg(at, node);
280 irq_set_chip_data(at, cfg);
286 static int alloc_irq_from(unsigned int from, int node)
288 return irq_alloc_desc_from(from, node);
291 static void free_irq_at(unsigned int at, struct irq_cfg *cfg)
293 free_irq_cfg(at, cfg);
299 unsigned int unused[3];
301 unsigned int unused2[11];
305 static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
307 return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
308 + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
311 static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
313 struct io_apic __iomem *io_apic = io_apic_base(apic);
314 writel(vector, &io_apic->eoi);
317 static inline unsigned int io_apic_read(unsigned int apic, unsigned int reg)
319 struct io_apic __iomem *io_apic = io_apic_base(apic);
320 writel(reg, &io_apic->index);
321 return readl(&io_apic->data);
324 static inline void io_apic_write(unsigned int apic, unsigned int reg, unsigned int value)
326 struct io_apic __iomem *io_apic = io_apic_base(apic);
327 writel(reg, &io_apic->index);
328 writel(value, &io_apic->data);
332 * Re-write a value: to be used for read-modify-write
333 * cycles where the read already set up the index register.
335 * Older SiS APIC requires we rewrite the index register
337 static inline void io_apic_modify(unsigned int apic, unsigned int reg, unsigned int value)
339 struct io_apic __iomem *io_apic = io_apic_base(apic);
342 writel(reg, &io_apic->index);
343 writel(value, &io_apic->data);
346 static bool io_apic_level_ack_pending(struct irq_cfg *cfg)
348 struct irq_pin_list *entry;
351 raw_spin_lock_irqsave(&ioapic_lock, flags);
352 for_each_irq_pin(entry, cfg->irq_2_pin) {
357 reg = io_apic_read(entry->apic, 0x10 + pin*2);
358 /* Is the remote IRR bit set? */
359 if (reg & IO_APIC_REDIR_REMOTE_IRR) {
360 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
364 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
370 struct { u32 w1, w2; };
371 struct IO_APIC_route_entry entry;
374 static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin)
376 union entry_union eu;
378 eu.w1 = io_apic_read(apic, 0x10 + 2 * pin);
379 eu.w2 = io_apic_read(apic, 0x11 + 2 * pin);
383 static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin)
385 union entry_union eu;
387 raw_spin_lock_irqsave(&ioapic_lock, flags);
388 eu.entry = __ioapic_read_entry(apic, pin);
389 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
394 * When we write a new IO APIC routing entry, we need to write the high
395 * word first! If the mask bit in the low word is clear, we will enable
396 * the interrupt, and we need to make sure the entry is fully populated
397 * before that happens.
400 __ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
402 union entry_union eu = {{0, 0}};
405 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
406 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
409 static void ioapic_write_entry(int apic, int pin, struct IO_APIC_route_entry e)
412 raw_spin_lock_irqsave(&ioapic_lock, flags);
413 __ioapic_write_entry(apic, pin, e);
414 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
418 * When we mask an IO APIC routing entry, we need to write the low
419 * word first, in order to set the mask bit before we change the
422 static void ioapic_mask_entry(int apic, int pin)
425 union entry_union eu = { .entry.mask = 1 };
427 raw_spin_lock_irqsave(&ioapic_lock, flags);
428 io_apic_write(apic, 0x10 + 2*pin, eu.w1);
429 io_apic_write(apic, 0x11 + 2*pin, eu.w2);
430 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
434 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
435 * shared ISA-space IRQs, so we have to support them. We are super
436 * fast in the common case, and fast for shared ISA-space IRQs.
439 __add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
441 struct irq_pin_list **last, *entry;
443 /* don't allow duplicates */
444 last = &cfg->irq_2_pin;
445 for_each_irq_pin(entry, cfg->irq_2_pin) {
446 if (entry->apic == apic && entry->pin == pin)
451 entry = alloc_irq_pin_list(node);
453 printk(KERN_ERR "can not alloc irq_pin_list (%d,%d,%d)\n",
464 static void add_pin_to_irq_node(struct irq_cfg *cfg, int node, int apic, int pin)
466 if (__add_pin_to_irq_node(cfg, node, apic, pin))
467 panic("IO-APIC: failed to add irq-pin. Can not proceed\n");
471 * Reroute an IRQ to a different pin.
473 static void __init replace_pin_at_irq_node(struct irq_cfg *cfg, int node,
474 int oldapic, int oldpin,
475 int newapic, int newpin)
477 struct irq_pin_list *entry;
479 for_each_irq_pin(entry, cfg->irq_2_pin) {
480 if (entry->apic == oldapic && entry->pin == oldpin) {
481 entry->apic = newapic;
483 /* every one is different, right? */
488 /* old apic/pin didn't exist, so just add new ones */
489 add_pin_to_irq_node(cfg, node, newapic, newpin);
492 static void __io_apic_modify_irq(struct irq_pin_list *entry,
493 int mask_and, int mask_or,
494 void (*final)(struct irq_pin_list *entry))
496 unsigned int reg, pin;
499 reg = io_apic_read(entry->apic, 0x10 + pin * 2);
502 io_apic_modify(entry->apic, 0x10 + pin * 2, reg);
507 static void io_apic_modify_irq(struct irq_cfg *cfg,
508 int mask_and, int mask_or,
509 void (*final)(struct irq_pin_list *entry))
511 struct irq_pin_list *entry;
513 for_each_irq_pin(entry, cfg->irq_2_pin)
514 __io_apic_modify_irq(entry, mask_and, mask_or, final);
517 static void io_apic_sync(struct irq_pin_list *entry)
520 * Synchronize the IO-APIC and the CPU by doing
521 * a dummy read from the IO-APIC
523 struct io_apic __iomem *io_apic;
524 io_apic = io_apic_base(entry->apic);
525 readl(&io_apic->data);
528 static void mask_ioapic(struct irq_cfg *cfg)
532 raw_spin_lock_irqsave(&ioapic_lock, flags);
533 io_apic_modify_irq(cfg, ~0, IO_APIC_REDIR_MASKED, &io_apic_sync);
534 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
537 static void mask_ioapic_irq(struct irq_data *data)
539 mask_ioapic(data->chip_data);
542 static void __unmask_ioapic(struct irq_cfg *cfg)
544 io_apic_modify_irq(cfg, ~IO_APIC_REDIR_MASKED, 0, NULL);
547 static void unmask_ioapic(struct irq_cfg *cfg)
551 raw_spin_lock_irqsave(&ioapic_lock, flags);
552 __unmask_ioapic(cfg);
553 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
556 static void unmask_ioapic_irq(struct irq_data *data)
558 unmask_ioapic(data->chip_data);
562 * IO-APIC versions below 0x20 don't support EOI register.
563 * For the record, here is the information about various versions:
565 * 1Xh I/OAPIC or I/O(x)APIC which are not PCI 2.2 Compliant
566 * 2Xh I/O(x)APIC which is PCI 2.2 Compliant
569 * Some of the Intel ICH Specs (ICH2 to ICH5) documents the io-apic
570 * version as 0x2. This is an error with documentation and these ICH chips
571 * use io-apic's of version 0x20.
573 * For IO-APIC's with EOI register, we use that to do an explicit EOI.
574 * Otherwise, we simulate the EOI message manually by changing the trigger
575 * mode to edge and then back to level, with RTE being masked during this.
577 static void __eoi_ioapic_pin(int apic, int pin, int vector, struct irq_cfg *cfg)
579 if (mpc_ioapic_ver(apic) >= 0x20) {
581 * Intr-remapping uses pin number as the virtual vector
582 * in the RTE. Actual vector is programmed in
583 * intr-remapping table entry. Hence for the io-apic
584 * EOI we use the pin number.
586 if (cfg && irq_remapped(cfg))
587 io_apic_eoi(apic, pin);
589 io_apic_eoi(apic, vector);
591 struct IO_APIC_route_entry entry, entry1;
593 entry = entry1 = __ioapic_read_entry(apic, pin);
596 * Mask the entry and change the trigger mode to edge.
599 entry1.trigger = IOAPIC_EDGE;
601 __ioapic_write_entry(apic, pin, entry1);
604 * Restore the previous level triggered entry.
606 __ioapic_write_entry(apic, pin, entry);
610 static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg)
612 struct irq_pin_list *entry;
615 raw_spin_lock_irqsave(&ioapic_lock, flags);
616 for_each_irq_pin(entry, cfg->irq_2_pin)
617 __eoi_ioapic_pin(entry->apic, entry->pin, cfg->vector, cfg);
618 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
621 static void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
623 struct IO_APIC_route_entry entry;
625 /* Check delivery_mode to be sure we're not clearing an SMI pin */
626 entry = ioapic_read_entry(apic, pin);
627 if (entry.delivery_mode == dest_SMI)
631 * Make sure the entry is masked and re-read the contents to check
632 * if it is a level triggered pin and if the remote-IRR is set.
636 ioapic_write_entry(apic, pin, entry);
637 entry = ioapic_read_entry(apic, pin);
644 * Make sure the trigger mode is set to level. Explicit EOI
645 * doesn't clear the remote-IRR if the trigger mode is not
648 if (!entry.trigger) {
649 entry.trigger = IOAPIC_LEVEL;
650 ioapic_write_entry(apic, pin, entry);
653 raw_spin_lock_irqsave(&ioapic_lock, flags);
654 __eoi_ioapic_pin(apic, pin, entry.vector, NULL);
655 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
659 * Clear the rest of the bits in the IO-APIC RTE except for the mask
662 ioapic_mask_entry(apic, pin);
663 entry = ioapic_read_entry(apic, pin);
665 printk(KERN_ERR "Unable to reset IRR for apic: %d, pin :%d\n",
666 mpc_ioapic_id(apic), pin);
669 static void clear_IO_APIC (void)
673 for (apic = 0; apic < nr_ioapics; apic++)
674 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
675 clear_IO_APIC_pin(apic, pin);
680 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
681 * specific CPU-side IRQs.
685 static int pirq_entries[MAX_PIRQS] = {
686 [0 ... MAX_PIRQS - 1] = -1
689 static int __init ioapic_pirq_setup(char *str)
692 int ints[MAX_PIRQS+1];
694 get_options(str, ARRAY_SIZE(ints), ints);
696 apic_printk(APIC_VERBOSE, KERN_INFO
697 "PIRQ redirection, working around broken MP-BIOS.\n");
699 if (ints[0] < MAX_PIRQS)
702 for (i = 0; i < max; i++) {
703 apic_printk(APIC_VERBOSE, KERN_DEBUG
704 "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
706 * PIRQs are mapped upside down, usually.
708 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
713 __setup("pirq=", ioapic_pirq_setup);
714 #endif /* CONFIG_X86_32 */
717 * Saves all the IO-APIC RTE's
719 int save_ioapic_entries(void)
724 for (apic = 0; apic < nr_ioapics; apic++) {
725 if (!ioapics[apic].saved_registers) {
730 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
731 ioapics[apic].saved_registers[pin] =
732 ioapic_read_entry(apic, pin);
739 * Mask all IO APIC entries.
741 void mask_ioapic_entries(void)
745 for (apic = 0; apic < nr_ioapics; apic++) {
746 if (!ioapics[apic].saved_registers)
749 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
750 struct IO_APIC_route_entry entry;
752 entry = ioapics[apic].saved_registers[pin];
755 ioapic_write_entry(apic, pin, entry);
762 * Restore IO APIC entries which was saved in the ioapic structure.
764 int restore_ioapic_entries(void)
768 for (apic = 0; apic < nr_ioapics; apic++) {
769 if (!ioapics[apic].saved_registers)
772 for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
773 ioapic_write_entry(apic, pin,
774 ioapics[apic].saved_registers[pin]);
780 * Find the IRQ entry number of a certain pin.
782 static int find_irq_entry(int ioapic_idx, int pin, int type)
786 for (i = 0; i < mp_irq_entries; i++)
787 if (mp_irqs[i].irqtype == type &&
788 (mp_irqs[i].dstapic == mpc_ioapic_id(ioapic_idx) ||
789 mp_irqs[i].dstapic == MP_APIC_ALL) &&
790 mp_irqs[i].dstirq == pin)
797 * Find the pin to which IRQ[irq] (ISA) is connected
799 static int __init find_isa_irq_pin(int irq, int type)
803 for (i = 0; i < mp_irq_entries; i++) {
804 int lbus = mp_irqs[i].srcbus;
806 if (test_bit(lbus, mp_bus_not_pci) &&
807 (mp_irqs[i].irqtype == type) &&
808 (mp_irqs[i].srcbusirq == irq))
810 return mp_irqs[i].dstirq;
815 static int __init find_isa_irq_apic(int irq, int type)
819 for (i = 0; i < mp_irq_entries; i++) {
820 int lbus = mp_irqs[i].srcbus;
822 if (test_bit(lbus, mp_bus_not_pci) &&
823 (mp_irqs[i].irqtype == type) &&
824 (mp_irqs[i].srcbusirq == irq))
828 if (i < mp_irq_entries) {
831 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
832 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic)
839 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
841 * EISA Edge/Level control register, ELCR
843 static int EISA_ELCR(unsigned int irq)
845 if (irq < legacy_pic->nr_legacy_irqs) {
846 unsigned int port = 0x4d0 + (irq >> 3);
847 return (inb(port) >> (irq & 7)) & 1;
849 apic_printk(APIC_VERBOSE, KERN_INFO
850 "Broken MPtable reports ISA irq %d\n", irq);
856 /* ISA interrupts are always polarity zero edge triggered,
857 * when listed as conforming in the MP table. */
859 #define default_ISA_trigger(idx) (0)
860 #define default_ISA_polarity(idx) (0)
862 /* EISA interrupts are always polarity zero and can be edge or level
863 * trigger depending on the ELCR value. If an interrupt is listed as
864 * EISA conforming in the MP table, that means its trigger type must
865 * be read in from the ELCR */
867 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].srcbusirq))
868 #define default_EISA_polarity(idx) default_ISA_polarity(idx)
870 /* PCI interrupts are always polarity one level triggered,
871 * when listed as conforming in the MP table. */
873 #define default_PCI_trigger(idx) (1)
874 #define default_PCI_polarity(idx) (1)
876 /* MCA interrupts are always polarity zero level triggered,
877 * when listed as conforming in the MP table. */
879 #define default_MCA_trigger(idx) (1)
880 #define default_MCA_polarity(idx) default_ISA_polarity(idx)
882 static int irq_polarity(int idx)
884 int bus = mp_irqs[idx].srcbus;
888 * Determine IRQ line polarity (high active or low active):
890 switch (mp_irqs[idx].irqflag & 3)
892 case 0: /* conforms, ie. bus-type dependent polarity */
893 if (test_bit(bus, mp_bus_not_pci))
894 polarity = default_ISA_polarity(idx);
896 polarity = default_PCI_polarity(idx);
898 case 1: /* high active */
903 case 2: /* reserved */
905 printk(KERN_WARNING "broken BIOS!!\n");
909 case 3: /* low active */
914 default: /* invalid */
916 printk(KERN_WARNING "broken BIOS!!\n");
924 static int irq_trigger(int idx)
926 int bus = mp_irqs[idx].srcbus;
930 * Determine IRQ trigger mode (edge or level sensitive):
932 switch ((mp_irqs[idx].irqflag>>2) & 3)
934 case 0: /* conforms, ie. bus-type dependent */
935 if (test_bit(bus, mp_bus_not_pci))
936 trigger = default_ISA_trigger(idx);
938 trigger = default_PCI_trigger(idx);
939 #if defined(CONFIG_EISA) || defined(CONFIG_MCA)
940 switch (mp_bus_id_to_type[bus]) {
941 case MP_BUS_ISA: /* ISA pin */
943 /* set before the switch */
946 case MP_BUS_EISA: /* EISA pin */
948 trigger = default_EISA_trigger(idx);
951 case MP_BUS_PCI: /* PCI pin */
953 /* set before the switch */
956 case MP_BUS_MCA: /* MCA pin */
958 trigger = default_MCA_trigger(idx);
963 printk(KERN_WARNING "broken BIOS!!\n");
975 case 2: /* reserved */
977 printk(KERN_WARNING "broken BIOS!!\n");
986 default: /* invalid */
988 printk(KERN_WARNING "broken BIOS!!\n");
996 static int pin_2_irq(int idx, int apic, int pin)
999 int bus = mp_irqs[idx].srcbus;
1000 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
1003 * Debugging check, we are in big trouble if this message pops up!
1005 if (mp_irqs[idx].dstirq != pin)
1006 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
1008 if (test_bit(bus, mp_bus_not_pci)) {
1009 irq = mp_irqs[idx].srcbusirq;
1011 u32 gsi = gsi_cfg->gsi_base + pin;
1013 if (gsi >= NR_IRQS_LEGACY)
1016 irq = gsi_top + gsi;
1019 #ifdef CONFIG_X86_32
1021 * PCI IRQ command line redirection. Yes, limits are hardcoded.
1023 if ((pin >= 16) && (pin <= 23)) {
1024 if (pirq_entries[pin-16] != -1) {
1025 if (!pirq_entries[pin-16]) {
1026 apic_printk(APIC_VERBOSE, KERN_DEBUG
1027 "disabling PIRQ%d\n", pin-16);
1029 irq = pirq_entries[pin-16];
1030 apic_printk(APIC_VERBOSE, KERN_DEBUG
1031 "using PIRQ%d -> IRQ %d\n",
1042 * Find a specific PCI IRQ entry.
1043 * Not an __init, possibly needed by modules
1045 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin,
1046 struct io_apic_irq_attr *irq_attr)
1048 int ioapic_idx, i, best_guess = -1;
1050 apic_printk(APIC_DEBUG,
1051 "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
1053 if (test_bit(bus, mp_bus_not_pci)) {
1054 apic_printk(APIC_VERBOSE,
1055 "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
1058 for (i = 0; i < mp_irq_entries; i++) {
1059 int lbus = mp_irqs[i].srcbus;
1061 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1062 if (mpc_ioapic_id(ioapic_idx) == mp_irqs[i].dstapic ||
1063 mp_irqs[i].dstapic == MP_APIC_ALL)
1066 if (!test_bit(lbus, mp_bus_not_pci) &&
1067 !mp_irqs[i].irqtype &&
1069 (slot == ((mp_irqs[i].srcbusirq >> 2) & 0x1f))) {
1070 int irq = pin_2_irq(i, ioapic_idx, mp_irqs[i].dstirq);
1072 if (!(ioapic_idx || IO_APIC_IRQ(irq)))
1075 if (pin == (mp_irqs[i].srcbusirq & 3)) {
1076 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1083 * Use the first all-but-pin matching entry as a
1084 * best-guess fuzzy result for broken mptables.
1086 if (best_guess < 0) {
1087 set_io_apic_irq_attr(irq_attr, ioapic_idx,
1097 EXPORT_SYMBOL(IO_APIC_get_PCI_irq_vector);
1099 void lock_vector_lock(void)
1101 /* Used to the online set of cpus does not change
1102 * during assign_irq_vector.
1104 raw_spin_lock(&vector_lock);
1107 void unlock_vector_lock(void)
1109 raw_spin_unlock(&vector_lock);
1113 __assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1116 * NOTE! The local APIC isn't very good at handling
1117 * multiple interrupts at the same interrupt level.
1118 * As the interrupt level is determined by taking the
1119 * vector number and shifting that right by 4, we
1120 * want to spread these out a bit so that they don't
1121 * all fall in the same interrupt level.
1123 * Also, we've got to be careful not to trash gate
1124 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1126 static int current_vector = FIRST_EXTERNAL_VECTOR + VECTOR_OFFSET_START;
1127 static int current_offset = VECTOR_OFFSET_START % 8;
1128 unsigned int old_vector;
1130 cpumask_var_t tmp_mask;
1132 if (cfg->move_in_progress)
1135 if (!alloc_cpumask_var(&tmp_mask, GFP_ATOMIC))
1138 old_vector = cfg->vector;
1140 cpumask_and(tmp_mask, mask, cpu_online_mask);
1141 cpumask_and(tmp_mask, cfg->domain, tmp_mask);
1142 if (!cpumask_empty(tmp_mask)) {
1143 free_cpumask_var(tmp_mask);
1148 /* Only try and allocate irqs on cpus that are present */
1150 for_each_cpu_and(cpu, mask, cpu_online_mask) {
1154 apic->vector_allocation_domain(cpu, tmp_mask);
1156 vector = current_vector;
1157 offset = current_offset;
1160 if (vector >= first_system_vector) {
1161 /* If out of vectors on large boxen, must share them. */
1162 offset = (offset + 1) % 8;
1163 vector = FIRST_EXTERNAL_VECTOR + offset;
1165 if (unlikely(current_vector == vector))
1168 if (test_bit(vector, used_vectors))
1171 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1172 if (per_cpu(vector_irq, new_cpu)[vector] != -1)
1175 current_vector = vector;
1176 current_offset = offset;
1178 cfg->move_in_progress = 1;
1179 cpumask_copy(cfg->old_domain, cfg->domain);
1181 for_each_cpu_and(new_cpu, tmp_mask, cpu_online_mask)
1182 per_cpu(vector_irq, new_cpu)[vector] = irq;
1183 cfg->vector = vector;
1184 cpumask_copy(cfg->domain, tmp_mask);
1188 free_cpumask_var(tmp_mask);
1192 int assign_irq_vector(int irq, struct irq_cfg *cfg, const struct cpumask *mask)
1195 unsigned long flags;
1197 raw_spin_lock_irqsave(&vector_lock, flags);
1198 err = __assign_irq_vector(irq, cfg, mask);
1199 raw_spin_unlock_irqrestore(&vector_lock, flags);
1203 static void __clear_irq_vector(int irq, struct irq_cfg *cfg)
1207 BUG_ON(!cfg->vector);
1209 vector = cfg->vector;
1210 for_each_cpu_and(cpu, cfg->domain, cpu_online_mask)
1211 per_cpu(vector_irq, cpu)[vector] = -1;
1214 cpumask_clear(cfg->domain);
1216 if (likely(!cfg->move_in_progress))
1218 for_each_cpu_and(cpu, cfg->old_domain, cpu_online_mask) {
1219 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS;
1221 if (per_cpu(vector_irq, cpu)[vector] != irq)
1223 per_cpu(vector_irq, cpu)[vector] = -1;
1227 cfg->move_in_progress = 0;
1230 void __setup_vector_irq(int cpu)
1232 /* Initialize vector_irq on a new cpu */
1234 struct irq_cfg *cfg;
1237 * vector_lock will make sure that we don't run into irq vector
1238 * assignments that might be happening on another cpu in parallel,
1239 * while we setup our initial vector to irq mappings.
1241 raw_spin_lock(&vector_lock);
1242 /* Mark the inuse vectors */
1243 for_each_active_irq(irq) {
1244 cfg = irq_get_chip_data(irq);
1248 * If it is a legacy IRQ handled by the legacy PIC, this cpu
1249 * will be part of the irq_cfg's domain.
1251 if (irq < legacy_pic->nr_legacy_irqs && !IO_APIC_IRQ(irq))
1252 cpumask_set_cpu(cpu, cfg->domain);
1254 if (!cpumask_test_cpu(cpu, cfg->domain))
1256 vector = cfg->vector;
1257 per_cpu(vector_irq, cpu)[vector] = irq;
1259 /* Mark the free vectors */
1260 for (vector = 0; vector < NR_VECTORS; ++vector) {
1261 irq = per_cpu(vector_irq, cpu)[vector];
1266 if (!cpumask_test_cpu(cpu, cfg->domain))
1267 per_cpu(vector_irq, cpu)[vector] = -1;
1269 raw_spin_unlock(&vector_lock);
1272 static struct irq_chip ioapic_chip;
1274 #ifdef CONFIG_X86_32
1275 static inline int IO_APIC_irq_trigger(int irq)
1279 for (apic = 0; apic < nr_ioapics; apic++) {
1280 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1281 idx = find_irq_entry(apic, pin, mp_INT);
1282 if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
1283 return irq_trigger(idx);
1287 * nonexistent IRQs are edge default
1292 static inline int IO_APIC_irq_trigger(int irq)
1298 static void ioapic_register_intr(unsigned int irq, struct irq_cfg *cfg,
1299 unsigned long trigger)
1301 struct irq_chip *chip = &ioapic_chip;
1302 irq_flow_handler_t hdl;
1305 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
1306 trigger == IOAPIC_LEVEL) {
1307 irq_set_status_flags(irq, IRQ_LEVEL);
1310 irq_clear_status_flags(irq, IRQ_LEVEL);
1314 if (irq_remapped(cfg)) {
1315 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
1316 irq_remap_modify_chip_defaults(chip);
1317 fasteoi = trigger != 0;
1320 hdl = fasteoi ? handle_fasteoi_irq : handle_edge_irq;
1321 irq_set_chip_and_handler_name(irq, chip, hdl,
1322 fasteoi ? "fasteoi" : "edge");
1326 static int setup_ir_ioapic_entry(int irq,
1327 struct IR_IO_APIC_route_entry *entry,
1328 unsigned int destination, int vector,
1329 struct io_apic_irq_attr *attr)
1333 int ioapic_id = mpc_ioapic_id(attr->ioapic);
1334 struct intel_iommu *iommu = map_ioapic_to_ir(ioapic_id);
1337 pr_warn("No mapping iommu for ioapic %d\n", ioapic_id);
1341 index = alloc_irte(iommu, irq, 1);
1343 pr_warn("Failed to allocate IRTE for ioapic %d\n", ioapic_id);
1347 prepare_irte(&irte, vector, destination);
1349 /* Set source-id of interrupt request */
1350 set_ioapic_sid(&irte, ioapic_id);
1352 modify_irte(irq, &irte);
1354 apic_printk(APIC_VERBOSE, KERN_DEBUG "IOAPIC[%d]: "
1355 "Set IRTE entry (P:%d FPD:%d Dst_Mode:%d "
1356 "Redir_hint:%d Trig_Mode:%d Dlvry_Mode:%X "
1357 "Avail:%X Vector:%02X Dest:%08X "
1358 "SID:%04X SQ:%X SVT:%X)\n",
1359 attr->ioapic, irte.present, irte.fpd, irte.dst_mode,
1360 irte.redir_hint, irte.trigger_mode, irte.dlvry_mode,
1361 irte.avail, irte.vector, irte.dest_id,
1362 irte.sid, irte.sq, irte.svt);
1364 memset(entry, 0, sizeof(*entry));
1366 entry->index2 = (index >> 15) & 0x1;
1369 entry->index = (index & 0x7fff);
1371 * IO-APIC RTE will be configured with virtual vector.
1372 * irq handler will do the explicit EOI to the io-apic.
1374 entry->vector = attr->ioapic_pin;
1375 entry->mask = 0; /* enable IRQ */
1376 entry->trigger = attr->trigger;
1377 entry->polarity = attr->polarity;
1379 /* Mask level triggered irqs.
1380 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1388 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
1389 unsigned int destination, int vector,
1390 struct io_apic_irq_attr *attr)
1392 if (intr_remapping_enabled)
1393 return setup_ir_ioapic_entry(irq,
1394 (struct IR_IO_APIC_route_entry *)entry,
1395 destination, vector, attr);
1397 memset(entry, 0, sizeof(*entry));
1399 entry->delivery_mode = apic->irq_delivery_mode;
1400 entry->dest_mode = apic->irq_dest_mode;
1401 entry->dest = destination;
1402 entry->vector = vector;
1403 entry->mask = 0; /* enable IRQ */
1404 entry->trigger = attr->trigger;
1405 entry->polarity = attr->polarity;
1408 * Mask level triggered irqs.
1409 * Use IRQ_DELAYED_DISABLE for edge triggered irqs.
1417 static void setup_ioapic_irq(unsigned int irq, struct irq_cfg *cfg,
1418 struct io_apic_irq_attr *attr)
1420 struct IO_APIC_route_entry entry;
1423 if (!IO_APIC_IRQ(irq))
1426 * For legacy irqs, cfg->domain starts with cpu 0 for legacy
1427 * controllers like 8259. Now that IO-APIC can handle this irq, update
1430 if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
1431 apic->vector_allocation_domain(0, cfg->domain);
1433 if (assign_irq_vector(irq, cfg, apic->target_cpus()))
1436 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
1438 apic_printk(APIC_VERBOSE,KERN_DEBUG
1439 "IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
1440 "IRQ %d Mode:%i Active:%i Dest:%d)\n",
1441 attr->ioapic, mpc_ioapic_id(attr->ioapic), attr->ioapic_pin,
1442 cfg->vector, irq, attr->trigger, attr->polarity, dest);
1444 if (setup_ioapic_entry(irq, &entry, dest, cfg->vector, attr)) {
1445 pr_warn("Failed to setup ioapic entry for ioapic %d, pin %d\n",
1446 mpc_ioapic_id(attr->ioapic), attr->ioapic_pin);
1447 __clear_irq_vector(irq, cfg);
1452 ioapic_register_intr(irq, cfg, attr->trigger);
1453 if (irq < legacy_pic->nr_legacy_irqs)
1454 legacy_pic->mask(irq);
1456 ioapic_write_entry(attr->ioapic, attr->ioapic_pin, entry);
1459 static bool __init io_apic_pin_not_connected(int idx, int ioapic_idx, int pin)
1464 apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
1465 mpc_ioapic_id(ioapic_idx), pin);
1469 static void __init __io_apic_setup_irqs(unsigned int ioapic_idx)
1471 int idx, node = cpu_to_node(0);
1472 struct io_apic_irq_attr attr;
1473 unsigned int pin, irq;
1475 for (pin = 0; pin < ioapics[ioapic_idx].nr_registers; pin++) {
1476 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1477 if (io_apic_pin_not_connected(idx, ioapic_idx, pin))
1480 irq = pin_2_irq(idx, ioapic_idx, pin);
1482 if ((ioapic_idx > 0) && (irq > 16))
1486 * Skip the timer IRQ if there's a quirk handler
1487 * installed and if it returns 1:
1489 if (apic->multi_timer_check &&
1490 apic->multi_timer_check(ioapic_idx, irq))
1493 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1496 io_apic_setup_irq_pin(irq, node, &attr);
1500 static void __init setup_IO_APIC_irqs(void)
1502 unsigned int ioapic_idx;
1504 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
1506 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1507 __io_apic_setup_irqs(ioapic_idx);
1511 * for the gsit that is not in first ioapic
1512 * but could not use acpi_register_gsi()
1513 * like some special sci in IBM x3330
1515 void setup_IO_APIC_irq_extra(u32 gsi)
1517 int ioapic_idx = 0, pin, idx, irq, node = cpu_to_node(0);
1518 struct io_apic_irq_attr attr;
1521 * Convert 'gsi' to 'ioapic.pin'.
1523 ioapic_idx = mp_find_ioapic(gsi);
1527 pin = mp_find_ioapic_pin(ioapic_idx, gsi);
1528 idx = find_irq_entry(ioapic_idx, pin, mp_INT);
1532 irq = pin_2_irq(idx, ioapic_idx, pin);
1534 /* Only handle the non legacy irqs on secondary ioapics */
1535 if (ioapic_idx == 0 || irq < NR_IRQS_LEGACY)
1538 set_io_apic_irq_attr(&attr, ioapic_idx, pin, irq_trigger(idx),
1541 io_apic_setup_irq_pin_once(irq, node, &attr);
1545 * Set up the timer pin, possibly with the 8259A-master behind.
1547 static void __init setup_timer_IRQ0_pin(unsigned int ioapic_idx,
1548 unsigned int pin, int vector)
1550 struct IO_APIC_route_entry entry;
1552 if (intr_remapping_enabled)
1555 memset(&entry, 0, sizeof(entry));
1558 * We use logical delivery to get the timer IRQ
1561 entry.dest_mode = apic->irq_dest_mode;
1562 entry.mask = 0; /* don't mask IRQ for edge */
1563 entry.dest = apic->cpu_mask_to_apicid(apic->target_cpus());
1564 entry.delivery_mode = apic->irq_delivery_mode;
1567 entry.vector = vector;
1570 * The timer IRQ doesn't have to know that behind the
1571 * scene we may have a 8259A-master in AEOI mode ...
1573 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,
1577 * Add it to the IO-APIC irq-routing table:
1579 ioapic_write_entry(ioapic_idx, pin, entry);
1582 __apicdebuginit(void) print_IO_APIC(int ioapic_idx)
1585 union IO_APIC_reg_00 reg_00;
1586 union IO_APIC_reg_01 reg_01;
1587 union IO_APIC_reg_02 reg_02;
1588 union IO_APIC_reg_03 reg_03;
1589 unsigned long flags;
1591 raw_spin_lock_irqsave(&ioapic_lock, flags);
1592 reg_00.raw = io_apic_read(ioapic_idx, 0);
1593 reg_01.raw = io_apic_read(ioapic_idx, 1);
1594 if (reg_01.bits.version >= 0x10)
1595 reg_02.raw = io_apic_read(ioapic_idx, 2);
1596 if (reg_01.bits.version >= 0x20)
1597 reg_03.raw = io_apic_read(ioapic_idx, 3);
1598 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
1601 printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(ioapic_idx));
1602 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
1603 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
1604 printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
1605 printk(KERN_DEBUG "....... : LTS : %X\n", reg_00.bits.LTS);
1607 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
1608 printk(KERN_DEBUG "....... : max redirection entries: %02X\n",
1609 reg_01.bits.entries);
1611 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
1612 printk(KERN_DEBUG "....... : IO APIC version: %02X\n",
1613 reg_01.bits.version);
1616 * Some Intel chipsets with IO APIC VERSION of 0x1? don't have reg_02,
1617 * but the value of reg_02 is read as the previous read register
1618 * value, so ignore it if reg_02 == reg_01.
1620 if (reg_01.bits.version >= 0x10 && reg_02.raw != reg_01.raw) {
1621 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
1622 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
1626 * Some Intel chipsets with IO APIC VERSION of 0x2? don't have reg_02
1627 * or reg_03, but the value of reg_0[23] is read as the previous read
1628 * register value, so ignore it if reg_03 == reg_0[12].
1630 if (reg_01.bits.version >= 0x20 && reg_03.raw != reg_02.raw &&
1631 reg_03.raw != reg_01.raw) {
1632 printk(KERN_DEBUG ".... register #03: %08X\n", reg_03.raw);
1633 printk(KERN_DEBUG "....... : Boot DT : %X\n", reg_03.bits.boot_DT);
1636 printk(KERN_DEBUG ".... IRQ redirection table:\n");
1638 if (intr_remapping_enabled) {
1639 printk(KERN_DEBUG " NR Indx Fmt Mask Trig IRR"
1640 " Pol Stat Indx2 Zero Vect:\n");
1642 printk(KERN_DEBUG " NR Dst Mask Trig IRR Pol"
1643 " Stat Dmod Deli Vect:\n");
1646 for (i = 0; i <= reg_01.bits.entries; i++) {
1647 if (intr_remapping_enabled) {
1648 struct IO_APIC_route_entry entry;
1649 struct IR_IO_APIC_route_entry *ir_entry;
1651 entry = ioapic_read_entry(ioapic_idx, i);
1652 ir_entry = (struct IR_IO_APIC_route_entry *) &entry;
1653 printk(KERN_DEBUG " %02x %04X ",
1657 printk("%1d %1d %1d %1d %1d "
1658 "%1d %1d %X %02X\n",
1664 ir_entry->delivery_status,
1670 struct IO_APIC_route_entry entry;
1672 entry = ioapic_read_entry(ioapic_idx, i);
1673 printk(KERN_DEBUG " %02x %02X ",
1677 printk("%1d %1d %1d %1d %1d "
1683 entry.delivery_status,
1685 entry.delivery_mode,
1692 __apicdebuginit(void) print_IO_APICs(void)
1695 struct irq_cfg *cfg;
1698 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
1699 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1700 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
1701 mpc_ioapic_id(ioapic_idx),
1702 ioapics[ioapic_idx].nr_registers);
1705 * We are a bit conservative about what we expect. We have to
1706 * know about every hardware change ASAP.
1708 printk(KERN_INFO "testing the IO APIC.......................\n");
1710 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++)
1711 print_IO_APIC(ioapic_idx);
1713 printk(KERN_DEBUG "IRQ to pin mappings:\n");
1714 for_each_active_irq(irq) {
1715 struct irq_pin_list *entry;
1717 cfg = irq_get_chip_data(irq);
1720 entry = cfg->irq_2_pin;
1723 printk(KERN_DEBUG "IRQ%d ", irq);
1724 for_each_irq_pin(entry, cfg->irq_2_pin)
1725 printk("-> %d:%d", entry->apic, entry->pin);
1729 printk(KERN_INFO ".................................... done.\n");
1732 __apicdebuginit(void) print_APIC_field(int base)
1738 for (i = 0; i < 8; i++)
1739 printk(KERN_CONT "%08x", apic_read(base + i*0x10));
1741 printk(KERN_CONT "\n");
1744 __apicdebuginit(void) print_local_APIC(void *dummy)
1746 unsigned int i, v, ver, maxlvt;
1749 printk(KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
1750 smp_processor_id(), hard_smp_processor_id());
1751 v = apic_read(APIC_ID);
1752 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, read_apic_id());
1753 v = apic_read(APIC_LVR);
1754 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
1755 ver = GET_APIC_VERSION(v);
1756 maxlvt = lapic_get_maxlvt();
1758 v = apic_read(APIC_TASKPRI);
1759 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
1761 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1762 if (!APIC_XAPIC(ver)) {
1763 v = apic_read(APIC_ARBPRI);
1764 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
1765 v & APIC_ARBPRI_MASK);
1767 v = apic_read(APIC_PROCPRI);
1768 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
1772 * Remote read supported only in the 82489DX and local APIC for
1773 * Pentium processors.
1775 if (!APIC_INTEGRATED(ver) || maxlvt == 3) {
1776 v = apic_read(APIC_RRR);
1777 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1780 v = apic_read(APIC_LDR);
1781 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1782 if (!x2apic_enabled()) {
1783 v = apic_read(APIC_DFR);
1784 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1786 v = apic_read(APIC_SPIV);
1787 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1789 printk(KERN_DEBUG "... APIC ISR field:\n");
1790 print_APIC_field(APIC_ISR);
1791 printk(KERN_DEBUG "... APIC TMR field:\n");
1792 print_APIC_field(APIC_TMR);
1793 printk(KERN_DEBUG "... APIC IRR field:\n");
1794 print_APIC_field(APIC_IRR);
1796 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1797 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1798 apic_write(APIC_ESR, 0);
1800 v = apic_read(APIC_ESR);
1801 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1804 icr = apic_icr_read();
1805 printk(KERN_DEBUG "... APIC ICR: %08x\n", (u32)icr);
1806 printk(KERN_DEBUG "... APIC ICR2: %08x\n", (u32)(icr >> 32));
1808 v = apic_read(APIC_LVTT);
1809 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1811 if (maxlvt > 3) { /* PC is LVT#4. */
1812 v = apic_read(APIC_LVTPC);
1813 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1815 v = apic_read(APIC_LVT0);
1816 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1817 v = apic_read(APIC_LVT1);
1818 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1820 if (maxlvt > 2) { /* ERR is LVT#3. */
1821 v = apic_read(APIC_LVTERR);
1822 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1825 v = apic_read(APIC_TMICT);
1826 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1827 v = apic_read(APIC_TMCCT);
1828 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1829 v = apic_read(APIC_TDCR);
1830 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1832 if (boot_cpu_has(X86_FEATURE_EXTAPIC)) {
1833 v = apic_read(APIC_EFEAT);
1834 maxlvt = (v >> 16) & 0xff;
1835 printk(KERN_DEBUG "... APIC EFEAT: %08x\n", v);
1836 v = apic_read(APIC_ECTRL);
1837 printk(KERN_DEBUG "... APIC ECTRL: %08x\n", v);
1838 for (i = 0; i < maxlvt; i++) {
1839 v = apic_read(APIC_EILVTn(i));
1840 printk(KERN_DEBUG "... APIC EILVT%d: %08x\n", i, v);
1846 __apicdebuginit(void) print_local_APICs(int maxcpu)
1854 for_each_online_cpu(cpu) {
1857 smp_call_function_single(cpu, print_local_APIC, NULL, 1);
1862 __apicdebuginit(void) print_PIC(void)
1865 unsigned long flags;
1867 if (!legacy_pic->nr_legacy_irqs)
1870 printk(KERN_DEBUG "\nprinting PIC contents\n");
1872 raw_spin_lock_irqsave(&i8259A_lock, flags);
1874 v = inb(0xa1) << 8 | inb(0x21);
1875 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1877 v = inb(0xa0) << 8 | inb(0x20);
1878 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1882 v = inb(0xa0) << 8 | inb(0x20);
1886 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
1888 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1890 v = inb(0x4d1) << 8 | inb(0x4d0);
1891 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1894 static int __initdata show_lapic = 1;
1895 static __init int setup_show_lapic(char *arg)
1899 if (strcmp(arg, "all") == 0) {
1900 show_lapic = CONFIG_NR_CPUS;
1902 get_option(&arg, &num);
1909 __setup("show_lapic=", setup_show_lapic);
1911 __apicdebuginit(int) print_ICs(void)
1913 if (apic_verbosity == APIC_QUIET)
1918 /* don't print out if apic is not there */
1919 if (!cpu_has_apic && !apic_from_smp_config())
1922 print_local_APICs(show_lapic);
1928 late_initcall(print_ICs);
1931 /* Where if anywhere is the i8259 connect in external int mode */
1932 static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
1934 void __init enable_IO_APIC(void)
1936 int i8259_apic, i8259_pin;
1939 if (!legacy_pic->nr_legacy_irqs)
1942 for(apic = 0; apic < nr_ioapics; apic++) {
1944 /* See if any of the pins is in ExtINT mode */
1945 for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
1946 struct IO_APIC_route_entry entry;
1947 entry = ioapic_read_entry(apic, pin);
1949 /* If the interrupt line is enabled and in ExtInt mode
1950 * I have found the pin where the i8259 is connected.
1952 if ((entry.mask == 0) && (entry.delivery_mode == dest_ExtINT)) {
1953 ioapic_i8259.apic = apic;
1954 ioapic_i8259.pin = pin;
1960 /* Look to see what if the MP table has reported the ExtINT */
1961 /* If we could not find the appropriate pin by looking at the ioapic
1962 * the i8259 probably is not connected the ioapic but give the
1963 * mptable a chance anyway.
1965 i8259_pin = find_isa_irq_pin(0, mp_ExtINT);
1966 i8259_apic = find_isa_irq_apic(0, mp_ExtINT);
1967 /* Trust the MP table if nothing is setup in the hardware */
1968 if ((ioapic_i8259.pin == -1) && (i8259_pin >= 0)) {
1969 printk(KERN_WARNING "ExtINT not setup in hardware but reported by MP table\n");
1970 ioapic_i8259.pin = i8259_pin;
1971 ioapic_i8259.apic = i8259_apic;
1973 /* Complain if the MP table and the hardware disagree */
1974 if (((ioapic_i8259.apic != i8259_apic) || (ioapic_i8259.pin != i8259_pin)) &&
1975 (i8259_pin >= 0) && (ioapic_i8259.pin >= 0))
1977 printk(KERN_WARNING "ExtINT in hardware and MP table differ\n");
1981 * Do not trust the IO-APIC being empty at bootup
1987 * Not an __init, needed by the reboot code
1989 void disable_IO_APIC(void)
1992 * Clear the IO-APIC before rebooting:
1996 if (!legacy_pic->nr_legacy_irqs)
2000 * If the i8259 is routed through an IOAPIC
2001 * Put that IOAPIC in virtual wire mode
2002 * so legacy interrupts can be delivered.
2004 * With interrupt-remapping, for now we will use virtual wire A mode,
2005 * as virtual wire B is little complex (need to configure both
2006 * IOAPIC RTE as well as interrupt-remapping table entry).
2007 * As this gets called during crash dump, keep this simple for now.
2009 if (ioapic_i8259.pin != -1 && !intr_remapping_enabled) {
2010 struct IO_APIC_route_entry entry;
2012 memset(&entry, 0, sizeof(entry));
2013 entry.mask = 0; /* Enabled */
2014 entry.trigger = 0; /* Edge */
2016 entry.polarity = 0; /* High */
2017 entry.delivery_status = 0;
2018 entry.dest_mode = 0; /* Physical */
2019 entry.delivery_mode = dest_ExtINT; /* ExtInt */
2021 entry.dest = read_apic_id();
2024 * Add it to the IO-APIC irq-routing table:
2026 ioapic_write_entry(ioapic_i8259.apic, ioapic_i8259.pin, entry);
2030 * Use virtual wire A mode when interrupt remapping is enabled.
2032 if (cpu_has_apic || apic_from_smp_config())
2033 disconnect_bsp_APIC(!intr_remapping_enabled &&
2034 ioapic_i8259.pin != -1);
2037 #ifdef CONFIG_X86_32
2039 * function to set the IO-APIC physical IDs based on the
2040 * values stored in the MPC table.
2042 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
2044 void __init setup_ioapic_ids_from_mpc_nocheck(void)
2046 union IO_APIC_reg_00 reg_00;
2047 physid_mask_t phys_id_present_map;
2050 unsigned char old_id;
2051 unsigned long flags;
2054 * This is broken; anything with a real cpu count has to
2055 * circumvent this idiocy regardless.
2057 apic->ioapic_phys_id_map(&phys_cpu_present_map, &phys_id_present_map);
2060 * Set the IOAPIC ID to the value stored in the MPC table.
2062 for (ioapic_idx = 0; ioapic_idx < nr_ioapics; ioapic_idx++) {
2063 /* Read the register 0 value */
2064 raw_spin_lock_irqsave(&ioapic_lock, flags);
2065 reg_00.raw = io_apic_read(ioapic_idx, 0);
2066 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2068 old_id = mpc_ioapic_id(ioapic_idx);
2070 if (mpc_ioapic_id(ioapic_idx) >= get_physical_broadcast()) {
2071 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
2072 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2073 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2075 ioapics[ioapic_idx].mp_config.apicid = reg_00.bits.ID;
2079 * Sanity check, is the ID really free? Every APIC in a
2080 * system must have a unique ID or we get lots of nice
2081 * 'stuck on smp_invalidate_needed IPI wait' messages.
2083 if (apic->check_apicid_used(&phys_id_present_map,
2084 mpc_ioapic_id(ioapic_idx))) {
2085 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
2086 ioapic_idx, mpc_ioapic_id(ioapic_idx));
2087 for (i = 0; i < get_physical_broadcast(); i++)
2088 if (!physid_isset(i, phys_id_present_map))
2090 if (i >= get_physical_broadcast())
2091 panic("Max APIC ID exceeded!\n");
2092 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
2094 physid_set(i, phys_id_present_map);
2095 ioapics[ioapic_idx].mp_config.apicid = i;
2098 apic->apicid_to_cpu_present(mpc_ioapic_id(ioapic_idx),
2100 apic_printk(APIC_VERBOSE, "Setting %d in the "
2101 "phys_id_present_map\n",
2102 mpc_ioapic_id(ioapic_idx));
2103 physids_or(phys_id_present_map, phys_id_present_map, tmp);
2107 * We need to adjust the IRQ routing table
2108 * if the ID changed.
2110 if (old_id != mpc_ioapic_id(ioapic_idx))
2111 for (i = 0; i < mp_irq_entries; i++)
2112 if (mp_irqs[i].dstapic == old_id)
2114 = mpc_ioapic_id(ioapic_idx);
2117 * Update the ID register according to the right value
2118 * from the MPC table if they are different.
2120 if (mpc_ioapic_id(ioapic_idx) == reg_00.bits.ID)
2123 apic_printk(APIC_VERBOSE, KERN_INFO
2124 "...changing IO-APIC physical APIC ID to %d ...",
2125 mpc_ioapic_id(ioapic_idx));
2127 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
2128 raw_spin_lock_irqsave(&ioapic_lock, flags);
2129 io_apic_write(ioapic_idx, 0, reg_00.raw);
2130 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2135 raw_spin_lock_irqsave(&ioapic_lock, flags);
2136 reg_00.raw = io_apic_read(ioapic_idx, 0);
2137 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2138 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx))
2139 printk("could not set ID!\n");
2141 apic_printk(APIC_VERBOSE, " ok.\n");
2145 void __init setup_ioapic_ids_from_mpc(void)
2151 * Don't check I/O APIC IDs for xAPIC systems. They have
2152 * no meaning without the serial APIC bus.
2154 if (!(boot_cpu_data.x86_vendor == X86_VENDOR_INTEL)
2155 || APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
2157 setup_ioapic_ids_from_mpc_nocheck();
2161 int no_timer_check __initdata;
2163 static int __init notimercheck(char *s)
2168 __setup("no_timer_check", notimercheck);
2171 * There is a nasty bug in some older SMP boards, their mptable lies
2172 * about the timer IRQ. We do the following to work around the situation:
2174 * - timer IRQ defaults to IO-APIC IRQ
2175 * - if this function detects that timer IRQs are defunct, then we fall
2176 * back to ISA timer IRQs
2178 static int __init timer_irq_works(void)
2180 unsigned long t1 = jiffies;
2181 unsigned long flags;
2186 local_save_flags(flags);
2188 /* Let ten ticks pass... */
2189 mdelay((10 * 1000) / HZ);
2190 local_irq_restore(flags);
2193 * Expect a few ticks at least, to be sure some possible
2194 * glue logic does not lock up after one or two first
2195 * ticks in a non-ExtINT mode. Also the local APIC
2196 * might have cached one ExtINT interrupt. Finally, at
2197 * least one tick may be lost due to delays.
2201 if (time_after(jiffies, t1 + 4))
2207 * In the SMP+IOAPIC case it might happen that there are an unspecified
2208 * number of pending IRQ events unhandled. These cases are very rare,
2209 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
2210 * better to do it this way as thus we do not have to be aware of
2211 * 'pending' interrupts in the IRQ path, except at this point.
2214 * Edge triggered needs to resend any interrupt
2215 * that was delayed but this is now handled in the device
2220 * Starting up a edge-triggered IO-APIC interrupt is
2221 * nasty - we need to make sure that we get the edge.
2222 * If it is already asserted for some reason, we need
2223 * return 1 to indicate that is was pending.
2225 * This is not complete - we should be able to fake
2226 * an edge even if it isn't on the 8259A...
2229 static unsigned int startup_ioapic_irq(struct irq_data *data)
2231 int was_pending = 0, irq = data->irq;
2232 unsigned long flags;
2234 raw_spin_lock_irqsave(&ioapic_lock, flags);
2235 if (irq < legacy_pic->nr_legacy_irqs) {
2236 legacy_pic->mask(irq);
2237 if (legacy_pic->irq_pending(irq))
2240 __unmask_ioapic(data->chip_data);
2241 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2246 static int ioapic_retrigger_irq(struct irq_data *data)
2248 struct irq_cfg *cfg = data->chip_data;
2249 unsigned long flags;
2251 raw_spin_lock_irqsave(&vector_lock, flags);
2252 apic->send_IPI_mask(cpumask_of(cpumask_first(cfg->domain)), cfg->vector);
2253 raw_spin_unlock_irqrestore(&vector_lock, flags);
2259 * Level and edge triggered IO-APIC interrupts need different handling,
2260 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
2261 * handled with the level-triggered descriptor, but that one has slightly
2262 * more overhead. Level-triggered interrupts cannot be handled with the
2263 * edge-triggered handler, without risking IRQ storms and other ugly
2268 void send_cleanup_vector(struct irq_cfg *cfg)
2270 cpumask_var_t cleanup_mask;
2272 if (unlikely(!alloc_cpumask_var(&cleanup_mask, GFP_ATOMIC))) {
2274 for_each_cpu_and(i, cfg->old_domain, cpu_online_mask)
2275 apic->send_IPI_mask(cpumask_of(i), IRQ_MOVE_CLEANUP_VECTOR);
2277 cpumask_and(cleanup_mask, cfg->old_domain, cpu_online_mask);
2278 apic->send_IPI_mask(cleanup_mask, IRQ_MOVE_CLEANUP_VECTOR);
2279 free_cpumask_var(cleanup_mask);
2281 cfg->move_in_progress = 0;
2284 static void __target_IO_APIC_irq(unsigned int irq, unsigned int dest, struct irq_cfg *cfg)
2287 struct irq_pin_list *entry;
2288 u8 vector = cfg->vector;
2290 for_each_irq_pin(entry, cfg->irq_2_pin) {
2296 * With interrupt-remapping, destination information comes
2297 * from interrupt-remapping table entry.
2299 if (!irq_remapped(cfg))
2300 io_apic_write(apic, 0x11 + pin*2, dest);
2301 reg = io_apic_read(apic, 0x10 + pin*2);
2302 reg &= ~IO_APIC_REDIR_VECTOR_MASK;
2304 io_apic_modify(apic, 0x10 + pin*2, reg);
2309 * Either sets data->affinity to a valid value, and returns
2310 * ->cpu_mask_to_apicid of that in dest_id, or returns -1 and
2311 * leaves data->affinity untouched.
2313 int __ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2314 unsigned int *dest_id)
2316 struct irq_cfg *cfg = data->chip_data;
2318 if (!cpumask_intersects(mask, cpu_online_mask))
2321 if (assign_irq_vector(data->irq, data->chip_data, mask))
2324 cpumask_copy(data->affinity, mask);
2326 *dest_id = apic->cpu_mask_to_apicid_and(mask, cfg->domain);
2331 ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2334 unsigned int dest, irq = data->irq;
2335 unsigned long flags;
2338 raw_spin_lock_irqsave(&ioapic_lock, flags);
2339 ret = __ioapic_set_affinity(data, mask, &dest);
2341 /* Only the high 8 bits are valid. */
2342 dest = SET_APIC_LOGICAL_ID(dest);
2343 __target_IO_APIC_irq(irq, dest, data->chip_data);
2345 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
2349 #ifdef CONFIG_IRQ_REMAP
2352 * Migrate the IO-APIC irq in the presence of intr-remapping.
2354 * For both level and edge triggered, irq migration is a simple atomic
2355 * update(of vector and cpu destination) of IRTE and flush the hardware cache.
2357 * For level triggered, we eliminate the io-apic RTE modification (with the
2358 * updated vector information), by using a virtual vector (io-apic pin number).
2359 * Real vector that is used for interrupting cpu will be coming from
2360 * the interrupt-remapping table entry.
2362 * As the migration is a simple atomic update of IRTE, the same mechanism
2363 * is used to migrate MSI irq's in the presence of interrupt-remapping.
2366 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2369 struct irq_cfg *cfg = data->chip_data;
2370 unsigned int dest, irq = data->irq;
2373 if (!cpumask_intersects(mask, cpu_online_mask))
2376 if (get_irte(irq, &irte))
2379 if (assign_irq_vector(irq, cfg, mask))
2382 dest = apic->cpu_mask_to_apicid_and(cfg->domain, mask);
2384 irte.vector = cfg->vector;
2385 irte.dest_id = IRTE_DEST(dest);
2388 * Atomically updates the IRTE with the new destination, vector
2389 * and flushes the interrupt entry cache.
2391 modify_irte(irq, &irte);
2394 * After this point, all the interrupts will start arriving
2395 * at the new destination. So, time to cleanup the previous
2396 * vector allocation.
2398 if (cfg->move_in_progress)
2399 send_cleanup_vector(cfg);
2401 cpumask_copy(data->affinity, mask);
2407 ir_ioapic_set_affinity(struct irq_data *data, const struct cpumask *mask,
2414 asmlinkage void smp_irq_move_cleanup_interrupt(void)
2416 unsigned vector, me;
2422 me = smp_processor_id();
2423 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
2426 struct irq_desc *desc;
2427 struct irq_cfg *cfg;
2428 irq = __this_cpu_read(vector_irq[vector]);
2433 desc = irq_to_desc(irq);
2438 raw_spin_lock(&desc->lock);
2441 * Check if the irq migration is in progress. If so, we
2442 * haven't received the cleanup request yet for this irq.
2444 if (cfg->move_in_progress)
2447 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2450 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
2452 * Check if the vector that needs to be cleanedup is
2453 * registered at the cpu's IRR. If so, then this is not
2454 * the best time to clean it up. Lets clean it up in the
2455 * next attempt by sending another IRQ_MOVE_CLEANUP_VECTOR
2458 if (irr & (1 << (vector % 32))) {
2459 apic->send_IPI_self(IRQ_MOVE_CLEANUP_VECTOR);
2462 __this_cpu_write(vector_irq[vector], -1);
2464 raw_spin_unlock(&desc->lock);
2470 static void __irq_complete_move(struct irq_cfg *cfg, unsigned vector)
2474 if (likely(!cfg->move_in_progress))
2477 me = smp_processor_id();
2479 if (vector == cfg->vector && cpumask_test_cpu(me, cfg->domain))
2480 send_cleanup_vector(cfg);
2483 static void irq_complete_move(struct irq_cfg *cfg)
2485 __irq_complete_move(cfg, ~get_irq_regs()->orig_ax);
2488 void irq_force_complete_move(int irq)
2490 struct irq_cfg *cfg = irq_get_chip_data(irq);
2495 __irq_complete_move(cfg, cfg->vector);
2498 static inline void irq_complete_move(struct irq_cfg *cfg) { }
2501 static void ack_apic_edge(struct irq_data *data)
2503 irq_complete_move(data->chip_data);
2508 atomic_t irq_mis_count;
2510 static void ack_apic_level(struct irq_data *data)
2512 struct irq_cfg *cfg = data->chip_data;
2513 int i, do_unmask_irq = 0, irq = data->irq;
2516 irq_complete_move(cfg);
2517 #ifdef CONFIG_GENERIC_PENDING_IRQ
2518 /* If we are moving the irq we need to mask it */
2519 if (unlikely(irqd_is_setaffinity_pending(data))) {
2526 * It appears there is an erratum which affects at least version 0x11
2527 * of I/O APIC (that's the 82093AA and cores integrated into various
2528 * chipsets). Under certain conditions a level-triggered interrupt is
2529 * erroneously delivered as edge-triggered one but the respective IRR
2530 * bit gets set nevertheless. As a result the I/O unit expects an EOI
2531 * message but it will never arrive and further interrupts are blocked
2532 * from the source. The exact reason is so far unknown, but the
2533 * phenomenon was observed when two consecutive interrupt requests
2534 * from a given source get delivered to the same CPU and the source is
2535 * temporarily disabled in between.
2537 * A workaround is to simulate an EOI message manually. We achieve it
2538 * by setting the trigger mode to edge and then to level when the edge
2539 * trigger mode gets detected in the TMR of a local APIC for a
2540 * level-triggered interrupt. We mask the source for the time of the
2541 * operation to prevent an edge-triggered interrupt escaping meanwhile.
2542 * The idea is from Manfred Spraul. --macro
2544 * Also in the case when cpu goes offline, fixup_irqs() will forward
2545 * any unhandled interrupt on the offlined cpu to the new cpu
2546 * destination that is handling the corresponding interrupt. This
2547 * interrupt forwarding is done via IPI's. Hence, in this case also
2548 * level-triggered io-apic interrupt will be seen as an edge
2549 * interrupt in the IRR. And we can't rely on the cpu's EOI
2550 * to be broadcasted to the IO-APIC's which will clear the remoteIRR
2551 * corresponding to the level-triggered interrupt. Hence on IO-APIC's
2552 * supporting EOI register, we do an explicit EOI to clear the
2553 * remote IRR and on IO-APIC's which don't have an EOI register,
2554 * we use the above logic (mask+edge followed by unmask+level) from
2555 * Manfred Spraul to clear the remote IRR.
2558 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
2561 * We must acknowledge the irq before we move it or the acknowledge will
2562 * not propagate properly.
2567 * Tail end of clearing remote IRR bit (either by delivering the EOI
2568 * message via io-apic EOI register write or simulating it using
2569 * mask+edge followed by unnask+level logic) manually when the
2570 * level triggered interrupt is seen as the edge triggered interrupt
2573 if (!(v & (1 << (i & 0x1f)))) {
2574 atomic_inc(&irq_mis_count);
2576 eoi_ioapic_irq(irq, cfg);
2579 /* Now we can move and renable the irq */
2580 if (unlikely(do_unmask_irq)) {
2581 /* Only migrate the irq if the ack has been received.
2583 * On rare occasions the broadcast level triggered ack gets
2584 * delayed going to ioapics, and if we reprogram the
2585 * vector while Remote IRR is still set the irq will never
2588 * To prevent this scenario we read the Remote IRR bit
2589 * of the ioapic. This has two effects.
2590 * - On any sane system the read of the ioapic will
2591 * flush writes (and acks) going to the ioapic from
2593 * - We get to see if the ACK has actually been delivered.
2595 * Based on failed experiments of reprogramming the
2596 * ioapic entry from outside of irq context starting
2597 * with masking the ioapic entry and then polling until
2598 * Remote IRR was clear before reprogramming the
2599 * ioapic I don't trust the Remote IRR bit to be
2600 * completey accurate.
2602 * However there appears to be no other way to plug
2603 * this race, so if the Remote IRR bit is not
2604 * accurate and is causing problems then it is a hardware bug
2605 * and you can go talk to the chipset vendor about it.
2607 if (!io_apic_level_ack_pending(cfg))
2608 irq_move_masked_irq(data);
2613 #ifdef CONFIG_IRQ_REMAP
2614 static void ir_ack_apic_edge(struct irq_data *data)
2619 static void ir_ack_apic_level(struct irq_data *data)
2622 eoi_ioapic_irq(data->irq, data->chip_data);
2625 static void ir_print_prefix(struct irq_data *data, struct seq_file *p)
2627 seq_printf(p, " IR-%s", data->chip->name);
2630 static void irq_remap_modify_chip_defaults(struct irq_chip *chip)
2632 chip->irq_print_chip = ir_print_prefix;
2633 chip->irq_ack = ir_ack_apic_edge;
2634 chip->irq_eoi = ir_ack_apic_level;
2637 chip->irq_set_affinity = ir_ioapic_set_affinity;
2640 #endif /* CONFIG_IRQ_REMAP */
2642 static struct irq_chip ioapic_chip __read_mostly = {
2644 .irq_startup = startup_ioapic_irq,
2645 .irq_mask = mask_ioapic_irq,
2646 .irq_unmask = unmask_ioapic_irq,
2647 .irq_ack = ack_apic_edge,
2648 .irq_eoi = ack_apic_level,
2650 .irq_set_affinity = ioapic_set_affinity,
2652 .irq_retrigger = ioapic_retrigger_irq,
2655 static inline void init_IO_APIC_traps(void)
2657 struct irq_cfg *cfg;
2661 * NOTE! The local APIC isn't very good at handling
2662 * multiple interrupts at the same interrupt level.
2663 * As the interrupt level is determined by taking the
2664 * vector number and shifting that right by 4, we
2665 * want to spread these out a bit so that they don't
2666 * all fall in the same interrupt level.
2668 * Also, we've got to be careful not to trash gate
2669 * 0x80, because int 0x80 is hm, kind of importantish. ;)
2671 for_each_active_irq(irq) {
2672 cfg = irq_get_chip_data(irq);
2673 if (IO_APIC_IRQ(irq) && cfg && !cfg->vector) {
2675 * Hmm.. We don't have an entry for this,
2676 * so default to an old-fashioned 8259
2677 * interrupt if we can..
2679 if (irq < legacy_pic->nr_legacy_irqs)
2680 legacy_pic->make_irq(irq);
2682 /* Strange. Oh, well.. */
2683 irq_set_chip(irq, &no_irq_chip);
2689 * The local APIC irq-chip implementation:
2692 static void mask_lapic_irq(struct irq_data *data)
2696 v = apic_read(APIC_LVT0);
2697 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
2700 static void unmask_lapic_irq(struct irq_data *data)
2704 v = apic_read(APIC_LVT0);
2705 apic_write(APIC_LVT0, v & ~APIC_LVT_MASKED);
2708 static void ack_lapic_irq(struct irq_data *data)
2713 static struct irq_chip lapic_chip __read_mostly = {
2714 .name = "local-APIC",
2715 .irq_mask = mask_lapic_irq,
2716 .irq_unmask = unmask_lapic_irq,
2717 .irq_ack = ack_lapic_irq,
2720 static void lapic_register_intr(int irq)
2722 irq_clear_status_flags(irq, IRQ_LEVEL);
2723 irq_set_chip_and_handler_name(irq, &lapic_chip, handle_edge_irq,
2728 * This looks a bit hackish but it's about the only one way of sending
2729 * a few INTA cycles to 8259As and any associated glue logic. ICR does
2730 * not support the ExtINT mode, unfortunately. We need to send these
2731 * cycles as some i82489DX-based boards have glue logic that keeps the
2732 * 8259A interrupt line asserted until INTA. --macro
2734 static inline void __init unlock_ExtINT_logic(void)
2737 struct IO_APIC_route_entry entry0, entry1;
2738 unsigned char save_control, save_freq_select;
2740 pin = find_isa_irq_pin(8, mp_INT);
2745 apic = find_isa_irq_apic(8, mp_INT);
2751 entry0 = ioapic_read_entry(apic, pin);
2752 clear_IO_APIC_pin(apic, pin);
2754 memset(&entry1, 0, sizeof(entry1));
2756 entry1.dest_mode = 0; /* physical delivery */
2757 entry1.mask = 0; /* unmask IRQ now */
2758 entry1.dest = hard_smp_processor_id();
2759 entry1.delivery_mode = dest_ExtINT;
2760 entry1.polarity = entry0.polarity;
2764 ioapic_write_entry(apic, pin, entry1);
2766 save_control = CMOS_READ(RTC_CONTROL);
2767 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
2768 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
2770 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
2775 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
2779 CMOS_WRITE(save_control, RTC_CONTROL);
2780 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
2781 clear_IO_APIC_pin(apic, pin);
2783 ioapic_write_entry(apic, pin, entry0);
2786 static int disable_timer_pin_1 __initdata;
2787 /* Actually the next is obsolete, but keep it for paranoid reasons -AK */
2788 static int __init disable_timer_pin_setup(char *arg)
2790 disable_timer_pin_1 = 1;
2793 early_param("disable_timer_pin_1", disable_timer_pin_setup);
2795 int timer_through_8259 __initdata;
2798 * This code may look a bit paranoid, but it's supposed to cooperate with
2799 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
2800 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
2801 * fanatically on his truly buggy board.
2803 * FIXME: really need to revamp this for all platforms.
2805 static inline void __init check_timer(void)
2807 struct irq_cfg *cfg = irq_get_chip_data(0);
2808 int node = cpu_to_node(0);
2809 int apic1, pin1, apic2, pin2;
2810 unsigned long flags;
2813 local_irq_save(flags);
2816 * get/set the timer IRQ vector:
2818 legacy_pic->mask(0);
2819 assign_irq_vector(0, cfg, apic->target_cpus());
2822 * As IRQ0 is to be enabled in the 8259A, the virtual
2823 * wire has to be disabled in the local APIC. Also
2824 * timer interrupts need to be acknowledged manually in
2825 * the 8259A for the i82489DX when using the NMI
2826 * watchdog as that APIC treats NMIs as level-triggered.
2827 * The AEOI mode will finish them in the 8259A
2830 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
2831 legacy_pic->init(1);
2833 pin1 = find_isa_irq_pin(0, mp_INT);
2834 apic1 = find_isa_irq_apic(0, mp_INT);
2835 pin2 = ioapic_i8259.pin;
2836 apic2 = ioapic_i8259.apic;
2838 apic_printk(APIC_QUIET, KERN_INFO "..TIMER: vector=0x%02X "
2839 "apic1=%d pin1=%d apic2=%d pin2=%d\n",
2840 cfg->vector, apic1, pin1, apic2, pin2);
2843 * Some BIOS writers are clueless and report the ExtINTA
2844 * I/O APIC input from the cascaded 8259A as the timer
2845 * interrupt input. So just in case, if only one pin
2846 * was found above, try it both directly and through the
2850 if (intr_remapping_enabled)
2851 panic("BIOS bug: timer not connected to IO-APIC");
2855 } else if (pin2 == -1) {
2862 * Ok, does IRQ0 through the IOAPIC work?
2865 add_pin_to_irq_node(cfg, node, apic1, pin1);
2866 setup_timer_IRQ0_pin(apic1, pin1, cfg->vector);
2868 /* for edge trigger, setup_ioapic_irq already
2869 * leave it unmasked.
2870 * so only need to unmask if it is level-trigger
2871 * do we really have level trigger timer?
2874 idx = find_irq_entry(apic1, pin1, mp_INT);
2875 if (idx != -1 && irq_trigger(idx))
2878 if (timer_irq_works()) {
2879 if (disable_timer_pin_1 > 0)
2880 clear_IO_APIC_pin(0, pin1);
2883 if (intr_remapping_enabled)
2884 panic("timer doesn't work through Interrupt-remapped IO-APIC");
2885 local_irq_disable();
2886 clear_IO_APIC_pin(apic1, pin1);
2888 apic_printk(APIC_QUIET, KERN_ERR "..MP-BIOS bug: "
2889 "8254 timer not connected to IO-APIC\n");
2891 apic_printk(APIC_QUIET, KERN_INFO "...trying to set up timer "
2892 "(IRQ0) through the 8259A ...\n");
2893 apic_printk(APIC_QUIET, KERN_INFO
2894 "..... (found apic %d pin %d) ...\n", apic2, pin2);
2896 * legacy devices should be connected to IO APIC #0
2898 replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
2899 setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
2900 legacy_pic->unmask(0);
2901 if (timer_irq_works()) {
2902 apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
2903 timer_through_8259 = 1;
2907 * Cleanup, just in case ...
2909 local_irq_disable();
2910 legacy_pic->mask(0);
2911 clear_IO_APIC_pin(apic2, pin2);
2912 apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
2915 apic_printk(APIC_QUIET, KERN_INFO
2916 "...trying to set up timer as Virtual Wire IRQ...\n");
2918 lapic_register_intr(0);
2919 apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
2920 legacy_pic->unmask(0);
2922 if (timer_irq_works()) {
2923 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2926 local_irq_disable();
2927 legacy_pic->mask(0);
2928 apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
2929 apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
2931 apic_printk(APIC_QUIET, KERN_INFO
2932 "...trying to set up timer as ExtINT IRQ...\n");
2934 legacy_pic->init(0);
2935 legacy_pic->make_irq(0);
2936 apic_write(APIC_LVT0, APIC_DM_EXTINT);
2938 unlock_ExtINT_logic();
2940 if (timer_irq_works()) {
2941 apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
2944 local_irq_disable();
2945 apic_printk(APIC_QUIET, KERN_INFO "..... failed :(.\n");
2946 panic("IO-APIC + timer doesn't work! Boot with apic=debug and send a "
2947 "report. Then try booting with the 'noapic' option.\n");
2949 local_irq_restore(flags);
2953 * Traditionally ISA IRQ2 is the cascade IRQ, and is not available
2954 * to devices. However there may be an I/O APIC pin available for
2955 * this interrupt regardless. The pin may be left unconnected, but
2956 * typically it will be reused as an ExtINT cascade interrupt for
2957 * the master 8259A. In the MPS case such a pin will normally be
2958 * reported as an ExtINT interrupt in the MP table. With ACPI
2959 * there is no provision for ExtINT interrupts, and in the absence
2960 * of an override it would be treated as an ordinary ISA I/O APIC
2961 * interrupt, that is edge-triggered and unmasked by default. We
2962 * used to do this, but it caused problems on some systems because
2963 * of the NMI watchdog and sometimes IRQ0 of the 8254 timer using
2964 * the same ExtINT cascade interrupt to drive the local APIC of the
2965 * bootstrap processor. Therefore we refrain from routing IRQ2 to
2966 * the I/O APIC in all cases now. No actual device should request
2967 * it anyway. --macro
2969 #define PIC_IRQS (1UL << PIC_CASCADE_IR)
2971 void __init setup_IO_APIC(void)
2975 * calling enable_IO_APIC() is moved to setup_local_APIC for BP
2977 io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
2979 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
2981 * Set up IO-APIC IRQ routing.
2983 x86_init.mpparse.setup_ioapic_ids();
2986 setup_IO_APIC_irqs();
2987 init_IO_APIC_traps();
2988 if (legacy_pic->nr_legacy_irqs)
2993 * Called after all the initialization is done. If we didn't find any
2994 * APIC bugs then we can allow the modify fast path
2997 static int __init io_apic_bug_finalize(void)
2999 if (sis_apic_bug == -1)
3004 late_initcall(io_apic_bug_finalize);
3006 static void resume_ioapic_id(int ioapic_idx)
3008 unsigned long flags;
3009 union IO_APIC_reg_00 reg_00;
3011 raw_spin_lock_irqsave(&ioapic_lock, flags);
3012 reg_00.raw = io_apic_read(ioapic_idx, 0);
3013 if (reg_00.bits.ID != mpc_ioapic_id(ioapic_idx)) {
3014 reg_00.bits.ID = mpc_ioapic_id(ioapic_idx);
3015 io_apic_write(ioapic_idx, 0, reg_00.raw);
3017 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3020 static void ioapic_resume(void)
3024 for (ioapic_idx = nr_ioapics - 1; ioapic_idx >= 0; ioapic_idx--)
3025 resume_ioapic_id(ioapic_idx);
3027 restore_ioapic_entries();
3030 static struct syscore_ops ioapic_syscore_ops = {
3031 .suspend = save_ioapic_entries,
3032 .resume = ioapic_resume,
3035 static int __init ioapic_init_ops(void)
3037 register_syscore_ops(&ioapic_syscore_ops);
3042 device_initcall(ioapic_init_ops);
3045 * Dynamic irq allocate and deallocation
3047 unsigned int create_irq_nr(unsigned int from, int node)
3049 struct irq_cfg *cfg;
3050 unsigned long flags;
3051 unsigned int ret = 0;
3054 if (from < nr_irqs_gsi)
3057 irq = alloc_irq_from(from, node);
3060 cfg = alloc_irq_cfg(irq, node);
3062 free_irq_at(irq, NULL);
3066 raw_spin_lock_irqsave(&vector_lock, flags);
3067 if (!__assign_irq_vector(irq, cfg, apic->target_cpus()))
3069 raw_spin_unlock_irqrestore(&vector_lock, flags);
3072 irq_set_chip_data(irq, cfg);
3073 irq_clear_status_flags(irq, IRQ_NOREQUEST);
3075 free_irq_at(irq, cfg);
3080 int create_irq(void)
3082 int node = cpu_to_node(0);
3083 unsigned int irq_want;
3086 irq_want = nr_irqs_gsi;
3087 irq = create_irq_nr(irq_want, node);
3095 void destroy_irq(unsigned int irq)
3097 struct irq_cfg *cfg = irq_get_chip_data(irq);
3098 unsigned long flags;
3100 irq_set_status_flags(irq, IRQ_NOREQUEST|IRQ_NOPROBE);
3102 if (irq_remapped(cfg))
3104 raw_spin_lock_irqsave(&vector_lock, flags);
3105 __clear_irq_vector(irq, cfg);
3106 raw_spin_unlock_irqrestore(&vector_lock, flags);
3107 free_irq_at(irq, cfg);
3111 * MSI message composition
3113 #ifdef CONFIG_PCI_MSI
3114 static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq,
3115 struct msi_msg *msg, u8 hpet_id)
3117 struct irq_cfg *cfg;
3125 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3129 dest = apic->cpu_mask_to_apicid_and(cfg->domain, apic->target_cpus());
3131 if (irq_remapped(cfg)) {
3136 ir_index = map_irq_to_irte_handle(irq, &sub_handle);
3137 BUG_ON(ir_index == -1);
3139 prepare_irte(&irte, cfg->vector, dest);
3141 /* Set source-id of interrupt request */
3143 set_msi_sid(&irte, pdev);
3145 set_hpet_sid(&irte, hpet_id);
3147 modify_irte(irq, &irte);
3149 msg->address_hi = MSI_ADDR_BASE_HI;
3150 msg->data = sub_handle;
3151 msg->address_lo = MSI_ADDR_BASE_LO | MSI_ADDR_IR_EXT_INT |
3153 MSI_ADDR_IR_INDEX1(ir_index) |
3154 MSI_ADDR_IR_INDEX2(ir_index);
3156 if (x2apic_enabled())
3157 msg->address_hi = MSI_ADDR_BASE_HI |
3158 MSI_ADDR_EXT_DEST_ID(dest);
3160 msg->address_hi = MSI_ADDR_BASE_HI;
3164 ((apic->irq_dest_mode == 0) ?
3165 MSI_ADDR_DEST_MODE_PHYSICAL:
3166 MSI_ADDR_DEST_MODE_LOGICAL) |
3167 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3168 MSI_ADDR_REDIRECTION_CPU:
3169 MSI_ADDR_REDIRECTION_LOWPRI) |
3170 MSI_ADDR_DEST_ID(dest);
3173 MSI_DATA_TRIGGER_EDGE |
3174 MSI_DATA_LEVEL_ASSERT |
3175 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3176 MSI_DATA_DELIVERY_FIXED:
3177 MSI_DATA_DELIVERY_LOWPRI) |
3178 MSI_DATA_VECTOR(cfg->vector);
3185 msi_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3187 struct irq_cfg *cfg = data->chip_data;
3191 if (__ioapic_set_affinity(data, mask, &dest))
3194 __get_cached_msi_msg(data->msi_desc, &msg);
3196 msg.data &= ~MSI_DATA_VECTOR_MASK;
3197 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3198 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3199 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3201 __write_msi_msg(data->msi_desc, &msg);
3205 #endif /* CONFIG_SMP */
3208 * IRQ Chip for MSI PCI/PCI-X/PCI-Express Devices,
3209 * which implement the MSI or MSI-X Capability Structure.
3211 static struct irq_chip msi_chip = {
3213 .irq_unmask = unmask_msi_irq,
3214 .irq_mask = mask_msi_irq,
3215 .irq_ack = ack_apic_edge,
3217 .irq_set_affinity = msi_set_affinity,
3219 .irq_retrigger = ioapic_retrigger_irq,
3223 * Map the PCI dev to the corresponding remapping hardware unit
3224 * and allocate 'nvec' consecutive interrupt-remapping table entries
3227 static int msi_alloc_irte(struct pci_dev *dev, int irq, int nvec)
3229 struct intel_iommu *iommu;
3232 iommu = map_dev_to_ir(dev);
3235 "Unable to map PCI %s to iommu\n", pci_name(dev));
3239 index = alloc_irte(iommu, irq, nvec);
3242 "Unable to allocate %d IRTE for PCI %s\n", nvec,
3249 static int setup_msi_irq(struct pci_dev *dev, struct msi_desc *msidesc, int irq)
3251 struct irq_chip *chip = &msi_chip;
3255 ret = msi_compose_msg(dev, irq, &msg, -1);
3259 irq_set_msi_desc(irq, msidesc);
3260 write_msi_msg(irq, &msg);
3262 if (irq_remapped(irq_get_chip_data(irq))) {
3263 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3264 irq_remap_modify_chip_defaults(chip);
3267 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3269 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for MSI/MSI-X\n", irq);
3274 int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
3276 int node, ret, sub_handle, index = 0;
3277 unsigned int irq, irq_want;
3278 struct msi_desc *msidesc;
3279 struct intel_iommu *iommu = NULL;
3281 /* x86 doesn't support multiple MSI yet */
3282 if (type == PCI_CAP_ID_MSI && nvec > 1)
3285 node = dev_to_node(&dev->dev);
3286 irq_want = nr_irqs_gsi;
3288 list_for_each_entry(msidesc, &dev->msi_list, list) {
3289 irq = create_irq_nr(irq_want, node);
3293 if (!intr_remapping_enabled)
3298 * allocate the consecutive block of IRTE's
3301 index = msi_alloc_irte(dev, irq, nvec);
3307 iommu = map_dev_to_ir(dev);
3313 * setup the mapping between the irq and the IRTE
3314 * base index, the sub_handle pointing to the
3315 * appropriate interrupt remap table entry.
3317 set_irte_irq(irq, iommu, index, sub_handle);
3320 ret = setup_msi_irq(dev, msidesc, irq);
3332 void native_teardown_msi_irq(unsigned int irq)
3337 #ifdef CONFIG_DMAR_TABLE
3340 dmar_msi_set_affinity(struct irq_data *data, const struct cpumask *mask,
3343 struct irq_cfg *cfg = data->chip_data;
3344 unsigned int dest, irq = data->irq;
3347 if (__ioapic_set_affinity(data, mask, &dest))
3350 dmar_msi_read(irq, &msg);
3352 msg.data &= ~MSI_DATA_VECTOR_MASK;
3353 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3354 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3355 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3356 msg.address_hi = MSI_ADDR_BASE_HI | MSI_ADDR_EXT_DEST_ID(dest);
3358 dmar_msi_write(irq, &msg);
3363 #endif /* CONFIG_SMP */
3365 static struct irq_chip dmar_msi_type = {
3367 .irq_unmask = dmar_msi_unmask,
3368 .irq_mask = dmar_msi_mask,
3369 .irq_ack = ack_apic_edge,
3371 .irq_set_affinity = dmar_msi_set_affinity,
3373 .irq_retrigger = ioapic_retrigger_irq,
3376 int arch_setup_dmar_msi(unsigned int irq)
3381 ret = msi_compose_msg(NULL, irq, &msg, -1);
3384 dmar_msi_write(irq, &msg);
3385 irq_set_chip_and_handler_name(irq, &dmar_msi_type, handle_edge_irq,
3391 #ifdef CONFIG_HPET_TIMER
3394 static int hpet_msi_set_affinity(struct irq_data *data,
3395 const struct cpumask *mask, bool force)
3397 struct irq_cfg *cfg = data->chip_data;
3401 if (__ioapic_set_affinity(data, mask, &dest))
3404 hpet_msi_read(data->handler_data, &msg);
3406 msg.data &= ~MSI_DATA_VECTOR_MASK;
3407 msg.data |= MSI_DATA_VECTOR(cfg->vector);
3408 msg.address_lo &= ~MSI_ADDR_DEST_ID_MASK;
3409 msg.address_lo |= MSI_ADDR_DEST_ID(dest);
3411 hpet_msi_write(data->handler_data, &msg);
3416 #endif /* CONFIG_SMP */
3418 static struct irq_chip hpet_msi_type = {
3420 .irq_unmask = hpet_msi_unmask,
3421 .irq_mask = hpet_msi_mask,
3422 .irq_ack = ack_apic_edge,
3424 .irq_set_affinity = hpet_msi_set_affinity,
3426 .irq_retrigger = ioapic_retrigger_irq,
3429 int arch_setup_hpet_msi(unsigned int irq, unsigned int id)
3431 struct irq_chip *chip = &hpet_msi_type;
3435 if (intr_remapping_enabled) {
3436 struct intel_iommu *iommu = map_hpet_to_ir(id);
3442 index = alloc_irte(iommu, irq, 1);
3447 ret = msi_compose_msg(NULL, irq, &msg, id);
3451 hpet_msi_write(irq_get_handler_data(irq), &msg);
3452 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
3453 if (irq_remapped(irq_get_chip_data(irq)))
3454 irq_remap_modify_chip_defaults(chip);
3456 irq_set_chip_and_handler_name(irq, chip, handle_edge_irq, "edge");
3461 #endif /* CONFIG_PCI_MSI */
3463 * Hypertransport interrupt support
3465 #ifdef CONFIG_HT_IRQ
3469 static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
3471 struct ht_irq_msg msg;
3472 fetch_ht_irq_msg(irq, &msg);
3474 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
3475 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
3477 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
3478 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
3480 write_ht_irq_msg(irq, &msg);
3484 ht_set_affinity(struct irq_data *data, const struct cpumask *mask, bool force)
3486 struct irq_cfg *cfg = data->chip_data;
3489 if (__ioapic_set_affinity(data, mask, &dest))
3492 target_ht_irq(data->irq, dest, cfg->vector);
3498 static struct irq_chip ht_irq_chip = {
3500 .irq_mask = mask_ht_irq,
3501 .irq_unmask = unmask_ht_irq,
3502 .irq_ack = ack_apic_edge,
3504 .irq_set_affinity = ht_set_affinity,
3506 .irq_retrigger = ioapic_retrigger_irq,
3509 int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
3511 struct irq_cfg *cfg;
3518 err = assign_irq_vector(irq, cfg, apic->target_cpus());
3520 struct ht_irq_msg msg;
3523 dest = apic->cpu_mask_to_apicid_and(cfg->domain,
3524 apic->target_cpus());
3526 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
3530 HT_IRQ_LOW_DEST_ID(dest) |
3531 HT_IRQ_LOW_VECTOR(cfg->vector) |
3532 ((apic->irq_dest_mode == 0) ?
3533 HT_IRQ_LOW_DM_PHYSICAL :
3534 HT_IRQ_LOW_DM_LOGICAL) |
3535 HT_IRQ_LOW_RQEOI_EDGE |
3536 ((apic->irq_delivery_mode != dest_LowestPrio) ?
3537 HT_IRQ_LOW_MT_FIXED :
3538 HT_IRQ_LOW_MT_ARBITRATED) |
3539 HT_IRQ_LOW_IRQ_MASKED;
3541 write_ht_irq_msg(irq, &msg);
3543 irq_set_chip_and_handler_name(irq, &ht_irq_chip,
3544 handle_edge_irq, "edge");
3546 dev_printk(KERN_DEBUG, &dev->dev, "irq %d for HT\n", irq);
3550 #endif /* CONFIG_HT_IRQ */
3553 io_apic_setup_irq_pin(unsigned int irq, int node, struct io_apic_irq_attr *attr)
3555 struct irq_cfg *cfg = alloc_irq_and_cfg_at(irq, node);
3560 ret = __add_pin_to_irq_node(cfg, node, attr->ioapic, attr->ioapic_pin);
3562 setup_ioapic_irq(irq, cfg, attr);
3566 int io_apic_setup_irq_pin_once(unsigned int irq, int node,
3567 struct io_apic_irq_attr *attr)
3569 unsigned int ioapic_idx = attr->ioapic, pin = attr->ioapic_pin;
3572 /* Avoid redundant programming */
3573 if (test_bit(pin, ioapics[ioapic_idx].pin_programmed)) {
3574 pr_debug("Pin %d-%d already programmed\n",
3575 mpc_ioapic_id(ioapic_idx), pin);
3578 ret = io_apic_setup_irq_pin(irq, node, attr);
3580 set_bit(pin, ioapics[ioapic_idx].pin_programmed);
3584 static int __init io_apic_get_redir_entries(int ioapic)
3586 union IO_APIC_reg_01 reg_01;
3587 unsigned long flags;
3589 raw_spin_lock_irqsave(&ioapic_lock, flags);
3590 reg_01.raw = io_apic_read(ioapic, 1);
3591 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3593 /* The register returns the maximum index redir index
3594 * supported, which is one less than the total number of redir
3597 return reg_01.bits.entries + 1;
3600 static void __init probe_nr_irqs_gsi(void)
3604 nr = gsi_top + NR_IRQS_LEGACY;
3605 if (nr > nr_irqs_gsi)
3608 printk(KERN_DEBUG "nr_irqs_gsi: %d\n", nr_irqs_gsi);
3611 int get_nr_irqs_gsi(void)
3616 int __init arch_probe_nr_irqs(void)
3620 if (nr_irqs > (NR_VECTORS * nr_cpu_ids))
3621 nr_irqs = NR_VECTORS * nr_cpu_ids;
3623 nr = nr_irqs_gsi + 8 * nr_cpu_ids;
3624 #if defined(CONFIG_PCI_MSI) || defined(CONFIG_HT_IRQ)
3626 * for MSI and HT dyn irq
3628 nr += nr_irqs_gsi * 16;
3633 return NR_IRQS_LEGACY;
3636 int io_apic_set_pci_routing(struct device *dev, int irq,
3637 struct io_apic_irq_attr *irq_attr)
3641 if (!IO_APIC_IRQ(irq)) {
3642 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
3647 node = dev ? dev_to_node(dev) : cpu_to_node(0);
3649 return io_apic_setup_irq_pin_once(irq, node, irq_attr);
3652 #ifdef CONFIG_X86_32
3653 static int __init io_apic_get_unique_id(int ioapic, int apic_id)
3655 union IO_APIC_reg_00 reg_00;
3656 static physid_mask_t apic_id_map = PHYSID_MASK_NONE;
3658 unsigned long flags;
3662 * The P4 platform supports up to 256 APIC IDs on two separate APIC
3663 * buses (one for LAPICs, one for IOAPICs), where predecessors only
3664 * supports up to 16 on one shared APIC bus.
3666 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
3667 * advantage of new APIC bus architecture.
3670 if (physids_empty(apic_id_map))
3671 apic->ioapic_phys_id_map(&phys_cpu_present_map, &apic_id_map);
3673 raw_spin_lock_irqsave(&ioapic_lock, flags);
3674 reg_00.raw = io_apic_read(ioapic, 0);
3675 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3677 if (apic_id >= get_physical_broadcast()) {
3678 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
3679 "%d\n", ioapic, apic_id, reg_00.bits.ID);
3680 apic_id = reg_00.bits.ID;
3684 * Every APIC in a system must have a unique ID or we get lots of nice
3685 * 'stuck on smp_invalidate_needed IPI wait' messages.
3687 if (apic->check_apicid_used(&apic_id_map, apic_id)) {
3689 for (i = 0; i < get_physical_broadcast(); i++) {
3690 if (!apic->check_apicid_used(&apic_id_map, i))
3694 if (i == get_physical_broadcast())
3695 panic("Max apic_id exceeded!\n");
3697 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
3698 "trying %d\n", ioapic, apic_id, i);
3703 apic->apicid_to_cpu_present(apic_id, &tmp);
3704 physids_or(apic_id_map, apic_id_map, tmp);
3706 if (reg_00.bits.ID != apic_id) {
3707 reg_00.bits.ID = apic_id;
3709 raw_spin_lock_irqsave(&ioapic_lock, flags);
3710 io_apic_write(ioapic, 0, reg_00.raw);
3711 reg_00.raw = io_apic_read(ioapic, 0);
3712 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3715 if (reg_00.bits.ID != apic_id) {
3716 printk("IOAPIC[%d]: Unable to change apic_id!\n", ioapic);
3721 apic_printk(APIC_VERBOSE, KERN_INFO
3722 "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
3727 static u8 __init io_apic_unique_id(u8 id)
3729 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
3730 !APIC_XAPIC(apic_version[boot_cpu_physical_apicid]))
3731 return io_apic_get_unique_id(nr_ioapics, id);
3736 static u8 __init io_apic_unique_id(u8 id)
3739 DECLARE_BITMAP(used, 256);
3741 bitmap_zero(used, 256);
3742 for (i = 0; i < nr_ioapics; i++) {
3743 __set_bit(mpc_ioapic_id(i), used);
3745 if (!test_bit(id, used))
3747 return find_first_zero_bit(used, 256);
3751 static int __init io_apic_get_version(int ioapic)
3753 union IO_APIC_reg_01 reg_01;
3754 unsigned long flags;
3756 raw_spin_lock_irqsave(&ioapic_lock, flags);
3757 reg_01.raw = io_apic_read(ioapic, 1);
3758 raw_spin_unlock_irqrestore(&ioapic_lock, flags);
3760 return reg_01.bits.version;
3763 int acpi_get_override_irq(u32 gsi, int *trigger, int *polarity)
3765 int ioapic, pin, idx;
3767 if (skip_ioapic_setup)
3770 ioapic = mp_find_ioapic(gsi);
3774 pin = mp_find_ioapic_pin(ioapic, gsi);
3778 idx = find_irq_entry(ioapic, pin, mp_INT);
3782 *trigger = irq_trigger(idx);
3783 *polarity = irq_polarity(idx);
3788 * This function currently is only a helper for the i386 smp boot process where
3789 * we need to reprogram the ioredtbls to cater for the cpus which have come online
3790 * so mask in all cases should simply be apic->target_cpus()
3793 void __init setup_ioapic_dest(void)
3795 int pin, ioapic, irq, irq_entry;
3796 const struct cpumask *mask;
3797 struct irq_data *idata;
3799 if (skip_ioapic_setup == 1)
3802 for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
3803 for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
3804 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
3805 if (irq_entry == -1)
3807 irq = pin_2_irq(irq_entry, ioapic, pin);
3809 if ((ioapic > 0) && (irq > 16))
3812 idata = irq_get_irq_data(irq);
3815 * Honour affinities which have been set in early boot
3817 if (!irqd_can_balance(idata) || irqd_affinity_was_set(idata))
3818 mask = idata->affinity;
3820 mask = apic->target_cpus();
3822 if (intr_remapping_enabled)
3823 ir_ioapic_set_affinity(idata, mask, false);
3825 ioapic_set_affinity(idata, mask, false);
3831 #define IOAPIC_RESOURCE_NAME_SIZE 11
3833 static struct resource *ioapic_resources;
3835 static struct resource * __init ioapic_setup_resources(int nr_ioapics)
3838 struct resource *res;
3842 if (nr_ioapics <= 0)
3845 n = IOAPIC_RESOURCE_NAME_SIZE + sizeof(struct resource);
3848 mem = alloc_bootmem(n);
3851 mem += sizeof(struct resource) * nr_ioapics;
3853 for (i = 0; i < nr_ioapics; i++) {
3855 res[i].flags = IORESOURCE_MEM | IORESOURCE_BUSY;
3856 snprintf(mem, IOAPIC_RESOURCE_NAME_SIZE, "IOAPIC %u", i);
3857 mem += IOAPIC_RESOURCE_NAME_SIZE;
3860 ioapic_resources = res;
3865 void __init ioapic_and_gsi_init(void)
3867 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
3868 struct resource *ioapic_res;
3871 ioapic_res = ioapic_setup_resources(nr_ioapics);
3872 for (i = 0; i < nr_ioapics; i++) {
3873 if (smp_found_config) {
3874 ioapic_phys = mpc_ioapic_addr(i);
3875 #ifdef CONFIG_X86_32
3878 "WARNING: bogus zero IO-APIC "
3879 "address found in MPTABLE, "
3880 "disabling IO/APIC support!\n");
3881 smp_found_config = 0;
3882 skip_ioapic_setup = 1;
3883 goto fake_ioapic_page;
3887 #ifdef CONFIG_X86_32
3890 ioapic_phys = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
3891 ioapic_phys = __pa(ioapic_phys);
3893 set_fixmap_nocache(idx, ioapic_phys);
3894 apic_printk(APIC_VERBOSE, "mapped IOAPIC to %08lx (%08lx)\n",
3895 __fix_to_virt(idx) + (ioapic_phys & ~PAGE_MASK),
3899 ioapic_res->start = ioapic_phys;
3900 ioapic_res->end = ioapic_phys + IO_APIC_SLOT_SIZE - 1;
3904 probe_nr_irqs_gsi();
3907 void __init ioapic_insert_resources(void)
3910 struct resource *r = ioapic_resources;
3915 "IO APIC resources couldn't be allocated.\n");
3919 for (i = 0; i < nr_ioapics; i++) {
3920 insert_resource(&iomem_resource, r);
3925 int mp_find_ioapic(u32 gsi)
3929 if (nr_ioapics == 0)
3932 /* Find the IOAPIC that manages this GSI. */
3933 for (i = 0; i < nr_ioapics; i++) {
3934 struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
3935 if ((gsi >= gsi_cfg->gsi_base)
3936 && (gsi <= gsi_cfg->gsi_end))
3940 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
3944 int mp_find_ioapic_pin(int ioapic, u32 gsi)
3946 struct mp_ioapic_gsi *gsi_cfg;
3948 if (WARN_ON(ioapic == -1))
3951 gsi_cfg = mp_ioapic_gsi_routing(ioapic);
3952 if (WARN_ON(gsi > gsi_cfg->gsi_end))
3955 return gsi - gsi_cfg->gsi_base;
3958 static __init int bad_ioapic(unsigned long address)
3960 if (nr_ioapics >= MAX_IO_APICS) {
3961 printk(KERN_WARNING "WARNING: Max # of I/O APICs (%d) exceeded "
3962 "(found %d), skipping\n", MAX_IO_APICS, nr_ioapics);
3966 printk(KERN_WARNING "WARNING: Bogus (zero) I/O APIC address"
3967 " found in table, skipping!\n");
3973 void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
3977 struct mp_ioapic_gsi *gsi_cfg;
3979 if (bad_ioapic(address))
3984 ioapics[idx].mp_config.type = MP_IOAPIC;
3985 ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
3986 ioapics[idx].mp_config.apicaddr = address;
3988 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
3989 ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
3990 ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
3993 * Build basic GSI lookup table to facilitate gsi->io_apic lookups
3994 * and to prevent reprogramming of IOAPIC pins (PCI GSIs).
3996 entries = io_apic_get_redir_entries(idx);
3997 gsi_cfg = mp_ioapic_gsi_routing(idx);
3998 gsi_cfg->gsi_base = gsi_base;
3999 gsi_cfg->gsi_end = gsi_base + entries - 1;
4002 * The number of IO-APIC IRQ registers (== #pins):
4004 ioapics[idx].nr_registers = entries;
4006 if (gsi_cfg->gsi_end >= gsi_top)
4007 gsi_top = gsi_cfg->gsi_end + 1;
4009 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
4010 "GSI %d-%d\n", idx, mpc_ioapic_id(idx),
4011 mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
4012 gsi_cfg->gsi_base, gsi_cfg->gsi_end);
4017 /* Enable IOAPIC early just for system timer */
4018 void __init pre_init_apic_IRQ0(void)
4020 struct io_apic_irq_attr attr = { 0, 0, 0, 0 };
4022 printk(KERN_INFO "Early APIC setup for system timer0\n");
4024 physid_set_mask_of_physid(boot_cpu_physical_apicid,
4025 &phys_cpu_present_map);
4029 io_apic_setup_irq_pin(0, 0, &attr);
4030 irq_set_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq,