2 * apb_timer.c: Driver for Langwell APB timers
4 * (C) Copyright 2009 Intel Corporation
5 * Author: Jacob Pan (jacob.jun.pan@intel.com)
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; version 2
13 * Langwell is the south complex of Intel Moorestown MID platform. There are
14 * eight external timers in total that can be used by the operating system.
15 * The timer information, such as frequency and addresses, is provided to the
17 * Timer interrupts are routed via FW/HW emulated IOAPIC independently via
18 * individual redirection table entries (RTE).
19 * Unlike HPET, there is no master counter, therefore one of the timers are
20 * used as clocksource. The overall allocation looks like:
21 * - timer 0 - NR_CPUs for per cpu timer
22 * - one timer for clocksource
23 * - one timer for watchdog driver.
24 * It is also worth notice that APB timer does not support true one-shot mode,
25 * free-running mode will be used here to emulate one-shot mode.
26 * APB timer can also be used as broadcast timer along with per cpu local APIC
27 * timer, but by default APB timer has higher rating than local APIC timers.
30 #include <linux/clocksource.h>
31 #include <linux/clockchips.h>
32 #include <linux/delay.h>
33 #include <linux/errno.h>
34 #include <linux/init.h>
35 #include <linux/sysdev.h>
36 #include <linux/slab.h>
38 #include <linux/pci.h>
39 #include <linux/sfi.h>
40 #include <linux/interrupt.h>
41 #include <linux/cpu.h>
42 #include <linux/irq.h>
44 #include <asm/fixmap.h>
45 #include <asm/apb_timer.h>
49 #define APBT_MASK CLOCKSOURCE_MASK(32)
51 #define APBT_CLOCKEVENT_RATING 110
52 #define APBT_CLOCKSOURCE_RATING 250
53 #define APBT_MIN_DELTA_USEC 200
55 #define EVT_TO_APBT_DEV(evt) container_of(evt, struct apbt_dev, evt)
56 #define APBT_CLOCKEVENT0_NUM (0)
57 #define APBT_CLOCKEVENT1_NUM (1)
58 #define APBT_CLOCKSOURCE_NUM (2)
60 static unsigned long apbt_address;
61 static int apb_timer_block_enabled;
62 static void __iomem *apbt_virt_address;
63 static int phy_cs_timer_id;
66 * Common DW APB timer info
68 static uint64_t apbt_freq;
70 static void apbt_set_mode(enum clock_event_mode mode,
71 struct clock_event_device *evt);
72 static int apbt_next_event(unsigned long delta,
73 struct clock_event_device *evt);
74 static cycle_t apbt_read_clocksource(struct clocksource *cs);
75 static void apbt_restart_clocksource(struct clocksource *cs);
78 struct clock_event_device evt;
88 static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
91 static unsigned int apbt_num_timers_used;
92 static struct apbt_dev *apbt_devs;
95 static inline unsigned long apbt_readl_reg(unsigned long a)
97 return readl(apbt_virt_address + a);
100 static inline void apbt_writel_reg(unsigned long d, unsigned long a)
102 writel(d, apbt_virt_address + a);
105 static inline unsigned long apbt_readl(int n, unsigned long a)
107 return readl(apbt_virt_address + a + n * APBTMRS_REG_SIZE);
110 static inline void apbt_writel(int n, unsigned long d, unsigned long a)
112 writel(d, apbt_virt_address + a + n * APBTMRS_REG_SIZE);
115 static inline void apbt_set_mapping(void)
117 struct sfi_timer_table_entry *mtmr;
119 if (apbt_virt_address) {
120 pr_debug("APBT base already mapped\n");
123 mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
125 printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
126 APBT_CLOCKEVENT0_NUM);
129 apbt_address = (unsigned long)mtmr->phys_addr;
131 printk(KERN_WARNING "No timer base from SFI, use default\n");
132 apbt_address = APBT_DEFAULT_BASE;
134 apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE);
135 if (apbt_virt_address) {
136 pr_debug("Mapped APBT physical addr %p at virtual addr %p\n",\
137 (void *)apbt_address, (void *)apbt_virt_address);
139 pr_debug("Failed mapping APBT phy address at %p\n",\
140 (void *)apbt_address);
143 apbt_freq = mtmr->freq_hz / USEC_PER_SEC;
146 /* Now figure out the physical timer id for clocksource device */
147 mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM);
151 /* Now figure out the physical timer id */
152 phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff)
154 pr_debug("Use timer %d for clocksource\n", phy_cs_timer_id);
158 panic("Failed to setup APB system timer\n");
162 static inline void apbt_clear_mapping(void)
164 iounmap(apbt_virt_address);
165 apbt_virt_address = NULL;
169 * APBT timer interrupt enable / disable
171 static inline int is_apbt_capable(void)
173 return apbt_virt_address ? 1 : 0;
176 static struct clocksource clocksource_apbt = {
178 .rating = APBT_CLOCKSOURCE_RATING,
179 .read = apbt_read_clocksource,
181 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
182 .resume = apbt_restart_clocksource,
185 /* boot APB clock event device */
186 static struct clock_event_device apbt_clockevent = {
188 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
189 .set_mode = apbt_set_mode,
190 .set_next_event = apbt_next_event,
193 .rating = APBT_CLOCKEVENT_RATING,
197 * start count down from 0xffff_ffff. this is done by toggling the enable bit
198 * then load initial load count to ~0.
200 static void apbt_start_counter(int n)
202 unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
204 ctrl &= ~APBTMR_CONTROL_ENABLE;
205 apbt_writel(n, ctrl, APBTMR_N_CONTROL);
206 apbt_writel(n, ~0, APBTMR_N_LOAD_COUNT);
207 /* enable, mask interrupt */
208 ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
209 ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
210 apbt_writel(n, ctrl, APBTMR_N_CONTROL);
211 /* read it once to get cached counter value initialized */
212 apbt_read_clocksource(&clocksource_apbt);
215 static irqreturn_t apbt_interrupt_handler(int irq, void *data)
217 struct apbt_dev *dev = (struct apbt_dev *)data;
218 struct clock_event_device *aevt = &dev->evt;
220 if (!aevt->event_handler) {
221 printk(KERN_INFO "Spurious APBT timer interrupt on %d\n",
225 aevt->event_handler(aevt);
229 static void apbt_restart_clocksource(struct clocksource *cs)
231 apbt_start_counter(phy_cs_timer_id);
234 static void apbt_enable_int(int n)
236 unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
237 /* clear pending intr */
238 apbt_readl(n, APBTMR_N_EOI);
239 ctrl &= ~APBTMR_CONTROL_INT;
240 apbt_writel(n, ctrl, APBTMR_N_CONTROL);
243 static void apbt_disable_int(int n)
245 unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
247 ctrl |= APBTMR_CONTROL_INT;
248 apbt_writel(n, ctrl, APBTMR_N_CONTROL);
252 static int __init apbt_clockevent_register(void)
254 struct sfi_timer_table_entry *mtmr;
255 struct apbt_dev *adev = &__get_cpu_var(cpu_apbt_dev);
257 mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
259 printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
260 APBT_CLOCKEVENT0_NUM);
265 * We need to calculate the scaled math multiplication factor for
266 * nanosecond to apbt tick conversion.
267 * mult = (nsec/cycle)*2^APBT_SHIFT
269 apbt_clockevent.mult = div_sc((unsigned long) mtmr->freq_hz
270 , NSEC_PER_SEC, APBT_SHIFT);
272 /* Calculate the min / max delta */
273 apbt_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
275 apbt_clockevent.min_delta_ns = clockevent_delta2ns(
276 APBT_MIN_DELTA_USEC*apbt_freq,
279 * Start apbt with the boot cpu mask and make it
280 * global if not used for per cpu timer.
282 apbt_clockevent.cpumask = cpumask_of(smp_processor_id());
283 adev->num = smp_processor_id();
284 memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device));
286 if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
287 adev->evt.rating = APBT_CLOCKEVENT_RATING - 100;
288 global_clock_event = &adev->evt;
289 printk(KERN_DEBUG "%s clockevent registered as global\n",
290 global_clock_event->name);
293 if (request_irq(apbt_clockevent.irq, apbt_interrupt_handler,
294 IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
295 apbt_clockevent.name, adev)) {
296 printk(KERN_ERR "Failed request IRQ for APBT%d\n",
297 apbt_clockevent.irq);
300 clockevents_register_device(&adev->evt);
301 /* Start APBT 0 interrupts */
302 apbt_enable_int(APBT_CLOCKEVENT0_NUM);
310 static void apbt_setup_irq(struct apbt_dev *adev)
312 /* timer0 irq has been setup early */
316 irq_modify_status(adev->irq, 0, IRQ_MOVE_PCNTXT);
317 irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
318 /* APB timer irqs are set up as mp_irqs, timer is edge type */
319 __irq_set_handler(adev->irq, handle_edge_irq, 0, "edge");
321 if (system_state == SYSTEM_BOOTING) {
322 if (request_irq(adev->irq, apbt_interrupt_handler,
323 IRQF_TIMER | IRQF_DISABLED |
326 printk(KERN_ERR "Failed request IRQ for APBT%d\n",
330 enable_irq(adev->irq);
333 /* Should be called with per cpu */
334 void apbt_setup_secondary_clock(void)
336 struct apbt_dev *adev;
337 struct clock_event_device *aevt;
340 /* Don't register boot CPU clockevent */
341 cpu = smp_processor_id();
345 * We need to calculate the scaled math multiplication factor for
346 * nanosecond to apbt tick conversion.
347 * mult = (nsec/cycle)*2^APBT_SHIFT
349 printk(KERN_INFO "Init per CPU clockevent %d\n", cpu);
350 adev = &per_cpu(cpu_apbt_dev, cpu);
353 memcpy(aevt, &apbt_clockevent, sizeof(*aevt));
354 aevt->cpumask = cpumask_of(cpu);
355 aevt->name = adev->name;
356 aevt->mode = CLOCK_EVT_MODE_UNUSED;
358 printk(KERN_INFO "Registering CPU %d clockevent device %s, mask %08x\n",
359 cpu, aevt->name, *(u32 *)aevt->cpumask);
361 apbt_setup_irq(adev);
363 clockevents_register_device(aevt);
365 apbt_enable_int(cpu);
371 * this notify handler process CPU hotplug events. in case of S0i3, nonboot
372 * cpus are disabled/enabled frequently, for performance reasons, we keep the
373 * per cpu timer irq registered so that we do need to do free_irq/request_irq.
375 * TODO: it might be more reliable to directly disable percpu clockevent device
376 * without the notifier chain. currently, cpu 0 may get interrupts from other
377 * cpu timers during the offline process due to the ordering of notification.
378 * the extra interrupt is harmless.
380 static int apbt_cpuhp_notify(struct notifier_block *n,
381 unsigned long action, void *hcpu)
383 unsigned long cpu = (unsigned long)hcpu;
384 struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu);
386 switch (action & 0xf) {
388 disable_irq(adev->irq);
389 apbt_disable_int(cpu);
390 if (system_state == SYSTEM_RUNNING) {
391 pr_debug("skipping APBT CPU %lu offline\n", cpu);
393 pr_debug("APBT clockevent for cpu %lu offline\n", cpu);
394 free_irq(adev->irq, adev);
398 pr_debug("APBT notified %lu, no action\n", action);
403 static __init int apbt_late_init(void)
405 if (mrst_timer_options == MRST_TIMER_LAPIC_APBT ||
406 !apb_timer_block_enabled)
408 /* This notifier should be called after workqueue is ready */
409 hotcpu_notifier(apbt_cpuhp_notify, -20);
412 fs_initcall(apbt_late_init);
415 void apbt_setup_secondary_clock(void) {}
417 #endif /* CONFIG_SMP */
419 static void apbt_set_mode(enum clock_event_mode mode,
420 struct clock_event_device *evt)
425 struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
427 BUG_ON(!apbt_virt_address);
429 timer_num = adev->num;
430 pr_debug("%s CPU %d timer %d mode=%d\n",
431 __func__, first_cpu(*evt->cpumask), timer_num, mode);
434 case CLOCK_EVT_MODE_PERIODIC:
435 delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * apbt_clockevent.mult;
436 delta >>= apbt_clockevent.shift;
437 ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
438 ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
439 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
441 * DW APB p. 46, have to disable timer before load counter,
442 * may cause sync problem.
444 ctrl &= ~APBTMR_CONTROL_ENABLE;
445 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
447 pr_debug("Setting clock period %d for HZ %d\n", (int)delta, HZ);
448 apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT);
449 ctrl |= APBTMR_CONTROL_ENABLE;
450 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
452 /* APB timer does not have one-shot mode, use free running mode */
453 case CLOCK_EVT_MODE_ONESHOT:
454 ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
456 * set free running mode, this mode will let timer reload max
457 * timeout which will give time (3min on 25MHz clock) to rearm
458 * the next event, therefore emulate the one-shot mode.
460 ctrl &= ~APBTMR_CONTROL_ENABLE;
461 ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
463 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
464 /* write again to set free running mode */
465 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
468 * DW APB p. 46, load counter with all 1s before starting free
471 apbt_writel(timer_num, ~0, APBTMR_N_LOAD_COUNT);
472 ctrl &= ~APBTMR_CONTROL_INT;
473 ctrl |= APBTMR_CONTROL_ENABLE;
474 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
477 case CLOCK_EVT_MODE_UNUSED:
478 case CLOCK_EVT_MODE_SHUTDOWN:
479 apbt_disable_int(timer_num);
480 ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
481 ctrl &= ~APBTMR_CONTROL_ENABLE;
482 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
485 case CLOCK_EVT_MODE_RESUME:
486 apbt_enable_int(timer_num);
491 static int apbt_next_event(unsigned long delta,
492 struct clock_event_device *evt)
497 struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
499 timer_num = adev->num;
501 ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
502 ctrl &= ~APBTMR_CONTROL_ENABLE;
503 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
504 /* write new count */
505 apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT);
506 ctrl |= APBTMR_CONTROL_ENABLE;
507 apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
511 static cycle_t apbt_read_clocksource(struct clocksource *cs)
513 unsigned long current_count;
515 current_count = apbt_readl(phy_cs_timer_id, APBTMR_N_CURRENT_VALUE);
516 return (cycle_t)~current_count;
519 static int apbt_clocksource_register(void)
524 /* Start the counter, use timer 2 as source, timer 0/1 for event */
525 apbt_start_counter(phy_cs_timer_id);
527 /* Verify whether apbt counter works */
528 t1 = apbt_read_clocksource(&clocksource_apbt);
532 * We don't know the TSC frequency yet, but waiting for
533 * 200000 TSC cycles is safe:
540 } while ((now - start) < 200000UL);
542 /* APBT is the only always on clocksource, it has to work! */
543 if (t1 == apbt_read_clocksource(&clocksource_apbt))
544 panic("APBT counter not counting. APBT disabled\n");
546 clocksource_register_khz(&clocksource_apbt, (u32)apbt_freq*1000);
552 * Early setup the APBT timer, only use timer 0 for booting then switch to
553 * per CPU timer if possible.
554 * returns 1 if per cpu apbt is setup
555 * returns 0 if no per cpu apbt is chosen
556 * panic if set up failed, this is the only platform timer on Moorestown.
558 void __init apbt_time_init(void)
562 struct sfi_timer_table_entry *p_mtmr;
563 unsigned int percpu_timer;
564 struct apbt_dev *adev;
567 if (apb_timer_block_enabled)
570 if (apbt_virt_address) {
571 pr_debug("Found APBT version 0x%lx\n",\
572 apbt_readl_reg(APBTMRS_COMP_VERSION));
576 * Read the frequency and check for a sane value, for ESL model
577 * we extend the possible clock range to allow time scaling.
580 if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) {
581 pr_debug("APBT has invalid freq 0x%llx\n", apbt_freq);
584 if (apbt_clocksource_register()) {
585 pr_debug("APBT has failed to register clocksource\n");
588 if (!apbt_clockevent_register())
589 apb_timer_block_enabled = 1;
591 pr_debug("APBT has failed to register clockevent\n");
595 /* kernel cmdline disable apb timer, so we will use lapic timers */
596 if (mrst_timer_options == MRST_TIMER_LAPIC_APBT) {
597 printk(KERN_INFO "apbt: disabled per cpu timer\n");
600 pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus());
601 if (num_possible_cpus() <= sfi_mtimer_num) {
603 apbt_num_timers_used = num_possible_cpus();
606 apbt_num_timers_used = 1;
607 adev = &per_cpu(cpu_apbt_dev, 0);
608 adev->flags &= ~APBT_DEV_USED;
610 pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used);
612 /* here we set up per CPU timer data structure */
613 apbt_devs = kzalloc(sizeof(struct apbt_dev) * apbt_num_timers_used,
616 printk(KERN_ERR "Failed to allocate APB timer devices\n");
619 for (i = 0; i < apbt_num_timers_used; i++) {
620 adev = &per_cpu(cpu_apbt_dev, i);
623 p_mtmr = sfi_get_mtmr(i);
625 adev->tick = p_mtmr->freq_hz;
626 adev->irq = p_mtmr->irq;
628 printk(KERN_ERR "Failed to get timer for cpu %d\n", i);
630 sprintf(adev->name, "apbt%d", i);
637 apbt_clear_mapping();
638 apb_timer_block_enabled = 0;
639 panic("failed to enable APB timer\n");
642 static inline void apbt_disable(int n)
644 if (is_apbt_capable()) {
645 unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
646 ctrl &= ~APBTMR_CONTROL_ENABLE;
647 apbt_writel(n, ctrl, APBTMR_N_CONTROL);
651 /* called before apb_timer_enable, use early map */
652 unsigned long apbt_quick_calibrate()
657 unsigned long khz = 0;
661 apbt_start_counter(phy_cs_timer_id);
663 /* check if the timer can count down, otherwise return */
664 old = apbt_read_clocksource(&clocksource_apbt);
667 if (old != apbt_read_clocksource(&clocksource_apbt))
674 loop = (apbt_freq * 1000) << 4;
676 /* restart the timer to ensure it won't get to 0 in the calibration */
677 apbt_start_counter(phy_cs_timer_id);
679 old = apbt_read_clocksource(&clocksource_apbt);
682 t1 = __native_read_tsc();
685 new = apbt_read_clocksource(&clocksource_apbt);
688 t2 = __native_read_tsc();
691 if (unlikely(loop >> shift == 0)) {
693 "APBT TSC calibration failed, not enough resolution\n");
696 scale = (int)div_u64((t2 - t1), loop >> shift);
697 khz = (scale * apbt_freq * 1000) >> shift;
698 printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz);