arch/x86/include/asm/vmx.h

   1 #ifndef VMX_H
   2 #define VMX_H
   3
   4 /*
   5  * vmx.h: VMX Architecture related definitions
   6  * Copyright (c) 2004, Intel Corporation.
   7  *
   8  * This program is free software; you can redistribute it and/or modify it
   9  * under the terms and conditions of the GNU General Public License,
  10  * version 2, as published by the Free Software Foundation.
  11  *
  12  * This program is distributed in the hope it will be useful, but WITHOUT
  13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  15  * more details.
  16  *
  17  * You should have received a copy of the GNU General Public License along with
  18  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
  19  * Place - Suite 330, Boston, MA 02111-1307 USA.
  20  *
  21  * A few random additions are:
  22  * Copyright (C) 2006 Qumranet
  23  *    Avi Kivity <avi@qumranet.com>
  24  *    Yaniv Kamay <yaniv@qumranet.com>
  25  *
  26  */
  27
  28 #include <linux/types.h>
  29
  30 /*
  31  * Definitions of Primary Processor-Based VM-Execution Controls.
  32  */
  33 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
  34 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
  35 #define CPU_BASED_HLT_EXITING                   0x00000080
  36 #define CPU_BASED_INVLPG_EXITING                0x00000200
  37 #define CPU_BASED_MWAIT_EXITING                 0x00000400
  38 #define CPU_BASED_RDPMC_EXITING                 0x00000800
  39 #define CPU_BASED_RDTSC_EXITING                 0x00001000
  40 #define CPU_BASED_CR3_LOAD_EXITING              0x00008000
  41 #define CPU_BASED_CR3_STORE_EXITING             0x00010000
  42 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
  43 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
  44 #define CPU_BASED_TPR_SHADOW                    0x00200000
  45 #define CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
  46 #define CPU_BASED_MOV_DR_EXITING                0x00800000
  47 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
  48 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
  49 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
  50 #define CPU_BASED_MONITOR_EXITING               0x20000000
  51 #define CPU_BASED_PAUSE_EXITING                 0x40000000
  52 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
  53 /*
  54  * Definitions of Secondary Processor-Based VM-Execution Controls.
  55  */
  56 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
  57 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
  58 #define SECONDARY_EXEC_RDTSCP                   0x00000008
  59 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
  60 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
  61 #define SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
  62 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
  63
  64
  65 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
  66 #define PIN_BASED_NMI_EXITING                   0x00000008
  67 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
  68
  69 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
  70 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
  71 #define VM_EXIT_SAVE_IA32_PAT                   0x00040000
  72 #define VM_EXIT_LOAD_IA32_PAT                   0x00080000
  73
  74 #define VM_ENTRY_IA32E_MODE                     0x00000200
  75 #define VM_ENTRY_SMM                            0x00000400
  76 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
  77 #define VM_ENTRY_LOAD_IA32_PAT                  0x00004000
  78
  79 /* VMCS Encodings */
  80 enum vmcs_field {
  81         VIRTUAL_PROCESSOR_ID            = 0x00000000,
  82         GUEST_ES_SELECTOR               = 0x00000800,
  83         GUEST_CS_SELECTOR               = 0x00000802,
  84         GUEST_SS_SELECTOR               = 0x00000804,
  85         GUEST_DS_SELECTOR               = 0x00000806,
  86         GUEST_FS_SELECTOR               = 0x00000808,
  87         GUEST_GS_SELECTOR               = 0x0000080a,
  88         GUEST_LDTR_SELECTOR             = 0x0000080c,
  89         GUEST_TR_SELECTOR               = 0x0000080e,
  90         HOST_ES_SELECTOR                = 0x00000c00,
  91         HOST_CS_SELECTOR                = 0x00000c02,
  92         HOST_SS_SELECTOR                = 0x00000c04,
  93         HOST_DS_SELECTOR                = 0x00000c06,
  94         HOST_FS_SELECTOR                = 0x00000c08,
  95         HOST_GS_SELECTOR                = 0x00000c0a,
  96         HOST_TR_SELECTOR                = 0x00000c0c,
  97         IO_BITMAP_A                     = 0x00002000,
  98         IO_BITMAP_A_HIGH                = 0x00002001,
  99         IO_BITMAP_B                     = 0x00002002,
 100         IO_BITMAP_B_HIGH                = 0x00002003,
 101         MSR_BITMAP                      = 0x00002004,
 102         MSR_BITMAP_HIGH                 = 0x00002005,
 103         VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
 104         VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
 105         VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
 106         VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
 107         VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
 108         VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
 109         TSC_OFFSET                      = 0x00002010,
 110         TSC_OFFSET_HIGH                 = 0x00002011,
 111         VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
 112         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
 113         APIC_ACCESS_ADDR                = 0x00002014,
 114         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
 115         EPT_POINTER                     = 0x0000201a,
 116         EPT_POINTER_HIGH                = 0x0000201b,
 117         GUEST_PHYSICAL_ADDRESS          = 0x00002400,
 118         GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
 119         VMCS_LINK_POINTER               = 0x00002800,
 120         VMCS_LINK_POINTER_HIGH          = 0x00002801,
 121         GUEST_IA32_DEBUGCTL             = 0x00002802,
 122         GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
 123         GUEST_IA32_PAT                  = 0x00002804,
 124         GUEST_IA32_PAT_HIGH             = 0x00002805,
 125         GUEST_IA32_EFER                 = 0x00002806,
 126         GUEST_IA32_EFER_HIGH            = 0x00002807,
 127         GUEST_PDPTR0                    = 0x0000280a,
 128         GUEST_PDPTR0_HIGH               = 0x0000280b,
 129         GUEST_PDPTR1                    = 0x0000280c,
 130         GUEST_PDPTR1_HIGH               = 0x0000280d,
 131         GUEST_PDPTR2                    = 0x0000280e,
 132         GUEST_PDPTR2_HIGH               = 0x0000280f,
 133         GUEST_PDPTR3                    = 0x00002810,
 134         GUEST_PDPTR3_HIGH               = 0x00002811,
 135         HOST_IA32_PAT                   = 0x00002c00,
 136         HOST_IA32_PAT_HIGH              = 0x00002c01,
 137         HOST_IA32_EFER                  = 0x00002c02,
 138         HOST_IA32_EFER_HIGH             = 0x00002c03,
 139         PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
 140         CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
 141         EXCEPTION_BITMAP                = 0x00004004,
 142         PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
 143         PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
 144         CR3_TARGET_COUNT                = 0x0000400a,
 145         VM_EXIT_CONTROLS                = 0x0000400c,
 146         VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
 147         VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
 148         VM_ENTRY_CONTROLS               = 0x00004012,
 149         VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
 150         VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
 151         VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
 152         VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
 153         TPR_THRESHOLD                   = 0x0000401c,
 154         SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
 155         PLE_GAP                         = 0x00004020,
 156         PLE_WINDOW                      = 0x00004022,
 157         VM_INSTRUCTION_ERROR            = 0x00004400,
 158         VM_EXIT_REASON                  = 0x00004402,
 159         VM_EXIT_INTR_INFO               = 0x00004404,
 160         VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
 161         IDT_VECTORING_INFO_FIELD        = 0x00004408,
 162         IDT_VECTORING_ERROR_CODE        = 0x0000440a,
 163         VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
 164         VMX_INSTRUCTION_INFO            = 0x0000440e,
 165         GUEST_ES_LIMIT                  = 0x00004800,
 166         GUEST_CS_LIMIT                  = 0x00004802,
 167         GUEST_SS_LIMIT                  = 0x00004804,
 168         GUEST_DS_LIMIT                  = 0x00004806,
 169         GUEST_FS_LIMIT                  = 0x00004808,
 170         GUEST_GS_LIMIT                  = 0x0000480a,
 171         GUEST_LDTR_LIMIT                = 0x0000480c,
 172         GUEST_TR_LIMIT                  = 0x0000480e,
 173         GUEST_GDTR_LIMIT                = 0x00004810,
 174         GUEST_IDTR_LIMIT                = 0x00004812,
 175         GUEST_ES_AR_BYTES               = 0x00004814,
 176         GUEST_CS_AR_BYTES               = 0x00004816,
 177         GUEST_SS_AR_BYTES               = 0x00004818,
 178         GUEST_DS_AR_BYTES               = 0x0000481a,
 179         GUEST_FS_AR_BYTES               = 0x0000481c,
 180         GUEST_GS_AR_BYTES               = 0x0000481e,
 181         GUEST_LDTR_AR_BYTES             = 0x00004820,
 182         GUEST_TR_AR_BYTES               = 0x00004822,
 183         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
 184         GUEST_ACTIVITY_STATE            = 0X00004826,
 185         GUEST_SYSENTER_CS               = 0x0000482A,
 186         HOST_IA32_SYSENTER_CS           = 0x00004c00,
 187         CR0_GUEST_HOST_MASK             = 0x00006000,
 188         CR4_GUEST_HOST_MASK             = 0x00006002,
 189         CR0_READ_SHADOW                 = 0x00006004,
 190         CR4_READ_SHADOW                 = 0x00006006,
 191         CR3_TARGET_VALUE0               = 0x00006008,
 192         CR3_TARGET_VALUE1               = 0x0000600a,
 193         CR3_TARGET_VALUE2               = 0x0000600c,
 194         CR3_TARGET_VALUE3               = 0x0000600e,
 195         EXIT_QUALIFICATION              = 0x00006400,
 196         GUEST_LINEAR_ADDRESS            = 0x0000640a,
 197         GUEST_CR0                       = 0x00006800,
 198         GUEST_CR3                       = 0x00006802,
 199         GUEST_CR4                       = 0x00006804,
 200         GUEST_ES_BASE                   = 0x00006806,
 201         GUEST_CS_BASE                   = 0x00006808,
 202         GUEST_SS_BASE                   = 0x0000680a,
 203         GUEST_DS_BASE                   = 0x0000680c,
 204         GUEST_FS_BASE                   = 0x0000680e,
 205         GUEST_GS_BASE                   = 0x00006810,
 206         GUEST_LDTR_BASE                 = 0x00006812,
 207         GUEST_TR_BASE                   = 0x00006814,
 208         GUEST_GDTR_BASE                 = 0x00006816,
 209         GUEST_IDTR_BASE                 = 0x00006818,
 210         GUEST_DR7                       = 0x0000681a,
 211         GUEST_RSP                       = 0x0000681c,
 212         GUEST_RIP                       = 0x0000681e,
 213         GUEST_RFLAGS                    = 0x00006820,
 214         GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
 215         GUEST_SYSENTER_ESP              = 0x00006824,
 216         GUEST_SYSENTER_EIP              = 0x00006826,
 217         HOST_CR0                        = 0x00006c00,
 218         HOST_CR3                        = 0x00006c02,
 219         HOST_CR4                        = 0x00006c04,
 220         HOST_FS_BASE                    = 0x00006c06,
 221         HOST_GS_BASE                    = 0x00006c08,
 222         HOST_TR_BASE                    = 0x00006c0a,
 223         HOST_GDTR_BASE                  = 0x00006c0c,
 224         HOST_IDTR_BASE                  = 0x00006c0e,
 225         HOST_IA32_SYSENTER_ESP          = 0x00006c10,
 226         HOST_IA32_SYSENTER_EIP          = 0x00006c12,
 227         HOST_RSP                        = 0x00006c14,
 228         HOST_RIP                        = 0x00006c16,
 229 };
 230
 231 #define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000
 232
 233 #define EXIT_REASON_EXCEPTION_NMI       0
 234 #define EXIT_REASON_EXTERNAL_INTERRUPT  1
 235 #define EXIT_REASON_TRIPLE_FAULT        2
 236
 237 #define EXIT_REASON_PENDING_INTERRUPT   7
 238 #define EXIT_REASON_NMI_WINDOW          8
 239 #define EXIT_REASON_TASK_SWITCH         9
 240 #define EXIT_REASON_CPUID               10
 241 #define EXIT_REASON_HLT                 12
 242 #define EXIT_REASON_INVLPG              14
 243 #define EXIT_REASON_RDPMC               15
 244 #define EXIT_REASON_RDTSC               16
 245 #define EXIT_REASON_VMCALL              18
 246 #define EXIT_REASON_VMCLEAR             19
 247 #define EXIT_REASON_VMLAUNCH            20
 248 #define EXIT_REASON_VMPTRLD             21
 249 #define EXIT_REASON_VMPTRST             22
 250 #define EXIT_REASON_VMREAD              23
 251 #define EXIT_REASON_VMRESUME            24
 252 #define EXIT_REASON_VMWRITE             25
 253 #define EXIT_REASON_VMOFF               26
 254 #define EXIT_REASON_VMON                27
 255 #define EXIT_REASON_CR_ACCESS           28
 256 #define EXIT_REASON_DR_ACCESS           29
 257 #define EXIT_REASON_IO_INSTRUCTION      30
 258 #define EXIT_REASON_MSR_READ            31
 259 #define EXIT_REASON_MSR_WRITE           32
 260 #define EXIT_REASON_MWAIT_INSTRUCTION   36
 261 #define EXIT_REASON_MONITOR_INSTRUCTION 39
 262 #define EXIT_REASON_PAUSE_INSTRUCTION   40
 263 #define EXIT_REASON_MCE_DURING_VMENTRY   41
 264 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
 265 #define EXIT_REASON_APIC_ACCESS         44
 266 #define EXIT_REASON_EPT_VIOLATION       48
 267 #define EXIT_REASON_EPT_MISCONFIG       49
 268 #define EXIT_REASON_WBINVD              54
 269
 270 /*
 271  * Interruption-information format
 272  */
 273 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
 274 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
 275 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
 276 #define INTR_INFO_UNBLOCK_NMI           0x1000          /* 12 */
 277 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
 278 #define INTR_INFO_RESVD_BITS_MASK       0x7ffff000
 279
 280 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
 281 #define VECTORING_INFO_TYPE_MASK                INTR_INFO_INTR_TYPE_MASK
 282 #define VECTORING_INFO_DELIVER_CODE_MASK        INTR_INFO_DELIVER_CODE_MASK
 283 #define VECTORING_INFO_VALID_MASK               INTR_INFO_VALID_MASK
 284
 285 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
 286 #define INTR_TYPE_NMI_INTR              (2 << 8) /* NMI */
 287 #define INTR_TYPE_HARD_EXCEPTION        (3 << 8) /* processor exception */
 288 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
 289 #define INTR_TYPE_SOFT_EXCEPTION        (6 << 8) /* software exception */
 290
 291 /* GUEST_INTERRUPTIBILITY_INFO flags. */
 292 #define GUEST_INTR_STATE_STI            0x00000001
 293 #define GUEST_INTR_STATE_MOV_SS         0x00000002
 294 #define GUEST_INTR_STATE_SMI            0x00000004
 295 #define GUEST_INTR_STATE_NMI            0x00000008
 296
 297 /*
 298  * Exit Qualifications for MOV for Control Register Access
 299  */
 300 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control reg.*/
 301 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
 302 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose reg. */
 303 #define LMSW_SOURCE_DATA_SHIFT 16
 304 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
 305 #define REG_EAX                         (0 << 8)
 306 #define REG_ECX                         (1 << 8)
 307 #define REG_EDX                         (2 << 8)
 308 #define REG_EBX                         (3 << 8)
 309 #define REG_ESP                         (4 << 8)
 310 #define REG_EBP                         (5 << 8)
 311 #define REG_ESI                         (6 << 8)
 312 #define REG_EDI                         (7 << 8)
 313 #define REG_R8                         (8 << 8)
 314 #define REG_R9                         (9 << 8)
 315 #define REG_R10                        (10 << 8)
 316 #define REG_R11                        (11 << 8)
 317 #define REG_R12                        (12 << 8)
 318 #define REG_R13                        (13 << 8)
 319 #define REG_R14                        (14 << 8)
 320 #define REG_R15                        (15 << 8)
 321
 322 /*
 323  * Exit Qualifications for MOV for Debug Register Access
 324  */
 325 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug reg. */
 326 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
 327 #define TYPE_MOV_TO_DR                  (0 << 4)
 328 #define TYPE_MOV_FROM_DR                (1 << 4)
 329 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
 330
 331
 332 /* segment AR */
 333 #define SEGMENT_AR_L_MASK (1 << 13)
 334
 335 #define AR_TYPE_ACCESSES_MASK 1
 336 #define AR_TYPE_READABLE_MASK (1 << 1)
 337 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
 338 #define AR_TYPE_CODE_MASK (1 << 3)
 339 #define AR_TYPE_MASK 0x0f
 340 #define AR_TYPE_BUSY_64_TSS 11
 341 #define AR_TYPE_BUSY_32_TSS 11
 342 #define AR_TYPE_BUSY_16_TSS 3
 343 #define AR_TYPE_LDT 2
 344
 345 #define AR_UNUSABLE_MASK (1 << 16)
 346 #define AR_S_MASK (1 << 4)
 347 #define AR_P_MASK (1 << 7)
 348 #define AR_L_MASK (1 << 13)
 349 #define AR_DB_MASK (1 << 14)
 350 #define AR_G_MASK (1 << 15)
 351 #define AR_DPL_SHIFT 5
 352 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
 353
 354 #define AR_RESERVD_MASK 0xfffe0f00
 355
 356 #define TSS_PRIVATE_MEMSLOT                     (KVM_MEMORY_SLOTS + 0)
 357 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT        (KVM_MEMORY_SLOTS + 1)
 358 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT      (KVM_MEMORY_SLOTS + 2)
 359
 360 #define VMX_NR_VPIDS                            (1 << 16)
 361 #define VMX_VPID_EXTENT_SINGLE_CONTEXT          1
 362 #define VMX_VPID_EXTENT_ALL_CONTEXT             2
 363
 364 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR          0
 365 #define VMX_EPT_EXTENT_CONTEXT                  1
 366 #define VMX_EPT_EXTENT_GLOBAL                   2
 367
 368 #define VMX_EPT_EXECUTE_ONLY_BIT                (1ull)
 369 #define VMX_EPT_PAGE_WALK_4_BIT                 (1ull << 6)
 370 #define VMX_EPTP_UC_BIT                         (1ull << 8)
 371 #define VMX_EPTP_WB_BIT                         (1ull << 14)
 372 #define VMX_EPT_2MB_PAGE_BIT                    (1ull << 16)
 373 #define VMX_EPT_1GB_PAGE_BIT                    (1ull << 17)
 374 #define VMX_EPT_EXTENT_INDIVIDUAL_BIT           (1ull << 24)
 375 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
 376 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
 377
 378 #define VMX_EPT_DEFAULT_GAW                     3
 379 #define VMX_EPT_MAX_GAW                         0x4
 380 #define VMX_EPT_MT_EPTE_SHIFT                   3
 381 #define VMX_EPT_GAW_EPTP_SHIFT                  3
 382 #define VMX_EPT_DEFAULT_MT                      0x6ull
 383 #define VMX_EPT_READABLE_MASK                   0x1ull
 384 #define VMX_EPT_WRITABLE_MASK                   0x2ull
 385 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
 386 #define VMX_EPT_IPAT_BIT                        (1ull << 6)
 387
 388 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
 389
 390
 391 #define ASM_VMX_VMCLEAR_RAX       ".byte 0x66, 0x0f, 0xc7, 0x30"
 392 #define ASM_VMX_VMLAUNCH          ".byte 0x0f, 0x01, 0xc2"
 393 #define ASM_VMX_VMRESUME          ".byte 0x0f, 0x01, 0xc3"
 394 #define ASM_VMX_VMPTRLD_RAX       ".byte 0x0f, 0xc7, 0x30"
 395 #define ASM_VMX_VMREAD_RDX_RAX    ".byte 0x0f, 0x78, 0xd0"
 396 #define ASM_VMX_VMWRITE_RAX_RDX   ".byte 0x0f, 0x79, 0xd0"
 397 #define ASM_VMX_VMWRITE_RSP_RDX   ".byte 0x0f, 0x79, 0xd4"
 398 #define ASM_VMX_VMXOFF            ".byte 0x0f, 0x01, 0xc4"
 399 #define ASM_VMX_VMXON_RAX         ".byte 0xf3, 0x0f, 0xc7, 0x30"
 400 #define ASM_VMX_INVEPT            ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
 401 #define ASM_VMX_INVVPID           ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
 402
 403 struct vmx_msr_entry {
 404         u32 index;
 405         u32 reserved;
 406         u64 value;
 407 } __aligned(16);
 408
 409 #endif