36cbe2a917939525471980b9db455ef481544125
[pandora-kernel.git] / arch / x86 / include / asm / vmx.h
1 #ifndef VMX_H
2 #define VMX_H
3
4 /*
5  * vmx.h: VMX Architecture related definitions
6  * Copyright (c) 2004, Intel Corporation.
7  *
8  * This program is free software; you can redistribute it and/or modify it
9  * under the terms and conditions of the GNU General Public License,
10  * version 2, as published by the Free Software Foundation.
11  *
12  * This program is distributed in the hope it will be useful, but WITHOUT
13  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
15  * more details.
16  *
17  * You should have received a copy of the GNU General Public License along with
18  * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
19  * Place - Suite 330, Boston, MA 02111-1307 USA.
20  *
21  * A few random additions are:
22  * Copyright (C) 2006 Qumranet
23  *    Avi Kivity <avi@qumranet.com>
24  *    Yaniv Kamay <yaniv@qumranet.com>
25  *
26  */
27
28 #include <linux/types.h>
29
30 /*
31  * Definitions of Primary Processor-Based VM-Execution Controls.
32  */
33 #define CPU_BASED_VIRTUAL_INTR_PENDING          0x00000004
34 #define CPU_BASED_USE_TSC_OFFSETING             0x00000008
35 #define CPU_BASED_HLT_EXITING                   0x00000080
36 #define CPU_BASED_INVLPG_EXITING                0x00000200
37 #define CPU_BASED_MWAIT_EXITING                 0x00000400
38 #define CPU_BASED_RDPMC_EXITING                 0x00000800
39 #define CPU_BASED_RDTSC_EXITING                 0x00001000
40 #define CPU_BASED_CR3_LOAD_EXITING              0x00008000
41 #define CPU_BASED_CR3_STORE_EXITING             0x00010000
42 #define CPU_BASED_CR8_LOAD_EXITING              0x00080000
43 #define CPU_BASED_CR8_STORE_EXITING             0x00100000
44 #define CPU_BASED_TPR_SHADOW                    0x00200000
45 #define CPU_BASED_VIRTUAL_NMI_PENDING           0x00400000
46 #define CPU_BASED_MOV_DR_EXITING                0x00800000
47 #define CPU_BASED_UNCOND_IO_EXITING             0x01000000
48 #define CPU_BASED_USE_IO_BITMAPS                0x02000000
49 #define CPU_BASED_USE_MSR_BITMAPS               0x10000000
50 #define CPU_BASED_MONITOR_EXITING               0x20000000
51 #define CPU_BASED_PAUSE_EXITING                 0x40000000
52 #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS   0x80000000
53 /*
54  * Definitions of Secondary Processor-Based VM-Execution Controls.
55  */
56 #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES 0x00000001
57 #define SECONDARY_EXEC_ENABLE_EPT               0x00000002
58 #define SECONDARY_EXEC_RDTSCP                   0x00000008
59 #define SECONDARY_EXEC_ENABLE_VPID              0x00000020
60 #define SECONDARY_EXEC_WBINVD_EXITING           0x00000040
61 #define SECONDARY_EXEC_UNRESTRICTED_GUEST       0x00000080
62 #define SECONDARY_EXEC_PAUSE_LOOP_EXITING       0x00000400
63
64
65 #define PIN_BASED_EXT_INTR_MASK                 0x00000001
66 #define PIN_BASED_NMI_EXITING                   0x00000008
67 #define PIN_BASED_VIRTUAL_NMIS                  0x00000020
68
69 #define VM_EXIT_SAVE_DEBUG_CONTROLS             0x00000002
70 #define VM_EXIT_HOST_ADDR_SPACE_SIZE            0x00000200
71 #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL      0x00001000
72 #define VM_EXIT_ACK_INTR_ON_EXIT                0x00008000
73 #define VM_EXIT_SAVE_IA32_PAT                   0x00040000
74 #define VM_EXIT_LOAD_IA32_PAT                   0x00080000
75 #define VM_EXIT_SAVE_IA32_EFER                  0x00100000
76 #define VM_EXIT_LOAD_IA32_EFER                  0x00200000
77 #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER       0x00400000
78
79 #define VM_ENTRY_LOAD_DEBUG_CONTROLS            0x00000002
80 #define VM_ENTRY_IA32E_MODE                     0x00000200
81 #define VM_ENTRY_SMM                            0x00000400
82 #define VM_ENTRY_DEACT_DUAL_MONITOR             0x00000800
83 #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL     0x00002000
84 #define VM_ENTRY_LOAD_IA32_PAT                  0x00004000
85 #define VM_ENTRY_LOAD_IA32_EFER                 0x00008000
86
87 /* VMCS Encodings */
88 enum vmcs_field {
89         VIRTUAL_PROCESSOR_ID            = 0x00000000,
90         GUEST_ES_SELECTOR               = 0x00000800,
91         GUEST_CS_SELECTOR               = 0x00000802,
92         GUEST_SS_SELECTOR               = 0x00000804,
93         GUEST_DS_SELECTOR               = 0x00000806,
94         GUEST_FS_SELECTOR               = 0x00000808,
95         GUEST_GS_SELECTOR               = 0x0000080a,
96         GUEST_LDTR_SELECTOR             = 0x0000080c,
97         GUEST_TR_SELECTOR               = 0x0000080e,
98         HOST_ES_SELECTOR                = 0x00000c00,
99         HOST_CS_SELECTOR                = 0x00000c02,
100         HOST_SS_SELECTOR                = 0x00000c04,
101         HOST_DS_SELECTOR                = 0x00000c06,
102         HOST_FS_SELECTOR                = 0x00000c08,
103         HOST_GS_SELECTOR                = 0x00000c0a,
104         HOST_TR_SELECTOR                = 0x00000c0c,
105         IO_BITMAP_A                     = 0x00002000,
106         IO_BITMAP_A_HIGH                = 0x00002001,
107         IO_BITMAP_B                     = 0x00002002,
108         IO_BITMAP_B_HIGH                = 0x00002003,
109         MSR_BITMAP                      = 0x00002004,
110         MSR_BITMAP_HIGH                 = 0x00002005,
111         VM_EXIT_MSR_STORE_ADDR          = 0x00002006,
112         VM_EXIT_MSR_STORE_ADDR_HIGH     = 0x00002007,
113         VM_EXIT_MSR_LOAD_ADDR           = 0x00002008,
114         VM_EXIT_MSR_LOAD_ADDR_HIGH      = 0x00002009,
115         VM_ENTRY_MSR_LOAD_ADDR          = 0x0000200a,
116         VM_ENTRY_MSR_LOAD_ADDR_HIGH     = 0x0000200b,
117         TSC_OFFSET                      = 0x00002010,
118         TSC_OFFSET_HIGH                 = 0x00002011,
119         VIRTUAL_APIC_PAGE_ADDR          = 0x00002012,
120         VIRTUAL_APIC_PAGE_ADDR_HIGH     = 0x00002013,
121         APIC_ACCESS_ADDR                = 0x00002014,
122         APIC_ACCESS_ADDR_HIGH           = 0x00002015,
123         EPT_POINTER                     = 0x0000201a,
124         EPT_POINTER_HIGH                = 0x0000201b,
125         GUEST_PHYSICAL_ADDRESS          = 0x00002400,
126         GUEST_PHYSICAL_ADDRESS_HIGH     = 0x00002401,
127         VMCS_LINK_POINTER               = 0x00002800,
128         VMCS_LINK_POINTER_HIGH          = 0x00002801,
129         GUEST_IA32_DEBUGCTL             = 0x00002802,
130         GUEST_IA32_DEBUGCTL_HIGH        = 0x00002803,
131         GUEST_IA32_PAT                  = 0x00002804,
132         GUEST_IA32_PAT_HIGH             = 0x00002805,
133         GUEST_IA32_EFER                 = 0x00002806,
134         GUEST_IA32_EFER_HIGH            = 0x00002807,
135         GUEST_IA32_PERF_GLOBAL_CTRL     = 0x00002808,
136         GUEST_IA32_PERF_GLOBAL_CTRL_HIGH= 0x00002809,
137         GUEST_PDPTR0                    = 0x0000280a,
138         GUEST_PDPTR0_HIGH               = 0x0000280b,
139         GUEST_PDPTR1                    = 0x0000280c,
140         GUEST_PDPTR1_HIGH               = 0x0000280d,
141         GUEST_PDPTR2                    = 0x0000280e,
142         GUEST_PDPTR2_HIGH               = 0x0000280f,
143         GUEST_PDPTR3                    = 0x00002810,
144         GUEST_PDPTR3_HIGH               = 0x00002811,
145         HOST_IA32_PAT                   = 0x00002c00,
146         HOST_IA32_PAT_HIGH              = 0x00002c01,
147         HOST_IA32_EFER                  = 0x00002c02,
148         HOST_IA32_EFER_HIGH             = 0x00002c03,
149         HOST_IA32_PERF_GLOBAL_CTRL      = 0x00002c04,
150         HOST_IA32_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
151         PIN_BASED_VM_EXEC_CONTROL       = 0x00004000,
152         CPU_BASED_VM_EXEC_CONTROL       = 0x00004002,
153         EXCEPTION_BITMAP                = 0x00004004,
154         PAGE_FAULT_ERROR_CODE_MASK      = 0x00004006,
155         PAGE_FAULT_ERROR_CODE_MATCH     = 0x00004008,
156         CR3_TARGET_COUNT                = 0x0000400a,
157         VM_EXIT_CONTROLS                = 0x0000400c,
158         VM_EXIT_MSR_STORE_COUNT         = 0x0000400e,
159         VM_EXIT_MSR_LOAD_COUNT          = 0x00004010,
160         VM_ENTRY_CONTROLS               = 0x00004012,
161         VM_ENTRY_MSR_LOAD_COUNT         = 0x00004014,
162         VM_ENTRY_INTR_INFO_FIELD        = 0x00004016,
163         VM_ENTRY_EXCEPTION_ERROR_CODE   = 0x00004018,
164         VM_ENTRY_INSTRUCTION_LEN        = 0x0000401a,
165         TPR_THRESHOLD                   = 0x0000401c,
166         SECONDARY_VM_EXEC_CONTROL       = 0x0000401e,
167         PLE_GAP                         = 0x00004020,
168         PLE_WINDOW                      = 0x00004022,
169         VM_INSTRUCTION_ERROR            = 0x00004400,
170         VM_EXIT_REASON                  = 0x00004402,
171         VM_EXIT_INTR_INFO               = 0x00004404,
172         VM_EXIT_INTR_ERROR_CODE         = 0x00004406,
173         IDT_VECTORING_INFO_FIELD        = 0x00004408,
174         IDT_VECTORING_ERROR_CODE        = 0x0000440a,
175         VM_EXIT_INSTRUCTION_LEN         = 0x0000440c,
176         VMX_INSTRUCTION_INFO            = 0x0000440e,
177         GUEST_ES_LIMIT                  = 0x00004800,
178         GUEST_CS_LIMIT                  = 0x00004802,
179         GUEST_SS_LIMIT                  = 0x00004804,
180         GUEST_DS_LIMIT                  = 0x00004806,
181         GUEST_FS_LIMIT                  = 0x00004808,
182         GUEST_GS_LIMIT                  = 0x0000480a,
183         GUEST_LDTR_LIMIT                = 0x0000480c,
184         GUEST_TR_LIMIT                  = 0x0000480e,
185         GUEST_GDTR_LIMIT                = 0x00004810,
186         GUEST_IDTR_LIMIT                = 0x00004812,
187         GUEST_ES_AR_BYTES               = 0x00004814,
188         GUEST_CS_AR_BYTES               = 0x00004816,
189         GUEST_SS_AR_BYTES               = 0x00004818,
190         GUEST_DS_AR_BYTES               = 0x0000481a,
191         GUEST_FS_AR_BYTES               = 0x0000481c,
192         GUEST_GS_AR_BYTES               = 0x0000481e,
193         GUEST_LDTR_AR_BYTES             = 0x00004820,
194         GUEST_TR_AR_BYTES               = 0x00004822,
195         GUEST_INTERRUPTIBILITY_INFO     = 0x00004824,
196         GUEST_ACTIVITY_STATE            = 0X00004826,
197         GUEST_SYSENTER_CS               = 0x0000482A,
198         HOST_IA32_SYSENTER_CS           = 0x00004c00,
199         CR0_GUEST_HOST_MASK             = 0x00006000,
200         CR4_GUEST_HOST_MASK             = 0x00006002,
201         CR0_READ_SHADOW                 = 0x00006004,
202         CR4_READ_SHADOW                 = 0x00006006,
203         CR3_TARGET_VALUE0               = 0x00006008,
204         CR3_TARGET_VALUE1               = 0x0000600a,
205         CR3_TARGET_VALUE2               = 0x0000600c,
206         CR3_TARGET_VALUE3               = 0x0000600e,
207         EXIT_QUALIFICATION              = 0x00006400,
208         GUEST_LINEAR_ADDRESS            = 0x0000640a,
209         GUEST_CR0                       = 0x00006800,
210         GUEST_CR3                       = 0x00006802,
211         GUEST_CR4                       = 0x00006804,
212         GUEST_ES_BASE                   = 0x00006806,
213         GUEST_CS_BASE                   = 0x00006808,
214         GUEST_SS_BASE                   = 0x0000680a,
215         GUEST_DS_BASE                   = 0x0000680c,
216         GUEST_FS_BASE                   = 0x0000680e,
217         GUEST_GS_BASE                   = 0x00006810,
218         GUEST_LDTR_BASE                 = 0x00006812,
219         GUEST_TR_BASE                   = 0x00006814,
220         GUEST_GDTR_BASE                 = 0x00006816,
221         GUEST_IDTR_BASE                 = 0x00006818,
222         GUEST_DR7                       = 0x0000681a,
223         GUEST_RSP                       = 0x0000681c,
224         GUEST_RIP                       = 0x0000681e,
225         GUEST_RFLAGS                    = 0x00006820,
226         GUEST_PENDING_DBG_EXCEPTIONS    = 0x00006822,
227         GUEST_SYSENTER_ESP              = 0x00006824,
228         GUEST_SYSENTER_EIP              = 0x00006826,
229         HOST_CR0                        = 0x00006c00,
230         HOST_CR3                        = 0x00006c02,
231         HOST_CR4                        = 0x00006c04,
232         HOST_FS_BASE                    = 0x00006c06,
233         HOST_GS_BASE                    = 0x00006c08,
234         HOST_TR_BASE                    = 0x00006c0a,
235         HOST_GDTR_BASE                  = 0x00006c0c,
236         HOST_IDTR_BASE                  = 0x00006c0e,
237         HOST_IA32_SYSENTER_ESP          = 0x00006c10,
238         HOST_IA32_SYSENTER_EIP          = 0x00006c12,
239         HOST_RSP                        = 0x00006c14,
240         HOST_RIP                        = 0x00006c16,
241 };
242
243 #define VMX_EXIT_REASONS_FAILED_VMENTRY         0x80000000
244
245 #define EXIT_REASON_EXCEPTION_NMI       0
246 #define EXIT_REASON_EXTERNAL_INTERRUPT  1
247 #define EXIT_REASON_TRIPLE_FAULT        2
248
249 #define EXIT_REASON_PENDING_INTERRUPT   7
250 #define EXIT_REASON_NMI_WINDOW          8
251 #define EXIT_REASON_TASK_SWITCH         9
252 #define EXIT_REASON_CPUID               10
253 #define EXIT_REASON_HLT                 12
254 #define EXIT_REASON_INVD                13
255 #define EXIT_REASON_INVLPG              14
256 #define EXIT_REASON_RDPMC               15
257 #define EXIT_REASON_RDTSC               16
258 #define EXIT_REASON_VMCALL              18
259 #define EXIT_REASON_VMCLEAR             19
260 #define EXIT_REASON_VMLAUNCH            20
261 #define EXIT_REASON_VMPTRLD             21
262 #define EXIT_REASON_VMPTRST             22
263 #define EXIT_REASON_VMREAD              23
264 #define EXIT_REASON_VMRESUME            24
265 #define EXIT_REASON_VMWRITE             25
266 #define EXIT_REASON_VMOFF               26
267 #define EXIT_REASON_VMON                27
268 #define EXIT_REASON_CR_ACCESS           28
269 #define EXIT_REASON_DR_ACCESS           29
270 #define EXIT_REASON_IO_INSTRUCTION      30
271 #define EXIT_REASON_MSR_READ            31
272 #define EXIT_REASON_MSR_WRITE           32
273 #define EXIT_REASON_INVALID_STATE       33
274 #define EXIT_REASON_MWAIT_INSTRUCTION   36
275 #define EXIT_REASON_MONITOR_INSTRUCTION 39
276 #define EXIT_REASON_PAUSE_INSTRUCTION   40
277 #define EXIT_REASON_MCE_DURING_VMENTRY   41
278 #define EXIT_REASON_TPR_BELOW_THRESHOLD 43
279 #define EXIT_REASON_APIC_ACCESS         44
280 #define EXIT_REASON_EPT_VIOLATION       48
281 #define EXIT_REASON_EPT_MISCONFIG       49
282 #define EXIT_REASON_INVEPT              50
283 #define EXIT_REASON_INVVPID             53
284 #define EXIT_REASON_WBINVD              54
285 #define EXIT_REASON_XSETBV              55
286
287 /*
288  * Interruption-information format
289  */
290 #define INTR_INFO_VECTOR_MASK           0xff            /* 7:0 */
291 #define INTR_INFO_INTR_TYPE_MASK        0x700           /* 10:8 */
292 #define INTR_INFO_DELIVER_CODE_MASK     0x800           /* 11 */
293 #define INTR_INFO_UNBLOCK_NMI           0x1000          /* 12 */
294 #define INTR_INFO_VALID_MASK            0x80000000      /* 31 */
295 #define INTR_INFO_RESVD_BITS_MASK       0x7ffff000
296
297 #define VECTORING_INFO_VECTOR_MASK              INTR_INFO_VECTOR_MASK
298 #define VECTORING_INFO_TYPE_MASK                INTR_INFO_INTR_TYPE_MASK
299 #define VECTORING_INFO_DELIVER_CODE_MASK        INTR_INFO_DELIVER_CODE_MASK
300 #define VECTORING_INFO_VALID_MASK               INTR_INFO_VALID_MASK
301
302 #define INTR_TYPE_EXT_INTR              (0 << 8) /* external interrupt */
303 #define INTR_TYPE_NMI_INTR              (2 << 8) /* NMI */
304 #define INTR_TYPE_HARD_EXCEPTION        (3 << 8) /* processor exception */
305 #define INTR_TYPE_SOFT_INTR             (4 << 8) /* software interrupt */
306 #define INTR_TYPE_SOFT_EXCEPTION        (6 << 8) /* software exception */
307
308 /* GUEST_INTERRUPTIBILITY_INFO flags. */
309 #define GUEST_INTR_STATE_STI            0x00000001
310 #define GUEST_INTR_STATE_MOV_SS         0x00000002
311 #define GUEST_INTR_STATE_SMI            0x00000004
312 #define GUEST_INTR_STATE_NMI            0x00000008
313
314 /* GUEST_ACTIVITY_STATE flags */
315 #define GUEST_ACTIVITY_ACTIVE           0
316 #define GUEST_ACTIVITY_HLT              1
317 #define GUEST_ACTIVITY_SHUTDOWN         2
318 #define GUEST_ACTIVITY_WAIT_SIPI        3
319
320 /*
321  * Exit Qualifications for MOV for Control Register Access
322  */
323 #define CONTROL_REG_ACCESS_NUM          0x7     /* 2:0, number of control reg.*/
324 #define CONTROL_REG_ACCESS_TYPE         0x30    /* 5:4, access type */
325 #define CONTROL_REG_ACCESS_REG          0xf00   /* 10:8, general purpose reg. */
326 #define LMSW_SOURCE_DATA_SHIFT 16
327 #define LMSW_SOURCE_DATA  (0xFFFF << LMSW_SOURCE_DATA_SHIFT) /* 16:31 lmsw source */
328 #define REG_EAX                         (0 << 8)
329 #define REG_ECX                         (1 << 8)
330 #define REG_EDX                         (2 << 8)
331 #define REG_EBX                         (3 << 8)
332 #define REG_ESP                         (4 << 8)
333 #define REG_EBP                         (5 << 8)
334 #define REG_ESI                         (6 << 8)
335 #define REG_EDI                         (7 << 8)
336 #define REG_R8                         (8 << 8)
337 #define REG_R9                         (9 << 8)
338 #define REG_R10                        (10 << 8)
339 #define REG_R11                        (11 << 8)
340 #define REG_R12                        (12 << 8)
341 #define REG_R13                        (13 << 8)
342 #define REG_R14                        (14 << 8)
343 #define REG_R15                        (15 << 8)
344
345 /*
346  * Exit Qualifications for MOV for Debug Register Access
347  */
348 #define DEBUG_REG_ACCESS_NUM            0x7     /* 2:0, number of debug reg. */
349 #define DEBUG_REG_ACCESS_TYPE           0x10    /* 4, direction of access */
350 #define TYPE_MOV_TO_DR                  (0 << 4)
351 #define TYPE_MOV_FROM_DR                (1 << 4)
352 #define DEBUG_REG_ACCESS_REG(eq)        (((eq) >> 8) & 0xf) /* 11:8, general purpose reg. */
353
354
355 /*
356  * Exit Qualifications for APIC-Access
357  */
358 #define APIC_ACCESS_OFFSET              0xfff   /* 11:0, offset within the APIC page */
359 #define APIC_ACCESS_TYPE                0xf000  /* 15:12, access type */
360 #define TYPE_LINEAR_APIC_INST_READ      (0 << 12)
361 #define TYPE_LINEAR_APIC_INST_WRITE     (1 << 12)
362 #define TYPE_LINEAR_APIC_INST_FETCH     (2 << 12)
363 #define TYPE_LINEAR_APIC_EVENT          (3 << 12)
364 #define TYPE_PHYSICAL_APIC_EVENT        (10 << 12)
365 #define TYPE_PHYSICAL_APIC_INST         (15 << 12)
366
367 /* segment AR */
368 #define SEGMENT_AR_L_MASK (1 << 13)
369
370 #define AR_TYPE_ACCESSES_MASK 1
371 #define AR_TYPE_READABLE_MASK (1 << 1)
372 #define AR_TYPE_WRITEABLE_MASK (1 << 2)
373 #define AR_TYPE_CODE_MASK (1 << 3)
374 #define AR_TYPE_MASK 0x0f
375 #define AR_TYPE_BUSY_64_TSS 11
376 #define AR_TYPE_BUSY_32_TSS 11
377 #define AR_TYPE_BUSY_16_TSS 3
378 #define AR_TYPE_LDT 2
379
380 #define AR_UNUSABLE_MASK (1 << 16)
381 #define AR_S_MASK (1 << 4)
382 #define AR_P_MASK (1 << 7)
383 #define AR_L_MASK (1 << 13)
384 #define AR_DB_MASK (1 << 14)
385 #define AR_G_MASK (1 << 15)
386 #define AR_DPL_SHIFT 5
387 #define AR_DPL(ar) (((ar) >> AR_DPL_SHIFT) & 3)
388
389 #define AR_RESERVD_MASK 0xfffe0f00
390
391 #define TSS_PRIVATE_MEMSLOT                     (KVM_MEMORY_SLOTS + 0)
392 #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT        (KVM_MEMORY_SLOTS + 1)
393 #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT      (KVM_MEMORY_SLOTS + 2)
394
395 #define VMX_NR_VPIDS                            (1 << 16)
396 #define VMX_VPID_EXTENT_SINGLE_CONTEXT          1
397 #define VMX_VPID_EXTENT_ALL_CONTEXT             2
398
399 #define VMX_EPT_EXTENT_INDIVIDUAL_ADDR          0
400 #define VMX_EPT_EXTENT_CONTEXT                  1
401 #define VMX_EPT_EXTENT_GLOBAL                   2
402
403 #define VMX_EPT_EXECUTE_ONLY_BIT                (1ull)
404 #define VMX_EPT_PAGE_WALK_4_BIT                 (1ull << 6)
405 #define VMX_EPTP_UC_BIT                         (1ull << 8)
406 #define VMX_EPTP_WB_BIT                         (1ull << 14)
407 #define VMX_EPT_2MB_PAGE_BIT                    (1ull << 16)
408 #define VMX_EPT_1GB_PAGE_BIT                    (1ull << 17)
409 #define VMX_EPT_EXTENT_INDIVIDUAL_BIT           (1ull << 24)
410 #define VMX_EPT_EXTENT_CONTEXT_BIT              (1ull << 25)
411 #define VMX_EPT_EXTENT_GLOBAL_BIT               (1ull << 26)
412
413 #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT      (1ull << 9) /* (41 - 32) */
414 #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT      (1ull << 10) /* (42 - 32) */
415
416 #define VMX_EPT_DEFAULT_GAW                     3
417 #define VMX_EPT_MAX_GAW                         0x4
418 #define VMX_EPT_MT_EPTE_SHIFT                   3
419 #define VMX_EPT_GAW_EPTP_SHIFT                  3
420 #define VMX_EPT_DEFAULT_MT                      0x6ull
421 #define VMX_EPT_READABLE_MASK                   0x1ull
422 #define VMX_EPT_WRITABLE_MASK                   0x2ull
423 #define VMX_EPT_EXECUTABLE_MASK                 0x4ull
424 #define VMX_EPT_IPAT_BIT                        (1ull << 6)
425
426 #define VMX_EPT_IDENTITY_PAGETABLE_ADDR         0xfffbc000ul
427
428
429 #define ASM_VMX_VMCLEAR_RAX       ".byte 0x66, 0x0f, 0xc7, 0x30"
430 #define ASM_VMX_VMLAUNCH          ".byte 0x0f, 0x01, 0xc2"
431 #define ASM_VMX_VMRESUME          ".byte 0x0f, 0x01, 0xc3"
432 #define ASM_VMX_VMPTRLD_RAX       ".byte 0x0f, 0xc7, 0x30"
433 #define ASM_VMX_VMREAD_RDX_RAX    ".byte 0x0f, 0x78, 0xd0"
434 #define ASM_VMX_VMWRITE_RAX_RDX   ".byte 0x0f, 0x79, 0xd0"
435 #define ASM_VMX_VMWRITE_RSP_RDX   ".byte 0x0f, 0x79, 0xd4"
436 #define ASM_VMX_VMXOFF            ".byte 0x0f, 0x01, 0xc4"
437 #define ASM_VMX_VMXON_RAX         ".byte 0xf3, 0x0f, 0xc7, 0x30"
438 #define ASM_VMX_INVEPT            ".byte 0x66, 0x0f, 0x38, 0x80, 0x08"
439 #define ASM_VMX_INVVPID           ".byte 0x66, 0x0f, 0x38, 0x81, 0x08"
440
441 struct vmx_msr_entry {
442         u32 index;
443         u32 reserved;
444         u64 value;
445 } __aligned(16);
446
447 /*
448  * Exit Qualifications for entry failure during or after loading guest state
449  */
450 #define ENTRY_FAIL_DEFAULT              0
451 #define ENTRY_FAIL_PDPTE                2
452 #define ENTRY_FAIL_NMI                  3
453 #define ENTRY_FAIL_VMCS_LINK_PTR        4
454
455 /*
456  * VM-instruction error numbers
457  */
458 enum vm_instruction_error_number {
459         VMXERR_VMCALL_IN_VMX_ROOT_OPERATION = 1,
460         VMXERR_VMCLEAR_INVALID_ADDRESS = 2,
461         VMXERR_VMCLEAR_VMXON_POINTER = 3,
462         VMXERR_VMLAUNCH_NONCLEAR_VMCS = 4,
463         VMXERR_VMRESUME_NONLAUNCHED_VMCS = 5,
464         VMXERR_VMRESUME_AFTER_VMXOFF = 6,
465         VMXERR_ENTRY_INVALID_CONTROL_FIELD = 7,
466         VMXERR_ENTRY_INVALID_HOST_STATE_FIELD = 8,
467         VMXERR_VMPTRLD_INVALID_ADDRESS = 9,
468         VMXERR_VMPTRLD_VMXON_POINTER = 10,
469         VMXERR_VMPTRLD_INCORRECT_VMCS_REVISION_ID = 11,
470         VMXERR_UNSUPPORTED_VMCS_COMPONENT = 12,
471         VMXERR_VMWRITE_READ_ONLY_VMCS_COMPONENT = 13,
472         VMXERR_VMXON_IN_VMX_ROOT_OPERATION = 15,
473         VMXERR_ENTRY_INVALID_EXECUTIVE_VMCS_POINTER = 16,
474         VMXERR_ENTRY_NONLAUNCHED_EXECUTIVE_VMCS = 17,
475         VMXERR_ENTRY_EXECUTIVE_VMCS_POINTER_NOT_VMXON_POINTER = 18,
476         VMXERR_VMCALL_NONCLEAR_VMCS = 19,
477         VMXERR_VMCALL_INVALID_VM_EXIT_CONTROL_FIELDS = 20,
478         VMXERR_VMCALL_INCORRECT_MSEG_REVISION_ID = 22,
479         VMXERR_VMXOFF_UNDER_DUAL_MONITOR_TREATMENT_OF_SMIS_AND_SMM = 23,
480         VMXERR_VMCALL_INVALID_SMM_MONITOR_FEATURES = 24,
481         VMXERR_ENTRY_INVALID_VM_EXECUTION_CONTROL_FIELDS_IN_EXECUTIVE_VMCS = 25,
482         VMXERR_ENTRY_EVENTS_BLOCKED_BY_MOV_SS = 26,
483         VMXERR_INVALID_OPERAND_TO_INVEPT_INVVPID = 28,
484 };
485
486 #endif