arch/x86/include/asm/perf_event.h

   1 #ifndef _ASM_X86_PERF_EVENT_H
   2 #define _ASM_X86_PERF_EVENT_H
   3
   4 /*
   5  * Performance event hw details:
   6  */
   7
   8 #define X86_PMC_MAX_GENERIC                                    32
   9 #define X86_PMC_MAX_FIXED                                       3
  10
  11 #define X86_PMC_IDX_GENERIC                                     0
  12 #define X86_PMC_IDX_FIXED                                      32
  13 #define X86_PMC_IDX_MAX                                        64
  14
  15 #define MSR_ARCH_PERFMON_PERFCTR0                             0xc1
  16 #define MSR_ARCH_PERFMON_PERFCTR1                             0xc2
  17
  18 #define MSR_ARCH_PERFMON_EVENTSEL0                           0x186
  19 #define MSR_ARCH_PERFMON_EVENTSEL1                           0x187
  20
  21 #define ARCH_PERFMON_EVENTSEL_EVENT                     0x000000FFULL
  22 #define ARCH_PERFMON_EVENTSEL_UMASK                     0x0000FF00ULL
  23 #define ARCH_PERFMON_EVENTSEL_USR                       (1ULL << 16)
  24 #define ARCH_PERFMON_EVENTSEL_OS                        (1ULL << 17)
  25 #define ARCH_PERFMON_EVENTSEL_EDGE                      (1ULL << 18)
  26 #define ARCH_PERFMON_EVENTSEL_INT                       (1ULL << 20)
  27 #define ARCH_PERFMON_EVENTSEL_ANY                       (1ULL << 21)
  28 #define ARCH_PERFMON_EVENTSEL_ENABLE                    (1ULL << 22)
  29 #define ARCH_PERFMON_EVENTSEL_INV                       (1ULL << 23)
  30 #define ARCH_PERFMON_EVENTSEL_CMASK                     0xFF000000ULL
  31
  32 #define AMD64_EVENTSEL_EVENT    \
  33         (ARCH_PERFMON_EVENTSEL_EVENT | (0x0FULL << 32))
  34 #define INTEL_ARCH_EVENT_MASK   \
  35         (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
  36
  37 #define X86_RAW_EVENT_MASK              \
  38         (ARCH_PERFMON_EVENTSEL_EVENT |  \
  39          ARCH_PERFMON_EVENTSEL_UMASK |  \
  40          ARCH_PERFMON_EVENTSEL_EDGE  |  \
  41          ARCH_PERFMON_EVENTSEL_INV   |  \
  42          ARCH_PERFMON_EVENTSEL_CMASK)
  43 #define AMD64_RAW_EVENT_MASK            \
  44         (X86_RAW_EVENT_MASK          |  \
  45          AMD64_EVENTSEL_EVENT)
  46
  47 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_SEL                 0x3c
  48 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_UMASK         (0x00 << 8)
  49 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX                  0
  50 #define ARCH_PERFMON_UNHALTED_CORE_CYCLES_PRESENT \
  51                 (1 << (ARCH_PERFMON_UNHALTED_CORE_CYCLES_INDEX))
  52
  53 #define ARCH_PERFMON_BRANCH_MISSES_RETIRED                       6
  54
  55 /*
  56  * Intel "Architectural Performance Monitoring" CPUID
  57  * detection/enumeration details:
  58  */
  59 union cpuid10_eax {
  60         struct {
  61                 unsigned int version_id:8;
  62                 unsigned int num_counters:8;
  63                 unsigned int bit_width:8;
  64                 unsigned int mask_length:8;
  65         } split;
  66         unsigned int full;
  67 };
  68
  69 union cpuid10_edx {
  70         struct {
  71                 unsigned int num_counters_fixed:4;
  72                 unsigned int reserved:28;
  73         } split;
  74         unsigned int full;
  75 };
  76
  77
  78 /*
  79  * Fixed-purpose performance events:
  80  */
  81
  82 /*
  83  * All 3 fixed-mode PMCs are configured via this single MSR:
  84  */
  85 #define MSR_ARCH_PERFMON_FIXED_CTR_CTRL                 0x38d
  86
  87 /*
  88  * The counts are available in three separate MSRs:
  89  */
  90
  91 /* Instr_Retired.Any: */
  92 #define MSR_ARCH_PERFMON_FIXED_CTR0                     0x309
  93 #define X86_PMC_IDX_FIXED_INSTRUCTIONS                  (X86_PMC_IDX_FIXED + 0)
  94
  95 /* CPU_CLK_Unhalted.Core: */
  96 #define MSR_ARCH_PERFMON_FIXED_CTR1                     0x30a
  97 #define X86_PMC_IDX_FIXED_CPU_CYCLES                    (X86_PMC_IDX_FIXED + 1)
  98
  99 /* CPU_CLK_Unhalted.Ref: */
 100 #define MSR_ARCH_PERFMON_FIXED_CTR2                     0x30b
 101 #define X86_PMC_IDX_FIXED_BUS_CYCLES                    (X86_PMC_IDX_FIXED + 2)
 102
 103 /*
 104  * We model BTS tracing as another fixed-mode PMC.
 105  *
 106  * We choose a value in the middle of the fixed event range, since lower
 107  * values are used by actual fixed events and higher values are used
 108  * to indicate other overflow conditions in the PERF_GLOBAL_STATUS msr.
 109  */
 110 #define X86_PMC_IDX_FIXED_BTS                           (X86_PMC_IDX_FIXED + 16)
 111
 112 /* IbsFetchCtl bits/masks */
 113 #define IBS_FETCH_RAND_EN               (1ULL<<57)
 114 #define IBS_FETCH_VAL                   (1ULL<<49)
 115 #define IBS_FETCH_ENABLE                (1ULL<<48)
 116 #define IBS_FETCH_CNT                   0xFFFF0000ULL
 117 #define IBS_FETCH_MAX_CNT               0x0000FFFFULL
 118
 119 /* IbsOpCtl bits */
 120 #define IBS_OP_CNT_CTL                  (1ULL<<19)
 121 #define IBS_OP_VAL                      (1ULL<<18)
 122 #define IBS_OP_ENABLE                   (1ULL<<17)
 123 #define IBS_OP_MAX_CNT                  0x0000FFFFULL
 124
 125 #ifdef CONFIG_PERF_EVENTS
 126 extern void init_hw_perf_events(void);
 127 extern void perf_events_lapic_init(void);
 128
 129 #define PERF_EVENT_INDEX_OFFSET                 0
 130
 131 /*
 132  * Abuse bit 3 of the cpu eflags register to indicate proper PEBS IP fixups.
 133  * This flag is otherwise unused and ABI specified to be 0, so nobody should
 134  * care what we do with it.
 135  */
 136 #define PERF_EFLAGS_EXACT       (1UL << 3)
 137
 138 struct pt_regs;
 139 extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
 140 extern unsigned long perf_misc_flags(struct pt_regs *regs);
 141 #define perf_misc_flags(regs)   perf_misc_flags(regs)
 142
 143 #else
 144 static inline void init_hw_perf_events(void)            { }
 145 static inline void perf_events_lapic_init(void) { }
 146 #endif
 147
 148 #endif /* _ASM_X86_PERF_EVENT_H */