2 * Copyright (C) 2007-2009 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
21 #define _ASM_X86_AMD_IOMMU_TYPES_H
23 #include <linux/types.h>
24 #include <linux/list.h>
25 #include <linux/spinlock.h>
28 * Maximum number of IOMMUs supported
33 * some size calculation constants
35 #define DEV_TABLE_ENTRY_SIZE 32
36 #define ALIAS_TABLE_ENTRY_SIZE 2
37 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *))
39 /* Length of the MMIO region for the AMD IOMMU */
40 #define MMIO_REGION_LENGTH 0x4000
42 /* Capability offsets used by the driver */
43 #define MMIO_CAP_HDR_OFFSET 0x00
44 #define MMIO_RANGE_OFFSET 0x0c
45 #define MMIO_MISC_OFFSET 0x10
47 /* Masks, shifts and macros to parse the device range capability */
48 #define MMIO_RANGE_LD_MASK 0xff000000
49 #define MMIO_RANGE_FD_MASK 0x00ff0000
50 #define MMIO_RANGE_BUS_MASK 0x0000ff00
51 #define MMIO_RANGE_LD_SHIFT 24
52 #define MMIO_RANGE_FD_SHIFT 16
53 #define MMIO_RANGE_BUS_SHIFT 8
54 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
55 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
56 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
57 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
59 /* Flag masks for the AMD IOMMU exclusion range */
60 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
61 #define MMIO_EXCL_ALLOW_MASK 0x02ULL
63 /* Used offsets into the MMIO space */
64 #define MMIO_DEV_TABLE_OFFSET 0x0000
65 #define MMIO_CMD_BUF_OFFSET 0x0008
66 #define MMIO_EVT_BUF_OFFSET 0x0010
67 #define MMIO_CONTROL_OFFSET 0x0018
68 #define MMIO_EXCL_BASE_OFFSET 0x0020
69 #define MMIO_EXCL_LIMIT_OFFSET 0x0028
70 #define MMIO_CMD_HEAD_OFFSET 0x2000
71 #define MMIO_CMD_TAIL_OFFSET 0x2008
72 #define MMIO_EVT_HEAD_OFFSET 0x2010
73 #define MMIO_EVT_TAIL_OFFSET 0x2018
74 #define MMIO_STATUS_OFFSET 0x2020
76 /* MMIO status bits */
77 #define MMIO_STATUS_COM_WAIT_INT_MASK 0x04
79 /* event logging constants */
80 #define EVENT_ENTRY_SIZE 0x10
81 #define EVENT_TYPE_SHIFT 28
82 #define EVENT_TYPE_MASK 0xf
83 #define EVENT_TYPE_ILL_DEV 0x1
84 #define EVENT_TYPE_IO_FAULT 0x2
85 #define EVENT_TYPE_DEV_TAB_ERR 0x3
86 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
87 #define EVENT_TYPE_ILL_CMD 0x5
88 #define EVENT_TYPE_CMD_HARD_ERR 0x6
89 #define EVENT_TYPE_IOTLB_INV_TO 0x7
90 #define EVENT_TYPE_INV_DEV_REQ 0x8
91 #define EVENT_DEVID_MASK 0xffff
92 #define EVENT_DEVID_SHIFT 0
93 #define EVENT_DOMID_MASK 0xffff
94 #define EVENT_DOMID_SHIFT 0
95 #define EVENT_FLAGS_MASK 0xfff
96 #define EVENT_FLAGS_SHIFT 0x10
98 /* feature control bits */
99 #define CONTROL_IOMMU_EN 0x00ULL
100 #define CONTROL_HT_TUN_EN 0x01ULL
101 #define CONTROL_EVT_LOG_EN 0x02ULL
102 #define CONTROL_EVT_INT_EN 0x03ULL
103 #define CONTROL_COMWAIT_EN 0x04ULL
104 #define CONTROL_PASSPW_EN 0x08ULL
105 #define CONTROL_RESPASSPW_EN 0x09ULL
106 #define CONTROL_COHERENT_EN 0x0aULL
107 #define CONTROL_ISOC_EN 0x0bULL
108 #define CONTROL_CMDBUF_EN 0x0cULL
109 #define CONTROL_PPFLOG_EN 0x0dULL
110 #define CONTROL_PPFINT_EN 0x0eULL
112 /* command specific defines */
113 #define CMD_COMPL_WAIT 0x01
114 #define CMD_INV_DEV_ENTRY 0x02
115 #define CMD_INV_IOMMU_PAGES 0x03
117 #define CMD_COMPL_WAIT_STORE_MASK 0x01
118 #define CMD_COMPL_WAIT_INT_MASK 0x02
119 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01
120 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02
122 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
124 /* macros and definitions for device table entries */
125 #define DEV_ENTRY_VALID 0x00
126 #define DEV_ENTRY_TRANSLATION 0x01
127 #define DEV_ENTRY_IR 0x3d
128 #define DEV_ENTRY_IW 0x3e
129 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
130 #define DEV_ENTRY_EX 0x67
131 #define DEV_ENTRY_SYSMGT1 0x68
132 #define DEV_ENTRY_SYSMGT2 0x69
133 #define DEV_ENTRY_INIT_PASS 0xb8
134 #define DEV_ENTRY_EINT_PASS 0xb9
135 #define DEV_ENTRY_NMI_PASS 0xba
136 #define DEV_ENTRY_LINT0_PASS 0xbe
137 #define DEV_ENTRY_LINT1_PASS 0xbf
138 #define DEV_ENTRY_MODE_MASK 0x07
139 #define DEV_ENTRY_MODE_SHIFT 0x09
141 /* constants to configure the command buffer */
142 #define CMD_BUFFER_SIZE 8192
143 #define CMD_BUFFER_ENTRIES 512
144 #define MMIO_CMD_SIZE_SHIFT 56
145 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
147 /* constants for event buffer handling */
148 #define EVT_BUFFER_SIZE 8192 /* 512 entries */
149 #define EVT_LEN_MASK (0x9ULL << 56)
151 #define PAGE_MODE_NONE 0x00
152 #define PAGE_MODE_1_LEVEL 0x01
153 #define PAGE_MODE_2_LEVEL 0x02
154 #define PAGE_MODE_3_LEVEL 0x03
155 #define PAGE_MODE_4_LEVEL 0x04
156 #define PAGE_MODE_5_LEVEL 0x05
157 #define PAGE_MODE_6_LEVEL 0x06
159 #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9))
160 #define PM_LEVEL_SIZE(x) (((x) < 6) ? \
161 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
162 (0xffffffffffffffffULL))
163 #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
164 #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL)
165 #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \
166 IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
167 #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL)
170 #define PM_ADDR_MASK 0x000ffffffffff000ULL
171 #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \
172 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
173 #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr))
176 * Returns the page table level to use for a given page size
177 * Pagesize is expected to be a power-of-two
179 #define PAGE_SIZE_LEVEL(pagesize) \
180 ((__ffs(pagesize) - 12) / 9)
182 * Returns the number of ptes to use for a given page size
183 * Pagesize is expected to be a power-of-two
185 #define PAGE_SIZE_PTE_COUNT(pagesize) \
186 (1ULL << ((__ffs(pagesize) - 12) % 9))
189 * Aligns a given io-virtual address to a given page size
190 * Pagesize is expected to be a power-of-two
192 #define PAGE_SIZE_ALIGN(address, pagesize) \
193 ((address) & ~((pagesize) - 1))
195 * Creates an IOMMU PTE for an address an a given pagesize
196 * The PTE has no permission bits set
197 * Pagesize is expected to be a power-of-two larger than 4096
199 #define PAGE_SIZE_PTE(address, pagesize) \
200 (((address) | ((pagesize) - 1)) & \
201 (~(pagesize >> 1)) & PM_ADDR_MASK)
204 * Takes a PTE value with mode=0x07 and returns the page size it maps
206 #define PTE_PAGE_SIZE(pte) \
207 (1ULL << (1 + ffz(((pte) | 0xfffULL))))
209 #define IOMMU_PTE_P (1ULL << 0)
210 #define IOMMU_PTE_TV (1ULL << 1)
211 #define IOMMU_PTE_U (1ULL << 59)
212 #define IOMMU_PTE_FC (1ULL << 60)
213 #define IOMMU_PTE_IR (1ULL << 61)
214 #define IOMMU_PTE_IW (1ULL << 62)
216 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
217 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
218 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
219 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
221 #define IOMMU_PROT_MASK 0x03
222 #define IOMMU_PROT_IR 0x01
223 #define IOMMU_PROT_IW 0x02
225 /* IOMMU capabilities */
226 #define IOMMU_CAP_IOTLB 24
227 #define IOMMU_CAP_NPCACHE 26
229 #define MAX_DOMAIN_ID 65536
231 /* FIXME: move this macro to <linux/pci.h> */
232 #define PCI_BUS(x) (((x) >> 8) & 0xff)
234 /* Protection domain flags */
235 #define PD_DMA_OPS_MASK (1UL << 0) /* domain used for dma_ops */
236 #define PD_DEFAULT_MASK (1UL << 1) /* domain is a default dma_ops
237 domain for an IOMMU */
238 #define PD_PASSTHROUGH_MASK (1UL << 2) /* domain has no page
241 extern bool amd_iommu_dump;
242 #define DUMP_printk(format, arg...) \
244 if (amd_iommu_dump) \
245 printk(KERN_INFO "AMD-Vi: " format, ## arg); \
248 /* global flag if IOMMUs cache non-present entries */
249 extern bool amd_iommu_np_cache;
252 * Make iterating over all IOMMUs easier
254 #define for_each_iommu(iommu) \
255 list_for_each_entry((iommu), &amd_iommu_list, list)
256 #define for_each_iommu_safe(iommu, next) \
257 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
259 #define APERTURE_RANGE_SHIFT 27 /* 128 MB */
260 #define APERTURE_RANGE_SIZE (1ULL << APERTURE_RANGE_SHIFT)
261 #define APERTURE_RANGE_PAGES (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
262 #define APERTURE_MAX_RANGES 32 /* allows 4GB of DMA address space */
263 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
264 #define APERTURE_PAGE_INDEX(a) (((a) >> 21) & 0x3fULL)
267 * This structure contains generic data for IOMMU protection domains
268 * independent of their use.
270 struct protection_domain {
271 struct list_head list; /* for list of all protection domains */
272 struct list_head dev_list; /* List of all devices in this domain */
273 spinlock_t lock; /* mostly used to lock the page table*/
274 u16 id; /* the domain id written to the device table */
275 int mode; /* paging mode (0-6 levels) */
276 u64 *pt_root; /* page table root pointer */
277 unsigned long flags; /* flags to find out type of domain */
278 bool updated; /* complete domain flush required */
279 unsigned dev_cnt; /* devices assigned to this domain */
280 unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
281 void *priv; /* private data */
286 * This struct contains device specific data for the IOMMU
288 struct iommu_dev_data {
289 struct list_head list; /* For domain->dev_list */
290 struct device *dev; /* Device this data belong to */
291 struct device *alias; /* The Alias Device */
292 struct protection_domain *domain; /* Domain the device is bound to */
293 atomic_t bind; /* Domain attach reverent count */
297 * For dynamic growth the aperture size is split into ranges of 128MB of
298 * DMA address space each. This struct represents one such range.
300 struct aperture_range {
302 /* address allocation bitmap */
303 unsigned long *bitmap;
306 * Array of PTE pages for the aperture. In this array we save all the
307 * leaf pages of the domain page table used for the aperture. This way
308 * we don't need to walk the page table to find a specific PTE. We can
309 * just calculate its address in constant time.
313 unsigned long offset;
317 * Data container for a dma_ops specific protection domain
319 struct dma_ops_domain {
320 struct list_head list;
322 /* generic protection domain information */
323 struct protection_domain domain;
325 /* size of the aperture for the mappings */
326 unsigned long aperture_size;
328 /* address we start to search for free addresses */
329 unsigned long next_address;
331 /* address space relevant data */
332 struct aperture_range *aperture[APERTURE_MAX_RANGES];
334 /* This will be set to true when TLB needs to be flushed */
338 * if this is a preallocated domain, keep the device for which it was
339 * preallocated in this variable
345 * Structure where we save information about one hardware AMD IOMMU in the
349 struct list_head list;
351 /* Index within the IOMMU array */
354 /* locks the accesses to the hardware */
357 /* Pointer to PCI device of this IOMMU */
360 /* physical address of MMIO space */
362 /* virtual address of MMIO space */
365 /* capabilities of that IOMMU read from ACPI */
369 * Capability pointer. There could be more than one IOMMU per PCI
370 * device function if there are more than one AMD IOMMU capability
375 /* pci domain of this IOMMU */
378 /* first device this IOMMU handles. read from PCI */
380 /* last device this IOMMU handles. read from PCI */
383 /* start of exclusion range of that IOMMU */
385 /* length of exclusion range of that IOMMU */
386 u64 exclusion_length;
388 /* command buffer virtual address */
390 /* size of command buffer */
393 /* size of event buffer */
395 /* event buffer virtual address */
397 /* MSI number for event interrupt */
400 /* true if interrupts for this IOMMU are already enabled */
403 /* if one, we need to send a completion wait command */
406 /* becomes true if a command buffer reset is running */
407 bool reset_in_progress;
409 /* default dma_ops domain for that IOMMU */
410 struct dma_ops_domain *default_dom;
414 * List with all IOMMUs in the system. This list is not locked because it is
415 * only written and read at driver initialization or suspend time
417 extern struct list_head amd_iommu_list;
420 * Array with pointers to each IOMMU struct
421 * The indices are referenced in the protection domains
423 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
425 /* Number of IOMMUs present in the system */
426 extern int amd_iommus_present;
429 * Declarations for the global list of all protection domains
431 extern spinlock_t amd_iommu_pd_lock;
432 extern struct list_head amd_iommu_pd_list;
435 * Structure defining one entry in the device table
437 struct dev_table_entry {
442 * One entry for unity mappings parsed out of the ACPI table.
444 struct unity_map_entry {
445 struct list_head list;
447 /* starting device id this entry is used for (including) */
449 /* end device id this entry is used for (including) */
452 /* start address to unity map (including) */
454 /* end address to unity map (including) */
457 /* required protection */
462 * List of all unity mappings. It is not locked because as runtime it is only
463 * read. It is created at ACPI table parsing time.
465 extern struct list_head amd_iommu_unity_map;
468 * Data structures for device handling
472 * Device table used by hardware. Read and write accesses by software are
473 * locked with the amd_iommu_pd_table lock.
475 extern struct dev_table_entry *amd_iommu_dev_table;
478 * Alias table to find requestor ids to device ids. Not locked because only
481 extern u16 *amd_iommu_alias_table;
484 * Reverse lookup table to find the IOMMU which translates a specific device.
486 extern struct amd_iommu **amd_iommu_rlookup_table;
488 /* size of the dma_ops aperture as power of 2 */
489 extern unsigned amd_iommu_aperture_order;
491 /* largest PCI device id we expect translation requests for */
492 extern u16 amd_iommu_last_bdf;
494 /* allocation bitmap for domain ids */
495 extern unsigned long *amd_iommu_pd_alloc_bitmap;
498 * If true, the addresses will be flushed on unmap time, not when
501 extern bool amd_iommu_unmap_flush;
503 /* takes bus and device/function and returns the device id
504 * FIXME: should that be in generic PCI code? */
505 static inline u16 calc_devid(u8 bus, u8 devfn)
507 return (((u16)bus) << 8) | devfn;
510 #ifdef CONFIG_AMD_IOMMU_STATS
512 struct __iommu_counter {
518 #define DECLARE_STATS_COUNTER(nm) \
519 static struct __iommu_counter nm = { \
523 #define INC_STATS_COUNTER(name) name.value += 1
524 #define ADD_STATS_COUNTER(name, x) name.value += (x)
525 #define SUB_STATS_COUNTER(name, x) name.value -= (x)
527 #else /* CONFIG_AMD_IOMMU_STATS */
529 #define DECLARE_STATS_COUNTER(name)
530 #define INC_STATS_COUNTER(name)
531 #define ADD_STATS_COUNTER(name, x)
532 #define SUB_STATS_COUNTER(name, x)
534 #endif /* CONFIG_AMD_IOMMU_STATS */
536 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */