arch/sparc64/kernel/smp.c

   1 /* smp.c: Sparc64 SMP support.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  */
   5
   6 #include <linux/module.h>
   7 #include <linux/kernel.h>
   8 #include <linux/sched.h>
   9 #include <linux/mm.h>
  10 #include <linux/pagemap.h>
  11 #include <linux/threads.h>
  12 #include <linux/smp.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel_stat.h>
  15 #include <linux/delay.h>
  16 #include <linux/init.h>
  17 #include <linux/spinlock.h>
  18 #include <linux/fs.h>
  19 #include <linux/seq_file.h>
  20 #include <linux/cache.h>
  21 #include <linux/jiffies.h>
  22 #include <linux/profile.h>
  23 #include <linux/lmb.h>
  24
  25 #include <asm/head.h>
  26 #include <asm/ptrace.h>
  27 #include <asm/atomic.h>
  28 #include <asm/tlbflush.h>
  29 #include <asm/mmu_context.h>
  30 #include <asm/cpudata.h>
  31 #include <asm/hvtramp.h>
  32 #include <asm/io.h>
  33 #include <asm/timer.h>
  34
  35 #include <asm/irq.h>
  36 #include <asm/irq_regs.h>
  37 #include <asm/page.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/oplib.h>
  40 #include <asm/uaccess.h>
  41 #include <asm/starfire.h>
  42 #include <asm/tlb.h>
  43 #include <asm/sections.h>
  44 #include <asm/prom.h>
  45 #include <asm/mdesc.h>
  46 #include <asm/ldc.h>
  47 #include <asm/hypervisor.h>
  48
  49 int sparc64_multi_core __read_mostly;
  50
  51 cpumask_t cpu_possible_map __read_mostly = CPU_MASK_NONE;
  52 cpumask_t cpu_online_map __read_mostly = CPU_MASK_NONE;
  53 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
  54 cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
  55         { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
  56
  57 EXPORT_SYMBOL(cpu_possible_map);
  58 EXPORT_SYMBOL(cpu_online_map);
  59 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
  60 EXPORT_SYMBOL(cpu_core_map);
  61
  62 static cpumask_t smp_commenced_mask;
  63
  64 void smp_info(struct seq_file *m)
  65 {
  66         int i;
  67
  68         seq_printf(m, "State:\n");
  69         for_each_online_cpu(i)
  70                 seq_printf(m, "CPU%d:\t\tonline\n", i);
  71 }
  72
  73 void smp_bogo(struct seq_file *m)
  74 {
  75         int i;
  76
  77         for_each_online_cpu(i)
  78                 seq_printf(m,
  79                            "Cpu%dClkTck\t: %016lx\n",
  80                            i, cpu_data(i).clock_tick);
  81 }
  82
  83 static __cacheline_aligned_in_smp DEFINE_SPINLOCK(call_lock);
  84
  85 extern void setup_sparc64_timer(void);
  86
  87 static volatile unsigned long callin_flag = 0;
  88
  89 void __cpuinit smp_callin(void)
  90 {
  91         int cpuid = hard_smp_processor_id();
  92
  93         __local_per_cpu_offset = __per_cpu_offset(cpuid);
  94
  95         if (tlb_type == hypervisor)
  96                 sun4v_ktsb_register();
  97
  98         __flush_tlb_all();
  99
 100         setup_sparc64_timer();
 101
 102         if (cheetah_pcache_forced_on)
 103                 cheetah_enable_pcache();
 104
 105         local_irq_enable();
 106
 107         callin_flag = 1;
 108         __asm__ __volatile__("membar #Sync\n\t"
 109                              "flush  %%g6" : : : "memory");
 110
 111         /* Clear this or we will die instantly when we
 112          * schedule back to this idler...
 113          */
 114         current_thread_info()->new_child = 0;
 115
 116         /* Attach to the address space of init_task. */
 117         atomic_inc(&init_mm.mm_count);
 118         current->active_mm = &init_mm;
 119
 120         while (!cpu_isset(cpuid, smp_commenced_mask))
 121                 rmb();
 122
 123         spin_lock(&call_lock);
 124         cpu_set(cpuid, cpu_online_map);
 125         spin_unlock(&call_lock);
 126
 127         /* idle thread is expected to have preempt disabled */
 128         preempt_disable();
 129 }
 130
 131 void cpu_panic(void)
 132 {
 133         printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
 134         panic("SMP bolixed\n");
 135 }
 136
 137 /* This tick register synchronization scheme is taken entirely from
 138  * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
 139  *
 140  * The only change I've made is to rework it so that the master
 141  * initiates the synchonization instead of the slave. -DaveM
 142  */
 143
 144 #define MASTER  0
 145 #define SLAVE   (SMP_CACHE_BYTES/sizeof(unsigned long))
 146
 147 #define NUM_ROUNDS      64      /* magic value */
 148 #define NUM_ITERS       5       /* likewise */
 149
 150 static DEFINE_SPINLOCK(itc_sync_lock);
 151 static unsigned long go[SLAVE + 1];
 152
 153 #define DEBUG_TICK_SYNC 0
 154
 155 static inline long get_delta (long *rt, long *master)
 156 {
 157         unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
 158         unsigned long tcenter, t0, t1, tm;
 159         unsigned long i;
 160
 161         for (i = 0; i < NUM_ITERS; i++) {
 162                 t0 = tick_ops->get_tick();
 163                 go[MASTER] = 1;
 164                 membar_storeload();
 165                 while (!(tm = go[SLAVE]))
 166                         rmb();
 167                 go[SLAVE] = 0;
 168                 wmb();
 169                 t1 = tick_ops->get_tick();
 170
 171                 if (t1 - t0 < best_t1 - best_t0)
 172                         best_t0 = t0, best_t1 = t1, best_tm = tm;
 173         }
 174
 175         *rt = best_t1 - best_t0;
 176         *master = best_tm - best_t0;
 177
 178         /* average best_t0 and best_t1 without overflow: */
 179         tcenter = (best_t0/2 + best_t1/2);
 180         if (best_t0 % 2 + best_t1 % 2 == 2)
 181                 tcenter++;
 182         return tcenter - best_tm;
 183 }
 184
 185 void smp_synchronize_tick_client(void)
 186 {
 187         long i, delta, adj, adjust_latency = 0, done = 0;
 188         unsigned long flags, rt, master_time_stamp, bound;
 189 #if DEBUG_TICK_SYNC
 190         struct {
 191                 long rt;        /* roundtrip time */
 192                 long master;    /* master's timestamp */
 193                 long diff;      /* difference between midpoint and master's timestamp */
 194                 long lat;       /* estimate of itc adjustment latency */
 195         } t[NUM_ROUNDS];
 196 #endif
 197
 198         go[MASTER] = 1;
 199
 200         while (go[MASTER])
 201                 rmb();
 202
 203         local_irq_save(flags);
 204         {
 205                 for (i = 0; i < NUM_ROUNDS; i++) {
 206                         delta = get_delta(&rt, &master_time_stamp);
 207                         if (delta == 0) {
 208                                 done = 1;       /* let's lock on to this... */
 209                                 bound = rt;
 210                         }
 211
 212                         if (!done) {
 213                                 if (i > 0) {
 214                                         adjust_latency += -delta;
 215                                         adj = -delta + adjust_latency/4;
 216                                 } else
 217                                         adj = -delta;
 218
 219                                 tick_ops->add_tick(adj);
 220                         }
 221 #if DEBUG_TICK_SYNC
 222                         t[i].rt = rt;
 223                         t[i].master = master_time_stamp;
 224                         t[i].diff = delta;
 225                         t[i].lat = adjust_latency/4;
 226 #endif
 227                 }
 228         }
 229         local_irq_restore(flags);
 230
 231 #if DEBUG_TICK_SYNC
 232         for (i = 0; i < NUM_ROUNDS; i++)
 233                 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
 234                        t[i].rt, t[i].master, t[i].diff, t[i].lat);
 235 #endif
 236
 237         printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
 238                "(last diff %ld cycles, maxerr %lu cycles)\n",
 239                smp_processor_id(), delta, rt);
 240 }
 241
 242 static void smp_start_sync_tick_client(int cpu);
 243
 244 static void smp_synchronize_one_tick(int cpu)
 245 {
 246         unsigned long flags, i;
 247
 248         go[MASTER] = 0;
 249
 250         smp_start_sync_tick_client(cpu);
 251
 252         /* wait for client to be ready */
 253         while (!go[MASTER])
 254                 rmb();
 255
 256         /* now let the client proceed into his loop */
 257         go[MASTER] = 0;
 258         membar_storeload();
 259
 260         spin_lock_irqsave(&itc_sync_lock, flags);
 261         {
 262                 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
 263                         while (!go[MASTER])
 264                                 rmb();
 265                         go[MASTER] = 0;
 266                         wmb();
 267                         go[SLAVE] = tick_ops->get_tick();
 268                         membar_storeload();
 269                 }
 270         }
 271         spin_unlock_irqrestore(&itc_sync_lock, flags);
 272 }
 273
 274 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
 275 /* XXX Put this in some common place. XXX */
 276 static unsigned long kimage_addr_to_ra(void *p)
 277 {
 278         unsigned long val = (unsigned long) p;
 279
 280         return kern_base + (val - KERNBASE);
 281 }
 282
 283 static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg)
 284 {
 285         extern unsigned long sparc64_ttable_tl0;
 286         extern unsigned long kern_locked_tte_data;
 287         struct hvtramp_descr *hdesc;
 288         unsigned long trampoline_ra;
 289         struct trap_per_cpu *tb;
 290         u64 tte_vaddr, tte_data;
 291         unsigned long hv_err;
 292         int i;
 293
 294         hdesc = kzalloc(sizeof(*hdesc) +
 295                         (sizeof(struct hvtramp_mapping) *
 296                          num_kernel_image_mappings - 1),
 297                         GFP_KERNEL);
 298         if (!hdesc) {
 299                 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
 300                        "hvtramp_descr.\n");
 301                 return;
 302         }
 303
 304         hdesc->cpu = cpu;
 305         hdesc->num_mappings = num_kernel_image_mappings;
 306
 307         tb = &trap_block[cpu];
 308         tb->hdesc = hdesc;
 309
 310         hdesc->fault_info_va = (unsigned long) &tb->fault_info;
 311         hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
 312
 313         hdesc->thread_reg = thread_reg;
 314
 315         tte_vaddr = (unsigned long) KERNBASE;
 316         tte_data = kern_locked_tte_data;
 317
 318         for (i = 0; i < hdesc->num_mappings; i++) {
 319                 hdesc->maps[i].vaddr = tte_vaddr;
 320                 hdesc->maps[i].tte   = tte_data;
 321                 tte_vaddr += 0x400000;
 322                 tte_data  += 0x400000;
 323         }
 324
 325         trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
 326
 327         hv_err = sun4v_cpu_start(cpu, trampoline_ra,
 328                                  kimage_addr_to_ra(&sparc64_ttable_tl0),
 329                                  __pa(hdesc));
 330         if (hv_err)
 331                 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
 332                        "gives error %lu\n", hv_err);
 333 }
 334 #endif
 335
 336 extern unsigned long sparc64_cpu_startup;
 337
 338 /* The OBP cpu startup callback truncates the 3rd arg cookie to
 339  * 32-bits (I think) so to be safe we have it read the pointer
 340  * contained here so we work on >4GB machines. -DaveM
 341  */
 342 static struct thread_info *cpu_new_thread = NULL;
 343
 344 static int __devinit smp_boot_one_cpu(unsigned int cpu)
 345 {
 346         struct trap_per_cpu *tb = &trap_block[cpu];
 347         unsigned long entry =
 348                 (unsigned long)(&sparc64_cpu_startup);
 349         unsigned long cookie =
 350                 (unsigned long)(&cpu_new_thread);
 351         struct task_struct *p;
 352         int timeout, ret;
 353
 354         p = fork_idle(cpu);
 355         if (IS_ERR(p))
 356                 return PTR_ERR(p);
 357         callin_flag = 0;
 358         cpu_new_thread = task_thread_info(p);
 359
 360         if (tlb_type == hypervisor) {
 361 #if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
 362                 if (ldom_domaining_enabled)
 363                         ldom_startcpu_cpuid(cpu,
 364                                             (unsigned long) cpu_new_thread);
 365                 else
 366 #endif
 367                         prom_startcpu_cpuid(cpu, entry, cookie);
 368         } else {
 369                 struct device_node *dp = of_find_node_by_cpuid(cpu);
 370
 371                 prom_startcpu(dp->node, entry, cookie);
 372         }
 373
 374         for (timeout = 0; timeout < 50000; timeout++) {
 375                 if (callin_flag)
 376                         break;
 377                 udelay(100);
 378         }
 379
 380         if (callin_flag) {
 381                 ret = 0;
 382         } else {
 383                 printk("Processor %d is stuck.\n", cpu);
 384                 ret = -ENODEV;
 385         }
 386         cpu_new_thread = NULL;
 387
 388         if (tb->hdesc) {
 389                 kfree(tb->hdesc);
 390                 tb->hdesc = NULL;
 391         }
 392
 393         return ret;
 394 }
 395
 396 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
 397 {
 398         u64 result, target;
 399         int stuck, tmp;
 400
 401         if (this_is_starfire) {
 402                 /* map to real upaid */
 403                 cpu = (((cpu & 0x3c) << 1) |
 404                         ((cpu & 0x40) >> 4) |
 405                         (cpu & 0x3));
 406         }
 407
 408         target = (cpu << 14) | 0x70;
 409 again:
 410         /* Ok, this is the real Spitfire Errata #54.
 411          * One must read back from a UDB internal register
 412          * after writes to the UDB interrupt dispatch, but
 413          * before the membar Sync for that write.
 414          * So we use the high UDB control register (ASI 0x7f,
 415          * ADDR 0x20) for the dummy read. -DaveM
 416          */
 417         tmp = 0x40;
 418         __asm__ __volatile__(
 419         "wrpr   %1, %2, %%pstate\n\t"
 420         "stxa   %4, [%0] %3\n\t"
 421         "stxa   %5, [%0+%8] %3\n\t"
 422         "add    %0, %8, %0\n\t"
 423         "stxa   %6, [%0+%8] %3\n\t"
 424         "membar #Sync\n\t"
 425         "stxa   %%g0, [%7] %3\n\t"
 426         "membar #Sync\n\t"
 427         "mov    0x20, %%g1\n\t"
 428         "ldxa   [%%g1] 0x7f, %%g0\n\t"
 429         "membar #Sync"
 430         : "=r" (tmp)
 431         : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
 432           "r" (data0), "r" (data1), "r" (data2), "r" (target),
 433           "r" (0x10), "0" (tmp)
 434         : "g1");
 435
 436         /* NOTE: PSTATE_IE is still clear. */
 437         stuck = 100000;
 438         do {
 439                 __asm__ __volatile__("ldxa [%%g0] %1, %0"
 440                         : "=r" (result)
 441                         : "i" (ASI_INTR_DISPATCH_STAT));
 442                 if (result == 0) {
 443                         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 444                                              : : "r" (pstate));
 445                         return;
 446                 }
 447                 stuck -= 1;
 448                 if (stuck == 0)
 449                         break;
 450         } while (result & 0x1);
 451         __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 452                              : : "r" (pstate));
 453         if (stuck == 0) {
 454                 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 455                        smp_processor_id(), result);
 456         } else {
 457                 udelay(2);
 458                 goto again;
 459         }
 460 }
 461
 462 static inline void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 463 {
 464         u64 pstate;
 465         int i;
 466
 467         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 468         for_each_cpu_mask(i, mask)
 469                 spitfire_xcall_helper(data0, data1, data2, pstate, i);
 470 }
 471
 472 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
 473  * packet, but we have no use for that.  However we do take advantage of
 474  * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
 475  */
 476 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 477 {
 478         u64 pstate, ver, busy_mask;
 479         int nack_busy_id, is_jbus, need_more;
 480
 481         if (cpus_empty(mask))
 482                 return;
 483
 484         /* Unfortunately, someone at Sun had the brilliant idea to make the
 485          * busy/nack fields hard-coded by ITID number for this Ultra-III
 486          * derivative processor.
 487          */
 488         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 489         is_jbus = ((ver >> 32) == __JALAPENO_ID ||
 490                    (ver >> 32) == __SERRANO_ID);
 491
 492         __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
 493
 494 retry:
 495         need_more = 0;
 496         __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
 497                              : : "r" (pstate), "i" (PSTATE_IE));
 498
 499         /* Setup the dispatch data registers. */
 500         __asm__ __volatile__("stxa      %0, [%3] %6\n\t"
 501                              "stxa      %1, [%4] %6\n\t"
 502                              "stxa      %2, [%5] %6\n\t"
 503                              "membar    #Sync\n\t"
 504                              : /* no outputs */
 505                              : "r" (data0), "r" (data1), "r" (data2),
 506                                "r" (0x40), "r" (0x50), "r" (0x60),
 507                                "i" (ASI_INTR_W));
 508
 509         nack_busy_id = 0;
 510         busy_mask = 0;
 511         {
 512                 int i;
 513
 514                 for_each_cpu_mask(i, mask) {
 515                         u64 target = (i << 14) | 0x70;
 516
 517                         if (is_jbus) {
 518                                 busy_mask |= (0x1UL << (i * 2));
 519                         } else {
 520                                 target |= (nack_busy_id << 24);
 521                                 busy_mask |= (0x1UL <<
 522                                               (nack_busy_id * 2));
 523                         }
 524                         __asm__ __volatile__(
 525                                 "stxa   %%g0, [%0] %1\n\t"
 526                                 "membar #Sync\n\t"
 527                                 : /* no outputs */
 528                                 : "r" (target), "i" (ASI_INTR_W));
 529                         nack_busy_id++;
 530                         if (nack_busy_id == 32) {
 531                                 need_more = 1;
 532                                 break;
 533                         }
 534                 }
 535         }
 536
 537         /* Now, poll for completion. */
 538         {
 539                 u64 dispatch_stat, nack_mask;
 540                 long stuck;
 541
 542                 stuck = 100000 * nack_busy_id;
 543                 nack_mask = busy_mask << 1;
 544                 do {
 545                         __asm__ __volatile__("ldxa      [%%g0] %1, %0"
 546                                              : "=r" (dispatch_stat)
 547                                              : "i" (ASI_INTR_DISPATCH_STAT));
 548                         if (!(dispatch_stat & (busy_mask | nack_mask))) {
 549                                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 550                                                      : : "r" (pstate));
 551                                 if (unlikely(need_more)) {
 552                                         int i, cnt = 0;
 553                                         for_each_cpu_mask(i, mask) {
 554                                                 cpu_clear(i, mask);
 555                                                 cnt++;
 556                                                 if (cnt == 32)
 557                                                         break;
 558                                         }
 559                                         goto retry;
 560                                 }
 561                                 return;
 562                         }
 563                         if (!--stuck)
 564                                 break;
 565                 } while (dispatch_stat & busy_mask);
 566
 567                 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
 568                                      : : "r" (pstate));
 569
 570                 if (dispatch_stat & busy_mask) {
 571                         /* Busy bits will not clear, continue instead
 572                          * of freezing up on this cpu.
 573                          */
 574                         printk("CPU[%d]: mondo stuckage result[%016lx]\n",
 575                                smp_processor_id(), dispatch_stat);
 576                 } else {
 577                         int i, this_busy_nack = 0;
 578
 579                         /* Delay some random time with interrupts enabled
 580                          * to prevent deadlock.
 581                          */
 582                         udelay(2 * nack_busy_id);
 583
 584                         /* Clear out the mask bits for cpus which did not
 585                          * NACK us.
 586                          */
 587                         for_each_cpu_mask(i, mask) {
 588                                 u64 check_mask;
 589
 590                                 if (is_jbus)
 591                                         check_mask = (0x2UL << (2*i));
 592                                 else
 593                                         check_mask = (0x2UL <<
 594                                                       this_busy_nack);
 595                                 if ((dispatch_stat & check_mask) == 0)
 596                                         cpu_clear(i, mask);
 597                                 this_busy_nack += 2;
 598                                 if (this_busy_nack == 64)
 599                                         break;
 600                         }
 601
 602                         goto retry;
 603                 }
 604         }
 605 }
 606
 607 /* Multi-cpu list version.  */
 608 static void hypervisor_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
 609 {
 610         struct trap_per_cpu *tb;
 611         u16 *cpu_list;
 612         u64 *mondo;
 613         cpumask_t error_mask;
 614         unsigned long flags, status;
 615         int cnt, retries, this_cpu, prev_sent, i;
 616
 617         if (cpus_empty(mask))
 618                 return;
 619
 620         /* We have to do this whole thing with interrupts fully disabled.
 621          * Otherwise if we send an xcall from interrupt context it will
 622          * corrupt both our mondo block and cpu list state.
 623          *
 624          * One consequence of this is that we cannot use timeout mechanisms
 625          * that depend upon interrupts being delivered locally.  So, for
 626          * example, we cannot sample jiffies and expect it to advance.
 627          *
 628          * Fortunately, udelay() uses %stick/%tick so we can use that.
 629          */
 630         local_irq_save(flags);
 631
 632         this_cpu = smp_processor_id();
 633         tb = &trap_block[this_cpu];
 634
 635         mondo = __va(tb->cpu_mondo_block_pa);
 636         mondo[0] = data0;
 637         mondo[1] = data1;
 638         mondo[2] = data2;
 639         wmb();
 640
 641         cpu_list = __va(tb->cpu_list_pa);
 642
 643         /* Setup the initial cpu list.  */
 644         cnt = 0;
 645         for_each_cpu_mask(i, mask)
 646                 cpu_list[cnt++] = i;
 647
 648         cpus_clear(error_mask);
 649         retries = 0;
 650         prev_sent = 0;
 651         do {
 652                 int forward_progress, n_sent;
 653
 654                 status = sun4v_cpu_mondo_send(cnt,
 655                                               tb->cpu_list_pa,
 656                                               tb->cpu_mondo_block_pa);
 657
 658                 /* HV_EOK means all cpus received the xcall, we're done.  */
 659                 if (likely(status == HV_EOK))
 660                         break;
 661
 662                 /* First, see if we made any forward progress.
 663                  *
 664                  * The hypervisor indicates successful sends by setting
 665                  * cpu list entries to the value 0xffff.
 666                  */
 667                 n_sent = 0;
 668                 for (i = 0; i < cnt; i++) {
 669                         if (likely(cpu_list[i] == 0xffff))
 670                                 n_sent++;
 671                 }
 672
 673                 forward_progress = 0;
 674                 if (n_sent > prev_sent)
 675                         forward_progress = 1;
 676
 677                 prev_sent = n_sent;
 678
 679                 /* If we get a HV_ECPUERROR, then one or more of the cpus
 680                  * in the list are in error state.  Use the cpu_state()
 681                  * hypervisor call to find out which cpus are in error state.
 682                  */
 683                 if (unlikely(status == HV_ECPUERROR)) {
 684                         for (i = 0; i < cnt; i++) {
 685                                 long err;
 686                                 u16 cpu;
 687
 688                                 cpu = cpu_list[i];
 689                                 if (cpu == 0xffff)
 690                                         continue;
 691
 692                                 err = sun4v_cpu_state(cpu);
 693                                 if (err >= 0 &&
 694                                     err == HV_CPU_STATE_ERROR) {
 695                                         cpu_list[i] = 0xffff;
 696                                         cpu_set(cpu, error_mask);
 697                                 }
 698                         }
 699                 } else if (unlikely(status != HV_EWOULDBLOCK))
 700                         goto fatal_mondo_error;
 701
 702                 /* Don't bother rewriting the CPU list, just leave the
 703                  * 0xffff and non-0xffff entries in there and the
 704                  * hypervisor will do the right thing.
 705                  *
 706                  * Only advance timeout state if we didn't make any
 707                  * forward progress.
 708                  */
 709                 if (unlikely(!forward_progress)) {
 710                         if (unlikely(++retries > 10000))
 711                                 goto fatal_mondo_timeout;
 712
 713                         /* Delay a little bit to let other cpus catch up
 714                          * on their cpu mondo queue work.
 715                          */
 716                         udelay(2 * cnt);
 717                 }
 718         } while (1);
 719
 720         local_irq_restore(flags);
 721
 722         if (unlikely(!cpus_empty(error_mask)))
 723                 goto fatal_mondo_cpu_error;
 724
 725         return;
 726
 727 fatal_mondo_cpu_error:
 728         printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
 729                "were in error state\n",
 730                this_cpu);
 731         printk(KERN_CRIT "CPU[%d]: Error mask [ ", this_cpu);
 732         for_each_cpu_mask(i, error_mask)
 733                 printk("%d ", i);
 734         printk("]\n");
 735         return;
 736
 737 fatal_mondo_timeout:
 738         local_irq_restore(flags);
 739         printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
 740                " progress after %d retries.\n",
 741                this_cpu, retries);
 742         goto dump_cpu_list_and_out;
 743
 744 fatal_mondo_error:
 745         local_irq_restore(flags);
 746         printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
 747                this_cpu, status);
 748         printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
 749                "mondo_block_pa(%lx)\n",
 750                this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
 751
 752 dump_cpu_list_and_out:
 753         printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
 754         for (i = 0; i < cnt; i++)
 755                 printk("%u ", cpu_list[i]);
 756         printk("]\n");
 757 }
 758
 759 /* Send cross call to all processors mentioned in MASK
 760  * except self.
 761  */
 762 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
 763 {
 764         u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
 765         int this_cpu = get_cpu();
 766
 767         cpus_and(mask, mask, cpu_online_map);
 768         cpu_clear(this_cpu, mask);
 769
 770         if (tlb_type == spitfire)
 771                 spitfire_xcall_deliver(data0, data1, data2, mask);
 772         else if (tlb_type == cheetah || tlb_type == cheetah_plus)
 773                 cheetah_xcall_deliver(data0, data1, data2, mask);
 774         else
 775                 hypervisor_xcall_deliver(data0, data1, data2, mask);
 776         /* NOTE: Caller runs local copy on master. */
 777
 778         put_cpu();
 779 }
 780
 781 extern unsigned long xcall_sync_tick;
 782
 783 static void smp_start_sync_tick_client(int cpu)
 784 {
 785         cpumask_t mask = cpumask_of_cpu(cpu);
 786
 787         smp_cross_call_masked(&xcall_sync_tick,
 788                               0, 0, 0, mask);
 789 }
 790
 791 extern unsigned long xcall_call_function;
 792
 793 void arch_send_call_function_ipi(cpumask_t mask)
 794 {
 795         smp_cross_call_masked(&xcall_call_function, 0, 0, 0, mask);
 796 }
 797
 798 extern unsigned long xcall_call_function_single;
 799
 800 void arch_send_call_function_single_ipi(int cpu)
 801 {
 802         cpumask_t mask = cpumask_of_cpu(cpu);
 803
 804         smp_cross_call_masked(&xcall_call_function_single, 0, 0, 0, mask);
 805 }
 806
 807 /* Send cross call to all processors except self. */
 808 #define smp_cross_call(func, ctx, data1, data2) \
 809         smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
 810
 811 void smp_call_function_client(int irq, struct pt_regs *regs)
 812 {
 813         clear_softint(1 << irq);
 814         generic_smp_call_function_interrupt();
 815 }
 816
 817 void smp_call_function_single_client(int irq, struct pt_regs *regs)
 818 {
 819         clear_softint(1 << irq);
 820         generic_smp_call_function_single_interrupt();
 821 }
 822
 823 static void tsb_sync(void *info)
 824 {
 825         struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
 826         struct mm_struct *mm = info;
 827
 828         /* It is not valid to test "currrent->active_mm == mm" here.
 829          *
 830          * The value of "current" is not changed atomically with
 831          * switch_mm().  But that's OK, we just need to check the
 832          * current cpu's trap block PGD physical address.
 833          */
 834         if (tp->pgd_paddr == __pa(mm->pgd))
 835                 tsb_context_switch(mm);
 836 }
 837
 838 void smp_tsb_sync(struct mm_struct *mm)
 839 {
 840         smp_call_function_mask(mm->cpu_vm_mask, tsb_sync, mm, 1);
 841 }
 842
 843 extern unsigned long xcall_flush_tlb_mm;
 844 extern unsigned long xcall_flush_tlb_pending;
 845 extern unsigned long xcall_flush_tlb_kernel_range;
 846 extern unsigned long xcall_report_regs;
 847 #ifdef CONFIG_MAGIC_SYSRQ
 848 extern unsigned long xcall_fetch_glob_regs;
 849 #endif
 850 extern unsigned long xcall_receive_signal;
 851 extern unsigned long xcall_new_mmu_context_version;
 852 #ifdef CONFIG_KGDB
 853 extern unsigned long xcall_kgdb_capture;
 854 #endif
 855
 856 #ifdef DCACHE_ALIASING_POSSIBLE
 857 extern unsigned long xcall_flush_dcache_page_cheetah;
 858 #endif
 859 extern unsigned long xcall_flush_dcache_page_spitfire;
 860
 861 #ifdef CONFIG_DEBUG_DCFLUSH
 862 extern atomic_t dcpage_flushes;
 863 extern atomic_t dcpage_flushes_xcall;
 864 #endif
 865
 866 static inline void __local_flush_dcache_page(struct page *page)
 867 {
 868 #ifdef DCACHE_ALIASING_POSSIBLE
 869         __flush_dcache_page(page_address(page),
 870                             ((tlb_type == spitfire) &&
 871                              page_mapping(page) != NULL));
 872 #else
 873         if (page_mapping(page) != NULL &&
 874             tlb_type == spitfire)
 875                 __flush_icache_page(__pa(page_address(page)));
 876 #endif
 877 }
 878
 879 void smp_flush_dcache_page_impl(struct page *page, int cpu)
 880 {
 881         cpumask_t mask = cpumask_of_cpu(cpu);
 882         int this_cpu;
 883
 884         if (tlb_type == hypervisor)
 885                 return;
 886
 887 #ifdef CONFIG_DEBUG_DCFLUSH
 888         atomic_inc(&dcpage_flushes);
 889 #endif
 890
 891         this_cpu = get_cpu();
 892
 893         if (cpu == this_cpu) {
 894                 __local_flush_dcache_page(page);
 895         } else if (cpu_online(cpu)) {
 896                 void *pg_addr = page_address(page);
 897                 u64 data0;
 898
 899                 if (tlb_type == spitfire) {
 900                         data0 =
 901                                 ((u64)&xcall_flush_dcache_page_spitfire);
 902                         if (page_mapping(page) != NULL)
 903                                 data0 |= ((u64)1 << 32);
 904                         spitfire_xcall_deliver(data0,
 905                                                __pa(pg_addr),
 906                                                (u64) pg_addr,
 907                                                mask);
 908                 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 909 #ifdef DCACHE_ALIASING_POSSIBLE
 910                         data0 =
 911                                 ((u64)&xcall_flush_dcache_page_cheetah);
 912                         cheetah_xcall_deliver(data0,
 913                                               __pa(pg_addr),
 914                                               0, mask);
 915 #endif
 916                 }
 917 #ifdef CONFIG_DEBUG_DCFLUSH
 918                 atomic_inc(&dcpage_flushes_xcall);
 919 #endif
 920         }
 921
 922         put_cpu();
 923 }
 924
 925 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
 926 {
 927         void *pg_addr = page_address(page);
 928         cpumask_t mask = cpu_online_map;
 929         u64 data0;
 930         int this_cpu;
 931
 932         if (tlb_type == hypervisor)
 933                 return;
 934
 935         this_cpu = get_cpu();
 936
 937         cpu_clear(this_cpu, mask);
 938
 939 #ifdef CONFIG_DEBUG_DCFLUSH
 940         atomic_inc(&dcpage_flushes);
 941 #endif
 942         if (cpus_empty(mask))
 943                 goto flush_self;
 944         if (tlb_type == spitfire) {
 945                 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
 946                 if (page_mapping(page) != NULL)
 947                         data0 |= ((u64)1 << 32);
 948                 spitfire_xcall_deliver(data0,
 949                                        __pa(pg_addr),
 950                                        (u64) pg_addr,
 951                                        mask);
 952         } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 953 #ifdef DCACHE_ALIASING_POSSIBLE
 954                 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
 955                 cheetah_xcall_deliver(data0,
 956                                       __pa(pg_addr),
 957                                       0, mask);
 958 #endif
 959         }
 960 #ifdef CONFIG_DEBUG_DCFLUSH
 961         atomic_inc(&dcpage_flushes_xcall);
 962 #endif
 963  flush_self:
 964         __local_flush_dcache_page(page);
 965
 966         put_cpu();
 967 }
 968
 969 static void __smp_receive_signal_mask(cpumask_t mask)
 970 {
 971         smp_cross_call_masked(&xcall_receive_signal, 0, 0, 0, mask);
 972 }
 973
 974 void smp_receive_signal(int cpu)
 975 {
 976         cpumask_t mask = cpumask_of_cpu(cpu);
 977
 978         if (cpu_online(cpu))
 979                 __smp_receive_signal_mask(mask);
 980 }
 981
 982 void smp_receive_signal_client(int irq, struct pt_regs *regs)
 983 {
 984         clear_softint(1 << irq);
 985 }
 986
 987 void smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
 988 {
 989         struct mm_struct *mm;
 990         unsigned long flags;
 991
 992         clear_softint(1 << irq);
 993
 994         /* See if we need to allocate a new TLB context because
 995          * the version of the one we are using is now out of date.
 996          */
 997         mm = current->active_mm;
 998         if (unlikely(!mm || (mm == &init_mm)))
 999                 return;
1000
1001         spin_lock_irqsave(&mm->context.lock, flags);
1002
1003         if (unlikely(!CTX_VALID(mm->context)))
1004                 get_new_mmu_context(mm);
1005
1006         spin_unlock_irqrestore(&mm->context.lock, flags);
1007
1008         load_secondary_context(mm);
1009         __flush_tlb_mm(CTX_HWBITS(mm->context),
1010                        SECONDARY_CONTEXT);
1011 }
1012
1013 void smp_new_mmu_context_version(void)
1014 {
1015         smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
1016 }
1017
1018 #ifdef CONFIG_KGDB
1019 void kgdb_roundup_cpus(unsigned long flags)
1020 {
1021         smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
1022 }
1023 #endif
1024
1025 void smp_report_regs(void)
1026 {
1027         smp_cross_call(&xcall_report_regs, 0, 0, 0);
1028 }
1029
1030 #ifdef CONFIG_MAGIC_SYSRQ
1031 void smp_fetch_global_regs(void)
1032 {
1033         smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1034 }
1035 #endif
1036
1037 /* We know that the window frames of the user have been flushed
1038  * to the stack before we get here because all callers of us
1039  * are flush_tlb_*() routines, and these run after flush_cache_*()
1040  * which performs the flushw.
1041  *
1042  * The SMP TLB coherency scheme we use works as follows:
1043  *
1044  * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1045  *    space has (potentially) executed on, this is the heuristic
1046  *    we use to avoid doing cross calls.
1047  *
1048  *    Also, for flushing from kswapd and also for clones, we
1049  *    use cpu_vm_mask as the list of cpus to make run the TLB.
1050  *
1051  * 2) TLB context numbers are shared globally across all processors
1052  *    in the system, this allows us to play several games to avoid
1053  *    cross calls.
1054  *
1055  *    One invariant is that when a cpu switches to a process, and
1056  *    that processes tsk->active_mm->cpu_vm_mask does not have the
1057  *    current cpu's bit set, that tlb context is flushed locally.
1058  *
1059  *    If the address space is non-shared (ie. mm->count == 1) we avoid
1060  *    cross calls when we want to flush the currently running process's
1061  *    tlb state.  This is done by clearing all cpu bits except the current
1062  *    processor's in current->active_mm->cpu_vm_mask and performing the
1063  *    flush locally only.  This will force any subsequent cpus which run
1064  *    this task to flush the context from the local tlb if the process
1065  *    migrates to another cpu (again).
1066  *
1067  * 3) For shared address spaces (threads) and swapping we bite the
1068  *    bullet for most cases and perform the cross call (but only to
1069  *    the cpus listed in cpu_vm_mask).
1070  *
1071  *    The performance gain from "optimizing" away the cross call for threads is
1072  *    questionable (in theory the big win for threads is the massive sharing of
1073  *    address space state across processors).
1074  */
1075
1076 /* This currently is only used by the hugetlb arch pre-fault
1077  * hook on UltraSPARC-III+ and later when changing the pagesize
1078  * bits of the context register for an address space.
1079  */
1080 void smp_flush_tlb_mm(struct mm_struct *mm)
1081 {
1082         u32 ctx = CTX_HWBITS(mm->context);
1083         int cpu = get_cpu();
1084
1085         if (atomic_read(&mm->mm_users) == 1) {
1086                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1087                 goto local_flush_and_out;
1088         }
1089
1090         smp_cross_call_masked(&xcall_flush_tlb_mm,
1091                               ctx, 0, 0,
1092                               mm->cpu_vm_mask);
1093
1094 local_flush_and_out:
1095         __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1096
1097         put_cpu();
1098 }
1099
1100 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1101 {
1102         u32 ctx = CTX_HWBITS(mm->context);
1103         int cpu = get_cpu();
1104
1105         if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1)
1106                 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
1107         else
1108                 smp_cross_call_masked(&xcall_flush_tlb_pending,
1109                                       ctx, nr, (unsigned long) vaddrs,
1110                                       mm->cpu_vm_mask);
1111
1112         __flush_tlb_pending(ctx, nr, vaddrs);
1113
1114         put_cpu();
1115 }
1116
1117 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1118 {
1119         start &= PAGE_MASK;
1120         end    = PAGE_ALIGN(end);
1121         if (start != end) {
1122                 smp_cross_call(&xcall_flush_tlb_kernel_range,
1123                                0, start, end);
1124
1125                 __flush_tlb_kernel_range(start, end);
1126         }
1127 }
1128
1129 /* CPU capture. */
1130 /* #define CAPTURE_DEBUG */
1131 extern unsigned long xcall_capture;
1132
1133 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1134 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1135 static unsigned long penguins_are_doing_time;
1136
1137 void smp_capture(void)
1138 {
1139         int result = atomic_add_ret(1, &smp_capture_depth);
1140
1141         if (result == 1) {
1142                 int ncpus = num_online_cpus();
1143
1144 #ifdef CAPTURE_DEBUG
1145                 printk("CPU[%d]: Sending penguins to jail...",
1146                        smp_processor_id());
1147 #endif
1148                 penguins_are_doing_time = 1;
1149                 membar_storestore_loadstore();
1150                 atomic_inc(&smp_capture_registry);
1151                 smp_cross_call(&xcall_capture, 0, 0, 0);
1152                 while (atomic_read(&smp_capture_registry) != ncpus)
1153                         rmb();
1154 #ifdef CAPTURE_DEBUG
1155                 printk("done\n");
1156 #endif
1157         }
1158 }
1159
1160 void smp_release(void)
1161 {
1162         if (atomic_dec_and_test(&smp_capture_depth)) {
1163 #ifdef CAPTURE_DEBUG
1164                 printk("CPU[%d]: Giving pardon to "
1165                        "imprisoned penguins\n",
1166                        smp_processor_id());
1167 #endif
1168                 penguins_are_doing_time = 0;
1169                 membar_storeload_storestore();
1170                 atomic_dec(&smp_capture_registry);
1171         }
1172 }
1173
1174 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
1175  * can service tlb flush xcalls...
1176  */
1177 extern void prom_world(int);
1178
1179 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
1180 {
1181         clear_softint(1 << irq);
1182
1183         preempt_disable();
1184
1185         __asm__ __volatile__("flushw");
1186         prom_world(1);
1187         atomic_inc(&smp_capture_registry);
1188         membar_storeload_storestore();
1189         while (penguins_are_doing_time)
1190                 rmb();
1191         atomic_dec(&smp_capture_registry);
1192         prom_world(0);
1193
1194         preempt_enable();
1195 }
1196
1197 /* /proc/profile writes can call this, don't __init it please. */
1198 int setup_profiling_timer(unsigned int multiplier)
1199 {
1200         return -EINVAL;
1201 }
1202
1203 void __init smp_prepare_cpus(unsigned int max_cpus)
1204 {
1205 }
1206
1207 void __devinit smp_prepare_boot_cpu(void)
1208 {
1209 }
1210
1211 void __devinit smp_fill_in_sib_core_maps(void)
1212 {
1213         unsigned int i;
1214
1215         for_each_present_cpu(i) {
1216                 unsigned int j;
1217
1218                 cpus_clear(cpu_core_map[i]);
1219                 if (cpu_data(i).core_id == 0) {
1220                         cpu_set(i, cpu_core_map[i]);
1221                         continue;
1222                 }
1223
1224                 for_each_present_cpu(j) {
1225                         if (cpu_data(i).core_id ==
1226                             cpu_data(j).core_id)
1227                                 cpu_set(j, cpu_core_map[i]);
1228                 }
1229         }
1230
1231         for_each_present_cpu(i) {
1232                 unsigned int j;
1233
1234                 cpus_clear(per_cpu(cpu_sibling_map, i));
1235                 if (cpu_data(i).proc_id == -1) {
1236                         cpu_set(i, per_cpu(cpu_sibling_map, i));
1237                         continue;
1238                 }
1239
1240                 for_each_present_cpu(j) {
1241                         if (cpu_data(i).proc_id ==
1242                             cpu_data(j).proc_id)
1243                                 cpu_set(j, per_cpu(cpu_sibling_map, i));
1244                 }
1245         }
1246 }
1247
1248 int __cpuinit __cpu_up(unsigned int cpu)
1249 {
1250         int ret = smp_boot_one_cpu(cpu);
1251
1252         if (!ret) {
1253                 cpu_set(cpu, smp_commenced_mask);
1254                 while (!cpu_isset(cpu, cpu_online_map))
1255                         mb();
1256                 if (!cpu_isset(cpu, cpu_online_map)) {
1257                         ret = -ENODEV;
1258                 } else {
1259                         /* On SUN4V, writes to %tick and %stick are
1260                          * not allowed.
1261                          */
1262                         if (tlb_type != hypervisor)
1263                                 smp_synchronize_one_tick(cpu);
1264                 }
1265         }
1266         return ret;
1267 }
1268
1269 #ifdef CONFIG_HOTPLUG_CPU
1270 void cpu_play_dead(void)
1271 {
1272         int cpu = smp_processor_id();
1273         unsigned long pstate;
1274
1275         idle_task_exit();
1276
1277         if (tlb_type == hypervisor) {
1278                 struct trap_per_cpu *tb = &trap_block[cpu];
1279
1280                 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1281                                 tb->cpu_mondo_pa, 0);
1282                 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1283                                 tb->dev_mondo_pa, 0);
1284                 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1285                                 tb->resum_mondo_pa, 0);
1286                 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1287                                 tb->nonresum_mondo_pa, 0);
1288         }
1289
1290         cpu_clear(cpu, smp_commenced_mask);
1291         membar_safe("#Sync");
1292
1293         local_irq_disable();
1294
1295         __asm__ __volatile__(
1296                 "rdpr   %%pstate, %0\n\t"
1297                 "wrpr   %0, %1, %%pstate"
1298                 : "=r" (pstate)
1299                 : "i" (PSTATE_IE));
1300
1301         while (1)
1302                 barrier();
1303 }
1304
1305 int __cpu_disable(void)
1306 {
1307         int cpu = smp_processor_id();
1308         cpuinfo_sparc *c;
1309         int i;
1310
1311         for_each_cpu_mask(i, cpu_core_map[cpu])
1312                 cpu_clear(cpu, cpu_core_map[i]);
1313         cpus_clear(cpu_core_map[cpu]);
1314
1315         for_each_cpu_mask(i, per_cpu(cpu_sibling_map, cpu))
1316                 cpu_clear(cpu, per_cpu(cpu_sibling_map, i));
1317         cpus_clear(per_cpu(cpu_sibling_map, cpu));
1318
1319         c = &cpu_data(cpu);
1320
1321         c->core_id = 0;
1322         c->proc_id = -1;
1323
1324         spin_lock(&call_lock);
1325         cpu_clear(cpu, cpu_online_map);
1326         spin_unlock(&call_lock);
1327
1328         smp_wmb();
1329
1330         /* Make sure no interrupts point to this cpu.  */
1331         fixup_irqs();
1332
1333         local_irq_enable();
1334         mdelay(1);
1335         local_irq_disable();
1336
1337         return 0;
1338 }
1339
1340 void __cpu_die(unsigned int cpu)
1341 {
1342         int i;
1343
1344         for (i = 0; i < 100; i++) {
1345                 smp_rmb();
1346                 if (!cpu_isset(cpu, smp_commenced_mask))
1347                         break;
1348                 msleep(100);
1349         }
1350         if (cpu_isset(cpu, smp_commenced_mask)) {
1351                 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1352         } else {
1353 #if defined(CONFIG_SUN_LDOMS)
1354                 unsigned long hv_err;
1355                 int limit = 100;
1356
1357                 do {
1358                         hv_err = sun4v_cpu_stop(cpu);
1359                         if (hv_err == HV_EOK) {
1360                                 cpu_clear(cpu, cpu_present_map);
1361                                 break;
1362                         }
1363                 } while (--limit > 0);
1364                 if (limit <= 0) {
1365                         printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1366                                hv_err);
1367                 }
1368 #endif
1369         }
1370 }
1371 #endif
1372
1373 void __init smp_cpus_done(unsigned int max_cpus)
1374 {
1375 }
1376
1377 void smp_send_reschedule(int cpu)
1378 {
1379         smp_receive_signal(cpu);
1380 }
1381
1382 /* This is a nop because we capture all other cpus
1383  * anyways when making the PROM active.
1384  */
1385 void smp_send_stop(void)
1386 {
1387 }
1388
1389 unsigned long __per_cpu_base __read_mostly;
1390 unsigned long __per_cpu_shift __read_mostly;
1391
1392 EXPORT_SYMBOL(__per_cpu_base);
1393 EXPORT_SYMBOL(__per_cpu_shift);
1394
1395 void __init real_setup_per_cpu_areas(void)
1396 {
1397         unsigned long paddr, goal, size, i;
1398         char *ptr;
1399
1400         /* Copy section for each CPU (we discard the original) */
1401         goal = PERCPU_ENOUGH_ROOM;
1402
1403         __per_cpu_shift = PAGE_SHIFT;
1404         for (size = PAGE_SIZE; size < goal; size <<= 1UL)
1405                 __per_cpu_shift++;
1406
1407         paddr = lmb_alloc(size * NR_CPUS, PAGE_SIZE);
1408         if (!paddr) {
1409                 prom_printf("Cannot allocate per-cpu memory.\n");
1410                 prom_halt();
1411         }
1412
1413         ptr = __va(paddr);
1414         __per_cpu_base = ptr - __per_cpu_start;
1415
1416         for (i = 0; i < NR_CPUS; i++, ptr += size)
1417                 memcpy(ptr, __per_cpu_start, __per_cpu_end - __per_cpu_start);
1418
1419         /* Setup %g5 for the boot cpu.  */
1420         __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1421 }