arch/sparc64/kernel/pci_sabre.c

   1 /* $Id: pci_sabre.c,v 1.42 2002/01/23 11:27:32 davem Exp $
   2  * pci_sabre.c: Sabre specific PCI controller support.
   3  *
   4  * Copyright (C) 1997, 1998, 1999 David S. Miller (davem@caipfs.rutgers.edu)
   5  * Copyright (C) 1998, 1999 Eddie C. Dost   (ecd@skynet.be)
   6  * Copyright (C) 1999 Jakub Jelinek   (jakub@redhat.com)
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/types.h>
  11 #include <linux/pci.h>
  12 #include <linux/init.h>
  13 #include <linux/slab.h>
  14 #include <linux/interrupt.h>
  15
  16 #include <asm/apb.h>
  17 #include <asm/pbm.h>
  18 #include <asm/iommu.h>
  19 #include <asm/irq.h>
  20 #include <asm/smp.h>
  21 #include <asm/oplib.h>
  22 #include <asm/prom.h>
  23
  24 #include "pci_impl.h"
  25 #include "iommu_common.h"
  26
  27 /* All SABRE registers are 64-bits.  The following accessor
  28  * routines are how they are accessed.  The REG parameter
  29  * is a physical address.
  30  */
  31 #define sabre_read(__reg) \
  32 ({      u64 __ret; \
  33         __asm__ __volatile__("ldxa [%1] %2, %0" \
  34                              : "=r" (__ret) \
  35                              : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
  36                              : "memory"); \
  37         __ret; \
  38 })
  39 #define sabre_write(__reg, __val) \
  40         __asm__ __volatile__("stxa %0, [%1] %2" \
  41                              : /* no outputs */ \
  42                              : "r" (__val), "r" (__reg), \
  43                                "i" (ASI_PHYS_BYPASS_EC_E) \
  44                              : "memory")
  45
  46 /* SABRE PCI controller register offsets and definitions. */
  47 #define SABRE_UE_AFSR           0x0030UL
  48 #define  SABRE_UEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  49 #define  SABRE_UEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  50 #define  SABRE_UEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  51 #define  SABRE_UEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  52 #define  SABRE_UEAFSR_SDTE       0x0200000000000000UL   /* Secondary DMA Translation Error */
  53 #define  SABRE_UEAFSR_PDTE       0x0100000000000000UL   /* Primary DMA Translation Error */
  54 #define  SABRE_UEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  55 #define  SABRE_UEAFSR_OFF        0x00000000e0000000UL   /* Offset (AFAR bits [5:3] */
  56 #define  SABRE_UEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  57 #define SABRE_UECE_AFAR         0x0038UL
  58 #define SABRE_CE_AFSR           0x0040UL
  59 #define  SABRE_CEAFSR_PDRD       0x4000000000000000UL   /* Primary PCI DMA Read */
  60 #define  SABRE_CEAFSR_PDWR       0x2000000000000000UL   /* Primary PCI DMA Write */
  61 #define  SABRE_CEAFSR_SDRD       0x0800000000000000UL   /* Secondary PCI DMA Read */
  62 #define  SABRE_CEAFSR_SDWR       0x0400000000000000UL   /* Secondary PCI DMA Write */
  63 #define  SABRE_CEAFSR_ESYND      0x00ff000000000000UL   /* ECC Syndrome */
  64 #define  SABRE_CEAFSR_BMSK       0x0000ffff00000000UL   /* Bytemask */
  65 #define  SABRE_CEAFSR_OFF        0x00000000e0000000UL   /* Offset */
  66 #define  SABRE_CEAFSR_BLK        0x0000000000800000UL   /* Was block operation */
  67 #define SABRE_UECE_AFAR_ALIAS   0x0048UL        /* Aliases to 0x0038 */
  68 #define SABRE_IOMMU_CONTROL     0x0200UL
  69 #define  SABRE_IOMMUCTRL_ERRSTS  0x0000000006000000UL   /* Error status bits */
  70 #define  SABRE_IOMMUCTRL_ERR     0x0000000001000000UL   /* Error present in IOTLB */
  71 #define  SABRE_IOMMUCTRL_LCKEN   0x0000000000800000UL   /* IOTLB lock enable */
  72 #define  SABRE_IOMMUCTRL_LCKPTR  0x0000000000780000UL   /* IOTLB lock pointer */
  73 #define  SABRE_IOMMUCTRL_TSBSZ   0x0000000000070000UL   /* TSB Size */
  74 #define  SABRE_IOMMU_TSBSZ_1K   0x0000000000000000
  75 #define  SABRE_IOMMU_TSBSZ_2K   0x0000000000010000
  76 #define  SABRE_IOMMU_TSBSZ_4K   0x0000000000020000
  77 #define  SABRE_IOMMU_TSBSZ_8K   0x0000000000030000
  78 #define  SABRE_IOMMU_TSBSZ_16K  0x0000000000040000
  79 #define  SABRE_IOMMU_TSBSZ_32K  0x0000000000050000
  80 #define  SABRE_IOMMU_TSBSZ_64K  0x0000000000060000
  81 #define  SABRE_IOMMU_TSBSZ_128K 0x0000000000070000
  82 #define  SABRE_IOMMUCTRL_TBWSZ   0x0000000000000004UL   /* TSB assumed page size */
  83 #define  SABRE_IOMMUCTRL_DENAB   0x0000000000000002UL   /* Diagnostic Mode Enable */
  84 #define  SABRE_IOMMUCTRL_ENAB    0x0000000000000001UL   /* IOMMU Enable */
  85 #define SABRE_IOMMU_TSBBASE     0x0208UL
  86 #define SABRE_IOMMU_FLUSH       0x0210UL
  87 #define SABRE_IMAP_A_SLOT0      0x0c00UL
  88 #define SABRE_IMAP_B_SLOT0      0x0c20UL
  89 #define SABRE_IMAP_SCSI         0x1000UL
  90 #define SABRE_IMAP_ETH          0x1008UL
  91 #define SABRE_IMAP_BPP          0x1010UL
  92 #define SABRE_IMAP_AU_REC       0x1018UL
  93 #define SABRE_IMAP_AU_PLAY      0x1020UL
  94 #define SABRE_IMAP_PFAIL        0x1028UL
  95 #define SABRE_IMAP_KMS          0x1030UL
  96 #define SABRE_IMAP_FLPY         0x1038UL
  97 #define SABRE_IMAP_SHW          0x1040UL
  98 #define SABRE_IMAP_KBD          0x1048UL
  99 #define SABRE_IMAP_MS           0x1050UL
 100 #define SABRE_IMAP_SER          0x1058UL
 101 #define SABRE_IMAP_UE           0x1070UL
 102 #define SABRE_IMAP_CE           0x1078UL
 103 #define SABRE_IMAP_PCIERR       0x1080UL
 104 #define SABRE_IMAP_GFX          0x1098UL
 105 #define SABRE_IMAP_EUPA         0x10a0UL
 106 #define SABRE_ICLR_A_SLOT0      0x1400UL
 107 #define SABRE_ICLR_B_SLOT0      0x1480UL
 108 #define SABRE_ICLR_SCSI         0x1800UL
 109 #define SABRE_ICLR_ETH          0x1808UL
 110 #define SABRE_ICLR_BPP          0x1810UL
 111 #define SABRE_ICLR_AU_REC       0x1818UL
 112 #define SABRE_ICLR_AU_PLAY      0x1820UL
 113 #define SABRE_ICLR_PFAIL        0x1828UL
 114 #define SABRE_ICLR_KMS          0x1830UL
 115 #define SABRE_ICLR_FLPY         0x1838UL
 116 #define SABRE_ICLR_SHW          0x1840UL
 117 #define SABRE_ICLR_KBD          0x1848UL
 118 #define SABRE_ICLR_MS           0x1850UL
 119 #define SABRE_ICLR_SER          0x1858UL
 120 #define SABRE_ICLR_UE           0x1870UL
 121 #define SABRE_ICLR_CE           0x1878UL
 122 #define SABRE_ICLR_PCIERR       0x1880UL
 123 #define SABRE_WRSYNC            0x1c20UL
 124 #define SABRE_PCICTRL           0x2000UL
 125 #define  SABRE_PCICTRL_MRLEN     0x0000001000000000UL   /* Use MemoryReadLine for block loads/stores */
 126 #define  SABRE_PCICTRL_SERR      0x0000000400000000UL   /* Set when SERR asserted on PCI bus */
 127 #define  SABRE_PCICTRL_ARBPARK   0x0000000000200000UL   /* Bus Parking 0=Ultra-IIi 1=prev-bus-owner */
 128 #define  SABRE_PCICTRL_CPUPRIO   0x0000000000100000UL   /* Ultra-IIi granted every other bus cycle */
 129 #define  SABRE_PCICTRL_ARBPRIO   0x00000000000f0000UL   /* Slot which is granted every other bus cycle */
 130 #define  SABRE_PCICTRL_ERREN     0x0000000000000100UL   /* PCI Error Interrupt Enable */
 131 #define  SABRE_PCICTRL_RTRYWE    0x0000000000000080UL   /* DMA Flow Control 0=wait-if-possible 1=retry */
 132 #define  SABRE_PCICTRL_AEN       0x000000000000000fUL   /* Slot PCI arbitration enables */
 133 #define SABRE_PIOAFSR           0x2010UL
 134 #define  SABRE_PIOAFSR_PMA       0x8000000000000000UL   /* Primary Master Abort */
 135 #define  SABRE_PIOAFSR_PTA       0x4000000000000000UL   /* Primary Target Abort */
 136 #define  SABRE_PIOAFSR_PRTRY     0x2000000000000000UL   /* Primary Excessive Retries */
 137 #define  SABRE_PIOAFSR_PPERR     0x1000000000000000UL   /* Primary Parity Error */
 138 #define  SABRE_PIOAFSR_SMA       0x0800000000000000UL   /* Secondary Master Abort */
 139 #define  SABRE_PIOAFSR_STA       0x0400000000000000UL   /* Secondary Target Abort */
 140 #define  SABRE_PIOAFSR_SRTRY     0x0200000000000000UL   /* Secondary Excessive Retries */
 141 #define  SABRE_PIOAFSR_SPERR     0x0100000000000000UL   /* Secondary Parity Error */
 142 #define  SABRE_PIOAFSR_BMSK      0x0000ffff00000000UL   /* Byte Mask */
 143 #define  SABRE_PIOAFSR_BLK       0x0000000080000000UL   /* Was Block Operation */
 144 #define SABRE_PIOAFAR           0x2018UL
 145 #define SABRE_PCIDIAG           0x2020UL
 146 #define  SABRE_PCIDIAG_DRTRY     0x0000000000000040UL   /* Disable PIO Retry Limit */
 147 #define  SABRE_PCIDIAG_IPAPAR    0x0000000000000008UL   /* Invert PIO Address Parity */
 148 #define  SABRE_PCIDIAG_IPDPAR    0x0000000000000004UL   /* Invert PIO Data Parity */
 149 #define  SABRE_PCIDIAG_IDDPAR    0x0000000000000002UL   /* Invert DMA Data Parity */
 150 #define  SABRE_PCIDIAG_ELPBK     0x0000000000000001UL   /* Loopback Enable - not supported */
 151 #define SABRE_PCITASR           0x2028UL
 152 #define  SABRE_PCITASR_EF        0x0000000000000080UL   /* Respond to 0xe0000000-0xffffffff */
 153 #define  SABRE_PCITASR_CD        0x0000000000000040UL   /* Respond to 0xc0000000-0xdfffffff */
 154 #define  SABRE_PCITASR_AB        0x0000000000000020UL   /* Respond to 0xa0000000-0xbfffffff */
 155 #define  SABRE_PCITASR_89        0x0000000000000010UL   /* Respond to 0x80000000-0x9fffffff */
 156 #define  SABRE_PCITASR_67        0x0000000000000008UL   /* Respond to 0x60000000-0x7fffffff */
 157 #define  SABRE_PCITASR_45        0x0000000000000004UL   /* Respond to 0x40000000-0x5fffffff */
 158 #define  SABRE_PCITASR_23        0x0000000000000002UL   /* Respond to 0x20000000-0x3fffffff */
 159 #define  SABRE_PCITASR_01        0x0000000000000001UL   /* Respond to 0x00000000-0x1fffffff */
 160 #define SABRE_PIOBUF_DIAG       0x5000UL
 161 #define SABRE_DMABUF_DIAGLO     0x5100UL
 162 #define SABRE_DMABUF_DIAGHI     0x51c0UL
 163 #define SABRE_IMAP_GFX_ALIAS    0x6000UL        /* Aliases to 0x1098 */
 164 #define SABRE_IMAP_EUPA_ALIAS   0x8000UL        /* Aliases to 0x10a0 */
 165 #define SABRE_IOMMU_VADIAG      0xa400UL
 166 #define SABRE_IOMMU_TCDIAG      0xa408UL
 167 #define SABRE_IOMMU_TAG         0xa580UL
 168 #define  SABRE_IOMMUTAG_ERRSTS   0x0000000001800000UL   /* Error status bits */
 169 #define  SABRE_IOMMUTAG_ERR      0x0000000000400000UL   /* Error present */
 170 #define  SABRE_IOMMUTAG_WRITE    0x0000000000200000UL   /* Page is writable */
 171 #define  SABRE_IOMMUTAG_STREAM   0x0000000000100000UL   /* Streamable bit - unused */
 172 #define  SABRE_IOMMUTAG_SIZE     0x0000000000080000UL   /* 0=8k 1=16k */
 173 #define  SABRE_IOMMUTAG_VPN      0x000000000007ffffUL   /* Virtual Page Number [31:13] */
 174 #define SABRE_IOMMU_DATA        0xa600UL
 175 #define SABRE_IOMMUDATA_VALID    0x0000000040000000UL   /* Valid */
 176 #define SABRE_IOMMUDATA_USED     0x0000000020000000UL   /* Used (for LRU algorithm) */
 177 #define SABRE_IOMMUDATA_CACHE    0x0000000010000000UL   /* Cacheable */
 178 #define SABRE_IOMMUDATA_PPN      0x00000000001fffffUL   /* Physical Page Number [33:13] */
 179 #define SABRE_PCI_IRQSTATE      0xa800UL
 180 #define SABRE_OBIO_IRQSTATE     0xa808UL
 181 #define SABRE_FFBCFG            0xf000UL
 182 #define  SABRE_FFBCFG_SPRQS      0x000000000f000000     /* Slave P_RQST queue size */
 183 #define  SABRE_FFBCFG_ONEREAD    0x0000000000004000     /* Slave supports one outstanding read */
 184 #define SABRE_MCCTRL0           0xf010UL
 185 #define  SABRE_MCCTRL0_RENAB     0x0000000080000000     /* Refresh Enable */
 186 #define  SABRE_MCCTRL0_EENAB     0x0000000010000000     /* Enable all ECC functions */
 187 #define  SABRE_MCCTRL0_11BIT     0x0000000000001000     /* Enable 11-bit column addressing */
 188 #define  SABRE_MCCTRL0_DPP       0x0000000000000f00     /* DIMM Pair Present Bits */
 189 #define  SABRE_MCCTRL0_RINTVL    0x00000000000000ff     /* Refresh Interval */
 190 #define SABRE_MCCTRL1           0xf018UL
 191 #define  SABRE_MCCTRL1_AMDC      0x0000000038000000     /* Advance Memdata Clock */
 192 #define  SABRE_MCCTRL1_ARDC      0x0000000007000000     /* Advance DRAM Read Data Clock */
 193 #define  SABRE_MCCTRL1_CSR       0x0000000000e00000     /* CAS to RAS delay for CBR refresh */
 194 #define  SABRE_MCCTRL1_CASRW     0x00000000001c0000     /* CAS length for read/write */
 195 #define  SABRE_MCCTRL1_RCD       0x0000000000038000     /* RAS to CAS delay */
 196 #define  SABRE_MCCTRL1_CP        0x0000000000007000     /* CAS Precharge */
 197 #define  SABRE_MCCTRL1_RP        0x0000000000000e00     /* RAS Precharge */
 198 #define  SABRE_MCCTRL1_RAS       0x00000000000001c0     /* Length of RAS for refresh */
 199 #define  SABRE_MCCTRL1_CASRW2    0x0000000000000038     /* Must be same as CASRW */
 200 #define  SABRE_MCCTRL1_RSC       0x0000000000000007     /* RAS after CAS hold time */
 201 #define SABRE_RESETCTRL         0xf020UL
 202
 203 #define SABRE_CONFIGSPACE       0x001000000UL
 204 #define SABRE_IOSPACE           0x002000000UL
 205 #define SABRE_IOSPACE_SIZE      0x000ffffffUL
 206 #define SABRE_MEMSPACE          0x100000000UL
 207 #define SABRE_MEMSPACE_SIZE     0x07fffffffUL
 208
 209 /* UltraSparc-IIi Programmer's Manual, page 325, PCI
 210  * configuration space address format:
 211  *
 212  *  32             24 23 16 15    11 10       8 7   2  1 0
 213  * ---------------------------------------------------------
 214  * |0 0 0 0 0 0 0 0 1| bus | device | function | reg | 0 0 |
 215  * ---------------------------------------------------------
 216  */
 217 #define SABRE_CONFIG_BASE(PBM)  \
 218         ((PBM)->config_space | (1UL << 24))
 219 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG)    \
 220         (((unsigned long)(BUS)   << 16) |       \
 221          ((unsigned long)(DEVFN) << 8)  |       \
 222          ((unsigned long)(REG)))
 223
 224 static int hummingbird_p;
 225 static struct pci_bus *sabre_root_bus;
 226
 227 static void *sabre_pci_config_mkaddr(struct pci_pbm_info *pbm,
 228                                      unsigned char bus,
 229                                      unsigned int devfn,
 230                                      int where)
 231 {
 232         if (!pbm)
 233                 return NULL;
 234         return (void *)
 235                 (SABRE_CONFIG_BASE(pbm) |
 236                  SABRE_CONFIG_ENCODE(bus, devfn, where));
 237 }
 238
 239 static int sabre_out_of_range(unsigned char devfn)
 240 {
 241         if (hummingbird_p)
 242                 return 0;
 243
 244         return (((PCI_SLOT(devfn) == 0) && (PCI_FUNC(devfn) > 0)) ||
 245                 ((PCI_SLOT(devfn) == 1) && (PCI_FUNC(devfn) > 1)) ||
 246                 (PCI_SLOT(devfn) > 1));
 247 }
 248
 249 static int __sabre_out_of_range(struct pci_pbm_info *pbm,
 250                                 unsigned char bus,
 251                                 unsigned char devfn)
 252 {
 253         if (hummingbird_p)
 254                 return 0;
 255
 256         return ((pbm->parent == 0) ||
 257                 ((pbm == &pbm->parent->pbm_B) &&
 258                  (bus == pbm->pci_first_busno) &&
 259                  PCI_SLOT(devfn) > 8) ||
 260                 ((pbm == &pbm->parent->pbm_A) &&
 261                  (bus == pbm->pci_first_busno) &&
 262                  PCI_SLOT(devfn) > 8));
 263 }
 264
 265 static int __sabre_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 266                                 int where, int size, u32 *value)
 267 {
 268         struct pci_pbm_info *pbm = bus_dev->sysdata;
 269         unsigned char bus = bus_dev->number;
 270         u32 *addr;
 271         u16 tmp16;
 272         u8 tmp8;
 273
 274         switch (size) {
 275         case 1:
 276                 *value = 0xff;
 277                 break;
 278         case 2:
 279                 *value = 0xffff;
 280                 break;
 281         case 4:
 282                 *value = 0xffffffff;
 283                 break;
 284         }
 285
 286         addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
 287         if (!addr)
 288                 return PCIBIOS_SUCCESSFUL;
 289
 290         if (__sabre_out_of_range(pbm, bus, devfn))
 291                 return PCIBIOS_SUCCESSFUL;
 292
 293         switch (size) {
 294         case 1:
 295                 pci_config_read8((u8 *) addr, &tmp8);
 296                 *value = tmp8;
 297                 break;
 298
 299         case 2:
 300                 if (where & 0x01) {
 301                         printk("pci_read_config_word: misaligned reg [%x]\n",
 302                                where);
 303                         return PCIBIOS_SUCCESSFUL;
 304                 }
 305                 pci_config_read16((u16 *) addr, &tmp16);
 306                 *value = tmp16;
 307                 break;
 308
 309         case 4:
 310                 if (where & 0x03) {
 311                         printk("pci_read_config_dword: misaligned reg [%x]\n",
 312                                where);
 313                         return PCIBIOS_SUCCESSFUL;
 314                 }
 315                 pci_config_read32(addr, value);
 316                 break;
 317         }
 318
 319         return PCIBIOS_SUCCESSFUL;
 320 }
 321
 322 static int sabre_read_pci_cfg(struct pci_bus *bus, unsigned int devfn,
 323                               int where, int size, u32 *value)
 324 {
 325         if (!bus->number && sabre_out_of_range(devfn)) {
 326                 switch (size) {
 327                 case 1:
 328                         *value = 0xff;
 329                         break;
 330                 case 2:
 331                         *value = 0xffff;
 332                         break;
 333                 case 4:
 334                         *value = 0xffffffff;
 335                         break;
 336                 }
 337                 return PCIBIOS_SUCCESSFUL;
 338         }
 339
 340         if (bus->number || PCI_SLOT(devfn))
 341                 return __sabre_read_pci_cfg(bus, devfn, where, size, value);
 342
 343         /* When accessing PCI config space of the PCI controller itself (bus
 344          * 0, device slot 0, function 0) there are restrictions.  Each
 345          * register must be accessed as it's natural size.  Thus, for example
 346          * the Vendor ID must be accessed as a 16-bit quantity.
 347          */
 348
 349         switch (size) {
 350         case 1:
 351                 if (where < 8) {
 352                         u32 tmp32;
 353                         u16 tmp16;
 354
 355                         __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
 356                         tmp16 = (u16) tmp32;
 357                         if (where & 1)
 358                                 *value = tmp16 >> 8;
 359                         else
 360                                 *value = tmp16 & 0xff;
 361                 } else
 362                         return __sabre_read_pci_cfg(bus, devfn, where, 1, value);
 363                 break;
 364
 365         case 2:
 366                 if (where < 8)
 367                         return __sabre_read_pci_cfg(bus, devfn, where, 2, value);
 368                 else {
 369                         u32 tmp32;
 370                         u8 tmp8;
 371
 372                         __sabre_read_pci_cfg(bus, devfn, where, 1, &tmp32);
 373                         tmp8 = (u8) tmp32;
 374                         *value = tmp8;
 375                         __sabre_read_pci_cfg(bus, devfn, where + 1, 1, &tmp32);
 376                         tmp8 = (u8) tmp32;
 377                         *value |= tmp8 << 8;
 378                 }
 379                 break;
 380
 381         case 4: {
 382                 u32 tmp32;
 383                 u16 tmp16;
 384
 385                 sabre_read_pci_cfg(bus, devfn, where, 2, &tmp32);
 386                 tmp16 = (u16) tmp32;
 387                 *value = tmp16;
 388                 sabre_read_pci_cfg(bus, devfn, where + 2, 2, &tmp32);
 389                 tmp16 = (u16) tmp32;
 390                 *value |= tmp16 << 16;
 391                 break;
 392         }
 393         }
 394         return PCIBIOS_SUCCESSFUL;
 395 }
 396
 397 static int __sabre_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
 398                                  int where, int size, u32 value)
 399 {
 400         struct pci_pbm_info *pbm = bus_dev->sysdata;
 401         unsigned char bus = bus_dev->number;
 402         u32 *addr;
 403
 404         addr = sabre_pci_config_mkaddr(pbm, bus, devfn, where);
 405         if (!addr)
 406                 return PCIBIOS_SUCCESSFUL;
 407
 408         if (__sabre_out_of_range(pbm, bus, devfn))
 409                 return PCIBIOS_SUCCESSFUL;
 410
 411         switch (size) {
 412         case 1:
 413                 pci_config_write8((u8 *) addr, value);
 414                 break;
 415
 416         case 2:
 417                 if (where & 0x01) {
 418                         printk("pci_write_config_word: misaligned reg [%x]\n",
 419                                where);
 420                         return PCIBIOS_SUCCESSFUL;
 421                 }
 422                 pci_config_write16((u16 *) addr, value);
 423                 break;
 424
 425         case 4:
 426                 if (where & 0x03) {
 427                         printk("pci_write_config_dword: misaligned reg [%x]\n",
 428                                where);
 429                         return PCIBIOS_SUCCESSFUL;
 430                 }
 431                 pci_config_write32(addr, value);
 432                 break;
 433         }
 434
 435         return PCIBIOS_SUCCESSFUL;
 436 }
 437
 438 static int sabre_write_pci_cfg(struct pci_bus *bus, unsigned int devfn,
 439                                int where, int size, u32 value)
 440 {
 441         if (bus->number)
 442                 return __sabre_write_pci_cfg(bus, devfn, where, size, value);
 443
 444         if (sabre_out_of_range(devfn))
 445                 return PCIBIOS_SUCCESSFUL;
 446
 447         switch (size) {
 448         case 1:
 449                 if (where < 8) {
 450                         u32 tmp32;
 451                         u16 tmp16;
 452
 453                         __sabre_read_pci_cfg(bus, devfn, where & ~1, 2, &tmp32);
 454                         tmp16 = (u16) tmp32;
 455                         if (where & 1) {
 456                                 value &= 0x00ff;
 457                                 value |= tmp16 << 8;
 458                         } else {
 459                                 value &= 0xff00;
 460                                 value |= tmp16;
 461                         }
 462                         tmp32 = (u32) tmp16;
 463                         return __sabre_write_pci_cfg(bus, devfn, where & ~1, 2, tmp32);
 464                 } else
 465                         return __sabre_write_pci_cfg(bus, devfn, where, 1, value);
 466                 break;
 467         case 2:
 468                 if (where < 8)
 469                         return __sabre_write_pci_cfg(bus, devfn, where, 2, value);
 470                 else {
 471                         __sabre_write_pci_cfg(bus, devfn, where, 1, value & 0xff);
 472                         __sabre_write_pci_cfg(bus, devfn, where + 1, 1, value >> 8);
 473                 }
 474                 break;
 475         case 4:
 476                 sabre_write_pci_cfg(bus, devfn, where, 2, value & 0xffff);
 477                 sabre_write_pci_cfg(bus, devfn, where + 2, 2, value >> 16);
 478                 break;
 479         }
 480         return PCIBIOS_SUCCESSFUL;
 481 }
 482
 483 static struct pci_ops sabre_ops = {
 484         .read =         sabre_read_pci_cfg,
 485         .write =        sabre_write_pci_cfg,
 486 };
 487
 488 static unsigned long sabre_pcislot_imap_offset(unsigned long ino)
 489 {
 490         unsigned int bus =  (ino & 0x10) >> 4;
 491         unsigned int slot = (ino & 0x0c) >> 2;
 492
 493         if (bus == 0)
 494                 return SABRE_IMAP_A_SLOT0 + (slot * 8);
 495         else
 496                 return SABRE_IMAP_B_SLOT0 + (slot * 8);
 497 }
 498
 499 static unsigned long __onboard_imap_off[] = {
 500 /*0x20*/        SABRE_IMAP_SCSI,
 501 /*0x21*/        SABRE_IMAP_ETH,
 502 /*0x22*/        SABRE_IMAP_BPP,
 503 /*0x23*/        SABRE_IMAP_AU_REC,
 504 /*0x24*/        SABRE_IMAP_AU_PLAY,
 505 /*0x25*/        SABRE_IMAP_PFAIL,
 506 /*0x26*/        SABRE_IMAP_KMS,
 507 /*0x27*/        SABRE_IMAP_FLPY,
 508 /*0x28*/        SABRE_IMAP_SHW,
 509 /*0x29*/        SABRE_IMAP_KBD,
 510 /*0x2a*/        SABRE_IMAP_MS,
 511 /*0x2b*/        SABRE_IMAP_SER,
 512 /*0x2c*/        0 /* reserved */,
 513 /*0x2d*/        0 /* reserved */,
 514 /*0x2e*/        SABRE_IMAP_UE,
 515 /*0x2f*/        SABRE_IMAP_CE,
 516 /*0x30*/        SABRE_IMAP_PCIERR,
 517 };
 518 #define SABRE_ONBOARD_IRQ_BASE          0x20
 519 #define SABRE_ONBOARD_IRQ_LAST          0x30
 520 #define sabre_onboard_imap_offset(__ino) \
 521         __onboard_imap_off[(__ino) - SABRE_ONBOARD_IRQ_BASE]
 522
 523 #define sabre_iclr_offset(ino)                                        \
 524         ((ino & 0x20) ? (SABRE_ICLR_SCSI + (((ino) & 0x1f) << 3)) :  \
 525                         (SABRE_ICLR_A_SLOT0 + (((ino) & 0x1f)<<3)))
 526
 527 /* When a device lives behind a bridge deeper in the PCI bus topology
 528  * than APB, a special sequence must run to make sure all pending DMA
 529  * transfers at the time of IRQ delivery are visible in the coherency
 530  * domain by the cpu.  This sequence is to perform a read on the far
 531  * side of the non-APB bridge, then perform a read of Sabre's DMA
 532  * write-sync register.
 533  */
 534 static void sabre_wsync_handler(unsigned int ino, void *_arg1, void *_arg2)
 535 {
 536         struct pci_dev *pdev = _arg1;
 537         unsigned long sync_reg = (unsigned long) _arg2;
 538         u16 _unused;
 539
 540         pci_read_config_word(pdev, PCI_VENDOR_ID, &_unused);
 541         sabre_read(sync_reg);
 542 }
 543
 544 static unsigned int sabre_irq_build(struct pci_pbm_info *pbm,
 545                                     struct pci_dev *pdev,
 546                                     unsigned int ino)
 547 {
 548         unsigned long imap, iclr;
 549         unsigned long imap_off, iclr_off;
 550         int inofixup = 0;
 551         int virt_irq;
 552
 553         ino &= PCI_IRQ_INO;
 554         if (ino < SABRE_ONBOARD_IRQ_BASE) {
 555                 /* PCI slot */
 556                 imap_off = sabre_pcislot_imap_offset(ino);
 557         } else {
 558                 /* onboard device */
 559                 if (ino > SABRE_ONBOARD_IRQ_LAST) {
 560                         prom_printf("sabre_irq_build: Wacky INO [%x]\n", ino);
 561                         prom_halt();
 562                 }
 563                 imap_off = sabre_onboard_imap_offset(ino);
 564         }
 565
 566         /* Now build the IRQ bucket. */
 567         imap = pbm->controller_regs + imap_off;
 568         imap += 4;
 569
 570         iclr_off = sabre_iclr_offset(ino);
 571         iclr = pbm->controller_regs + iclr_off;
 572         iclr += 4;
 573
 574         if ((ino & 0x20) == 0)
 575                 inofixup = ino & 0x03;
 576
 577         virt_irq = build_irq(inofixup, iclr, imap);
 578
 579         if (pdev) {
 580                 struct pcidev_cookie *pcp = pdev->sysdata;
 581
 582                 if (pdev->bus->number != pcp->pbm->pci_first_busno) {
 583                         struct pci_controller_info *p = pcp->pbm->parent;
 584
 585                         irq_install_pre_handler(virt_irq,
 586                                                 sabre_wsync_handler,
 587                                                 pdev,
 588                                                 (void *)
 589                                                 p->pbm_A.controller_regs +
 590                                                 SABRE_WRSYNC);
 591                 }
 592         }
 593         return virt_irq;
 594 }
 595
 596 /* SABRE error handling support. */
 597 static void sabre_check_iommu_error(struct pci_controller_info *p,
 598                                     unsigned long afsr,
 599                                     unsigned long afar)
 600 {
 601         struct pci_iommu *iommu = p->pbm_A.iommu;
 602         unsigned long iommu_tag[16];
 603         unsigned long iommu_data[16];
 604         unsigned long flags;
 605         u64 control;
 606         int i;
 607
 608         spin_lock_irqsave(&iommu->lock, flags);
 609         control = sabre_read(iommu->iommu_control);
 610         if (control & SABRE_IOMMUCTRL_ERR) {
 611                 char *type_string;
 612
 613                 /* Clear the error encountered bit.
 614                  * NOTE: On Sabre this is write 1 to clear,
 615                  *       which is different from Psycho.
 616                  */
 617                 sabre_write(iommu->iommu_control, control);
 618                 switch((control & SABRE_IOMMUCTRL_ERRSTS) >> 25UL) {
 619                 case 1:
 620                         type_string = "Invalid Error";
 621                         break;
 622                 case 3:
 623                         type_string = "ECC Error";
 624                         break;
 625                 default:
 626                         type_string = "Unknown";
 627                         break;
 628                 };
 629                 printk("SABRE%d: IOMMU Error, type[%s]\n",
 630                        p->index, type_string);
 631
 632                 /* Enter diagnostic mode and probe for error'd
 633                  * entries in the IOTLB.
 634                  */
 635                 control &= ~(SABRE_IOMMUCTRL_ERRSTS | SABRE_IOMMUCTRL_ERR);
 636                 sabre_write(iommu->iommu_control,
 637                             (control | SABRE_IOMMUCTRL_DENAB));
 638                 for (i = 0; i < 16; i++) {
 639                         unsigned long base = p->pbm_A.controller_regs;
 640
 641                         iommu_tag[i] =
 642                                 sabre_read(base + SABRE_IOMMU_TAG + (i * 8UL));
 643                         iommu_data[i] =
 644                                 sabre_read(base + SABRE_IOMMU_DATA + (i * 8UL));
 645                         sabre_write(base + SABRE_IOMMU_TAG + (i * 8UL), 0);
 646                         sabre_write(base + SABRE_IOMMU_DATA + (i * 8UL), 0);
 647                 }
 648                 sabre_write(iommu->iommu_control, control);
 649
 650                 for (i = 0; i < 16; i++) {
 651                         unsigned long tag, data;
 652
 653                         tag = iommu_tag[i];
 654                         if (!(tag & SABRE_IOMMUTAG_ERR))
 655                                 continue;
 656
 657                         data = iommu_data[i];
 658                         switch((tag & SABRE_IOMMUTAG_ERRSTS) >> 23UL) {
 659                         case 1:
 660                                 type_string = "Invalid Error";
 661                                 break;
 662                         case 3:
 663                                 type_string = "ECC Error";
 664                                 break;
 665                         default:
 666                                 type_string = "Unknown";
 667                                 break;
 668                         };
 669                         printk("SABRE%d: IOMMU TAG(%d)[RAW(%016lx)error(%s)wr(%d)sz(%dK)vpg(%08lx)]\n",
 670                                p->index, i, tag, type_string,
 671                                ((tag & SABRE_IOMMUTAG_WRITE) ? 1 : 0),
 672                                ((tag & SABRE_IOMMUTAG_SIZE) ? 64 : 8),
 673                                ((tag & SABRE_IOMMUTAG_VPN) << IOMMU_PAGE_SHIFT));
 674                         printk("SABRE%d: IOMMU DATA(%d)[RAW(%016lx)valid(%d)used(%d)cache(%d)ppg(%016lx)\n",
 675                                p->index, i, data,
 676                                ((data & SABRE_IOMMUDATA_VALID) ? 1 : 0),
 677                                ((data & SABRE_IOMMUDATA_USED) ? 1 : 0),
 678                                ((data & SABRE_IOMMUDATA_CACHE) ? 1 : 0),
 679                                ((data & SABRE_IOMMUDATA_PPN) << IOMMU_PAGE_SHIFT));
 680                 }
 681         }
 682         spin_unlock_irqrestore(&iommu->lock, flags);
 683 }
 684
 685 static irqreturn_t sabre_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
 686 {
 687         struct pci_controller_info *p = dev_id;
 688         unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_UE_AFSR;
 689         unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
 690         unsigned long afsr, afar, error_bits;
 691         int reported;
 692
 693         /* Latch uncorrectable error status. */
 694         afar = sabre_read(afar_reg);
 695         afsr = sabre_read(afsr_reg);
 696
 697         /* Clear the primary/secondary error status bits. */
 698         error_bits = afsr &
 699                 (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 700                  SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 701                  SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE);
 702         if (!error_bits)
 703                 return IRQ_NONE;
 704         sabre_write(afsr_reg, error_bits);
 705
 706         /* Log the error. */
 707         printk("SABRE%d: Uncorrectable Error, primary error type[%s%s]\n",
 708                p->index,
 709                ((error_bits & SABRE_UEAFSR_PDRD) ?
 710                 "DMA Read" :
 711                 ((error_bits & SABRE_UEAFSR_PDWR) ?
 712                  "DMA Write" : "???")),
 713                ((error_bits & SABRE_UEAFSR_PDTE) ?
 714                 ":Translation Error" : ""));
 715         printk("SABRE%d: bytemask[%04lx] dword_offset[%lx] was_block(%d)\n",
 716                p->index,
 717                (afsr & SABRE_UEAFSR_BMSK) >> 32UL,
 718                (afsr & SABRE_UEAFSR_OFF) >> 29UL,
 719                ((afsr & SABRE_UEAFSR_BLK) ? 1 : 0));
 720         printk("SABRE%d: UE AFAR [%016lx]\n", p->index, afar);
 721         printk("SABRE%d: UE Secondary errors [", p->index);
 722         reported = 0;
 723         if (afsr & SABRE_UEAFSR_SDRD) {
 724                 reported++;
 725                 printk("(DMA Read)");
 726         }
 727         if (afsr & SABRE_UEAFSR_SDWR) {
 728                 reported++;
 729                 printk("(DMA Write)");
 730         }
 731         if (afsr & SABRE_UEAFSR_SDTE) {
 732                 reported++;
 733                 printk("(Translation Error)");
 734         }
 735         if (!reported)
 736                 printk("(none)");
 737         printk("]\n");
 738
 739         /* Interrogate IOMMU for error status. */
 740         sabre_check_iommu_error(p, afsr, afar);
 741
 742         return IRQ_HANDLED;
 743 }
 744
 745 static irqreturn_t sabre_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
 746 {
 747         struct pci_controller_info *p = dev_id;
 748         unsigned long afsr_reg = p->pbm_A.controller_regs + SABRE_CE_AFSR;
 749         unsigned long afar_reg = p->pbm_A.controller_regs + SABRE_UECE_AFAR;
 750         unsigned long afsr, afar, error_bits;
 751         int reported;
 752
 753         /* Latch error status. */
 754         afar = sabre_read(afar_reg);
 755         afsr = sabre_read(afsr_reg);
 756
 757         /* Clear primary/secondary error status bits. */
 758         error_bits = afsr &
 759                 (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 760                  SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR);
 761         if (!error_bits)
 762                 return IRQ_NONE;
 763         sabre_write(afsr_reg, error_bits);
 764
 765         /* Log the error. */
 766         printk("SABRE%d: Correctable Error, primary error type[%s]\n",
 767                p->index,
 768                ((error_bits & SABRE_CEAFSR_PDRD) ?
 769                 "DMA Read" :
 770                 ((error_bits & SABRE_CEAFSR_PDWR) ?
 771                  "DMA Write" : "???")));
 772
 773         /* XXX Use syndrome and afar to print out module string just like
 774          * XXX UDB CE trap handler does... -DaveM
 775          */
 776         printk("SABRE%d: syndrome[%02lx] bytemask[%04lx] dword_offset[%lx] "
 777                "was_block(%d)\n",
 778                p->index,
 779                (afsr & SABRE_CEAFSR_ESYND) >> 48UL,
 780                (afsr & SABRE_CEAFSR_BMSK) >> 32UL,
 781                (afsr & SABRE_CEAFSR_OFF) >> 29UL,
 782                ((afsr & SABRE_CEAFSR_BLK) ? 1 : 0));
 783         printk("SABRE%d: CE AFAR [%016lx]\n", p->index, afar);
 784         printk("SABRE%d: CE Secondary errors [", p->index);
 785         reported = 0;
 786         if (afsr & SABRE_CEAFSR_SDRD) {
 787                 reported++;
 788                 printk("(DMA Read)");
 789         }
 790         if (afsr & SABRE_CEAFSR_SDWR) {
 791                 reported++;
 792                 printk("(DMA Write)");
 793         }
 794         if (!reported)
 795                 printk("(none)");
 796         printk("]\n");
 797
 798         return IRQ_HANDLED;
 799 }
 800
 801 static irqreturn_t sabre_pcierr_intr_other(struct pci_controller_info *p)
 802 {
 803         unsigned long csr_reg, csr, csr_error_bits;
 804         irqreturn_t ret = IRQ_NONE;
 805         u16 stat;
 806
 807         csr_reg = p->pbm_A.controller_regs + SABRE_PCICTRL;
 808         csr = sabre_read(csr_reg);
 809         csr_error_bits =
 810                 csr & SABRE_PCICTRL_SERR;
 811         if (csr_error_bits) {
 812                 /* Clear the errors.  */
 813                 sabre_write(csr_reg, csr);
 814
 815                 /* Log 'em.  */
 816                 if (csr_error_bits & SABRE_PCICTRL_SERR)
 817                         printk("SABRE%d: PCI SERR signal asserted.\n",
 818                                p->index);
 819                 ret = IRQ_HANDLED;
 820         }
 821         pci_read_config_word(sabre_root_bus->self,
 822                              PCI_STATUS, &stat);
 823         if (stat & (PCI_STATUS_PARITY |
 824                     PCI_STATUS_SIG_TARGET_ABORT |
 825                     PCI_STATUS_REC_TARGET_ABORT |
 826                     PCI_STATUS_REC_MASTER_ABORT |
 827                     PCI_STATUS_SIG_SYSTEM_ERROR)) {
 828                 printk("SABRE%d: PCI bus error, PCI_STATUS[%04x]\n",
 829                        p->index, stat);
 830                 pci_write_config_word(sabre_root_bus->self,
 831                                       PCI_STATUS, 0xffff);
 832                 ret = IRQ_HANDLED;
 833         }
 834         return ret;
 835 }
 836
 837 static irqreturn_t sabre_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
 838 {
 839         struct pci_controller_info *p = dev_id;
 840         unsigned long afsr_reg, afar_reg;
 841         unsigned long afsr, afar, error_bits;
 842         int reported;
 843
 844         afsr_reg = p->pbm_A.controller_regs + SABRE_PIOAFSR;
 845         afar_reg = p->pbm_A.controller_regs + SABRE_PIOAFAR;
 846
 847         /* Latch error status. */
 848         afar = sabre_read(afar_reg);
 849         afsr = sabre_read(afsr_reg);
 850
 851         /* Clear primary/secondary error status bits. */
 852         error_bits = afsr &
 853                 (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_PTA |
 854                  SABRE_PIOAFSR_PRTRY | SABRE_PIOAFSR_PPERR |
 855                  SABRE_PIOAFSR_SMA | SABRE_PIOAFSR_STA |
 856                  SABRE_PIOAFSR_SRTRY | SABRE_PIOAFSR_SPERR);
 857         if (!error_bits)
 858                 return sabre_pcierr_intr_other(p);
 859         sabre_write(afsr_reg, error_bits);
 860
 861         /* Log the error. */
 862         printk("SABRE%d: PCI Error, primary error type[%s]\n",
 863                p->index,
 864                (((error_bits & SABRE_PIOAFSR_PMA) ?
 865                  "Master Abort" :
 866                  ((error_bits & SABRE_PIOAFSR_PTA) ?
 867                   "Target Abort" :
 868                   ((error_bits & SABRE_PIOAFSR_PRTRY) ?
 869                    "Excessive Retries" :
 870                    ((error_bits & SABRE_PIOAFSR_PPERR) ?
 871                     "Parity Error" : "???"))))));
 872         printk("SABRE%d: bytemask[%04lx] was_block(%d)\n",
 873                p->index,
 874                (afsr & SABRE_PIOAFSR_BMSK) >> 32UL,
 875                (afsr & SABRE_PIOAFSR_BLK) ? 1 : 0);
 876         printk("SABRE%d: PCI AFAR [%016lx]\n", p->index, afar);
 877         printk("SABRE%d: PCI Secondary errors [", p->index);
 878         reported = 0;
 879         if (afsr & SABRE_PIOAFSR_SMA) {
 880                 reported++;
 881                 printk("(Master Abort)");
 882         }
 883         if (afsr & SABRE_PIOAFSR_STA) {
 884                 reported++;
 885                 printk("(Target Abort)");
 886         }
 887         if (afsr & SABRE_PIOAFSR_SRTRY) {
 888                 reported++;
 889                 printk("(Excessive Retries)");
 890         }
 891         if (afsr & SABRE_PIOAFSR_SPERR) {
 892                 reported++;
 893                 printk("(Parity Error)");
 894         }
 895         if (!reported)
 896                 printk("(none)");
 897         printk("]\n");
 898
 899         /* For the error types shown, scan both PCI buses for devices
 900          * which have logged that error type.
 901          */
 902
 903         /* If we see a Target Abort, this could be the result of an
 904          * IOMMU translation error of some sort.  It is extremely
 905          * useful to log this information as usually it indicates
 906          * a bug in the IOMMU support code or a PCI device driver.
 907          */
 908         if (error_bits & (SABRE_PIOAFSR_PTA | SABRE_PIOAFSR_STA)) {
 909                 sabre_check_iommu_error(p, afsr, afar);
 910                 pci_scan_for_target_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
 911                 pci_scan_for_target_abort(p, &p->pbm_B, p->pbm_B.pci_bus);
 912         }
 913         if (error_bits & (SABRE_PIOAFSR_PMA | SABRE_PIOAFSR_SMA)) {
 914                 pci_scan_for_master_abort(p, &p->pbm_A, p->pbm_A.pci_bus);
 915                 pci_scan_for_master_abort(p, &p->pbm_B, p->pbm_B.pci_bus);
 916         }
 917         /* For excessive retries, SABRE/PBM will abort the device
 918          * and there is no way to specifically check for excessive
 919          * retries in the config space status registers.  So what
 920          * we hope is that we'll catch it via the master/target
 921          * abort events.
 922          */
 923
 924         if (error_bits & (SABRE_PIOAFSR_PPERR | SABRE_PIOAFSR_SPERR)) {
 925                 pci_scan_for_parity_error(p, &p->pbm_A, p->pbm_A.pci_bus);
 926                 pci_scan_for_parity_error(p, &p->pbm_B, p->pbm_B.pci_bus);
 927         }
 928
 929         return IRQ_HANDLED;
 930 }
 931
 932 /* XXX What about PowerFail/PowerManagement??? -DaveM */
 933 #define SABRE_UE_INO            0x2e
 934 #define SABRE_CE_INO            0x2f
 935 #define SABRE_PCIERR_INO        0x30
 936 static void sabre_register_error_handlers(struct pci_controller_info *p)
 937 {
 938         struct pci_pbm_info *pbm = &p->pbm_A; /* arbitrary */
 939         unsigned long base = pbm->controller_regs;
 940         unsigned long irq, portid = pbm->portid;
 941         u64 tmp;
 942
 943         /* We clear the error bits in the appropriate AFSR before
 944          * registering the handler so that we don't get spurious
 945          * interrupts.
 946          */
 947         sabre_write(base + SABRE_UE_AFSR,
 948                     (SABRE_UEAFSR_PDRD | SABRE_UEAFSR_PDWR |
 949                      SABRE_UEAFSR_SDRD | SABRE_UEAFSR_SDWR |
 950                      SABRE_UEAFSR_SDTE | SABRE_UEAFSR_PDTE));
 951         irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_UE_INO);
 952         if (request_irq(irq, sabre_ue_intr,
 953                         SA_SHIRQ, "SABRE UE", p) < 0) {
 954                 prom_printf("SABRE%d: Cannot register UE interrupt.\n",
 955                             p->index);
 956                 prom_halt();
 957         }
 958
 959         sabre_write(base + SABRE_CE_AFSR,
 960                     (SABRE_CEAFSR_PDRD | SABRE_CEAFSR_PDWR |
 961                      SABRE_CEAFSR_SDRD | SABRE_CEAFSR_SDWR));
 962         irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_CE_INO);
 963         if (request_irq(irq, sabre_ce_intr,
 964                         SA_SHIRQ, "SABRE CE", p) < 0) {
 965                 prom_printf("SABRE%d: Cannot register CE interrupt.\n",
 966                             p->index);
 967                 prom_halt();
 968         }
 969
 970         irq = sabre_irq_build(pbm, NULL, (portid << 6) | SABRE_PCIERR_INO);
 971         if (request_irq(irq, sabre_pcierr_intr,
 972                         SA_SHIRQ, "SABRE PCIERR", p) < 0) {
 973                 prom_printf("SABRE%d: Cannot register PciERR interrupt.\n",
 974                             p->index);
 975                 prom_halt();
 976         }
 977
 978         tmp = sabre_read(base + SABRE_PCICTRL);
 979         tmp |= SABRE_PCICTRL_ERREN;
 980         sabre_write(base + SABRE_PCICTRL, tmp);
 981 }
 982
 983 static void sabre_resource_adjust(struct pci_dev *pdev,
 984                                   struct resource *res,
 985                                   struct resource *root)
 986 {
 987         struct pci_pbm_info *pbm = pdev->bus->sysdata;
 988         unsigned long base;
 989
 990         if (res->flags & IORESOURCE_IO)
 991                 base = pbm->controller_regs + SABRE_IOSPACE;
 992         else
 993                 base = pbm->controller_regs + SABRE_MEMSPACE;
 994
 995         res->start += base;
 996         res->end += base;
 997 }
 998
 999 static void sabre_base_address_update(struct pci_dev *pdev, int resource)
1000 {
1001         struct pcidev_cookie *pcp = pdev->sysdata;
1002         struct pci_pbm_info *pbm = pcp->pbm;
1003         struct resource *res;
1004         unsigned long base;
1005         u32 reg;
1006         int where, size, is_64bit;
1007
1008         res = &pdev->resource[resource];
1009         if (resource < 6) {
1010                 where = PCI_BASE_ADDRESS_0 + (resource * 4);
1011         } else if (resource == PCI_ROM_RESOURCE) {
1012                 where = pdev->rom_base_reg;
1013         } else {
1014                 /* Somebody might have asked allocation of a non-standard resource */
1015                 return;
1016         }
1017
1018         is_64bit = 0;
1019         if (res->flags & IORESOURCE_IO)
1020                 base = pbm->controller_regs + SABRE_IOSPACE;
1021         else {
1022                 base = pbm->controller_regs + SABRE_MEMSPACE;
1023                 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
1024                     == PCI_BASE_ADDRESS_MEM_TYPE_64)
1025                         is_64bit = 1;
1026         }
1027
1028         size = res->end - res->start;
1029         pci_read_config_dword(pdev, where, &reg);
1030         reg = ((reg & size) |
1031                (((u32)(res->start - base)) & ~size));
1032         if (resource == PCI_ROM_RESOURCE) {
1033                 reg |= PCI_ROM_ADDRESS_ENABLE;
1034                 res->flags |= IORESOURCE_ROM_ENABLE;
1035         }
1036         pci_write_config_dword(pdev, where, reg);
1037
1038         /* This knows that the upper 32-bits of the address
1039          * must be zero.  Our PCI common layer enforces this.
1040          */
1041         if (is_64bit)
1042                 pci_write_config_dword(pdev, where + 4, 0);
1043 }
1044
1045 static void apb_init(struct pci_controller_info *p, struct pci_bus *sabre_bus)
1046 {
1047         struct pci_dev *pdev;
1048
1049         list_for_each_entry(pdev, &sabre_bus->devices, bus_list) {
1050
1051                 if (pdev->vendor == PCI_VENDOR_ID_SUN &&
1052                     pdev->device == PCI_DEVICE_ID_SUN_SIMBA) {
1053                         u32 word32;
1054                         u16 word16;
1055
1056                         sabre_read_pci_cfg(pdev->bus, pdev->devfn,
1057                                            PCI_COMMAND, 2, &word32);
1058                         word16 = (u16) word32;
1059                         word16 |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
1060                                 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY |
1061                                 PCI_COMMAND_IO;
1062                         word32 = (u32) word16;
1063                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1064                                             PCI_COMMAND, 2, word32);
1065
1066                         /* Status register bits are "write 1 to clear". */
1067                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1068                                             PCI_STATUS, 2, 0xffff);
1069                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1070                                             PCI_SEC_STATUS, 2, 0xffff);
1071
1072                         /* Use a primary/seconday latency timer value
1073                          * of 64.
1074                          */
1075                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1076                                             PCI_LATENCY_TIMER, 1, 64);
1077                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1078                                             PCI_SEC_LATENCY_TIMER, 1, 64);
1079
1080                         /* Enable reporting/forwarding of master aborts,
1081                          * parity, and SERR.
1082                          */
1083                         sabre_write_pci_cfg(pdev->bus, pdev->devfn,
1084                                             PCI_BRIDGE_CONTROL, 1,
1085                                             (PCI_BRIDGE_CTL_PARITY |
1086                                              PCI_BRIDGE_CTL_SERR |
1087                                              PCI_BRIDGE_CTL_MASTER_ABORT));
1088                 }
1089         }
1090 }
1091
1092 static struct pcidev_cookie *alloc_bridge_cookie(struct pci_pbm_info *pbm)
1093 {
1094         struct pcidev_cookie *cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
1095
1096         if (!cookie) {
1097                 prom_printf("SABRE: Critical allocation failure.\n");
1098                 prom_halt();
1099         }
1100
1101         /* All we care about is the PBM. */
1102         cookie->pbm = pbm;
1103
1104         return cookie;
1105 }
1106
1107 static void sabre_scan_bus(struct pci_controller_info *p)
1108 {
1109         static int once;
1110         struct pci_bus *sabre_bus, *pbus;
1111         struct pci_pbm_info *pbm;
1112         struct pcidev_cookie *cookie;
1113         int sabres_scanned;
1114
1115         /* The APB bridge speaks to the Sabre host PCI bridge
1116          * at 66Mhz, but the front side of APB runs at 33Mhz
1117          * for both segments.
1118          */
1119         p->pbm_A.is_66mhz_capable = 0;
1120         p->pbm_B.is_66mhz_capable = 0;
1121
1122         /* This driver has not been verified to handle
1123          * multiple SABREs yet, so trap this.
1124          *
1125          * Also note that the SABRE host bridge is hardwired
1126          * to live at bus 0.
1127          */
1128         if (once != 0) {
1129                 prom_printf("SABRE: Multiple controllers unsupported.\n");
1130                 prom_halt();
1131         }
1132         once++;
1133
1134         cookie = alloc_bridge_cookie(&p->pbm_A);
1135
1136         sabre_bus = pci_scan_bus(p->pci_first_busno,
1137                                  p->pci_ops,
1138                                  &p->pbm_A);
1139         pci_fixup_host_bridge_self(sabre_bus);
1140         sabre_bus->self->sysdata = cookie;
1141
1142         sabre_root_bus = sabre_bus;
1143
1144         apb_init(p, sabre_bus);
1145
1146         sabres_scanned = 0;
1147
1148         list_for_each_entry(pbus, &sabre_bus->children, node) {
1149
1150                 if (pbus->number == p->pbm_A.pci_first_busno) {
1151                         pbm = &p->pbm_A;
1152                 } else if (pbus->number == p->pbm_B.pci_first_busno) {
1153                         pbm = &p->pbm_B;
1154                 } else
1155                         continue;
1156
1157                 cookie = alloc_bridge_cookie(pbm);
1158                 pbus->self->sysdata = cookie;
1159
1160                 sabres_scanned++;
1161
1162                 pbus->sysdata = pbm;
1163                 pbm->pci_bus = pbus;
1164                 pci_fill_in_pbm_cookies(pbus, pbm, pbm->prom_node);
1165                 pci_record_assignments(pbm, pbus);
1166                 pci_assign_unassigned(pbm, pbus);
1167                 pci_fixup_irq(pbm, pbus);
1168                 pci_determine_66mhz_disposition(pbm, pbus);
1169                 pci_setup_busmastering(pbm, pbus);
1170         }
1171
1172         if (!sabres_scanned) {
1173                 /* Hummingbird, no APBs. */
1174                 pbm = &p->pbm_A;
1175                 sabre_bus->sysdata = pbm;
1176                 pbm->pci_bus = sabre_bus;
1177                 pci_fill_in_pbm_cookies(sabre_bus, pbm, pbm->prom_node);
1178                 pci_record_assignments(pbm, sabre_bus);
1179                 pci_assign_unassigned(pbm, sabre_bus);
1180                 pci_fixup_irq(pbm, sabre_bus);
1181                 pci_determine_66mhz_disposition(pbm, sabre_bus);
1182                 pci_setup_busmastering(pbm, sabre_bus);
1183         }
1184
1185         sabre_register_error_handlers(p);
1186 }
1187
1188 static void sabre_iommu_init(struct pci_controller_info *p,
1189                              int tsbsize, unsigned long dvma_offset,
1190                              u32 dma_mask)
1191 {
1192         struct pci_iommu *iommu = p->pbm_A.iommu;
1193         unsigned long i;
1194         u64 control;
1195
1196         /* Register addresses. */
1197         iommu->iommu_control  = p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL;
1198         iommu->iommu_tsbbase  = p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE;
1199         iommu->iommu_flush    = p->pbm_A.controller_regs + SABRE_IOMMU_FLUSH;
1200         iommu->write_complete_reg = p->pbm_A.controller_regs + SABRE_WRSYNC;
1201         /* Sabre's IOMMU lacks ctx flushing. */
1202         iommu->iommu_ctxflush = 0;
1203
1204         /* Invalidate TLB Entries. */
1205         control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
1206         control |= SABRE_IOMMUCTRL_DENAB;
1207         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
1208
1209         for(i = 0; i < 16; i++) {
1210                 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TAG + (i * 8UL), 0);
1211                 sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_DATA + (i * 8UL), 0);
1212         }
1213
1214         /* Leave diag mode enabled for full-flushing done
1215          * in pci_iommu.c
1216          */
1217         pci_iommu_table_init(iommu, tsbsize * 1024 * 8, dvma_offset, dma_mask);
1218
1219         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_TSBBASE,
1220                     __pa(iommu->page_table));
1221
1222         control = sabre_read(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL);
1223         control &= ~(SABRE_IOMMUCTRL_TSBSZ | SABRE_IOMMUCTRL_TBWSZ);
1224         control |= SABRE_IOMMUCTRL_ENAB;
1225         switch(tsbsize) {
1226         case 64:
1227                 control |= SABRE_IOMMU_TSBSZ_64K;
1228                 break;
1229         case 128:
1230                 control |= SABRE_IOMMU_TSBSZ_128K;
1231                 break;
1232         default:
1233                 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
1234                 prom_halt();
1235                 break;
1236         }
1237         sabre_write(p->pbm_A.controller_regs + SABRE_IOMMU_CONTROL, control);
1238 }
1239
1240 static void pbm_register_toplevel_resources(struct pci_controller_info *p,
1241                                             struct pci_pbm_info *pbm)
1242 {
1243         char *name = pbm->name;
1244         unsigned long ibase = p->pbm_A.controller_regs + SABRE_IOSPACE;
1245         unsigned long mbase = p->pbm_A.controller_regs + SABRE_MEMSPACE;
1246         unsigned int devfn;
1247         unsigned long first, last, i;
1248         u8 *addr, map;
1249
1250         sprintf(name, "SABRE%d PBM%c",
1251                 p->index,
1252                 (pbm == &p->pbm_A ? 'A' : 'B'));
1253         pbm->io_space.name = pbm->mem_space.name = name;
1254
1255         devfn = PCI_DEVFN(1, (pbm == &p->pbm_A) ? 0 : 1);
1256         addr = sabre_pci_config_mkaddr(pbm, 0, devfn, APB_IO_ADDRESS_MAP);
1257         map = 0;
1258         pci_config_read8(addr, &map);
1259
1260         first = 8;
1261         last = 0;
1262         for (i = 0; i < 8; i++) {
1263                 if ((map & (1 << i)) != 0) {
1264                         if (first > i)
1265                                 first = i;
1266                         if (last < i)
1267                                 last = i;
1268                 }
1269         }
1270         pbm->io_space.start = ibase + (first << 21UL);
1271         pbm->io_space.end   = ibase + (last << 21UL) + ((1 << 21UL) - 1);
1272         pbm->io_space.flags = IORESOURCE_IO;
1273
1274         addr = sabre_pci_config_mkaddr(pbm, 0, devfn, APB_MEM_ADDRESS_MAP);
1275         map = 0;
1276         pci_config_read8(addr, &map);
1277
1278         first = 8;
1279         last = 0;
1280         for (i = 0; i < 8; i++) {
1281                 if ((map & (1 << i)) != 0) {
1282                         if (first > i)
1283                                 first = i;
1284                         if (last < i)
1285                                 last = i;
1286                 }
1287         }
1288         pbm->mem_space.start = mbase + (first << 29UL);
1289         pbm->mem_space.end   = mbase + (last << 29UL) + ((1 << 29UL) - 1);
1290         pbm->mem_space.flags = IORESOURCE_MEM;
1291
1292         if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
1293                 prom_printf("Cannot register PBM-%c's IO space.\n",
1294                             (pbm == &p->pbm_A ? 'A' : 'B'));
1295                 prom_halt();
1296         }
1297         if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
1298                 prom_printf("Cannot register PBM-%c's MEM space.\n",
1299                             (pbm == &p->pbm_A ? 'A' : 'B'));
1300                 prom_halt();
1301         }
1302
1303         /* Register legacy regions if this PBM covers that area. */
1304         if (pbm->io_space.start == ibase &&
1305             pbm->mem_space.start == mbase)
1306                 pci_register_legacy_regions(&pbm->io_space,
1307                                             &pbm->mem_space);
1308 }
1309
1310 static void sabre_pbm_init(struct pci_controller_info *p, struct device_node *dp, u32 dma_begin)
1311 {
1312         struct pci_pbm_info *pbm;
1313         struct device_node *node;
1314         struct property *prop;
1315         u32 *busrange;
1316         int len, simbas_found;
1317
1318         simbas_found = 0;
1319         node = dp->child;
1320         while (node != NULL) {
1321                 if (strcmp(node->name, "pci"))
1322                         goto next_pci;
1323
1324                 prop = of_find_property(node, "model", NULL);
1325                 if (!prop || strncmp(prop->value, "SUNW,simba", prop->length))
1326                         goto next_pci;
1327
1328                 simbas_found++;
1329
1330                 prop = of_find_property(node, "bus-range", NULL);
1331                 busrange = prop->value;
1332                 if (busrange[0] == 1)
1333                         pbm = &p->pbm_B;
1334                 else
1335                         pbm = &p->pbm_A;
1336
1337                 pbm->name = node->full_name;
1338                 printk("%s: SABRE PCI Bus Module\n", pbm->name);
1339
1340                 pbm->chip_type = PBM_CHIP_TYPE_SABRE;
1341                 pbm->parent = p;
1342                 pbm->prom_node = node;
1343                 pbm->pci_first_slot = 1;
1344                 pbm->pci_first_busno = busrange[0];
1345                 pbm->pci_last_busno = busrange[1];
1346
1347                 prop = of_find_property(node, "ranges", &len);
1348                 if (prop) {
1349                         pbm->pbm_ranges = prop->value;
1350                         pbm->num_pbm_ranges =
1351                                 (len / sizeof(struct linux_prom_pci_ranges));
1352                 } else {
1353                         pbm->num_pbm_ranges = 0;
1354                 }
1355
1356                 prop = of_find_property(node, "interrupt-map", &len);
1357                 if (prop) {
1358                         pbm->pbm_intmap = prop->value;
1359                         pbm->num_pbm_intmap =
1360                                 (len / sizeof(struct linux_prom_pci_intmap));
1361
1362                         prop = of_find_property(node, "interrupt-map-mask",
1363                                                 NULL);
1364                         pbm->pbm_intmask = prop->value;
1365                 } else {
1366                         pbm->num_pbm_intmap = 0;
1367                 }
1368
1369                 pbm_register_toplevel_resources(p, pbm);
1370
1371         next_pci:
1372                 node = node->sibling;
1373         }
1374         if (simbas_found == 0) {
1375                 /* No APBs underneath, probably this is a hummingbird
1376                  * system.
1377                  */
1378                 pbm = &p->pbm_A;
1379                 pbm->parent = p;
1380                 pbm->prom_node = dp;
1381                 pbm->pci_first_busno = p->pci_first_busno;
1382                 pbm->pci_last_busno = p->pci_last_busno;
1383
1384                 prop = of_find_property(dp, "ranges", &len);
1385                 if (prop) {
1386                         pbm->pbm_ranges = prop->value;
1387                         pbm->num_pbm_ranges =
1388                                 (len / sizeof(struct linux_prom_pci_ranges));
1389                 } else {
1390                         pbm->num_pbm_ranges = 0;
1391                 }
1392
1393                 prop = of_find_property(dp, "interrupt-map", &len);
1394                 if (prop) {
1395                         pbm->pbm_intmap = prop->value;
1396                         pbm->num_pbm_intmap =
1397                                 (len / sizeof(struct linux_prom_pci_intmap));
1398
1399                         prop = of_find_property(dp, "interrupt-map-mask",
1400                                                 NULL);
1401                         pbm->pbm_intmask = prop->value;
1402                 } else {
1403                         pbm->num_pbm_intmap = 0;
1404                 }
1405
1406                 pbm->name = dp->full_name;
1407                 printk("%s: SABRE PCI Bus Module\n", pbm->name);
1408
1409                 pbm->io_space.name = pbm->mem_space.name = pbm->name;
1410
1411                 /* Hack up top-level resources. */
1412                 pbm->io_space.start = p->pbm_A.controller_regs + SABRE_IOSPACE;
1413                 pbm->io_space.end   = pbm->io_space.start + (1UL << 24) - 1UL;
1414                 pbm->io_space.flags = IORESOURCE_IO;
1415
1416                 pbm->mem_space.start = p->pbm_A.controller_regs + SABRE_MEMSPACE;
1417                 pbm->mem_space.end   = pbm->mem_space.start + (unsigned long)dma_begin - 1UL;
1418                 pbm->mem_space.flags = IORESOURCE_MEM;
1419
1420                 if (request_resource(&ioport_resource, &pbm->io_space) < 0) {
1421                         prom_printf("Cannot register Hummingbird's IO space.\n");
1422                         prom_halt();
1423                 }
1424                 if (request_resource(&iomem_resource, &pbm->mem_space) < 0) {
1425                         prom_printf("Cannot register Hummingbird's MEM space.\n");
1426                         prom_halt();
1427                 }
1428
1429                 pci_register_legacy_regions(&pbm->io_space,
1430                                             &pbm->mem_space);
1431         }
1432 }
1433
1434 void sabre_init(struct device_node *dp, char *model_name)
1435 {
1436         struct linux_prom64_registers *pr_regs;
1437         struct pci_controller_info *p;
1438         struct pci_iommu *iommu;
1439         struct property *prop;
1440         int tsbsize;
1441         u32 *busrange;
1442         u32 *vdma;
1443         u32 upa_portid, dma_mask;
1444         u64 clear_irq;
1445
1446         hummingbird_p = 0;
1447         if (!strcmp(model_name, "pci108e,a001"))
1448                 hummingbird_p = 1;
1449         else if (!strcmp(model_name, "SUNW,sabre")) {
1450                 prop = of_find_property(dp, "compatible", NULL);
1451                 if (prop) {
1452                         const char *compat = prop->value;
1453
1454                         if (!strcmp(compat, "pci108e,a001"))
1455                                 hummingbird_p = 1;
1456                 }
1457                 if (!hummingbird_p) {
1458                         struct device_node *dp;
1459
1460                         /* Of course, Sun has to encode things a thousand
1461                          * different ways, inconsistently.
1462                          */
1463                         cpu_find_by_instance(0, &dp, NULL);
1464                         if (!strcmp(dp->name, "SUNW,UltraSPARC-IIe"))
1465                                 hummingbird_p = 1;
1466                 }
1467         }
1468
1469         p = kzalloc(sizeof(*p), GFP_ATOMIC);
1470         if (!p) {
1471                 prom_printf("SABRE: Error, kmalloc(pci_controller_info) failed.\n");
1472                 prom_halt();
1473         }
1474
1475         iommu = kzalloc(sizeof(*iommu), GFP_ATOMIC);
1476         if (!iommu) {
1477                 prom_printf("SABRE: Error, kmalloc(pci_iommu) failed.\n");
1478                 prom_halt();
1479         }
1480         p->pbm_A.iommu = p->pbm_B.iommu = iommu;
1481
1482         upa_portid = 0xff;
1483         prop = of_find_property(dp, "upa-portid", NULL);
1484         if (prop)
1485                 upa_portid = *(u32 *) prop->value;
1486
1487         p->next = pci_controller_root;
1488         pci_controller_root = p;
1489
1490         p->pbm_A.portid = upa_portid;
1491         p->pbm_B.portid = upa_portid;
1492         p->index = pci_num_controllers++;
1493         p->pbms_same_domain = 1;
1494         p->scan_bus = sabre_scan_bus;
1495         p->irq_build = sabre_irq_build;
1496         p->base_address_update = sabre_base_address_update;
1497         p->resource_adjust = sabre_resource_adjust;
1498         p->pci_ops = &sabre_ops;
1499
1500         /*
1501          * Map in SABRE register set and report the presence of this SABRE.
1502          */
1503
1504         prop = of_find_property(dp, "reg", NULL);
1505         pr_regs = prop->value;
1506
1507         /*
1508          * First REG in property is base of entire SABRE register space.
1509          */
1510         p->pbm_A.controller_regs = pr_regs[0].phys_addr;
1511         p->pbm_B.controller_regs = pr_regs[0].phys_addr;
1512
1513         /* Clear interrupts */
1514
1515         /* PCI first */
1516         for (clear_irq = SABRE_ICLR_A_SLOT0; clear_irq < SABRE_ICLR_B_SLOT0 + 0x80; clear_irq += 8)
1517                 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1518
1519         /* Then OBIO */
1520         for (clear_irq = SABRE_ICLR_SCSI; clear_irq < SABRE_ICLR_SCSI + 0x80; clear_irq += 8)
1521                 sabre_write(p->pbm_A.controller_regs + clear_irq, 0x0UL);
1522
1523         /* Error interrupts are enabled later after the bus scan. */
1524         sabre_write(p->pbm_A.controller_regs + SABRE_PCICTRL,
1525                     (SABRE_PCICTRL_MRLEN   | SABRE_PCICTRL_SERR |
1526                      SABRE_PCICTRL_ARBPARK | SABRE_PCICTRL_AEN));
1527
1528         /* Now map in PCI config space for entire SABRE. */
1529         p->pbm_A.config_space = p->pbm_B.config_space =
1530                 (p->pbm_A.controller_regs + SABRE_CONFIGSPACE);
1531
1532         prop = of_find_property(dp, "virtual-dma", NULL);
1533         vdma = prop->value;
1534
1535         dma_mask = vdma[0];
1536         switch(vdma[1]) {
1537                 case 0x20000000:
1538                         dma_mask |= 0x1fffffff;
1539                         tsbsize = 64;
1540                         break;
1541                 case 0x40000000:
1542                         dma_mask |= 0x3fffffff;
1543                         tsbsize = 128;
1544                         break;
1545
1546                 case 0x80000000:
1547                         dma_mask |= 0x7fffffff;
1548                         tsbsize = 128;
1549                         break;
1550                 default:
1551                         prom_printf("SABRE: strange virtual-dma size.\n");
1552                         prom_halt();
1553         }
1554
1555         sabre_iommu_init(p, tsbsize, vdma[0], dma_mask);
1556
1557         prop = of_find_property(dp, "bus-range", NULL);
1558         busrange = prop->value;
1559         p->pci_first_busno = busrange[0];
1560         p->pci_last_busno = busrange[1];
1561
1562         /*
1563          * Look for APB underneath.
1564          */
1565         sabre_pbm_init(p, dp, vdma[0]);
1566 }