arch/sparc/kernel/perf_event.c

   1 /* Performance event support for sparc64.
   2  *
   3  * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net>
   4  *
   5  * This code is based almost entirely upon the x86 perf event
   6  * code, which is:
   7  *
   8  *  Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
   9  *  Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
  10  *  Copyright (C) 2009 Jaswinder Singh Rajput
  11  *  Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
  12  *  Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
  13  */
  14
  15 #include <linux/perf_event.h>
  16 #include <linux/kprobes.h>
  17 #include <linux/ftrace.h>
  18 #include <linux/kernel.h>
  19 #include <linux/kdebug.h>
  20 #include <linux/mutex.h>
  21
  22 #include <asm/stacktrace.h>
  23 #include <asm/cpudata.h>
  24 #include <asm/uaccess.h>
  25 #include <asm/atomic.h>
  26 #include <asm/nmi.h>
  27 #include <asm/pcr.h>
  28
  29 #include "kstack.h"
  30
  31 /* Sparc64 chips have two performance counters, 32-bits each, with
  32  * overflow interrupts generated on transition from 0xffffffff to 0.
  33  * The counters are accessed in one go using a 64-bit register.
  34  *
  35  * Both counters are controlled using a single control register.  The
  36  * only way to stop all sampling is to clear all of the context (user,
  37  * supervisor, hypervisor) sampling enable bits.  But these bits apply
  38  * to both counters, thus the two counters can't be enabled/disabled
  39  * individually.
  40  *
  41  * The control register has two event fields, one for each of the two
  42  * counters.  It's thus nearly impossible to have one counter going
  43  * while keeping the other one stopped.  Therefore it is possible to
  44  * get overflow interrupts for counters not currently "in use" and
  45  * that condition must be checked in the overflow interrupt handler.
  46  *
  47  * So we use a hack, in that we program inactive counters with the
  48  * "sw_count0" and "sw_count1" events.  These count how many times
  49  * the instruction "sethi %hi(0xfc000), %g0" is executed.  It's an
  50  * unusual way to encode a NOP and therefore will not trigger in
  51  * normal code.
  52  */
  53
  54 #define MAX_HWEVENTS                    2
  55 #define MAX_PERIOD                      ((1UL << 32) - 1)
  56
  57 #define PIC_UPPER_INDEX                 0
  58 #define PIC_LOWER_INDEX                 1
  59 #define PIC_NO_INDEX                    -1
  60
  61 struct cpu_hw_events {
  62         /* Number of events currently scheduled onto this cpu.
  63          * This tells how many entries in the arrays below
  64          * are valid.
  65          */
  66         int                     n_events;
  67
  68         /* Number of new events added since the last hw_perf_disable().
  69          * This works because the perf event layer always adds new
  70          * events inside of a perf_{disable,enable}() sequence.
  71          */
  72         int                     n_added;
  73
  74         /* Array of events current scheduled on this cpu.  */
  75         struct perf_event       *event[MAX_HWEVENTS];
  76
  77         /* Array of encoded longs, specifying the %pcr register
  78          * encoding and the mask of PIC counters this even can
  79          * be scheduled on.  See perf_event_encode() et al.
  80          */
  81         unsigned long           events[MAX_HWEVENTS];
  82
  83         /* The current counter index assigned to an event.  When the
  84          * event hasn't been programmed into the cpu yet, this will
  85          * hold PIC_NO_INDEX.  The event->hw.idx value tells us where
  86          * we ought to schedule the event.
  87          */
  88         int                     current_idx[MAX_HWEVENTS];
  89
  90         /* Software copy of %pcr register on this cpu.  */
  91         u64                     pcr;
  92
  93         /* Enabled/disable state.  */
  94         int                     enabled;
  95
  96         unsigned int            group_flag;
  97 };
  98 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
  99
 100 /* An event map describes the characteristics of a performance
 101  * counter event.  In particular it gives the encoding as well as
 102  * a mask telling which counters the event can be measured on.
 103  */
 104 struct perf_event_map {
 105         u16     encoding;
 106         u8      pic_mask;
 107 #define PIC_NONE        0x00
 108 #define PIC_UPPER       0x01
 109 #define PIC_LOWER       0x02
 110 };
 111
 112 /* Encode a perf_event_map entry into a long.  */
 113 static unsigned long perf_event_encode(const struct perf_event_map *pmap)
 114 {
 115         return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
 116 }
 117
 118 static u8 perf_event_get_msk(unsigned long val)
 119 {
 120         return val & 0xff;
 121 }
 122
 123 static u64 perf_event_get_enc(unsigned long val)
 124 {
 125         return val >> 16;
 126 }
 127
 128 #define C(x) PERF_COUNT_HW_CACHE_##x
 129
 130 #define CACHE_OP_UNSUPPORTED    0xfffe
 131 #define CACHE_OP_NONSENSE       0xffff
 132
 133 typedef struct perf_event_map cache_map_t
 134                                 [PERF_COUNT_HW_CACHE_MAX]
 135                                 [PERF_COUNT_HW_CACHE_OP_MAX]
 136                                 [PERF_COUNT_HW_CACHE_RESULT_MAX];
 137
 138 struct sparc_pmu {
 139         const struct perf_event_map     *(*event_map)(int);
 140         const cache_map_t               *cache_map;
 141         int                             max_events;
 142         int                             upper_shift;
 143         int                             lower_shift;
 144         int                             event_mask;
 145         int                             hv_bit;
 146         int                             irq_bit;
 147         int                             upper_nop;
 148         int                             lower_nop;
 149 };
 150
 151 static const struct perf_event_map ultra3_perfmon_event_map[] = {
 152         [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER },
 153         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER },
 154         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER },
 155         [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
 156 };
 157
 158 static const struct perf_event_map *ultra3_event_map(int event_id)
 159 {
 160         return &ultra3_perfmon_event_map[event_id];
 161 }
 162
 163 static const cache_map_t ultra3_cache_map = {
 164 [C(L1D)] = {
 165         [C(OP_READ)] = {
 166                 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
 167                 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
 168         },
 169         [C(OP_WRITE)] = {
 170                 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
 171                 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
 172         },
 173         [C(OP_PREFETCH)] = {
 174                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 175                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 176         },
 177 },
 178 [C(L1I)] = {
 179         [C(OP_READ)] = {
 180                 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
 181                 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
 182         },
 183         [ C(OP_WRITE) ] = {
 184                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
 185                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
 186         },
 187         [ C(OP_PREFETCH) ] = {
 188                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 189                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 190         },
 191 },
 192 [C(LL)] = {
 193         [C(OP_READ)] = {
 194                 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
 195                 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
 196         },
 197         [C(OP_WRITE)] = {
 198                 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
 199                 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
 200         },
 201         [C(OP_PREFETCH)] = {
 202                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 203                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 204         },
 205 },
 206 [C(DTLB)] = {
 207         [C(OP_READ)] = {
 208                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 209                 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
 210         },
 211         [ C(OP_WRITE) ] = {
 212                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 213                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 214         },
 215         [ C(OP_PREFETCH) ] = {
 216                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 217                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 218         },
 219 },
 220 [C(ITLB)] = {
 221         [C(OP_READ)] = {
 222                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 223                 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
 224         },
 225         [ C(OP_WRITE) ] = {
 226                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 227                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 228         },
 229         [ C(OP_PREFETCH) ] = {
 230                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 231                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 232         },
 233 },
 234 [C(BPU)] = {
 235         [C(OP_READ)] = {
 236                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 237                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 238         },
 239         [ C(OP_WRITE) ] = {
 240                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 241                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 242         },
 243         [ C(OP_PREFETCH) ] = {
 244                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 245                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 246         },
 247 },
 248 };
 249
 250 static const struct sparc_pmu ultra3_pmu = {
 251         .event_map      = ultra3_event_map,
 252         .cache_map      = &ultra3_cache_map,
 253         .max_events     = ARRAY_SIZE(ultra3_perfmon_event_map),
 254         .upper_shift    = 11,
 255         .lower_shift    = 4,
 256         .event_mask     = 0x3f,
 257         .upper_nop      = 0x1c,
 258         .lower_nop      = 0x14,
 259 };
 260
 261 /* Niagara1 is very limited.  The upper PIC is hard-locked to count
 262  * only instructions, so it is free running which creates all kinds of
 263  * problems.  Some hardware designs make one wonder if the creator
 264  * even looked at how this stuff gets used by software.
 265  */
 266 static const struct perf_event_map niagara1_perfmon_event_map[] = {
 267         [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER },
 268         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER },
 269         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE },
 270         [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER },
 271 };
 272
 273 static const struct perf_event_map *niagara1_event_map(int event_id)
 274 {
 275         return &niagara1_perfmon_event_map[event_id];
 276 }
 277
 278 static const cache_map_t niagara1_cache_map = {
 279 [C(L1D)] = {
 280         [C(OP_READ)] = {
 281                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 282                 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
 283         },
 284         [C(OP_WRITE)] = {
 285                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 286                 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
 287         },
 288         [C(OP_PREFETCH)] = {
 289                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 290                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 291         },
 292 },
 293 [C(L1I)] = {
 294         [C(OP_READ)] = {
 295                 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
 296                 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
 297         },
 298         [ C(OP_WRITE) ] = {
 299                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
 300                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
 301         },
 302         [ C(OP_PREFETCH) ] = {
 303                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 304                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 305         },
 306 },
 307 [C(LL)] = {
 308         [C(OP_READ)] = {
 309                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 310                 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
 311         },
 312         [C(OP_WRITE)] = {
 313                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 314                 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
 315         },
 316         [C(OP_PREFETCH)] = {
 317                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 318                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 319         },
 320 },
 321 [C(DTLB)] = {
 322         [C(OP_READ)] = {
 323                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 324                 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
 325         },
 326         [ C(OP_WRITE) ] = {
 327                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 328                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 329         },
 330         [ C(OP_PREFETCH) ] = {
 331                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 332                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 333         },
 334 },
 335 [C(ITLB)] = {
 336         [C(OP_READ)] = {
 337                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 338                 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
 339         },
 340         [ C(OP_WRITE) ] = {
 341                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 342                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 343         },
 344         [ C(OP_PREFETCH) ] = {
 345                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 346                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 347         },
 348 },
 349 [C(BPU)] = {
 350         [C(OP_READ)] = {
 351                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 352                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 353         },
 354         [ C(OP_WRITE) ] = {
 355                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 356                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 357         },
 358         [ C(OP_PREFETCH) ] = {
 359                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 360                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 361         },
 362 },
 363 };
 364
 365 static const struct sparc_pmu niagara1_pmu = {
 366         .event_map      = niagara1_event_map,
 367         .cache_map      = &niagara1_cache_map,
 368         .max_events     = ARRAY_SIZE(niagara1_perfmon_event_map),
 369         .upper_shift    = 0,
 370         .lower_shift    = 4,
 371         .event_mask     = 0x7,
 372         .upper_nop      = 0x0,
 373         .lower_nop      = 0x0,
 374 };
 375
 376 static const struct perf_event_map niagara2_perfmon_event_map[] = {
 377         [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER },
 378         [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER },
 379         [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER },
 380         [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER },
 381         [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER },
 382         [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER },
 383 };
 384
 385 static const struct perf_event_map *niagara2_event_map(int event_id)
 386 {
 387         return &niagara2_perfmon_event_map[event_id];
 388 }
 389
 390 static const cache_map_t niagara2_cache_map = {
 391 [C(L1D)] = {
 392         [C(OP_READ)] = {
 393                 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
 394                 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
 395         },
 396         [C(OP_WRITE)] = {
 397                 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
 398                 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
 399         },
 400         [C(OP_PREFETCH)] = {
 401                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 402                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 403         },
 404 },
 405 [C(L1I)] = {
 406         [C(OP_READ)] = {
 407                 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
 408                 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
 409         },
 410         [ C(OP_WRITE) ] = {
 411                 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
 412                 [ C(RESULT_MISS)   ] = { CACHE_OP_NONSENSE },
 413         },
 414         [ C(OP_PREFETCH) ] = {
 415                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 416                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 417         },
 418 },
 419 [C(LL)] = {
 420         [C(OP_READ)] = {
 421                 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
 422                 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
 423         },
 424         [C(OP_WRITE)] = {
 425                 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
 426                 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
 427         },
 428         [C(OP_PREFETCH)] = {
 429                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 430                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 431         },
 432 },
 433 [C(DTLB)] = {
 434         [C(OP_READ)] = {
 435                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 436                 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
 437         },
 438         [ C(OP_WRITE) ] = {
 439                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 440                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 441         },
 442         [ C(OP_PREFETCH) ] = {
 443                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 444                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 445         },
 446 },
 447 [C(ITLB)] = {
 448         [C(OP_READ)] = {
 449                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 450                 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
 451         },
 452         [ C(OP_WRITE) ] = {
 453                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 454                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 455         },
 456         [ C(OP_PREFETCH) ] = {
 457                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 458                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 459         },
 460 },
 461 [C(BPU)] = {
 462         [C(OP_READ)] = {
 463                 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
 464                 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
 465         },
 466         [ C(OP_WRITE) ] = {
 467                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 468                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 469         },
 470         [ C(OP_PREFETCH) ] = {
 471                 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
 472                 [ C(RESULT_MISS)   ] = { CACHE_OP_UNSUPPORTED },
 473         },
 474 },
 475 };
 476
 477 static const struct sparc_pmu niagara2_pmu = {
 478         .event_map      = niagara2_event_map,
 479         .cache_map      = &niagara2_cache_map,
 480         .max_events     = ARRAY_SIZE(niagara2_perfmon_event_map),
 481         .upper_shift    = 19,
 482         .lower_shift    = 6,
 483         .event_mask     = 0xfff,
 484         .hv_bit         = 0x8,
 485         .irq_bit        = 0x30,
 486         .upper_nop      = 0x220,
 487         .lower_nop      = 0x220,
 488 };
 489
 490 static const struct sparc_pmu *sparc_pmu __read_mostly;
 491
 492 static u64 event_encoding(u64 event_id, int idx)
 493 {
 494         if (idx == PIC_UPPER_INDEX)
 495                 event_id <<= sparc_pmu->upper_shift;
 496         else
 497                 event_id <<= sparc_pmu->lower_shift;
 498         return event_id;
 499 }
 500
 501 static u64 mask_for_index(int idx)
 502 {
 503         return event_encoding(sparc_pmu->event_mask, idx);
 504 }
 505
 506 static u64 nop_for_index(int idx)
 507 {
 508         return event_encoding(idx == PIC_UPPER_INDEX ?
 509                               sparc_pmu->upper_nop :
 510                               sparc_pmu->lower_nop, idx);
 511 }
 512
 513 static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
 514 {
 515         u64 val, mask = mask_for_index(idx);
 516
 517         val = cpuc->pcr;
 518         val &= ~mask;
 519         val |= hwc->config;
 520         cpuc->pcr = val;
 521
 522         pcr_ops->write(cpuc->pcr);
 523 }
 524
 525 static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
 526 {
 527         u64 mask = mask_for_index(idx);
 528         u64 nop = nop_for_index(idx);
 529         u64 val;
 530
 531         val = cpuc->pcr;
 532         val &= ~mask;
 533         val |= nop;
 534         cpuc->pcr = val;
 535
 536         pcr_ops->write(cpuc->pcr);
 537 }
 538
 539 static u32 read_pmc(int idx)
 540 {
 541         u64 val;
 542
 543         read_pic(val);
 544         if (idx == PIC_UPPER_INDEX)
 545                 val >>= 32;
 546
 547         return val & 0xffffffff;
 548 }
 549
 550 static void write_pmc(int idx, u64 val)
 551 {
 552         u64 shift, mask, pic;
 553
 554         shift = 0;
 555         if (idx == PIC_UPPER_INDEX)
 556                 shift = 32;
 557
 558         mask = ((u64) 0xffffffff) << shift;
 559         val <<= shift;
 560
 561         read_pic(pic);
 562         pic &= ~mask;
 563         pic |= val;
 564         write_pic(pic);
 565 }
 566
 567 static u64 sparc_perf_event_update(struct perf_event *event,
 568                                    struct hw_perf_event *hwc, int idx)
 569 {
 570         int shift = 64 - 32;
 571         u64 prev_raw_count, new_raw_count;
 572         s64 delta;
 573
 574 again:
 575         prev_raw_count = atomic64_read(&hwc->prev_count);
 576         new_raw_count = read_pmc(idx);
 577
 578         if (atomic64_cmpxchg(&hwc->prev_count, prev_raw_count,
 579                              new_raw_count) != prev_raw_count)
 580                 goto again;
 581
 582         delta = (new_raw_count << shift) - (prev_raw_count << shift);
 583         delta >>= shift;
 584
 585         atomic64_add(delta, &event->count);
 586         atomic64_sub(delta, &hwc->period_left);
 587
 588         return new_raw_count;
 589 }
 590
 591 static int sparc_perf_event_set_period(struct perf_event *event,
 592                                        struct hw_perf_event *hwc, int idx)
 593 {
 594         s64 left = atomic64_read(&hwc->period_left);
 595         s64 period = hwc->sample_period;
 596         int ret = 0;
 597
 598         if (unlikely(left <= -period)) {
 599                 left = period;
 600                 atomic64_set(&hwc->period_left, left);
 601                 hwc->last_period = period;
 602                 ret = 1;
 603         }
 604
 605         if (unlikely(left <= 0)) {
 606                 left += period;
 607                 atomic64_set(&hwc->period_left, left);
 608                 hwc->last_period = period;
 609                 ret = 1;
 610         }
 611         if (left > MAX_PERIOD)
 612                 left = MAX_PERIOD;
 613
 614         atomic64_set(&hwc->prev_count, (u64)-left);
 615
 616         write_pmc(idx, (u64)(-left) & 0xffffffff);
 617
 618         perf_event_update_userpage(event);
 619
 620         return ret;
 621 }
 622
 623 /* If performance event entries have been added, move existing
 624  * events around (if necessary) and then assign new entries to
 625  * counters.
 626  */
 627 static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr)
 628 {
 629         int i;
 630
 631         if (!cpuc->n_added)
 632                 goto out;
 633
 634         /* Read in the counters which are moving.  */
 635         for (i = 0; i < cpuc->n_events; i++) {
 636                 struct perf_event *cp = cpuc->event[i];
 637
 638                 if (cpuc->current_idx[i] != PIC_NO_INDEX &&
 639                     cpuc->current_idx[i] != cp->hw.idx) {
 640                         sparc_perf_event_update(cp, &cp->hw,
 641                                                 cpuc->current_idx[i]);
 642                         cpuc->current_idx[i] = PIC_NO_INDEX;
 643                 }
 644         }
 645
 646         /* Assign to counters all unassigned events.  */
 647         for (i = 0; i < cpuc->n_events; i++) {
 648                 struct perf_event *cp = cpuc->event[i];
 649                 struct hw_perf_event *hwc = &cp->hw;
 650                 int idx = hwc->idx;
 651                 u64 enc;
 652
 653                 if (cpuc->current_idx[i] != PIC_NO_INDEX)
 654                         continue;
 655
 656                 sparc_perf_event_set_period(cp, hwc, idx);
 657                 cpuc->current_idx[i] = idx;
 658
 659                 enc = perf_event_get_enc(cpuc->events[i]);
 660                 pcr |= event_encoding(enc, idx);
 661         }
 662 out:
 663         return pcr;
 664 }
 665
 666 void hw_perf_enable(void)
 667 {
 668         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 669         u64 pcr;
 670
 671         if (cpuc->enabled)
 672                 return;
 673
 674         cpuc->enabled = 1;
 675         barrier();
 676
 677         pcr = cpuc->pcr;
 678         if (!cpuc->n_events) {
 679                 pcr = 0;
 680         } else {
 681                 pcr = maybe_change_configuration(cpuc, pcr);
 682
 683                 /* We require that all of the events have the same
 684                  * configuration, so just fetch the settings from the
 685                  * first entry.
 686                  */
 687                 cpuc->pcr = pcr | cpuc->event[0]->hw.config_base;
 688         }
 689
 690         pcr_ops->write(cpuc->pcr);
 691 }
 692
 693 void hw_perf_disable(void)
 694 {
 695         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 696         u64 val;
 697
 698         if (!cpuc->enabled)
 699                 return;
 700
 701         cpuc->enabled = 0;
 702         cpuc->n_added = 0;
 703
 704         val = cpuc->pcr;
 705         val &= ~(PCR_UTRACE | PCR_STRACE |
 706                  sparc_pmu->hv_bit | sparc_pmu->irq_bit);
 707         cpuc->pcr = val;
 708
 709         pcr_ops->write(cpuc->pcr);
 710 }
 711
 712 static void sparc_pmu_disable(struct perf_event *event)
 713 {
 714         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 715         struct hw_perf_event *hwc = &event->hw;
 716         unsigned long flags;
 717         int i;
 718
 719         local_irq_save(flags);
 720         perf_disable();
 721
 722         for (i = 0; i < cpuc->n_events; i++) {
 723                 if (event == cpuc->event[i]) {
 724                         int idx = cpuc->current_idx[i];
 725
 726                         /* Shift remaining entries down into
 727                          * the existing slot.
 728                          */
 729                         while (++i < cpuc->n_events) {
 730                                 cpuc->event[i - 1] = cpuc->event[i];
 731                                 cpuc->events[i - 1] = cpuc->events[i];
 732                                 cpuc->current_idx[i - 1] =
 733                                         cpuc->current_idx[i];
 734                         }
 735
 736                         /* Absorb the final count and turn off the
 737                          * event.
 738                          */
 739                         sparc_pmu_disable_event(cpuc, hwc, idx);
 740                         barrier();
 741                         sparc_perf_event_update(event, hwc, idx);
 742
 743                         perf_event_update_userpage(event);
 744
 745                         cpuc->n_events--;
 746                         break;
 747                 }
 748         }
 749
 750         perf_enable();
 751         local_irq_restore(flags);
 752 }
 753
 754 static int active_event_index(struct cpu_hw_events *cpuc,
 755                               struct perf_event *event)
 756 {
 757         int i;
 758
 759         for (i = 0; i < cpuc->n_events; i++) {
 760                 if (cpuc->event[i] == event)
 761                         break;
 762         }
 763         BUG_ON(i == cpuc->n_events);
 764         return cpuc->current_idx[i];
 765 }
 766
 767 static void sparc_pmu_read(struct perf_event *event)
 768 {
 769         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 770         int idx = active_event_index(cpuc, event);
 771         struct hw_perf_event *hwc = &event->hw;
 772
 773         sparc_perf_event_update(event, hwc, idx);
 774 }
 775
 776 static void sparc_pmu_unthrottle(struct perf_event *event)
 777 {
 778         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 779         int idx = active_event_index(cpuc, event);
 780         struct hw_perf_event *hwc = &event->hw;
 781
 782         sparc_pmu_enable_event(cpuc, hwc, idx);
 783 }
 784
 785 static atomic_t active_events = ATOMIC_INIT(0);
 786 static DEFINE_MUTEX(pmc_grab_mutex);
 787
 788 static void perf_stop_nmi_watchdog(void *unused)
 789 {
 790         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 791
 792         stop_nmi_watchdog(NULL);
 793         cpuc->pcr = pcr_ops->read();
 794 }
 795
 796 void perf_event_grab_pmc(void)
 797 {
 798         if (atomic_inc_not_zero(&active_events))
 799                 return;
 800
 801         mutex_lock(&pmc_grab_mutex);
 802         if (atomic_read(&active_events) == 0) {
 803                 if (atomic_read(&nmi_active) > 0) {
 804                         on_each_cpu(perf_stop_nmi_watchdog, NULL, 1);
 805                         BUG_ON(atomic_read(&nmi_active) != 0);
 806                 }
 807                 atomic_inc(&active_events);
 808         }
 809         mutex_unlock(&pmc_grab_mutex);
 810 }
 811
 812 void perf_event_release_pmc(void)
 813 {
 814         if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) {
 815                 if (atomic_read(&nmi_active) == 0)
 816                         on_each_cpu(start_nmi_watchdog, NULL, 1);
 817                 mutex_unlock(&pmc_grab_mutex);
 818         }
 819 }
 820
 821 static const struct perf_event_map *sparc_map_cache_event(u64 config)
 822 {
 823         unsigned int cache_type, cache_op, cache_result;
 824         const struct perf_event_map *pmap;
 825
 826         if (!sparc_pmu->cache_map)
 827                 return ERR_PTR(-ENOENT);
 828
 829         cache_type = (config >>  0) & 0xff;
 830         if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
 831                 return ERR_PTR(-EINVAL);
 832
 833         cache_op = (config >>  8) & 0xff;
 834         if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
 835                 return ERR_PTR(-EINVAL);
 836
 837         cache_result = (config >> 16) & 0xff;
 838         if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
 839                 return ERR_PTR(-EINVAL);
 840
 841         pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]);
 842
 843         if (pmap->encoding == CACHE_OP_UNSUPPORTED)
 844                 return ERR_PTR(-ENOENT);
 845
 846         if (pmap->encoding == CACHE_OP_NONSENSE)
 847                 return ERR_PTR(-EINVAL);
 848
 849         return pmap;
 850 }
 851
 852 static void hw_perf_event_destroy(struct perf_event *event)
 853 {
 854         perf_event_release_pmc();
 855 }
 856
 857 /* Make sure all events can be scheduled into the hardware at
 858  * the same time.  This is simplified by the fact that we only
 859  * need to support 2 simultaneous HW events.
 860  *
 861  * As a side effect, the evts[]->hw.idx values will be assigned
 862  * on success.  These are pending indexes.  When the events are
 863  * actually programmed into the chip, these values will propagate
 864  * to the per-cpu cpuc->current_idx[] slots, see the code in
 865  * maybe_change_configuration() for details.
 866  */
 867 static int sparc_check_constraints(struct perf_event **evts,
 868                                    unsigned long *events, int n_ev)
 869 {
 870         u8 msk0 = 0, msk1 = 0;
 871         int idx0 = 0;
 872
 873         /* This case is possible when we are invoked from
 874          * hw_perf_group_sched_in().
 875          */
 876         if (!n_ev)
 877                 return 0;
 878
 879         if (n_ev > perf_max_events)
 880                 return -1;
 881
 882         msk0 = perf_event_get_msk(events[0]);
 883         if (n_ev == 1) {
 884                 if (msk0 & PIC_LOWER)
 885                         idx0 = 1;
 886                 goto success;
 887         }
 888         BUG_ON(n_ev != 2);
 889         msk1 = perf_event_get_msk(events[1]);
 890
 891         /* If both events can go on any counter, OK.  */
 892         if (msk0 == (PIC_UPPER | PIC_LOWER) &&
 893             msk1 == (PIC_UPPER | PIC_LOWER))
 894                 goto success;
 895
 896         /* If one event is limited to a specific counter,
 897          * and the other can go on both, OK.
 898          */
 899         if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
 900             msk1 == (PIC_UPPER | PIC_LOWER)) {
 901                 if (msk0 & PIC_LOWER)
 902                         idx0 = 1;
 903                 goto success;
 904         }
 905
 906         if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
 907             msk0 == (PIC_UPPER | PIC_LOWER)) {
 908                 if (msk1 & PIC_UPPER)
 909                         idx0 = 1;
 910                 goto success;
 911         }
 912
 913         /* If the events are fixed to different counters, OK.  */
 914         if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
 915             (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
 916                 if (msk0 & PIC_LOWER)
 917                         idx0 = 1;
 918                 goto success;
 919         }
 920
 921         /* Otherwise, there is a conflict.  */
 922         return -1;
 923
 924 success:
 925         evts[0]->hw.idx = idx0;
 926         if (n_ev == 2)
 927                 evts[1]->hw.idx = idx0 ^ 1;
 928         return 0;
 929 }
 930
 931 static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
 932 {
 933         int eu = 0, ek = 0, eh = 0;
 934         struct perf_event *event;
 935         int i, n, first;
 936
 937         n = n_prev + n_new;
 938         if (n <= 1)
 939                 return 0;
 940
 941         first = 1;
 942         for (i = 0; i < n; i++) {
 943                 event = evts[i];
 944                 if (first) {
 945                         eu = event->attr.exclude_user;
 946                         ek = event->attr.exclude_kernel;
 947                         eh = event->attr.exclude_hv;
 948                         first = 0;
 949                 } else if (event->attr.exclude_user != eu ||
 950                            event->attr.exclude_kernel != ek ||
 951                            event->attr.exclude_hv != eh) {
 952                         return -EAGAIN;
 953                 }
 954         }
 955
 956         return 0;
 957 }
 958
 959 static int collect_events(struct perf_event *group, int max_count,
 960                           struct perf_event *evts[], unsigned long *events,
 961                           int *current_idx)
 962 {
 963         struct perf_event *event;
 964         int n = 0;
 965
 966         if (!is_software_event(group)) {
 967                 if (n >= max_count)
 968                         return -1;
 969                 evts[n] = group;
 970                 events[n] = group->hw.event_base;
 971                 current_idx[n++] = PIC_NO_INDEX;
 972         }
 973         list_for_each_entry(event, &group->sibling_list, group_entry) {
 974                 if (!is_software_event(event) &&
 975                     event->state != PERF_EVENT_STATE_OFF) {
 976                         if (n >= max_count)
 977                                 return -1;
 978                         evts[n] = event;
 979                         events[n] = event->hw.event_base;
 980                         current_idx[n++] = PIC_NO_INDEX;
 981                 }
 982         }
 983         return n;
 984 }
 985
 986 static int sparc_pmu_enable(struct perf_event *event)
 987 {
 988         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
 989         int n0, ret = -EAGAIN;
 990         unsigned long flags;
 991
 992         local_irq_save(flags);
 993         perf_disable();
 994
 995         n0 = cpuc->n_events;
 996         if (n0 >= perf_max_events)
 997                 goto out;
 998
 999         cpuc->event[n0] = event;
1000         cpuc->events[n0] = event->hw.event_base;
1001         cpuc->current_idx[n0] = PIC_NO_INDEX;
1002
1003         /*
1004          * If group events scheduling transaction was started,
1005          * skip the schedulability test here, it will be peformed
1006          * at commit time(->commit_txn) as a whole
1007          */
1008         if (cpuc->group_flag & PERF_EVENT_TXN_STARTED)
1009                 goto nocheck;
1010
1011         if (check_excludes(cpuc->event, n0, 1))
1012                 goto out;
1013         if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
1014                 goto out;
1015
1016 nocheck:
1017         cpuc->n_events++;
1018         cpuc->n_added++;
1019
1020         ret = 0;
1021 out:
1022         perf_enable();
1023         local_irq_restore(flags);
1024         return ret;
1025 }
1026
1027 static int __hw_perf_event_init(struct perf_event *event)
1028 {
1029         struct perf_event_attr *attr = &event->attr;
1030         struct perf_event *evts[MAX_HWEVENTS];
1031         struct hw_perf_event *hwc = &event->hw;
1032         unsigned long events[MAX_HWEVENTS];
1033         int current_idx_dmy[MAX_HWEVENTS];
1034         const struct perf_event_map *pmap;
1035         int n;
1036
1037         if (atomic_read(&nmi_active) < 0)
1038                 return -ENODEV;
1039
1040         if (attr->type == PERF_TYPE_HARDWARE) {
1041                 if (attr->config >= sparc_pmu->max_events)
1042                         return -EINVAL;
1043                 pmap = sparc_pmu->event_map(attr->config);
1044         } else if (attr->type == PERF_TYPE_HW_CACHE) {
1045                 pmap = sparc_map_cache_event(attr->config);
1046                 if (IS_ERR(pmap))
1047                         return PTR_ERR(pmap);
1048         } else
1049                 return -EOPNOTSUPP;
1050
1051         /* We save the enable bits in the config_base.  */
1052         hwc->config_base = sparc_pmu->irq_bit;
1053         if (!attr->exclude_user)
1054                 hwc->config_base |= PCR_UTRACE;
1055         if (!attr->exclude_kernel)
1056                 hwc->config_base |= PCR_STRACE;
1057         if (!attr->exclude_hv)
1058                 hwc->config_base |= sparc_pmu->hv_bit;
1059
1060         hwc->event_base = perf_event_encode(pmap);
1061
1062         n = 0;
1063         if (event->group_leader != event) {
1064                 n = collect_events(event->group_leader,
1065                                    perf_max_events - 1,
1066                                    evts, events, current_idx_dmy);
1067                 if (n < 0)
1068                         return -EINVAL;
1069         }
1070         events[n] = hwc->event_base;
1071         evts[n] = event;
1072
1073         if (check_excludes(evts, n, 1))
1074                 return -EINVAL;
1075
1076         if (sparc_check_constraints(evts, events, n + 1))
1077                 return -EINVAL;
1078
1079         hwc->idx = PIC_NO_INDEX;
1080
1081         /* Try to do all error checking before this point, as unwinding
1082          * state after grabbing the PMC is difficult.
1083          */
1084         perf_event_grab_pmc();
1085         event->destroy = hw_perf_event_destroy;
1086
1087         if (!hwc->sample_period) {
1088                 hwc->sample_period = MAX_PERIOD;
1089                 hwc->last_period = hwc->sample_period;
1090                 atomic64_set(&hwc->period_left, hwc->sample_period);
1091         }
1092
1093         return 0;
1094 }
1095
1096 /*
1097  * Start group events scheduling transaction
1098  * Set the flag to make pmu::enable() not perform the
1099  * schedulability test, it will be performed at commit time
1100  */
1101 static void sparc_pmu_start_txn(const struct pmu *pmu)
1102 {
1103         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1104
1105         cpuhw->group_flag |= PERF_EVENT_TXN_STARTED;
1106 }
1107
1108 /*
1109  * Stop group events scheduling transaction
1110  * Clear the flag and pmu::enable() will perform the
1111  * schedulability test.
1112  */
1113 static void sparc_pmu_cancel_txn(const struct pmu *pmu)
1114 {
1115         struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1116
1117         cpuhw->group_flag &= ~PERF_EVENT_TXN_STARTED;
1118 }
1119
1120 /*
1121  * Commit group events scheduling transaction
1122  * Perform the group schedulability test as a whole
1123  * Return 0 if success
1124  */
1125 static int sparc_pmu_commit_txn(const struct pmu *pmu)
1126 {
1127         struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1128         int n;
1129
1130         if (!sparc_pmu)
1131                 return -EINVAL;
1132
1133         cpuc = &__get_cpu_var(cpu_hw_events);
1134         n = cpuc->n_events;
1135         if (check_excludes(cpuc->event, 0, n))
1136                 return -EINVAL;
1137         if (sparc_check_constraints(cpuc->event, cpuc->events, n))
1138                 return -EAGAIN;
1139
1140         return 0;
1141 }
1142
1143 static const struct pmu pmu = {
1144         .enable         = sparc_pmu_enable,
1145         .disable        = sparc_pmu_disable,
1146         .read           = sparc_pmu_read,
1147         .unthrottle     = sparc_pmu_unthrottle,
1148         .start_txn      = sparc_pmu_start_txn,
1149         .cancel_txn     = sparc_pmu_cancel_txn,
1150         .commit_txn     = sparc_pmu_commit_txn,
1151 };
1152
1153 const struct pmu *hw_perf_event_init(struct perf_event *event)
1154 {
1155         int err = __hw_perf_event_init(event);
1156
1157         if (err)
1158                 return ERR_PTR(err);
1159         return &pmu;
1160 }
1161
1162 void perf_event_print_debug(void)
1163 {
1164         unsigned long flags;
1165         u64 pcr, pic;
1166         int cpu;
1167
1168         if (!sparc_pmu)
1169                 return;
1170
1171         local_irq_save(flags);
1172
1173         cpu = smp_processor_id();
1174
1175         pcr = pcr_ops->read();
1176         read_pic(pic);
1177
1178         pr_info("\n");
1179         pr_info("CPU#%d: PCR[%016llx] PIC[%016llx]\n",
1180                 cpu, pcr, pic);
1181
1182         local_irq_restore(flags);
1183 }
1184
1185 static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
1186                                             unsigned long cmd, void *__args)
1187 {
1188         struct die_args *args = __args;
1189         struct perf_sample_data data;
1190         struct cpu_hw_events *cpuc;
1191         struct pt_regs *regs;
1192         int i;
1193
1194         if (!atomic_read(&active_events))
1195                 return NOTIFY_DONE;
1196
1197         switch (cmd) {
1198         case DIE_NMI:
1199                 break;
1200
1201         default:
1202                 return NOTIFY_DONE;
1203         }
1204
1205         regs = args->regs;
1206
1207         perf_sample_data_init(&data, 0);
1208
1209         cpuc = &__get_cpu_var(cpu_hw_events);
1210
1211         /* If the PMU has the TOE IRQ enable bits, we need to do a
1212          * dummy write to the %pcr to clear the overflow bits and thus
1213          * the interrupt.
1214          *
1215          * Do this before we peek at the counters to determine
1216          * overflow so we don't lose any events.
1217          */
1218         if (sparc_pmu->irq_bit)
1219                 pcr_ops->write(cpuc->pcr);
1220
1221         for (i = 0; i < cpuc->n_events; i++) {
1222                 struct perf_event *event = cpuc->event[i];
1223                 int idx = cpuc->current_idx[i];
1224                 struct hw_perf_event *hwc;
1225                 u64 val;
1226
1227                 hwc = &event->hw;
1228                 val = sparc_perf_event_update(event, hwc, idx);
1229                 if (val & (1ULL << 31))
1230                         continue;
1231
1232                 data.period = event->hw.last_period;
1233                 if (!sparc_perf_event_set_period(event, hwc, idx))
1234                         continue;
1235
1236                 if (perf_event_overflow(event, 1, &data, regs))
1237                         sparc_pmu_disable_event(cpuc, hwc, idx);
1238         }
1239
1240         return NOTIFY_STOP;
1241 }
1242
1243 static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1244         .notifier_call          = perf_event_nmi_handler,
1245 };
1246
1247 static bool __init supported_pmu(void)
1248 {
1249         if (!strcmp(sparc_pmu_type, "ultra3") ||
1250             !strcmp(sparc_pmu_type, "ultra3+") ||
1251             !strcmp(sparc_pmu_type, "ultra3i") ||
1252             !strcmp(sparc_pmu_type, "ultra4+")) {
1253                 sparc_pmu = &ultra3_pmu;
1254                 return true;
1255         }
1256         if (!strcmp(sparc_pmu_type, "niagara")) {
1257                 sparc_pmu = &niagara1_pmu;
1258                 return true;
1259         }
1260         if (!strcmp(sparc_pmu_type, "niagara2")) {
1261                 sparc_pmu = &niagara2_pmu;
1262                 return true;
1263         }
1264         return false;
1265 }
1266
1267 void __init init_hw_perf_events(void)
1268 {
1269         pr_info("Performance events: ");
1270
1271         if (!supported_pmu()) {
1272                 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
1273                 return;
1274         }
1275
1276         pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
1277
1278         /* All sparc64 PMUs currently have 2 events.  */
1279         perf_max_events = 2;
1280
1281         register_die_notifier(&perf_event_nmi_notifier);
1282 }
1283
1284 static inline void callchain_store(struct perf_callchain_entry *entry, u64 ip)
1285 {
1286         if (entry->nr < PERF_MAX_STACK_DEPTH)
1287                 entry->ip[entry->nr++] = ip;
1288 }
1289
1290 static void perf_callchain_kernel(struct pt_regs *regs,
1291                                   struct perf_callchain_entry *entry)
1292 {
1293         unsigned long ksp, fp;
1294 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1295         int graph = 0;
1296 #endif
1297
1298         callchain_store(entry, PERF_CONTEXT_KERNEL);
1299         callchain_store(entry, regs->tpc);
1300
1301         ksp = regs->u_regs[UREG_I6];
1302         fp = ksp + STACK_BIAS;
1303         do {
1304                 struct sparc_stackf *sf;
1305                 struct pt_regs *regs;
1306                 unsigned long pc;
1307
1308                 if (!kstack_valid(current_thread_info(), fp))
1309                         break;
1310
1311                 sf = (struct sparc_stackf *) fp;
1312                 regs = (struct pt_regs *) (sf + 1);
1313
1314                 if (kstack_is_trap_frame(current_thread_info(), regs)) {
1315                         if (user_mode(regs))
1316                                 break;
1317                         pc = regs->tpc;
1318                         fp = regs->u_regs[UREG_I6] + STACK_BIAS;
1319                 } else {
1320                         pc = sf->callers_pc;
1321                         fp = (unsigned long)sf->fp + STACK_BIAS;
1322                 }
1323                 callchain_store(entry, pc);
1324 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1325                 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
1326                         int index = current->curr_ret_stack;
1327                         if (current->ret_stack && index >= graph) {
1328                                 pc = current->ret_stack[index - graph].ret;
1329                                 callchain_store(entry, pc);
1330                                 graph++;
1331                         }
1332                 }
1333 #endif
1334         } while (entry->nr < PERF_MAX_STACK_DEPTH);
1335 }
1336
1337 static void perf_callchain_user_64(struct pt_regs *regs,
1338                                    struct perf_callchain_entry *entry)
1339 {
1340         unsigned long ufp;
1341
1342         callchain_store(entry, PERF_CONTEXT_USER);
1343         callchain_store(entry, regs->tpc);
1344
1345         ufp = regs->u_regs[UREG_I6] + STACK_BIAS;
1346         do {
1347                 struct sparc_stackf *usf, sf;
1348                 unsigned long pc;
1349
1350                 usf = (struct sparc_stackf *) ufp;
1351                 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1352                         break;
1353
1354                 pc = sf.callers_pc;
1355                 ufp = (unsigned long)sf.fp + STACK_BIAS;
1356                 callchain_store(entry, pc);
1357         } while (entry->nr < PERF_MAX_STACK_DEPTH);
1358 }
1359
1360 static void perf_callchain_user_32(struct pt_regs *regs,
1361                                    struct perf_callchain_entry *entry)
1362 {
1363         unsigned long ufp;
1364
1365         callchain_store(entry, PERF_CONTEXT_USER);
1366         callchain_store(entry, regs->tpc);
1367
1368         ufp = regs->u_regs[UREG_I6] & 0xffffffffUL;
1369         do {
1370                 struct sparc_stackf32 *usf, sf;
1371                 unsigned long pc;
1372
1373                 usf = (struct sparc_stackf32 *) ufp;
1374                 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1375                         break;
1376
1377                 pc = sf.callers_pc;
1378                 ufp = (unsigned long)sf.fp;
1379                 callchain_store(entry, pc);
1380         } while (entry->nr < PERF_MAX_STACK_DEPTH);
1381 }
1382
1383 /* Like powerpc we can't get PMU interrupts within the PMU handler,
1384  * so no need for separate NMI and IRQ chains as on x86.
1385  */
1386 static DEFINE_PER_CPU(struct perf_callchain_entry, callchain);
1387
1388 struct perf_callchain_entry *perf_callchain(struct pt_regs *regs)
1389 {
1390         struct perf_callchain_entry *entry = &__get_cpu_var(callchain);
1391
1392         entry->nr = 0;
1393         if (!user_mode(regs)) {
1394                 stack_trace_flush();
1395                 perf_callchain_kernel(regs, entry);
1396                 if (current->mm)
1397                         regs = task_pt_regs(current);
1398                 else
1399                         regs = NULL;
1400         }
1401         if (regs) {
1402                 flushw_user();
1403                 if (test_thread_flag(TIF_32BIT))
1404                         perf_callchain_user_32(regs, entry);
1405                 else
1406                         perf_callchain_user_64(regs, entry);
1407         }
1408         return entry;
1409 }