arch/sparc/kernel/irq_64.c

   1 /* irq.c: UltraSparc IRQ handling/init/registry.
   2  *
   3  * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
   4  * Copyright (C) 1998  Eddie C. Dost    (ecd@skynet.be)
   5  * Copyright (C) 1998  Jakub Jelinek    (jj@ultra.linux.cz)
   6  */
   7
   8 #include <linux/module.h>
   9 #include <linux/sched.h>
  10 #include <linux/linkage.h>
  11 #include <linux/ptrace.h>
  12 #include <linux/errno.h>
  13 #include <linux/kernel_stat.h>
  14 #include <linux/signal.h>
  15 #include <linux/mm.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/slab.h>
  18 #include <linux/random.h>
  19 #include <linux/init.h>
  20 #include <linux/delay.h>
  21 #include <linux/proc_fs.h>
  22 #include <linux/seq_file.h>
  23 #include <linux/irq.h>
  24
  25 #include <asm/ptrace.h>
  26 #include <asm/processor.h>
  27 #include <asm/atomic.h>
  28 #include <asm/system.h>
  29 #include <asm/irq.h>
  30 #include <asm/io.h>
  31 #include <asm/iommu.h>
  32 #include <asm/upa.h>
  33 #include <asm/oplib.h>
  34 #include <asm/prom.h>
  35 #include <asm/timer.h>
  36 #include <asm/smp.h>
  37 #include <asm/starfire.h>
  38 #include <asm/uaccess.h>
  39 #include <asm/cache.h>
  40 #include <asm/cpudata.h>
  41 #include <asm/auxio.h>
  42 #include <asm/head.h>
  43 #include <asm/hypervisor.h>
  44 #include <asm/cacheflush.h>
  45
  46 #include "entry.h"
  47 #include "cpumap.h"
  48
  49 #define NUM_IVECS       (IMAP_INR + 1)
  50
  51 struct ino_bucket *ivector_table;
  52 unsigned long ivector_table_pa;
  53
  54 /* On several sun4u processors, it is illegal to mix bypass and
  55  * non-bypass accesses.  Therefore we access all INO buckets
  56  * using bypass accesses only.
  57  */
  58 static unsigned long bucket_get_chain_pa(unsigned long bucket_pa)
  59 {
  60         unsigned long ret;
  61
  62         __asm__ __volatile__("ldxa      [%1] %2, %0"
  63                              : "=&r" (ret)
  64                              : "r" (bucket_pa +
  65                                     offsetof(struct ino_bucket,
  66                                              __irq_chain_pa)),
  67                                "i" (ASI_PHYS_USE_EC));
  68
  69         return ret;
  70 }
  71
  72 static void bucket_clear_chain_pa(unsigned long bucket_pa)
  73 {
  74         __asm__ __volatile__("stxa      %%g0, [%0] %1"
  75                              : /* no outputs */
  76                              : "r" (bucket_pa +
  77                                     offsetof(struct ino_bucket,
  78                                              __irq_chain_pa)),
  79                                "i" (ASI_PHYS_USE_EC));
  80 }
  81
  82 static unsigned int bucket_get_virt_irq(unsigned long bucket_pa)
  83 {
  84         unsigned int ret;
  85
  86         __asm__ __volatile__("lduwa     [%1] %2, %0"
  87                              : "=&r" (ret)
  88                              : "r" (bucket_pa +
  89                                     offsetof(struct ino_bucket,
  90                                              __virt_irq)),
  91                                "i" (ASI_PHYS_USE_EC));
  92
  93         return ret;
  94 }
  95
  96 static void bucket_set_virt_irq(unsigned long bucket_pa,
  97                                 unsigned int virt_irq)
  98 {
  99         __asm__ __volatile__("stwa      %0, [%1] %2"
 100                              : /* no outputs */
 101                              : "r" (virt_irq),
 102                                "r" (bucket_pa +
 103                                     offsetof(struct ino_bucket,
 104                                              __virt_irq)),
 105                                "i" (ASI_PHYS_USE_EC));
 106 }
 107
 108 #define irq_work_pa(__cpu)      &(trap_block[(__cpu)].irq_worklist_pa)
 109
 110 static struct {
 111         unsigned int dev_handle;
 112         unsigned int dev_ino;
 113         unsigned int in_use;
 114 } virt_irq_table[NR_IRQS];
 115 static DEFINE_SPINLOCK(virt_irq_alloc_lock);
 116
 117 unsigned char virt_irq_alloc(unsigned int dev_handle,
 118                              unsigned int dev_ino)
 119 {
 120         unsigned long flags;
 121         unsigned char ent;
 122
 123         BUILD_BUG_ON(NR_IRQS >= 256);
 124
 125         spin_lock_irqsave(&virt_irq_alloc_lock, flags);
 126
 127         for (ent = 1; ent < NR_IRQS; ent++) {
 128                 if (!virt_irq_table[ent].in_use)
 129                         break;
 130         }
 131         if (ent >= NR_IRQS) {
 132                 printk(KERN_ERR "IRQ: Out of virtual IRQs.\n");
 133                 ent = 0;
 134         } else {
 135                 virt_irq_table[ent].dev_handle = dev_handle;
 136                 virt_irq_table[ent].dev_ino = dev_ino;
 137                 virt_irq_table[ent].in_use = 1;
 138         }
 139
 140         spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
 141
 142         return ent;
 143 }
 144
 145 #ifdef CONFIG_PCI_MSI
 146 void virt_irq_free(unsigned int virt_irq)
 147 {
 148         unsigned long flags;
 149
 150         if (virt_irq >= NR_IRQS)
 151                 return;
 152
 153         spin_lock_irqsave(&virt_irq_alloc_lock, flags);
 154
 155         virt_irq_table[virt_irq].in_use = 0;
 156
 157         spin_unlock_irqrestore(&virt_irq_alloc_lock, flags);
 158 }
 159 #endif
 160
 161 /*
 162  * /proc/interrupts printing:
 163  */
 164
 165 int show_interrupts(struct seq_file *p, void *v)
 166 {
 167         int i = *(loff_t *) v, j;
 168         struct irqaction * action;
 169         unsigned long flags;
 170
 171         if (i == 0) {
 172                 seq_printf(p, "           ");
 173                 for_each_online_cpu(j)
 174                         seq_printf(p, "CPU%d       ",j);
 175                 seq_putc(p, '\n');
 176         }
 177
 178         if (i < NR_IRQS) {
 179                 spin_lock_irqsave(&irq_desc[i].lock, flags);
 180                 action = irq_desc[i].action;
 181                 if (!action)
 182                         goto skip;
 183                 seq_printf(p, "%3d: ",i);
 184 #ifndef CONFIG_SMP
 185                 seq_printf(p, "%10u ", kstat_irqs(i));
 186 #else
 187                 for_each_online_cpu(j)
 188                         seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
 189 #endif
 190                 seq_printf(p, " %9s", irq_desc[i].chip->typename);
 191                 seq_printf(p, "  %s", action->name);
 192
 193                 for (action=action->next; action; action = action->next)
 194                         seq_printf(p, ", %s", action->name);
 195
 196                 seq_putc(p, '\n');
 197 skip:
 198                 spin_unlock_irqrestore(&irq_desc[i].lock, flags);
 199         } else if (i == NR_IRQS) {
 200                 seq_printf(p, "NMI: ");
 201                 for_each_online_cpu(j)
 202                         seq_printf(p, "%10u ", cpu_data(j).__nmi_count);
 203                 seq_printf(p, "     Non-maskable interrupts\n");
 204         }
 205         return 0;
 206 }
 207
 208 static unsigned int sun4u_compute_tid(unsigned long imap, unsigned long cpuid)
 209 {
 210         unsigned int tid;
 211
 212         if (this_is_starfire) {
 213                 tid = starfire_translate(imap, cpuid);
 214                 tid <<= IMAP_TID_SHIFT;
 215                 tid &= IMAP_TID_UPA;
 216         } else {
 217                 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
 218                         unsigned long ver;
 219
 220                         __asm__ ("rdpr %%ver, %0" : "=r" (ver));
 221                         if ((ver >> 32UL) == __JALAPENO_ID ||
 222                             (ver >> 32UL) == __SERRANO_ID) {
 223                                 tid = cpuid << IMAP_TID_SHIFT;
 224                                 tid &= IMAP_TID_JBUS;
 225                         } else {
 226                                 unsigned int a = cpuid & 0x1f;
 227                                 unsigned int n = (cpuid >> 5) & 0x1f;
 228
 229                                 tid = ((a << IMAP_AID_SHIFT) |
 230                                        (n << IMAP_NID_SHIFT));
 231                                 tid &= (IMAP_AID_SAFARI |
 232                                         IMAP_NID_SAFARI);;
 233                         }
 234                 } else {
 235                         tid = cpuid << IMAP_TID_SHIFT;
 236                         tid &= IMAP_TID_UPA;
 237                 }
 238         }
 239
 240         return tid;
 241 }
 242
 243 struct irq_handler_data {
 244         unsigned long   iclr;
 245         unsigned long   imap;
 246
 247         void            (*pre_handler)(unsigned int, void *, void *);
 248         void            *arg1;
 249         void            *arg2;
 250 };
 251
 252 #ifdef CONFIG_SMP
 253 static int irq_choose_cpu(unsigned int virt_irq)
 254 {
 255         cpumask_t mask;
 256         int cpuid;
 257
 258         cpumask_copy(&mask, irq_desc[virt_irq].affinity);
 259         if (cpus_equal(mask, cpu_online_map)) {
 260                 cpuid = map_to_cpu(virt_irq);
 261         } else {
 262                 cpumask_t tmp;
 263
 264                 cpus_and(tmp, cpu_online_map, mask);
 265                 cpuid = cpus_empty(tmp) ? map_to_cpu(virt_irq) : first_cpu(tmp);
 266         }
 267
 268         return cpuid;
 269 }
 270 #else
 271 static int irq_choose_cpu(unsigned int virt_irq)
 272 {
 273         return real_hard_smp_processor_id();
 274 }
 275 #endif
 276
 277 static void sun4u_irq_enable(unsigned int virt_irq)
 278 {
 279         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 280
 281         if (likely(data)) {
 282                 unsigned long cpuid, imap, val;
 283                 unsigned int tid;
 284
 285                 cpuid = irq_choose_cpu(virt_irq);
 286                 imap = data->imap;
 287
 288                 tid = sun4u_compute_tid(imap, cpuid);
 289
 290                 val = upa_readq(imap);
 291                 val &= ~(IMAP_TID_UPA | IMAP_TID_JBUS |
 292                          IMAP_AID_SAFARI | IMAP_NID_SAFARI);
 293                 val |= tid | IMAP_VALID;
 294                 upa_writeq(val, imap);
 295                 upa_writeq(ICLR_IDLE, data->iclr);
 296         }
 297 }
 298
 299 static int sun4u_set_affinity(unsigned int virt_irq,
 300                                const struct cpumask *mask)
 301 {
 302         sun4u_irq_enable(virt_irq);
 303
 304         return 0;
 305 }
 306
 307 /* Don't do anything.  The desc->status check for IRQ_DISABLED in
 308  * handler_irq() will skip the handler call and that will leave the
 309  * interrupt in the sent state.  The next ->enable() call will hit the
 310  * ICLR register to reset the state machine.
 311  *
 312  * This scheme is necessary, instead of clearing the Valid bit in the
 313  * IMAP register, to handle the case of IMAP registers being shared by
 314  * multiple INOs (and thus ICLR registers).  Since we use a different
 315  * virtual IRQ for each shared IMAP instance, the generic code thinks
 316  * there is only one user so it prematurely calls ->disable() on
 317  * free_irq().
 318  *
 319  * We have to provide an explicit ->disable() method instead of using
 320  * NULL to get the default.  The reason is that if the generic code
 321  * sees that, it also hooks up a default ->shutdown method which
 322  * invokes ->mask() which we do not want.  See irq_chip_set_defaults().
 323  */
 324 static void sun4u_irq_disable(unsigned int virt_irq)
 325 {
 326 }
 327
 328 static void sun4u_irq_eoi(unsigned int virt_irq)
 329 {
 330         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 331         struct irq_desc *desc = irq_desc + virt_irq;
 332
 333         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 334                 return;
 335
 336         if (likely(data))
 337                 upa_writeq(ICLR_IDLE, data->iclr);
 338 }
 339
 340 static void sun4v_irq_enable(unsigned int virt_irq)
 341 {
 342         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 343         unsigned long cpuid = irq_choose_cpu(virt_irq);
 344         int err;
 345
 346         err = sun4v_intr_settarget(ino, cpuid);
 347         if (err != HV_EOK)
 348                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 349                        "err(%d)\n", ino, cpuid, err);
 350         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 351         if (err != HV_EOK)
 352                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 353                        "err(%d)\n", ino, err);
 354         err = sun4v_intr_setenabled(ino, HV_INTR_ENABLED);
 355         if (err != HV_EOK)
 356                 printk(KERN_ERR "sun4v_intr_setenabled(%x): err(%d)\n",
 357                        ino, err);
 358 }
 359
 360 static int sun4v_set_affinity(unsigned int virt_irq,
 361                                const struct cpumask *mask)
 362 {
 363         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 364         unsigned long cpuid = irq_choose_cpu(virt_irq);
 365         int err;
 366
 367         err = sun4v_intr_settarget(ino, cpuid);
 368         if (err != HV_EOK)
 369                 printk(KERN_ERR "sun4v_intr_settarget(%x,%lu): "
 370                        "err(%d)\n", ino, cpuid, err);
 371
 372         return 0;
 373 }
 374
 375 static void sun4v_irq_disable(unsigned int virt_irq)
 376 {
 377         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 378         int err;
 379
 380         err = sun4v_intr_setenabled(ino, HV_INTR_DISABLED);
 381         if (err != HV_EOK)
 382                 printk(KERN_ERR "sun4v_intr_setenabled(%x): "
 383                        "err(%d)\n", ino, err);
 384 }
 385
 386 static void sun4v_irq_eoi(unsigned int virt_irq)
 387 {
 388         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 389         struct irq_desc *desc = irq_desc + virt_irq;
 390         int err;
 391
 392         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 393                 return;
 394
 395         err = sun4v_intr_setstate(ino, HV_INTR_STATE_IDLE);
 396         if (err != HV_EOK)
 397                 printk(KERN_ERR "sun4v_intr_setstate(%x): "
 398                        "err(%d)\n", ino, err);
 399 }
 400
 401 static void sun4v_virq_enable(unsigned int virt_irq)
 402 {
 403         unsigned long cpuid, dev_handle, dev_ino;
 404         int err;
 405
 406         cpuid = irq_choose_cpu(virt_irq);
 407
 408         dev_handle = virt_irq_table[virt_irq].dev_handle;
 409         dev_ino = virt_irq_table[virt_irq].dev_ino;
 410
 411         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 412         if (err != HV_EOK)
 413                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 414                        "err(%d)\n",
 415                        dev_handle, dev_ino, cpuid, err);
 416         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 417                                     HV_INTR_STATE_IDLE);
 418         if (err != HV_EOK)
 419                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 420                        "HV_INTR_STATE_IDLE): err(%d)\n",
 421                        dev_handle, dev_ino, err);
 422         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 423                                     HV_INTR_ENABLED);
 424         if (err != HV_EOK)
 425                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 426                        "HV_INTR_ENABLED): err(%d)\n",
 427                        dev_handle, dev_ino, err);
 428 }
 429
 430 static int sun4v_virt_set_affinity(unsigned int virt_irq,
 431                                     const struct cpumask *mask)
 432 {
 433         unsigned long cpuid, dev_handle, dev_ino;
 434         int err;
 435
 436         cpuid = irq_choose_cpu(virt_irq);
 437
 438         dev_handle = virt_irq_table[virt_irq].dev_handle;
 439         dev_ino = virt_irq_table[virt_irq].dev_ino;
 440
 441         err = sun4v_vintr_set_target(dev_handle, dev_ino, cpuid);
 442         if (err != HV_EOK)
 443                 printk(KERN_ERR "sun4v_vintr_set_target(%lx,%lx,%lu): "
 444                        "err(%d)\n",
 445                        dev_handle, dev_ino, cpuid, err);
 446
 447         return 0;
 448 }
 449
 450 static void sun4v_virq_disable(unsigned int virt_irq)
 451 {
 452         unsigned long dev_handle, dev_ino;
 453         int err;
 454
 455         dev_handle = virt_irq_table[virt_irq].dev_handle;
 456         dev_ino = virt_irq_table[virt_irq].dev_ino;
 457
 458         err = sun4v_vintr_set_valid(dev_handle, dev_ino,
 459                                     HV_INTR_DISABLED);
 460         if (err != HV_EOK)
 461                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 462                        "HV_INTR_DISABLED): err(%d)\n",
 463                        dev_handle, dev_ino, err);
 464 }
 465
 466 static void sun4v_virq_eoi(unsigned int virt_irq)
 467 {
 468         struct irq_desc *desc = irq_desc + virt_irq;
 469         unsigned long dev_handle, dev_ino;
 470         int err;
 471
 472         if (unlikely(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)))
 473                 return;
 474
 475         dev_handle = virt_irq_table[virt_irq].dev_handle;
 476         dev_ino = virt_irq_table[virt_irq].dev_ino;
 477
 478         err = sun4v_vintr_set_state(dev_handle, dev_ino,
 479                                     HV_INTR_STATE_IDLE);
 480         if (err != HV_EOK)
 481                 printk(KERN_ERR "sun4v_vintr_set_state(%lx,%lx,"
 482                        "HV_INTR_STATE_IDLE): err(%d)\n",
 483                        dev_handle, dev_ino, err);
 484 }
 485
 486 static struct irq_chip sun4u_irq = {
 487         .typename       = "sun4u",
 488         .enable         = sun4u_irq_enable,
 489         .disable        = sun4u_irq_disable,
 490         .eoi            = sun4u_irq_eoi,
 491         .set_affinity   = sun4u_set_affinity,
 492 };
 493
 494 static struct irq_chip sun4v_irq = {
 495         .typename       = "sun4v",
 496         .enable         = sun4v_irq_enable,
 497         .disable        = sun4v_irq_disable,
 498         .eoi            = sun4v_irq_eoi,
 499         .set_affinity   = sun4v_set_affinity,
 500 };
 501
 502 static struct irq_chip sun4v_virq = {
 503         .typename       = "vsun4v",
 504         .enable         = sun4v_virq_enable,
 505         .disable        = sun4v_virq_disable,
 506         .eoi            = sun4v_virq_eoi,
 507         .set_affinity   = sun4v_virt_set_affinity,
 508 };
 509
 510 static void pre_flow_handler(unsigned int virt_irq,
 511                                       struct irq_desc *desc)
 512 {
 513         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 514         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 515
 516         data->pre_handler(ino, data->arg1, data->arg2);
 517
 518         handle_fasteoi_irq(virt_irq, desc);
 519 }
 520
 521 void irq_install_pre_handler(int virt_irq,
 522                              void (*func)(unsigned int, void *, void *),
 523                              void *arg1, void *arg2)
 524 {
 525         struct irq_handler_data *data = get_irq_chip_data(virt_irq);
 526         struct irq_desc *desc = irq_desc + virt_irq;
 527
 528         data->pre_handler = func;
 529         data->arg1 = arg1;
 530         data->arg2 = arg2;
 531
 532         desc->handle_irq = pre_flow_handler;
 533 }
 534
 535 unsigned int build_irq(int inofixup, unsigned long iclr, unsigned long imap)
 536 {
 537         struct ino_bucket *bucket;
 538         struct irq_handler_data *data;
 539         unsigned int virt_irq;
 540         int ino;
 541
 542         BUG_ON(tlb_type == hypervisor);
 543
 544         ino = (upa_readq(imap) & (IMAP_IGN | IMAP_INO)) + inofixup;
 545         bucket = &ivector_table[ino];
 546         virt_irq = bucket_get_virt_irq(__pa(bucket));
 547         if (!virt_irq) {
 548                 virt_irq = virt_irq_alloc(0, ino);
 549                 bucket_set_virt_irq(__pa(bucket), virt_irq);
 550                 set_irq_chip_and_handler_name(virt_irq,
 551                                               &sun4u_irq,
 552                                               handle_fasteoi_irq,
 553                                               "IVEC");
 554         }
 555
 556         data = get_irq_chip_data(virt_irq);
 557         if (unlikely(data))
 558                 goto out;
 559
 560         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 561         if (unlikely(!data)) {
 562                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 563                 prom_halt();
 564         }
 565         set_irq_chip_data(virt_irq, data);
 566
 567         data->imap  = imap;
 568         data->iclr  = iclr;
 569
 570 out:
 571         return virt_irq;
 572 }
 573
 574 static unsigned int sun4v_build_common(unsigned long sysino,
 575                                        struct irq_chip *chip)
 576 {
 577         struct ino_bucket *bucket;
 578         struct irq_handler_data *data;
 579         unsigned int virt_irq;
 580
 581         BUG_ON(tlb_type != hypervisor);
 582
 583         bucket = &ivector_table[sysino];
 584         virt_irq = bucket_get_virt_irq(__pa(bucket));
 585         if (!virt_irq) {
 586                 virt_irq = virt_irq_alloc(0, sysino);
 587                 bucket_set_virt_irq(__pa(bucket), virt_irq);
 588                 set_irq_chip_and_handler_name(virt_irq, chip,
 589                                               handle_fasteoi_irq,
 590                                               "IVEC");
 591         }
 592
 593         data = get_irq_chip_data(virt_irq);
 594         if (unlikely(data))
 595                 goto out;
 596
 597         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 598         if (unlikely(!data)) {
 599                 prom_printf("IRQ: kzalloc(irq_handler_data) failed.\n");
 600                 prom_halt();
 601         }
 602         set_irq_chip_data(virt_irq, data);
 603
 604         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 605          * is done by hypervisor calls on sun4v platforms, not by direct
 606          * register accesses.
 607          */
 608         data->imap = ~0UL;
 609         data->iclr = ~0UL;
 610
 611 out:
 612         return virt_irq;
 613 }
 614
 615 unsigned int sun4v_build_irq(u32 devhandle, unsigned int devino)
 616 {
 617         unsigned long sysino = sun4v_devino_to_sysino(devhandle, devino);
 618
 619         return sun4v_build_common(sysino, &sun4v_irq);
 620 }
 621
 622 unsigned int sun4v_build_virq(u32 devhandle, unsigned int devino)
 623 {
 624         struct irq_handler_data *data;
 625         unsigned long hv_err, cookie;
 626         struct ino_bucket *bucket;
 627         struct irq_desc *desc;
 628         unsigned int virt_irq;
 629
 630         bucket = kzalloc(sizeof(struct ino_bucket), GFP_ATOMIC);
 631         if (unlikely(!bucket))
 632                 return 0;
 633         __flush_dcache_range((unsigned long) bucket,
 634                              ((unsigned long) bucket +
 635                               sizeof(struct ino_bucket)));
 636
 637         virt_irq = virt_irq_alloc(devhandle, devino);
 638         bucket_set_virt_irq(__pa(bucket), virt_irq);
 639
 640         set_irq_chip_and_handler_name(virt_irq, &sun4v_virq,
 641                                       handle_fasteoi_irq,
 642                                       "IVEC");
 643
 644         data = kzalloc(sizeof(struct irq_handler_data), GFP_ATOMIC);
 645         if (unlikely(!data))
 646                 return 0;
 647
 648         /* In order to make the LDC channel startup sequence easier,
 649          * especially wrt. locking, we do not let request_irq() enable
 650          * the interrupt.
 651          */
 652         desc = irq_desc + virt_irq;
 653         desc->status |= IRQ_NOAUTOEN;
 654
 655         set_irq_chip_data(virt_irq, data);
 656
 657         /* Catch accidental accesses to these things.  IMAP/ICLR handling
 658          * is done by hypervisor calls on sun4v platforms, not by direct
 659          * register accesses.
 660          */
 661         data->imap = ~0UL;
 662         data->iclr = ~0UL;
 663
 664         cookie = ~__pa(bucket);
 665         hv_err = sun4v_vintr_set_cookie(devhandle, devino, cookie);
 666         if (hv_err) {
 667                 prom_printf("IRQ: Fatal, cannot set cookie for [%x:%x] "
 668                             "err=%lu\n", devhandle, devino, hv_err);
 669                 prom_halt();
 670         }
 671
 672         return virt_irq;
 673 }
 674
 675 void ack_bad_irq(unsigned int virt_irq)
 676 {
 677         unsigned int ino = virt_irq_table[virt_irq].dev_ino;
 678
 679         if (!ino)
 680                 ino = 0xdeadbeef;
 681
 682         printk(KERN_CRIT "Unexpected IRQ from ino[%x] virt_irq[%u]\n",
 683                ino, virt_irq);
 684 }
 685
 686 void *hardirq_stack[NR_CPUS];
 687 void *softirq_stack[NR_CPUS];
 688
 689 static __attribute__((always_inline)) void *set_hardirq_stack(void)
 690 {
 691         void *orig_sp, *sp = hardirq_stack[smp_processor_id()];
 692
 693         __asm__ __volatile__("mov %%sp, %0" : "=r" (orig_sp));
 694         if (orig_sp < sp ||
 695             orig_sp > (sp + THREAD_SIZE)) {
 696                 sp += THREAD_SIZE - 192 - STACK_BIAS;
 697                 __asm__ __volatile__("mov %0, %%sp" : : "r" (sp));
 698         }
 699
 700         return orig_sp;
 701 }
 702 static __attribute__((always_inline)) void restore_hardirq_stack(void *orig_sp)
 703 {
 704         __asm__ __volatile__("mov %0, %%sp" : : "r" (orig_sp));
 705 }
 706
 707 void handler_irq(int irq, struct pt_regs *regs)
 708 {
 709         unsigned long pstate, bucket_pa;
 710         struct pt_regs *old_regs;
 711         void *orig_sp;
 712
 713         clear_softint(1 << irq);
 714
 715         old_regs = set_irq_regs(regs);
 716         irq_enter();
 717
 718         /* Grab an atomic snapshot of the pending IVECs.  */
 719         __asm__ __volatile__("rdpr      %%pstate, %0\n\t"
 720                              "wrpr      %0, %3, %%pstate\n\t"
 721                              "ldx       [%2], %1\n\t"
 722                              "stx       %%g0, [%2]\n\t"
 723                              "wrpr      %0, 0x0, %%pstate\n\t"
 724                              : "=&r" (pstate), "=&r" (bucket_pa)
 725                              : "r" (irq_work_pa(smp_processor_id())),
 726                                "i" (PSTATE_IE)
 727                              : "memory");
 728
 729         orig_sp = set_hardirq_stack();
 730
 731         while (bucket_pa) {
 732                 struct irq_desc *desc;
 733                 unsigned long next_pa;
 734                 unsigned int virt_irq;
 735
 736                 next_pa = bucket_get_chain_pa(bucket_pa);
 737                 virt_irq = bucket_get_virt_irq(bucket_pa);
 738                 bucket_clear_chain_pa(bucket_pa);
 739
 740                 desc = irq_desc + virt_irq;
 741
 742                 if (!(desc->status & IRQ_DISABLED))
 743                         desc->handle_irq(virt_irq, desc);
 744
 745                 bucket_pa = next_pa;
 746         }
 747
 748         restore_hardirq_stack(orig_sp);
 749
 750         irq_exit();
 751         set_irq_regs(old_regs);
 752 }
 753
 754 void do_softirq(void)
 755 {
 756         unsigned long flags;
 757
 758         if (in_interrupt())
 759                 return;
 760
 761         local_irq_save(flags);
 762
 763         if (local_softirq_pending()) {
 764                 void *orig_sp, *sp = softirq_stack[smp_processor_id()];
 765
 766                 sp += THREAD_SIZE - 192 - STACK_BIAS;
 767
 768                 __asm__ __volatile__("mov %%sp, %0\n\t"
 769                                      "mov %1, %%sp"
 770                                      : "=&r" (orig_sp)
 771                                      : "r" (sp));
 772                 __do_softirq();
 773                 __asm__ __volatile__("mov %0, %%sp"
 774                                      : : "r" (orig_sp));
 775         }
 776
 777         local_irq_restore(flags);
 778 }
 779
 780 #ifdef CONFIG_HOTPLUG_CPU
 781 void fixup_irqs(void)
 782 {
 783         unsigned int irq;
 784
 785         for (irq = 0; irq < NR_IRQS; irq++) {
 786                 unsigned long flags;
 787
 788                 spin_lock_irqsave(&irq_desc[irq].lock, flags);
 789                 if (irq_desc[irq].action &&
 790                     !(irq_desc[irq].status & IRQ_PER_CPU)) {
 791                         if (irq_desc[irq].chip->set_affinity)
 792                                 irq_desc[irq].chip->set_affinity(irq,
 793                                         irq_desc[irq].affinity);
 794                 }
 795                 spin_unlock_irqrestore(&irq_desc[irq].lock, flags);
 796         }
 797
 798         tick_ops->disable_irq();
 799 }
 800 #endif
 801
 802 struct sun5_timer {
 803         u64     count0;
 804         u64     limit0;
 805         u64     count1;
 806         u64     limit1;
 807 };
 808
 809 static struct sun5_timer *prom_timers;
 810 static u64 prom_limit0, prom_limit1;
 811
 812 static void map_prom_timers(void)
 813 {
 814         struct device_node *dp;
 815         const unsigned int *addr;
 816
 817         /* PROM timer node hangs out in the top level of device siblings... */
 818         dp = of_find_node_by_path("/");
 819         dp = dp->child;
 820         while (dp) {
 821                 if (!strcmp(dp->name, "counter-timer"))
 822                         break;
 823                 dp = dp->sibling;
 824         }
 825
 826         /* Assume if node is not present, PROM uses different tick mechanism
 827          * which we should not care about.
 828          */
 829         if (!dp) {
 830                 prom_timers = (struct sun5_timer *) 0;
 831                 return;
 832         }
 833
 834         /* If PROM is really using this, it must be mapped by him. */
 835         addr = of_get_property(dp, "address", NULL);
 836         if (!addr) {
 837                 prom_printf("PROM does not have timer mapped, trying to continue.\n");
 838                 prom_timers = (struct sun5_timer *) 0;
 839                 return;
 840         }
 841         prom_timers = (struct sun5_timer *) ((unsigned long)addr[0]);
 842 }
 843
 844 static void kill_prom_timer(void)
 845 {
 846         if (!prom_timers)
 847                 return;
 848
 849         /* Save them away for later. */
 850         prom_limit0 = prom_timers->limit0;
 851         prom_limit1 = prom_timers->limit1;
 852
 853         /* Just as in sun4c/sun4m PROM uses timer which ticks at IRQ 14.
 854          * We turn both off here just to be paranoid.
 855          */
 856         prom_timers->limit0 = 0;
 857         prom_timers->limit1 = 0;
 858
 859         /* Wheee, eat the interrupt packet too... */
 860         __asm__ __volatile__(
 861 "       mov     0x40, %%g2\n"
 862 "       ldxa    [%%g0] %0, %%g1\n"
 863 "       ldxa    [%%g2] %1, %%g1\n"
 864 "       stxa    %%g0, [%%g0] %0\n"
 865 "       membar  #Sync\n"
 866         : /* no outputs */
 867         : "i" (ASI_INTR_RECEIVE), "i" (ASI_INTR_R)
 868         : "g1", "g2");
 869 }
 870
 871 void notrace init_irqwork_curcpu(void)
 872 {
 873         int cpu = hard_smp_processor_id();
 874
 875         trap_block[cpu].irq_worklist_pa = 0UL;
 876 }
 877
 878 /* Please be very careful with register_one_mondo() and
 879  * sun4v_register_mondo_queues().
 880  *
 881  * On SMP this gets invoked from the CPU trampoline before
 882  * the cpu has fully taken over the trap table from OBP,
 883  * and it's kernel stack + %g6 thread register state is
 884  * not fully cooked yet.
 885  *
 886  * Therefore you cannot make any OBP calls, not even prom_printf,
 887  * from these two routines.
 888  */
 889 static void __cpuinit register_one_mondo(unsigned long paddr, unsigned long type, unsigned long qmask)
 890 {
 891         unsigned long num_entries = (qmask + 1) / 64;
 892         unsigned long status;
 893
 894         status = sun4v_cpu_qconf(type, paddr, num_entries);
 895         if (status != HV_EOK) {
 896                 prom_printf("SUN4V: sun4v_cpu_qconf(%lu:%lx:%lu) failed, "
 897                             "err %lu\n", type, paddr, num_entries, status);
 898                 prom_halt();
 899         }
 900 }
 901
 902 void __cpuinit notrace sun4v_register_mondo_queues(int this_cpu)
 903 {
 904         struct trap_per_cpu *tb = &trap_block[this_cpu];
 905
 906         register_one_mondo(tb->cpu_mondo_pa, HV_CPU_QUEUE_CPU_MONDO,
 907                            tb->cpu_mondo_qmask);
 908         register_one_mondo(tb->dev_mondo_pa, HV_CPU_QUEUE_DEVICE_MONDO,
 909                            tb->dev_mondo_qmask);
 910         register_one_mondo(tb->resum_mondo_pa, HV_CPU_QUEUE_RES_ERROR,
 911                            tb->resum_qmask);
 912         register_one_mondo(tb->nonresum_mondo_pa, HV_CPU_QUEUE_NONRES_ERROR,
 913                            tb->nonresum_qmask);
 914 }
 915
 916 /* Each queue region must be a power of 2 multiple of 64 bytes in
 917  * size.  The base real address must be aligned to the size of the
 918  * region.  Thus, an 8KB queue must be 8KB aligned, for example.
 919  */
 920 static void __init alloc_one_queue(unsigned long *pa_ptr, unsigned long qmask)
 921 {
 922         unsigned long size = PAGE_ALIGN(qmask + 1);
 923         unsigned long order = get_order(size);
 924         unsigned long p;
 925
 926         p = __get_free_pages(GFP_KERNEL, order);
 927         if (!p) {
 928                 prom_printf("SUN4V: Error, cannot allocate queue.\n");
 929                 prom_halt();
 930         }
 931
 932         *pa_ptr = __pa(p);
 933 }
 934
 935 static void __init init_cpu_send_mondo_info(struct trap_per_cpu *tb)
 936 {
 937 #ifdef CONFIG_SMP
 938         unsigned long page;
 939
 940         BUILD_BUG_ON((NR_CPUS * sizeof(u16)) > (PAGE_SIZE - 64));
 941
 942         page = get_zeroed_page(GFP_KERNEL);
 943         if (!page) {
 944                 prom_printf("SUN4V: Error, cannot allocate cpu mondo page.\n");
 945                 prom_halt();
 946         }
 947
 948         tb->cpu_mondo_block_pa = __pa(page);
 949         tb->cpu_list_pa = __pa(page + 64);
 950 #endif
 951 }
 952
 953 /* Allocate mondo and error queues for all possible cpus.  */
 954 static void __init sun4v_init_mondo_queues(void)
 955 {
 956         int cpu;
 957
 958         for_each_possible_cpu(cpu) {
 959                 struct trap_per_cpu *tb = &trap_block[cpu];
 960
 961                 alloc_one_queue(&tb->cpu_mondo_pa, tb->cpu_mondo_qmask);
 962                 alloc_one_queue(&tb->dev_mondo_pa, tb->dev_mondo_qmask);
 963                 alloc_one_queue(&tb->resum_mondo_pa, tb->resum_qmask);
 964                 alloc_one_queue(&tb->resum_kernel_buf_pa, tb->resum_qmask);
 965                 alloc_one_queue(&tb->nonresum_mondo_pa, tb->nonresum_qmask);
 966                 alloc_one_queue(&tb->nonresum_kernel_buf_pa,
 967                                 tb->nonresum_qmask);
 968         }
 969 }
 970
 971 static void __init init_send_mondo_info(void)
 972 {
 973         int cpu;
 974
 975         for_each_possible_cpu(cpu) {
 976                 struct trap_per_cpu *tb = &trap_block[cpu];
 977
 978                 init_cpu_send_mondo_info(tb);
 979         }
 980 }
 981
 982 static struct irqaction timer_irq_action = {
 983         .name = "timer",
 984 };
 985
 986 /* Only invoked on boot processor. */
 987 void __init init_IRQ(void)
 988 {
 989         unsigned long size;
 990
 991         map_prom_timers();
 992         kill_prom_timer();
 993
 994         size = sizeof(struct ino_bucket) * NUM_IVECS;
 995         ivector_table = kzalloc(size, GFP_KERNEL);
 996         if (!ivector_table) {
 997                 prom_printf("Fatal error, cannot allocate ivector_table\n");
 998                 prom_halt();
 999         }
1000         __flush_dcache_range((unsigned long) ivector_table,
1001                              ((unsigned long) ivector_table) + size);
1002
1003         ivector_table_pa = __pa(ivector_table);
1004
1005         if (tlb_type == hypervisor)
1006                 sun4v_init_mondo_queues();
1007
1008         init_send_mondo_info();
1009
1010         if (tlb_type == hypervisor) {
1011                 /* Load up the boot cpu's entries.  */
1012                 sun4v_register_mondo_queues(hard_smp_processor_id());
1013         }
1014
1015         /* We need to clear any IRQ's pending in the soft interrupt
1016          * registers, a spurious one could be left around from the
1017          * PROM timer which we just disabled.
1018          */
1019         clear_softint(get_softint());
1020
1021         /* Now that ivector table is initialized, it is safe
1022          * to receive IRQ vector traps.  We will normally take
1023          * one or two right now, in case some device PROM used
1024          * to boot us wants to speak to us.  We just ignore them.
1025          */
1026         __asm__ __volatile__("rdpr      %%pstate, %%g1\n\t"
1027                              "or        %%g1, %0, %%g1\n\t"
1028                              "wrpr      %%g1, 0x0, %%pstate"
1029                              : /* No outputs */
1030                              : "i" (PSTATE_IE)
1031                              : "g1");
1032
1033         irq_desc[0].action = &timer_irq_action;
1034 }