arch/sh/kernel/cpu/sh4a/setup-sh7770.c

   1 /*
   2  * SH7770 Setup
   3  *
   4  *  Copyright (C) 2006 - 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/sh_timer.h>
  15 #include <linux/io.h>
  16
  17 static struct plat_sci_port sci_platform_data[] = {
  18         {
  19                 .mapbase        = 0xff923000,
  20                 .flags          = UPF_BOOT_AUTOCONF,
  21                 .type           = PORT_SCIF,
  22                 .irqs           = { 61, 61, 61, 61 },
  23         }, {
  24                 .mapbase        = 0xff924000,
  25                 .flags          = UPF_BOOT_AUTOCONF,
  26                 .type           = PORT_SCIF,
  27                 .irqs           = { 62, 62, 62, 62 },
  28         }, {
  29                 .mapbase        = 0xff925000,
  30                 .flags          = UPF_BOOT_AUTOCONF,
  31                 .type           = PORT_SCIF,
  32                 .irqs           = { 63, 63, 63, 63 },
  33         }, {
  34                 .mapbase        = 0xff926000,
  35                 .flags          = UPF_BOOT_AUTOCONF,
  36                 .type           = PORT_SCIF,
  37                 .irqs           = { 64, 64, 64, 64 },
  38         }, {
  39                 .mapbase        = 0xff927000,
  40                 .flags          = UPF_BOOT_AUTOCONF,
  41                 .type           = PORT_SCIF,
  42                 .irqs           = { 65, 65, 65, 65 },
  43         }, {
  44                 .mapbase        = 0xff928000,
  45                 .flags          = UPF_BOOT_AUTOCONF,
  46                 .type           = PORT_SCIF,
  47                 .irqs           = { 66, 66, 66, 66 },
  48         }, {
  49                 .mapbase        = 0xff929000,
  50                 .flags          = UPF_BOOT_AUTOCONF,
  51                 .type           = PORT_SCIF,
  52                 .irqs           = { 67, 67, 67, 67 },
  53         }, {
  54                 .mapbase        = 0xff92a000,
  55                 .flags          = UPF_BOOT_AUTOCONF,
  56                 .type           = PORT_SCIF,
  57                 .irqs           = { 68, 68, 68, 68 },
  58         }, {
  59                 .mapbase        = 0xff92b000,
  60                 .flags          = UPF_BOOT_AUTOCONF,
  61                 .type           = PORT_SCIF,
  62                 .irqs           = { 69, 69, 69, 69 },
  63         }, {
  64                 .mapbase        = 0xff92c000,
  65                 .flags          = UPF_BOOT_AUTOCONF,
  66                 .type           = PORT_SCIF,
  67                 .irqs           = { 70, 70, 70, 70 },
  68         }, {
  69                 .flags = 0,
  70         }
  71 };
  72
  73 static struct platform_device sci_device = {
  74         .name           = "sh-sci",
  75         .id             = -1,
  76         .dev            = {
  77                 .platform_data  = sci_platform_data,
  78         },
  79 };
  80
  81 static struct sh_timer_config tmu0_platform_data = {
  82         .name = "TMU0",
  83         .channel_offset = 0x04,
  84         .timer_bit = 0,
  85         .clk = "peripheral_clk",
  86         .clockevent_rating = 200,
  87 };
  88
  89 static struct resource tmu0_resources[] = {
  90         [0] = {
  91                 .name   = "TMU0",
  92                 .start  = 0xffd80008,
  93                 .end    = 0xffd80013,
  94                 .flags  = IORESOURCE_MEM,
  95         },
  96         [1] = {
  97                 .start  = 16,
  98                 .flags  = IORESOURCE_IRQ,
  99         },
 100 };
 101
 102 static struct platform_device tmu0_device = {
 103         .name           = "sh_tmu",
 104         .id             = 0,
 105         .dev = {
 106                 .platform_data  = &tmu0_platform_data,
 107         },
 108         .resource       = tmu0_resources,
 109         .num_resources  = ARRAY_SIZE(tmu0_resources),
 110 };
 111
 112 static struct sh_timer_config tmu1_platform_data = {
 113         .name = "TMU1",
 114         .channel_offset = 0x10,
 115         .timer_bit = 1,
 116         .clk = "peripheral_clk",
 117         .clocksource_rating = 200,
 118 };
 119
 120 static struct resource tmu1_resources[] = {
 121         [0] = {
 122                 .name   = "TMU1",
 123                 .start  = 0xffd80014,
 124                 .end    = 0xffd8001f,
 125                 .flags  = IORESOURCE_MEM,
 126         },
 127         [1] = {
 128                 .start  = 17,
 129                 .flags  = IORESOURCE_IRQ,
 130         },
 131 };
 132
 133 static struct platform_device tmu1_device = {
 134         .name           = "sh_tmu",
 135         .id             = 1,
 136         .dev = {
 137                 .platform_data  = &tmu1_platform_data,
 138         },
 139         .resource       = tmu1_resources,
 140         .num_resources  = ARRAY_SIZE(tmu1_resources),
 141 };
 142
 143 static struct sh_timer_config tmu2_platform_data = {
 144         .name = "TMU2",
 145         .channel_offset = 0x1c,
 146         .timer_bit = 2,
 147         .clk = "peripheral_clk",
 148 };
 149
 150 static struct resource tmu2_resources[] = {
 151         [0] = {
 152                 .name   = "TMU2",
 153                 .start  = 0xffd80020,
 154                 .end    = 0xffd8002f,
 155                 .flags  = IORESOURCE_MEM,
 156         },
 157         [1] = {
 158                 .start  = 18,
 159                 .flags  = IORESOURCE_IRQ,
 160         },
 161 };
 162
 163 static struct platform_device tmu2_device = {
 164         .name           = "sh_tmu",
 165         .id             = 2,
 166         .dev = {
 167                 .platform_data  = &tmu2_platform_data,
 168         },
 169         .resource       = tmu2_resources,
 170         .num_resources  = ARRAY_SIZE(tmu2_resources),
 171 };
 172
 173 static struct sh_timer_config tmu3_platform_data = {
 174         .name = "TMU3",
 175         .channel_offset = 0x04,
 176         .timer_bit = 0,
 177         .clk = "peripheral_clk",
 178 };
 179
 180 static struct resource tmu3_resources[] = {
 181         [0] = {
 182                 .name   = "TMU3",
 183                 .start  = 0xffd81008,
 184                 .end    = 0xffd81013,
 185                 .flags  = IORESOURCE_MEM,
 186         },
 187         [1] = {
 188                 .start  = 19,
 189                 .flags  = IORESOURCE_IRQ,
 190         },
 191 };
 192
 193 static struct platform_device tmu3_device = {
 194         .name           = "sh_tmu",
 195         .id             = 3,
 196         .dev = {
 197                 .platform_data  = &tmu3_platform_data,
 198         },
 199         .resource       = tmu3_resources,
 200         .num_resources  = ARRAY_SIZE(tmu3_resources),
 201 };
 202
 203 static struct sh_timer_config tmu4_platform_data = {
 204         .name = "TMU4",
 205         .channel_offset = 0x10,
 206         .timer_bit = 1,
 207         .clk = "peripheral_clk",
 208 };
 209
 210 static struct resource tmu4_resources[] = {
 211         [0] = {
 212                 .name   = "TMU4",
 213                 .start  = 0xffd81014,
 214                 .end    = 0xffd8101f,
 215                 .flags  = IORESOURCE_MEM,
 216         },
 217         [1] = {
 218                 .start  = 20,
 219                 .flags  = IORESOURCE_IRQ,
 220         },
 221 };
 222
 223 static struct platform_device tmu4_device = {
 224         .name           = "sh_tmu",
 225         .id             = 4,
 226         .dev = {
 227                 .platform_data  = &tmu4_platform_data,
 228         },
 229         .resource       = tmu4_resources,
 230         .num_resources  = ARRAY_SIZE(tmu4_resources),
 231 };
 232
 233 static struct sh_timer_config tmu5_platform_data = {
 234         .name = "TMU5",
 235         .channel_offset = 0x1c,
 236         .timer_bit = 2,
 237         .clk = "peripheral_clk",
 238 };
 239
 240 static struct resource tmu5_resources[] = {
 241         [0] = {
 242                 .name   = "TMU5",
 243                 .start  = 0xffd81020,
 244                 .end    = 0xffd8102f,
 245                 .flags  = IORESOURCE_MEM,
 246         },
 247         [1] = {
 248                 .start  = 21,
 249                 .flags  = IORESOURCE_IRQ,
 250         },
 251 };
 252
 253 static struct platform_device tmu5_device = {
 254         .name           = "sh_tmu",
 255         .id             = 5,
 256         .dev = {
 257                 .platform_data  = &tmu5_platform_data,
 258         },
 259         .resource       = tmu5_resources,
 260         .num_resources  = ARRAY_SIZE(tmu5_resources),
 261 };
 262
 263 static struct sh_timer_config tmu6_platform_data = {
 264         .name = "TMU6",
 265         .channel_offset = 0x04,
 266         .timer_bit = 0,
 267         .clk = "peripheral_clk",
 268 };
 269
 270 static struct resource tmu6_resources[] = {
 271         [0] = {
 272                 .name   = "TMU6",
 273                 .start  = 0xffd82008,
 274                 .end    = 0xffd82013,
 275                 .flags  = IORESOURCE_MEM,
 276         },
 277         [1] = {
 278                 .start  = 22,
 279                 .flags  = IORESOURCE_IRQ,
 280         },
 281 };
 282
 283 static struct platform_device tmu6_device = {
 284         .name           = "sh_tmu",
 285         .id             = 6,
 286         .dev = {
 287                 .platform_data  = &tmu6_platform_data,
 288         },
 289         .resource       = tmu6_resources,
 290         .num_resources  = ARRAY_SIZE(tmu6_resources),
 291 };
 292
 293 static struct sh_timer_config tmu7_platform_data = {
 294         .name = "TMU7",
 295         .channel_offset = 0x10,
 296         .timer_bit = 1,
 297         .clk = "peripheral_clk",
 298 };
 299
 300 static struct resource tmu7_resources[] = {
 301         [0] = {
 302                 .name   = "TMU7",
 303                 .start  = 0xffd82014,
 304                 .end    = 0xffd8201f,
 305                 .flags  = IORESOURCE_MEM,
 306         },
 307         [1] = {
 308                 .start  = 23,
 309                 .flags  = IORESOURCE_IRQ,
 310         },
 311 };
 312
 313 static struct platform_device tmu7_device = {
 314         .name           = "sh_tmu",
 315         .id             = 7,
 316         .dev = {
 317                 .platform_data  = &tmu7_platform_data,
 318         },
 319         .resource       = tmu7_resources,
 320         .num_resources  = ARRAY_SIZE(tmu7_resources),
 321 };
 322
 323 static struct sh_timer_config tmu8_platform_data = {
 324         .name = "TMU8",
 325         .channel_offset = 0x1c,
 326         .timer_bit = 2,
 327         .clk = "peripheral_clk",
 328 };
 329
 330 static struct resource tmu8_resources[] = {
 331         [0] = {
 332                 .name   = "TMU8",
 333                 .start  = 0xffd82020,
 334                 .end    = 0xffd8202b,
 335                 .flags  = IORESOURCE_MEM,
 336         },
 337         [1] = {
 338                 .start  = 24,
 339                 .flags  = IORESOURCE_IRQ,
 340         },
 341 };
 342
 343 static struct platform_device tmu8_device = {
 344         .name           = "sh_tmu",
 345         .id             = 8,
 346         .dev = {
 347                 .platform_data  = &tmu8_platform_data,
 348         },
 349         .resource       = tmu8_resources,
 350         .num_resources  = ARRAY_SIZE(tmu8_resources),
 351 };
 352
 353 static struct platform_device *sh7770_devices[] __initdata = {
 354         &tmu0_device,
 355         &tmu1_device,
 356         &tmu2_device,
 357         &tmu3_device,
 358         &tmu4_device,
 359         &tmu5_device,
 360         &tmu6_device,
 361         &tmu7_device,
 362         &tmu8_device,
 363         &sci_device,
 364 };
 365
 366 static int __init sh7770_devices_setup(void)
 367 {
 368         return platform_add_devices(sh7770_devices,
 369                                     ARRAY_SIZE(sh7770_devices));
 370 }
 371 arch_initcall(sh7770_devices_setup);
 372
 373 static struct platform_device *sh7770_early_devices[] __initdata = {
 374         &tmu0_device,
 375         &tmu1_device,
 376         &tmu2_device,
 377         &tmu3_device,
 378         &tmu4_device,
 379         &tmu5_device,
 380         &tmu6_device,
 381         &tmu7_device,
 382         &tmu8_device,
 383 };
 384
 385 void __init plat_early_device_setup(void)
 386 {
 387         early_platform_add_devices(sh7770_early_devices,
 388                                    ARRAY_SIZE(sh7770_early_devices));
 389 }
 390
 391 enum {
 392         UNUSED = 0,
 393
 394         /* interrupt sources */
 395         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 396         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 397         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 398         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 399
 400         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
 401
 402         GPIO,
 403         TMU0, TMU1, TMU2, TMU2_TICPI,
 404         TMU3, TMU4, TMU5, TMU5_TICPI,
 405         TMU6, TMU7, TMU8,
 406         HAC, IPI, SPDIF, HUDI, I2C,
 407         DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
 408         I2S0, I2S1, I2S2, I2S3,
 409         SRC_RX, SRC_TX, SRC_SPDIF,
 410         DU, VIDEO_IN, REMOTE, YUV, USB, ATAPI, CAN, GPS, GFX2D,
 411         GFX3D_MBX, GFX3D_DMAC,
 412         EXBUS_ATA,
 413         SPI0, SPI1,
 414         SCIF089, SCIF1234, SCIF567,
 415         ADC,
 416         BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
 417         BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
 418         BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31,
 419
 420         /* interrupt groups */
 421         TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC,
 422 };
 423
 424 static struct intc_vect vectors[] __initdata = {
 425         INTC_VECT(GPIO, 0x3e0),
 426         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 427         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
 428         INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0),
 429         INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0),
 430         INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520),
 431         INTC_VECT(TMU8, 0x540),
 432         INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),
 433         INTC_VECT(SPDIF, 0x5e0),
 434         INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620),
 435         INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
 436         INTC_VECT(DMAC0_DMINT2, 0x680),
 437         INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0),
 438         INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700),
 439         INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740),
 440         INTC_VECT(SRC_SPDIF, 0x760),
 441         INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0),
 442         INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0),
 443         INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860),
 444         INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0),
 445         INTC_VECT(GFX2D, 0x8c0),
 446         INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920),
 447         INTC_VECT(EXBUS_ATA, 0x940),
 448         INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980),
 449         INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0),
 450         INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00),
 451         INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40),
 452         INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80),
 453         INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0),
 454         INTC_VECT(ADC, 0xb20),
 455         INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0),
 456         INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00),
 457         INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40),
 458         INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80),
 459         INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0),
 460         INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00),
 461         INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40),
 462         INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80),
 463         INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0),
 464         INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00),
 465         INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40),
 466         INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80),
 467         INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0),
 468         INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00),
 469         INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40),
 470         INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80),
 471 };
 472
 473 static struct intc_group groups[] __initdata = {
 474         INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
 475                    TMU5_TICPI, TMU6, TMU7, TMU8),
 476         INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2),
 477         INTC_GROUP(I2S, I2S0, I2S1, I2S2, I2S3),
 478         INTC_GROUP(SRC, SRC_RX, SRC_TX, SRC_SPDIF),
 479         INTC_GROUP(GFX3D, GFX3D_MBX, GFX3D_DMAC),
 480         INTC_GROUP(SPI, SPI0, SPI1),
 481         INTC_GROUP(SCIF, SCIF089, SCIF1234, SCIF567),
 482         INTC_GROUP(BBDMAC,
 483                    BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
 484                    BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
 485                    BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31),
 486 };
 487
 488 static struct intc_mask_reg mask_registers[] __initdata = {
 489         { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */
 490           { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D,
 491             GPS, CAN, ATAPI, USB, YUV, REMOTE, VIDEO_IN, DU, SRC, I2S,
 492             DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },
 493 };
 494
 495 static struct intc_prio_reg prio_registers[] __initdata = {
 496         { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } },
 497         { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
 498         { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } },
 499         { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } },
 500         { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } },
 501         { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } },
 502         { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } },
 503         { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } },
 504         { 0xffe00020, 0, 32, 8, /* INT2PRI8 */
 505           { BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, BBDMAC_15_18 } },
 506         { 0xffe00024, 0, 32, 8, /* INT2PRI9 */
 507           { BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, BBDMAC_28 } },
 508         { 0xffe00028, 0, 32, 8, /* INT2PRI10 */
 509           { BBDMAC_29, BBDMAC_30, BBDMAC_31 } },
 510         { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */
 511           { TMU1, TMU2, TMU2_TICPI, TMU3 } },
 512         { 0xffe00030, 0, 32, 8, /* INT2PRI12 */
 513           { TMU4, TMU5, TMU5_TICPI, TMU6 } },
 514         { 0xffe00034, 0, 32, 8, /* INT2PRI13 */
 515           { TMU7, TMU8 } },
 516 };
 517
 518 static DECLARE_INTC_DESC(intc_desc, "sh7770", vectors, groups,
 519                          mask_registers, prio_registers, NULL);
 520
 521 /* Support for external interrupt pins in IRQ mode */
 522 static struct intc_vect irq_vectors[] __initdata = {
 523         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 524         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 525         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 526 };
 527
 528 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 529         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 530           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, } },
 531 };
 532
 533 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 534         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 535                                                IRQ4, IRQ5, } },
 536 };
 537
 538 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 539         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 540                                             IRQ4, IRQ5, } },
 541 };
 542
 543 static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors,
 544                          NULL, irq_mask_registers, irq_prio_registers,
 545                          irq_sense_registers);
 546
 547 /* External interrupt pins in IRL mode */
 548 static struct intc_vect irl_vectors[] __initdata = {
 549         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 550         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 551         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 552         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 553         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 554         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 555         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 556         INTC_VECT(IRL_HHHL, 0x3c0),
 557 };
 558
 559 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 560         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 561           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 562             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 563             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 564             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 565 };
 566
 567 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 568         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 569           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 570             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 571             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 572             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 573             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 574 };
 575
 576 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
 577                          NULL, irl7654_mask_registers, NULL, NULL);
 578
 579 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 580                          NULL, irl3210_mask_registers, NULL, NULL);
 581
 582 #define INTC_ICR0       0xffd00000
 583 #define INTC_INTMSK0    0xffd00044
 584 #define INTC_INTMSK1    0xffd00048
 585 #define INTC_INTMSK2    0xffd40080
 586 #define INTC_INTMSKCLR1 0xffd00068
 587 #define INTC_INTMSKCLR2 0xffd40084
 588
 589 void __init plat_irq_setup(void)
 590 {
 591         /* disable IRQ7-0 */
 592         ctrl_outl(0xff000000, INTC_INTMSK0);
 593
 594         /* disable IRL3-0 + IRL7-4 */
 595         ctrl_outl(0xc0000000, INTC_INTMSK1);
 596         ctrl_outl(0xfffefffe, INTC_INTMSK2);
 597
 598         /* select IRL mode for IRL3-0 + IRL7-4 */
 599         ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 600
 601         /* disable holding function, ie enable "SH-4 Mode" */
 602         ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 603
 604         register_intc_controller(&intc_desc);
 605 }
 606
 607 void __init plat_irq_setup_pins(int mode)
 608 {
 609         switch (mode) {
 610         case IRQ_MODE_IRQ:
 611                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 612                 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 613                 register_intc_controller(&intc_irq_desc);
 614                 break;
 615         case IRQ_MODE_IRL7654:
 616                 /* enable IRL7-4 but don't provide any masking */
 617                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 618                 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
 619                 break;
 620         case IRQ_MODE_IRL3210:
 621                 /* enable IRL0-3 but don't provide any masking */
 622                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 623                 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
 624                 break;
 625         case IRQ_MODE_IRL7654_MASK:
 626                 /* enable IRL7-4 and mask using cpu intc controller */
 627                 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
 628                 register_intc_controller(&intc_irl7654_desc);
 629                 break;
 630         case IRQ_MODE_IRL3210_MASK:
 631                 /* enable IRL0-3 and mask using cpu intc controller */
 632                 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
 633                 register_intc_controller(&intc_irl3210_desc);
 634                 break;
 635         default:
 636                 BUG();
 637         }
 638 }