arch/sh/kernel/cpu/sh4a/setup-sh7757.c

   1 /*
   2  * SH7757 Setup
   3  *
   4  * Copyright (C) 2009  Renesas Solutions Corp.
   5  *
   6  *  based on setup-sh7785.c : Copyright (C) 2007  Paul Mundt
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/platform_device.h>
  13 #include <linux/init.h>
  14 #include <linux/serial.h>
  15 #include <linux/serial_sci.h>
  16 #include <linux/io.h>
  17 #include <linux/mm.h>
  18 #include <linux/sh_timer.h>
  19
  20 static struct plat_sci_port scif2_platform_data = {
  21         .mapbase        = 0xfe4b0000,           /* SCIF2 */
  22         .flags          = UPF_BOOT_AUTOCONF,
  23         .type           = PORT_SCIF,
  24         .irqs           = { 40, 40, 40, 40 },
  25 };
  26
  27 static struct platform_device scif2_device = {
  28         .name           = "sh-sci",
  29         .id             = 2,
  30         .dev            = {
  31                 .platform_data  = &scif2_platform_data,
  32         },
  33 };
  34
  35 static struct plat_sci_port scif3_platform_data = {
  36         .mapbase        = 0xfe4c0000,           /* SCIF3 */
  37         .flags          = UPF_BOOT_AUTOCONF,
  38         .type           = PORT_SCIF,
  39         .irqs           = { 76, 76, 76, 76 },
  40 };
  41
  42 static struct platform_device scif3_device = {
  43         .name           = "sh-sci",
  44         .id             = 3,
  45         .dev            = {
  46                 .platform_data  = &scif3_platform_data,
  47         },
  48 };
  49
  50 static struct plat_sci_port scif4_platform_data = {
  51         .mapbase        = 0xfe4d0000,           /* SCIF4 */
  52         .flags          = UPF_BOOT_AUTOCONF,
  53         .type           = PORT_SCIF,
  54         .irqs           = { 104, 104, 104, 104 },
  55 };
  56
  57 static struct platform_device scif4_device = {
  58         .name           = "sh-sci",
  59         .id             = 4,
  60         .dev            = {
  61                 .platform_data  = &scif4_platform_data,
  62         },
  63 };
  64
  65 static struct sh_timer_config tmu0_platform_data = {
  66         .channel_offset = 0x04,
  67         .timer_bit = 0,
  68         .clockevent_rating = 200,
  69 };
  70
  71 static struct resource tmu0_resources[] = {
  72         [0] = {
  73                 .start  = 0xfe430008,
  74                 .end    = 0xfe430013,
  75                 .flags  = IORESOURCE_MEM,
  76         },
  77         [1] = {
  78                 .start  = 28,
  79                 .flags  = IORESOURCE_IRQ,
  80         },
  81 };
  82
  83 static struct platform_device tmu0_device = {
  84         .name           = "sh_tmu",
  85         .id             = 0,
  86         .dev = {
  87                 .platform_data  = &tmu0_platform_data,
  88         },
  89         .resource       = tmu0_resources,
  90         .num_resources  = ARRAY_SIZE(tmu0_resources),
  91 };
  92
  93 static struct sh_timer_config tmu1_platform_data = {
  94         .channel_offset = 0x10,
  95         .timer_bit = 1,
  96         .clocksource_rating = 200,
  97 };
  98
  99 static struct resource tmu1_resources[] = {
 100         [0] = {
 101                 .start  = 0xfe430014,
 102                 .end    = 0xfe43001f,
 103                 .flags  = IORESOURCE_MEM,
 104         },
 105         [1] = {
 106                 .start  = 29,
 107                 .flags  = IORESOURCE_IRQ,
 108         },
 109 };
 110
 111 static struct platform_device tmu1_device = {
 112         .name           = "sh_tmu",
 113         .id             = 1,
 114         .dev = {
 115                 .platform_data  = &tmu1_platform_data,
 116         },
 117         .resource       = tmu1_resources,
 118         .num_resources  = ARRAY_SIZE(tmu1_resources),
 119 };
 120
 121 static struct platform_device *sh7757_devices[] __initdata = {
 122         &scif2_device,
 123         &scif3_device,
 124         &scif4_device,
 125         &tmu0_device,
 126         &tmu1_device,
 127 };
 128
 129 static int __init sh7757_devices_setup(void)
 130 {
 131         return platform_add_devices(sh7757_devices,
 132                                     ARRAY_SIZE(sh7757_devices));
 133 }
 134 arch_initcall(sh7757_devices_setup);
 135
 136 static struct platform_device *sh7757_early_devices[] __initdata = {
 137         &scif2_device,
 138         &scif3_device,
 139         &scif4_device,
 140         &tmu0_device,
 141         &tmu1_device,
 142 };
 143
 144 void __init plat_early_device_setup(void)
 145 {
 146         early_platform_add_devices(sh7757_early_devices,
 147                                    ARRAY_SIZE(sh7757_early_devices));
 148 }
 149
 150 enum {
 151         UNUSED = 0,
 152
 153         /* interrupt sources */
 154
 155         IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 156         IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 157         IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 158         IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
 159
 160         IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 161         IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 162         IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 163         IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
 164         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 165
 166         SDHI,
 167         DVC,
 168         IRQ8, IRQ9, IRQ10,
 169         WDT0,
 170         TMU0, TMU1, TMU2, TMU2_TICPI,
 171         HUDI,
 172
 173         ARC4,
 174         DMAC0,
 175         IRQ11,
 176         SCIF2,
 177         DMAC1_6,
 178         USB0,
 179         IRQ12,
 180         JMC,
 181         SPI1,
 182         IRQ13, IRQ14,
 183         USB1,
 184         TMR01, TMR23, TMR45,
 185         WDT1,
 186         FRT,
 187         LPC,
 188         SCIF0, SCIF1, SCIF3,
 189         PECI0I, PECI1I, PECI2I,
 190         IRQ15,
 191         ETHERC,
 192         SPI0,
 193         ADC1,
 194         DMAC1_8,
 195         SIM,
 196         TMU3, TMU4, TMU5,
 197         ADC0,
 198         SCIF4,
 199         IIC0_0, IIC0_1, IIC0_2, IIC0_3,
 200         IIC1_0, IIC1_1, IIC1_2, IIC1_3,
 201         IIC2_0, IIC2_1, IIC2_2, IIC2_3,
 202         IIC3_0, IIC3_1, IIC3_2, IIC3_3,
 203         IIC4_0, IIC4_1, IIC4_2, IIC4_3,
 204         IIC5_0, IIC5_1, IIC5_2, IIC5_3,
 205         IIC6_0, IIC6_1, IIC6_2, IIC6_3,
 206         IIC7_0, IIC7_1, IIC7_2, IIC7_3,
 207         IIC8_0, IIC8_1, IIC8_2, IIC8_3,
 208         IIC9_0, IIC9_1, IIC9_2, IIC9_3,
 209         PCIINTA,
 210         PCIE,
 211         SGPIO,
 212
 213         /* interrupt groups */
 214
 215         TMU012, TMU345,
 216 };
 217
 218 static struct intc_vect vectors[] __initdata = {
 219         INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
 220         INTC_VECT(SDHI, 0x4c0),
 221         INTC_VECT(DVC, 0x4e0),
 222         INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
 223         INTC_VECT(IRQ10, 0x540),
 224         INTC_VECT(WDT0, 0x560),
 225         INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
 226         INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
 227         INTC_VECT(HUDI, 0x600),
 228         INTC_VECT(ARC4, 0x620),
 229         INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
 230         INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
 231         INTC_VECT(DMAC0, 0x6c0),
 232         INTC_VECT(IRQ11, 0x6e0),
 233         INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
 234         INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
 235         INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
 236         INTC_VECT(DMAC1_6, 0x7c0), INTC_VECT(DMAC1_6, 0x7e0),
 237         INTC_VECT(USB0, 0x840),
 238         INTC_VECT(IRQ12, 0x880),
 239         INTC_VECT(JMC, 0x8a0),
 240         INTC_VECT(SPI1, 0x8c0),
 241         INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
 242         INTC_VECT(USB1, 0x920),
 243         INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
 244         INTC_VECT(TMR45, 0xa40),
 245         INTC_VECT(WDT1, 0xa60),
 246         INTC_VECT(FRT, 0xa80),
 247         INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
 248         INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
 249         INTC_VECT(LPC, 0xb20),
 250         INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
 251         INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
 252         INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
 253         INTC_VECT(PECI0I, 0xc00), INTC_VECT(PECI1I, 0xc20),
 254         INTC_VECT(PECI2I, 0xc40),
 255         INTC_VECT(IRQ15, 0xc60),
 256         INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
 257         INTC_VECT(SPI0, 0xcc0),
 258         INTC_VECT(ADC1, 0xce0),
 259         INTC_VECT(DMAC1_8, 0xd00), INTC_VECT(DMAC1_8, 0xd20),
 260         INTC_VECT(DMAC1_8, 0xd40), INTC_VECT(DMAC1_8, 0xd60),
 261         INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
 262         INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
 263         INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
 264         INTC_VECT(TMU5, 0xe40),
 265         INTC_VECT(ADC0, 0xe60),
 266         INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
 267         INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
 268         INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
 269         INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
 270         INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
 271         INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
 272         INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
 273         INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
 274         INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
 275         INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
 276         INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
 277         INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
 278         INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
 279         INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
 280         INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
 281         INTC_VECT(IIC6_2, 0x1920), INTC_VECT(IIC6_3, 0x1980),
 282         INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
 283         INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
 284         INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
 285         INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
 286         INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
 287         INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
 288         INTC_VECT(PCIINTA, 0x1ce0),
 289         INTC_VECT(PCIE, 0x1e00),
 290         INTC_VECT(SGPIO, 0x1f80),
 291         INTC_VECT(SGPIO, 0x1fa0),
 292 };
 293
 294 static struct intc_group groups[] __initdata = {
 295         INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
 296         INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
 297 };
 298
 299 static struct intc_mask_reg mask_registers[] __initdata = {
 300         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 301           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 302
 303         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 304           { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
 305             IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
 306             IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
 307             IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
 308             IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
 309             IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
 310             IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
 311             IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
 312
 313         { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
 314           { 0, 0, 0, 0, 0, 0, 0, 0,
 315             0, DMAC1_8, 0, PECI0I, LPC, FRT, WDT1, TMR45,
 316             TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0,
 317             HUDI, 0, WDT0, SCIF3, SCIF2, SDHI, TMU345, TMU012
 318              } },
 319
 320         { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
 321           { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
 322             IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
 323             ADC1, 0, DMAC1_6, ADC0, SPI0, SIM, PECI2I, PECI1I,
 324             ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
 325              } },
 326
 327         { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
 328           { IIC4_1, IIC4_2, IIC5_0, 0, 0, 0, SGPIO, 0,
 329             0, 0, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
 330             IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
 331             IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, PCIE, IIC2_2
 332              } },
 333
 334         { 0xffd100d0, 0xff1400d4, 32, /* INT2MSKR3 / INT2MSKCR4 */
 335           { 0, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, 0, 0,
 336             IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
 337             PCIINTA, 0, IIC4_0, 0, 0, 0, 0, IIC9_3,
 338             IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
 339              } },
 340 };
 341
 342 #define INTPRI          0xffd00010
 343 #define INT2PRI0        0xffd40000
 344 #define INT2PRI1        0xffd40004
 345 #define INT2PRI2        0xffd40008
 346 #define INT2PRI3        0xffd4000c
 347 #define INT2PRI4        0xffd40010
 348 #define INT2PRI5        0xffd40014
 349 #define INT2PRI6        0xffd40018
 350 #define INT2PRI7        0xffd4001c
 351 #define INT2PRI8        0xffd400a0
 352 #define INT2PRI9        0xffd400a4
 353 #define INT2PRI10       0xffd400a8
 354 #define INT2PRI11       0xffd400ac
 355 #define INT2PRI12       0xffd400b0
 356 #define INT2PRI13       0xffd400b4
 357 #define INT2PRI14       0xffd400b8
 358 #define INT2PRI15       0xffd400bc
 359 #define INT2PRI16       0xffd10000
 360 #define INT2PRI17       0xffd10004
 361 #define INT2PRI18       0xffd10008
 362 #define INT2PRI19       0xffd1000c
 363 #define INT2PRI20       0xffd10010
 364 #define INT2PRI21       0xffd10014
 365 #define INT2PRI22       0xffd10018
 366 #define INT2PRI23       0xffd1001c
 367 #define INT2PRI24       0xffd100a0
 368 #define INT2PRI25       0xffd100a4
 369 #define INT2PRI26       0xffd100a8
 370 #define INT2PRI27       0xffd100ac
 371 #define INT2PRI28       0xffd100b0
 372 #define INT2PRI29       0xffd100b4
 373 #define INT2PRI30       0xffd100b8
 374 #define INT2PRI31       0xffd100bc
 375
 376 static struct intc_prio_reg prio_registers[] __initdata = {
 377         { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
 378                               IRQ4, IRQ5, IRQ6, IRQ7 } },
 379
 380         { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
 381         { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
 382         { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, WDT0, IRQ8 } },
 383         { INT2PRI3, 0, 32, 8, { HUDI, DMAC0, ADC0, IRQ9 } },
 384         { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
 385         { INT2PRI5, 0, 32, 8, { TMR45, WDT1, FRT, LPC } },
 386         { INT2PRI6, 0, 32, 8, { PECI0I, ETHERC, DMAC1_8, 0 } },
 387         { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
 388         { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
 389         { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
 390         { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2I, PECI1I } },
 391         { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC1_6, IRQ14 } },
 392         { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
 393         { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
 394
 395         { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
 396         { INT2PRI17, 0, 32, 8, { PCIE, 0, 0, IIC1_0 } },
 397         { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
 398         { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
 399         { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
 400         { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
 401         { INT2PRI22, 0, 32, 8, { IIC9_2, 0, 0, 0 } },
 402         { INT2PRI23, 0, 32, 8, { 0, SGPIO, IIC3_2, IIC5_1 } },
 403         { INT2PRI24, 0, 32, 8, { 0, 0, 0, IIC1_1 } },
 404         { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
 405         { INT2PRI26, 0, 32, 8, { 0, 0, 0, IIC9_3 } },
 406         { INT2PRI27, 0, 32, 8, { PCIINTA, IIC6_0, IIC4_0, IIC6_1 } },
 407         { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, 0, IIC6_2 } },
 408         { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
 409         { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, 0 } },
 410         { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
 411 };
 412
 413 static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
 414                          mask_registers, prio_registers, NULL);
 415
 416 /* Support for external interrupt pins in IRQ mode */
 417 static struct intc_vect vectors_irq0123[] __initdata = {
 418         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 419         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 420 };
 421
 422 static struct intc_vect vectors_irq4567[] __initdata = {
 423         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 424         INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
 425 };
 426
 427 static struct intc_sense_reg sense_registers[] __initdata = {
 428         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 429                                             IRQ4, IRQ5, IRQ6, IRQ7 } },
 430 };
 431
 432 static struct intc_mask_reg ack_registers[] __initdata = {
 433         { 0xffd00024, 0, 32, /* INTREQ */
 434           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 435 };
 436
 437 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
 438                              vectors_irq0123, NULL, mask_registers,
 439                              prio_registers, sense_registers, ack_registers);
 440
 441 static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
 442                              vectors_irq4567, NULL, mask_registers,
 443                              prio_registers, sense_registers, ack_registers);
 444
 445 /* External interrupt pins in IRL mode */
 446 static struct intc_vect vectors_irl0123[] __initdata = {
 447         INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
 448         INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
 449         INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
 450         INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
 451         INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
 452         INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
 453         INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
 454         INTC_VECT(IRL0_HHHL, 0x3c0),
 455 };
 456
 457 static struct intc_vect vectors_irl4567[] __initdata = {
 458         INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
 459         INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
 460         INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
 461         INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
 462         INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
 463         INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
 464         INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
 465         INTC_VECT(IRL4_HHHL, 0xcc0),
 466 };
 467
 468 static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
 469                          NULL, mask_registers, NULL, NULL);
 470
 471 static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
 472                          NULL, mask_registers, NULL, NULL);
 473
 474 #define INTC_ICR0       0xffd00000
 475 #define INTC_INTMSK0    0xffd00044
 476 #define INTC_INTMSK1    0xffd00048
 477 #define INTC_INTMSK2    0xffd40080
 478 #define INTC_INTMSKCLR1 0xffd00068
 479 #define INTC_INTMSKCLR2 0xffd40084
 480
 481 void __init plat_irq_setup(void)
 482 {
 483         /* disable IRQ3-0 + IRQ7-4 */
 484         __raw_writel(0xff000000, INTC_INTMSK0);
 485
 486         /* disable IRL3-0 + IRL7-4 */
 487         __raw_writel(0xc0000000, INTC_INTMSK1);
 488         __raw_writel(0xfffefffe, INTC_INTMSK2);
 489
 490         /* select IRL mode for IRL3-0 + IRL7-4 */
 491         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 492
 493         /* disable holding function, ie enable "SH-4 Mode" */
 494         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 495
 496         register_intc_controller(&intc_desc);
 497 }
 498
 499 void __init plat_irq_setup_pins(int mode)
 500 {
 501         switch (mode) {
 502         case IRQ_MODE_IRQ7654:
 503                 /* select IRQ mode for IRL7-4 */
 504                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00400000, INTC_ICR0);
 505                 register_intc_controller(&intc_desc_irq4567);
 506                 break;
 507         case IRQ_MODE_IRQ3210:
 508                 /* select IRQ mode for IRL3-0 */
 509                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00800000, INTC_ICR0);
 510                 register_intc_controller(&intc_desc_irq0123);
 511                 break;
 512         case IRQ_MODE_IRL7654:
 513                 /* enable IRL7-4 but don't provide any masking */
 514                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 515                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 516                 break;
 517         case IRQ_MODE_IRL3210:
 518                 /* enable IRL0-3 but don't provide any masking */
 519                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 520                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 521                 break;
 522         case IRQ_MODE_IRL7654_MASK:
 523                 /* enable IRL7-4 and mask using cpu intc controller */
 524                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 525                 register_intc_controller(&intc_desc_irl4567);
 526                 break;
 527         case IRQ_MODE_IRL3210_MASK:
 528                 /* enable IRL0-3 and mask using cpu intc controller */
 529                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 530                 register_intc_controller(&intc_desc_irl0123);
 531                 break;
 532         default:
 533                 BUG();
 534         }
 535 }
 536
 537 void __init plat_mem_setup(void)
 538 {
 539 }