4 * Copyright (C) 2009 Renesas Solutions Corp.
6 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
8 * Based on SH7723 Setup
9 * Copyright (C) 2008 Paul Mundt
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
15 #include <linux/platform_device.h>
16 #include <linux/init.h>
17 #include <linux/serial.h>
19 #include <linux/serial_sci.h>
20 #include <linux/uio_driver.h>
21 #include <linux/sh_dma.h>
22 #include <linux/sh_timer.h>
24 #include <linux/notifier.h>
26 #include <asm/suspend.h>
27 #include <asm/clock.h>
28 #include <asm/mmzone.h>
30 #include <cpu/dma-register.h>
31 #include <cpu/sh7724.h>
34 static const struct sh_dmae_slave_config sh7724_dmae_slaves[] = {
36 .slave_id = SHDMA_SLAVE_SCIF0_TX,
38 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
41 .slave_id = SHDMA_SLAVE_SCIF0_RX,
43 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
46 .slave_id = SHDMA_SLAVE_SCIF1_TX,
48 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
51 .slave_id = SHDMA_SLAVE_SCIF1_RX,
53 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
56 .slave_id = SHDMA_SLAVE_SCIF2_TX,
58 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
61 .slave_id = SHDMA_SLAVE_SCIF2_RX,
63 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
66 .slave_id = SHDMA_SLAVE_SCIF3_TX,
68 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
71 .slave_id = SHDMA_SLAVE_SCIF3_RX,
73 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
76 .slave_id = SHDMA_SLAVE_SCIF4_TX,
78 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
81 .slave_id = SHDMA_SLAVE_SCIF4_RX,
83 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
86 .slave_id = SHDMA_SLAVE_SCIF5_TX,
88 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
91 .slave_id = SHDMA_SLAVE_SCIF5_RX,
93 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_8BIT),
96 .slave_id = SHDMA_SLAVE_USB0D0_TX,
98 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
101 .slave_id = SHDMA_SLAVE_USB0D0_RX,
103 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
106 .slave_id = SHDMA_SLAVE_USB0D1_TX,
108 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
111 .slave_id = SHDMA_SLAVE_USB0D1_RX,
113 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
116 .slave_id = SHDMA_SLAVE_USB1D0_TX,
118 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
121 .slave_id = SHDMA_SLAVE_USB1D0_RX,
123 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
126 .slave_id = SHDMA_SLAVE_USB1D1_TX,
128 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
131 .slave_id = SHDMA_SLAVE_USB1D1_RX,
133 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_32BIT),
136 .slave_id = SHDMA_SLAVE_SDHI0_TX,
138 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
141 .slave_id = SHDMA_SLAVE_SDHI0_RX,
143 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
146 .slave_id = SHDMA_SLAVE_SDHI1_TX,
148 .chcr = DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
151 .slave_id = SHDMA_SLAVE_SDHI1_RX,
153 .chcr = DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL(XMIT_SZ_16BIT),
158 static const struct sh_dmae_channel sh7724_dmae_channels[] = {
186 static const unsigned int ts_shift[] = TS_SHIFT;
188 static struct sh_dmae_pdata dma_platform_data = {
189 .slave = sh7724_dmae_slaves,
190 .slave_num = ARRAY_SIZE(sh7724_dmae_slaves),
191 .channel = sh7724_dmae_channels,
192 .channel_num = ARRAY_SIZE(sh7724_dmae_channels),
193 .ts_low_shift = CHCR_TS_LOW_SHIFT,
194 .ts_low_mask = CHCR_TS_LOW_MASK,
195 .ts_high_shift = CHCR_TS_HIGH_SHIFT,
196 .ts_high_mask = CHCR_TS_HIGH_MASK,
197 .ts_shift = ts_shift,
198 .ts_shift_num = ARRAY_SIZE(ts_shift),
199 .dmaor_init = DMAOR_INIT,
202 /* Resource order important! */
203 static struct resource sh7724_dmae0_resources[] = {
205 /* Channel registers and DMAOR */
208 .flags = IORESOURCE_MEM,
214 .flags = IORESOURCE_MEM,
220 .flags = IORESOURCE_IRQ,
223 /* IRQ for channels 0-3 */
226 .flags = IORESOURCE_IRQ,
229 /* IRQ for channels 4-5 */
232 .flags = IORESOURCE_IRQ,
236 /* Resource order important! */
237 static struct resource sh7724_dmae1_resources[] = {
239 /* Channel registers and DMAOR */
242 .flags = IORESOURCE_MEM,
248 .flags = IORESOURCE_MEM,
254 .flags = IORESOURCE_IRQ,
257 /* IRQ for channels 0-3 */
260 .flags = IORESOURCE_IRQ,
263 /* IRQ for channels 4-5 */
266 .flags = IORESOURCE_IRQ,
270 static struct platform_device dma0_device = {
271 .name = "sh-dma-engine",
273 .resource = sh7724_dmae0_resources,
274 .num_resources = ARRAY_SIZE(sh7724_dmae0_resources),
276 .platform_data = &dma_platform_data,
279 .hwblk_id = HWBLK_DMAC0,
283 static struct platform_device dma1_device = {
284 .name = "sh-dma-engine",
286 .resource = sh7724_dmae1_resources,
287 .num_resources = ARRAY_SIZE(sh7724_dmae1_resources),
289 .platform_data = &dma_platform_data,
292 .hwblk_id = HWBLK_DMAC1,
297 static struct plat_sci_port scif0_platform_data = {
298 .mapbase = 0xffe00000,
299 .flags = UPF_BOOT_AUTOCONF,
300 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
301 .scbrr_algo_id = SCBRR_ALGO_2,
303 .irqs = { 80, 80, 80, 80 },
306 static struct platform_device scif0_device = {
310 .platform_data = &scif0_platform_data,
314 static struct plat_sci_port scif1_platform_data = {
315 .mapbase = 0xffe10000,
316 .flags = UPF_BOOT_AUTOCONF,
317 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
318 .scbrr_algo_id = SCBRR_ALGO_2,
320 .irqs = { 81, 81, 81, 81 },
323 static struct platform_device scif1_device = {
327 .platform_data = &scif1_platform_data,
331 static struct plat_sci_port scif2_platform_data = {
332 .mapbase = 0xffe20000,
333 .flags = UPF_BOOT_AUTOCONF,
334 .scscr = SCSCR_RE | SCSCR_TE | SCSCR_REIE,
335 .scbrr_algo_id = SCBRR_ALGO_2,
337 .irqs = { 82, 82, 82, 82 },
340 static struct platform_device scif2_device = {
344 .platform_data = &scif2_platform_data,
348 static struct plat_sci_port scif3_platform_data = {
349 .mapbase = 0xa4e30000,
350 .flags = UPF_BOOT_AUTOCONF,
351 .scscr = SCSCR_RE | SCSCR_TE,
352 .scbrr_algo_id = SCBRR_ALGO_3,
354 .irqs = { 56, 56, 56, 56 },
357 static struct platform_device scif3_device = {
361 .platform_data = &scif3_platform_data,
365 static struct plat_sci_port scif4_platform_data = {
366 .mapbase = 0xa4e40000,
367 .flags = UPF_BOOT_AUTOCONF,
368 .scscr = SCSCR_RE | SCSCR_TE,
369 .scbrr_algo_id = SCBRR_ALGO_3,
371 .irqs = { 88, 88, 88, 88 },
374 static struct platform_device scif4_device = {
378 .platform_data = &scif4_platform_data,
382 static struct plat_sci_port scif5_platform_data = {
383 .mapbase = 0xa4e50000,
384 .flags = UPF_BOOT_AUTOCONF,
385 .scscr = SCSCR_RE | SCSCR_TE,
386 .scbrr_algo_id = SCBRR_ALGO_3,
388 .irqs = { 109, 109, 109, 109 },
391 static struct platform_device scif5_device = {
395 .platform_data = &scif5_platform_data,
400 static struct resource rtc_resources[] = {
403 .end = 0xa465fec0 + 0x58 - 1,
404 .flags = IORESOURCE_IO,
409 .flags = IORESOURCE_IRQ,
414 .flags = IORESOURCE_IRQ,
419 .flags = IORESOURCE_IRQ,
423 static struct platform_device rtc_device = {
426 .num_resources = ARRAY_SIZE(rtc_resources),
427 .resource = rtc_resources,
429 .hwblk_id = HWBLK_RTC,
434 static struct resource iic0_resources[] = {
438 .end = 0x04470018 - 1,
439 .flags = IORESOURCE_MEM,
444 .flags = IORESOURCE_IRQ,
448 static struct platform_device iic0_device = {
449 .name = "i2c-sh_mobile",
450 .id = 0, /* "i2c0" clock */
451 .num_resources = ARRAY_SIZE(iic0_resources),
452 .resource = iic0_resources,
454 .hwblk_id = HWBLK_IIC0,
459 static struct resource iic1_resources[] = {
463 .end = 0x04750018 - 1,
464 .flags = IORESOURCE_MEM,
469 .flags = IORESOURCE_IRQ,
473 static struct platform_device iic1_device = {
474 .name = "i2c-sh_mobile",
475 .id = 1, /* "i2c1" clock */
476 .num_resources = ARRAY_SIZE(iic1_resources),
477 .resource = iic1_resources,
479 .hwblk_id = HWBLK_IIC1,
484 static struct uio_info vpu_platform_data = {
490 static struct resource vpu_resources[] = {
495 .flags = IORESOURCE_MEM,
498 /* place holder for contiguous memory */
502 static struct platform_device vpu_device = {
503 .name = "uio_pdrv_genirq",
506 .platform_data = &vpu_platform_data,
508 .resource = vpu_resources,
509 .num_resources = ARRAY_SIZE(vpu_resources),
511 .hwblk_id = HWBLK_VPU,
516 static struct uio_info veu0_platform_data = {
522 static struct resource veu0_resources[] = {
527 .flags = IORESOURCE_MEM,
530 /* place holder for contiguous memory */
534 static struct platform_device veu0_device = {
535 .name = "uio_pdrv_genirq",
538 .platform_data = &veu0_platform_data,
540 .resource = veu0_resources,
541 .num_resources = ARRAY_SIZE(veu0_resources),
543 .hwblk_id = HWBLK_VEU0,
548 static struct uio_info veu1_platform_data = {
554 static struct resource veu1_resources[] = {
559 .flags = IORESOURCE_MEM,
562 /* place holder for contiguous memory */
566 static struct platform_device veu1_device = {
567 .name = "uio_pdrv_genirq",
570 .platform_data = &veu1_platform_data,
572 .resource = veu1_resources,
573 .num_resources = ARRAY_SIZE(veu1_resources),
575 .hwblk_id = HWBLK_VEU1,
580 static struct uio_info beu0_platform_data = {
583 .irq = evt2irq(0x8A0),
586 static struct resource beu0_resources[] = {
591 .flags = IORESOURCE_MEM,
594 /* place holder for contiguous memory */
598 static struct platform_device beu0_device = {
599 .name = "uio_pdrv_genirq",
602 .platform_data = &beu0_platform_data,
604 .resource = beu0_resources,
605 .num_resources = ARRAY_SIZE(beu0_resources),
607 .hwblk_id = HWBLK_BEU0,
612 static struct uio_info beu1_platform_data = {
615 .irq = evt2irq(0xA00),
618 static struct resource beu1_resources[] = {
623 .flags = IORESOURCE_MEM,
626 /* place holder for contiguous memory */
630 static struct platform_device beu1_device = {
631 .name = "uio_pdrv_genirq",
634 .platform_data = &beu1_platform_data,
636 .resource = beu1_resources,
637 .num_resources = ARRAY_SIZE(beu1_resources),
639 .hwblk_id = HWBLK_BEU1,
643 static struct sh_timer_config cmt_platform_data = {
644 .channel_offset = 0x60,
646 .clockevent_rating = 125,
647 .clocksource_rating = 200,
650 static struct resource cmt_resources[] = {
654 .flags = IORESOURCE_MEM,
658 .flags = IORESOURCE_IRQ,
662 static struct platform_device cmt_device = {
666 .platform_data = &cmt_platform_data,
668 .resource = cmt_resources,
669 .num_resources = ARRAY_SIZE(cmt_resources),
671 .hwblk_id = HWBLK_CMT,
675 static struct sh_timer_config tmu0_platform_data = {
676 .channel_offset = 0x04,
678 .clockevent_rating = 200,
681 static struct resource tmu0_resources[] = {
685 .flags = IORESOURCE_MEM,
689 .flags = IORESOURCE_IRQ,
693 static struct platform_device tmu0_device = {
697 .platform_data = &tmu0_platform_data,
699 .resource = tmu0_resources,
700 .num_resources = ARRAY_SIZE(tmu0_resources),
702 .hwblk_id = HWBLK_TMU0,
706 static struct sh_timer_config tmu1_platform_data = {
707 .channel_offset = 0x10,
709 .clocksource_rating = 200,
712 static struct resource tmu1_resources[] = {
716 .flags = IORESOURCE_MEM,
720 .flags = IORESOURCE_IRQ,
724 static struct platform_device tmu1_device = {
728 .platform_data = &tmu1_platform_data,
730 .resource = tmu1_resources,
731 .num_resources = ARRAY_SIZE(tmu1_resources),
733 .hwblk_id = HWBLK_TMU0,
737 static struct sh_timer_config tmu2_platform_data = {
738 .channel_offset = 0x1c,
742 static struct resource tmu2_resources[] = {
746 .flags = IORESOURCE_MEM,
750 .flags = IORESOURCE_IRQ,
754 static struct platform_device tmu2_device = {
758 .platform_data = &tmu2_platform_data,
760 .resource = tmu2_resources,
761 .num_resources = ARRAY_SIZE(tmu2_resources),
763 .hwblk_id = HWBLK_TMU0,
768 static struct sh_timer_config tmu3_platform_data = {
769 .channel_offset = 0x04,
773 static struct resource tmu3_resources[] = {
777 .flags = IORESOURCE_MEM,
781 .flags = IORESOURCE_IRQ,
785 static struct platform_device tmu3_device = {
789 .platform_data = &tmu3_platform_data,
791 .resource = tmu3_resources,
792 .num_resources = ARRAY_SIZE(tmu3_resources),
794 .hwblk_id = HWBLK_TMU1,
798 static struct sh_timer_config tmu4_platform_data = {
799 .channel_offset = 0x10,
803 static struct resource tmu4_resources[] = {
807 .flags = IORESOURCE_MEM,
811 .flags = IORESOURCE_IRQ,
815 static struct platform_device tmu4_device = {
819 .platform_data = &tmu4_platform_data,
821 .resource = tmu4_resources,
822 .num_resources = ARRAY_SIZE(tmu4_resources),
824 .hwblk_id = HWBLK_TMU1,
828 static struct sh_timer_config tmu5_platform_data = {
829 .channel_offset = 0x1c,
833 static struct resource tmu5_resources[] = {
837 .flags = IORESOURCE_MEM,
841 .flags = IORESOURCE_IRQ,
845 static struct platform_device tmu5_device = {
849 .platform_data = &tmu5_platform_data,
851 .resource = tmu5_resources,
852 .num_resources = ARRAY_SIZE(tmu5_resources),
854 .hwblk_id = HWBLK_TMU1,
859 static struct uio_info jpu_platform_data = {
865 static struct resource jpu_resources[] = {
870 .flags = IORESOURCE_MEM,
873 /* place holder for contiguous memory */
877 static struct platform_device jpu_device = {
878 .name = "uio_pdrv_genirq",
881 .platform_data = &jpu_platform_data,
883 .resource = jpu_resources,
884 .num_resources = ARRAY_SIZE(jpu_resources),
886 .hwblk_id = HWBLK_JPU,
891 static struct uio_info spu0_platform_data = {
897 static struct resource spu0_resources[] = {
902 .flags = IORESOURCE_MEM,
905 /* place holder for contiguous memory */
909 static struct platform_device spu0_device = {
910 .name = "uio_pdrv_genirq",
913 .platform_data = &spu0_platform_data,
915 .resource = spu0_resources,
916 .num_resources = ARRAY_SIZE(spu0_resources),
918 .hwblk_id = HWBLK_SPU,
923 static struct uio_info spu1_platform_data = {
929 static struct resource spu1_resources[] = {
934 .flags = IORESOURCE_MEM,
937 /* place holder for contiguous memory */
941 static struct platform_device spu1_device = {
942 .name = "uio_pdrv_genirq",
945 .platform_data = &spu1_platform_data,
947 .resource = spu1_resources,
948 .num_resources = ARRAY_SIZE(spu1_resources),
950 .hwblk_id = HWBLK_SPU,
954 static struct platform_device *sh7724_devices[] __initdata = {
983 static int __init sh7724_devices_setup(void)
985 platform_resource_setup_memory(&vpu_device, "vpu", 2 << 20);
986 platform_resource_setup_memory(&veu0_device, "veu0", 2 << 20);
987 platform_resource_setup_memory(&veu1_device, "veu1", 2 << 20);
988 platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
989 platform_resource_setup_memory(&spu0_device, "spu0", 2 << 20);
990 platform_resource_setup_memory(&spu1_device, "spu1", 2 << 20);
992 return platform_add_devices(sh7724_devices,
993 ARRAY_SIZE(sh7724_devices));
995 arch_initcall(sh7724_devices_setup);
997 static struct platform_device *sh7724_early_devices[] __initdata = {
1013 void __init plat_early_device_setup(void)
1015 early_platform_add_devices(sh7724_early_devices,
1016 ARRAY_SIZE(sh7724_early_devices));
1019 #define RAMCR_CACHE_L2FC 0x0002
1020 #define RAMCR_CACHE_L2E 0x0001
1021 #define L2_CACHE_ENABLE (RAMCR_CACHE_L2E|RAMCR_CACHE_L2FC)
1023 void l2_cache_init(void)
1025 /* Enable L2 cache */
1026 __raw_writel(L2_CACHE_ENABLE, RAMCR);
1034 /* interrupt sources */
1035 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
1037 DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3,
1038 _2DG_TRI, _2DG_INI, _2DG_CEI,
1039 DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3,
1040 VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU,
1048 RTC_ATI, RTC_PRI, RTC_CUI,
1049 DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR,
1050 DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR,
1052 SCIF_SCIF0, SCIF_SCIF1, SCIF_SCIF2,
1054 MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1055 SPU_SPUI0, SPU_SPUI1,
1059 I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
1060 I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
1065 TMU0_TUNI0, TMU0_TUNI1, TMU0_TUNI2,
1069 MMC_MMC2I, MMC_MMC3I,
1071 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
1073 /* interrupt groups */
1074 DMAC1A, _2DG, DMAC0A, VIO, USB, RTC,
1075 DMAC1B, DMAC0B, I2C0, I2C1, SDHI0, SDHI1, SPU, MMCIF,
1078 static struct intc_vect vectors[] __initdata = {
1079 INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
1080 INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
1081 INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
1082 INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
1084 INTC_VECT(DMAC1A_DEI0, 0x700),
1085 INTC_VECT(DMAC1A_DEI1, 0x720),
1086 INTC_VECT(DMAC1A_DEI2, 0x740),
1087 INTC_VECT(DMAC1A_DEI3, 0x760),
1089 INTC_VECT(_2DG_TRI, 0x780),
1090 INTC_VECT(_2DG_INI, 0x7A0),
1091 INTC_VECT(_2DG_CEI, 0x7C0),
1093 INTC_VECT(DMAC0A_DEI0, 0x800),
1094 INTC_VECT(DMAC0A_DEI1, 0x820),
1095 INTC_VECT(DMAC0A_DEI2, 0x840),
1096 INTC_VECT(DMAC0A_DEI3, 0x860),
1098 INTC_VECT(VIO_CEU0, 0x880),
1099 INTC_VECT(VIO_BEU0, 0x8A0),
1100 INTC_VECT(VIO_VEU1, 0x8C0),
1101 INTC_VECT(VIO_VOU, 0x8E0),
1103 INTC_VECT(SCIFA3, 0x900),
1104 INTC_VECT(VPU, 0x980),
1105 INTC_VECT(TPU, 0x9A0),
1106 INTC_VECT(CEU1, 0x9E0),
1107 INTC_VECT(BEU1, 0xA00),
1108 INTC_VECT(USB0, 0xA20),
1109 INTC_VECT(USB1, 0xA40),
1110 INTC_VECT(ATAPI, 0xA60),
1112 INTC_VECT(RTC_ATI, 0xA80),
1113 INTC_VECT(RTC_PRI, 0xAA0),
1114 INTC_VECT(RTC_CUI, 0xAC0),
1116 INTC_VECT(DMAC1B_DEI4, 0xB00),
1117 INTC_VECT(DMAC1B_DEI5, 0xB20),
1118 INTC_VECT(DMAC1B_DADERR, 0xB40),
1120 INTC_VECT(DMAC0B_DEI4, 0xB80),
1121 INTC_VECT(DMAC0B_DEI5, 0xBA0),
1122 INTC_VECT(DMAC0B_DADERR, 0xBC0),
1124 INTC_VECT(KEYSC, 0xBE0),
1125 INTC_VECT(SCIF_SCIF0, 0xC00),
1126 INTC_VECT(SCIF_SCIF1, 0xC20),
1127 INTC_VECT(SCIF_SCIF2, 0xC40),
1128 INTC_VECT(VEU0, 0xC60),
1129 INTC_VECT(MSIOF_MSIOFI0, 0xC80),
1130 INTC_VECT(MSIOF_MSIOFI1, 0xCA0),
1131 INTC_VECT(SPU_SPUI0, 0xCC0),
1132 INTC_VECT(SPU_SPUI1, 0xCE0),
1133 INTC_VECT(SCIFA4, 0xD00),
1135 INTC_VECT(ICB, 0xD20),
1136 INTC_VECT(ETHI, 0xD60),
1138 INTC_VECT(I2C1_ALI, 0xD80),
1139 INTC_VECT(I2C1_TACKI, 0xDA0),
1140 INTC_VECT(I2C1_WAITI, 0xDC0),
1141 INTC_VECT(I2C1_DTEI, 0xDE0),
1143 INTC_VECT(I2C0_ALI, 0xE00),
1144 INTC_VECT(I2C0_TACKI, 0xE20),
1145 INTC_VECT(I2C0_WAITI, 0xE40),
1146 INTC_VECT(I2C0_DTEI, 0xE60),
1148 INTC_VECT(SDHI0, 0xE80),
1149 INTC_VECT(SDHI0, 0xEA0),
1150 INTC_VECT(SDHI0, 0xEC0),
1151 INTC_VECT(SDHI0, 0xEE0),
1153 INTC_VECT(CMT, 0xF00),
1154 INTC_VECT(TSIF, 0xF20),
1155 INTC_VECT(FSI, 0xF80),
1156 INTC_VECT(SCIFA5, 0xFA0),
1158 INTC_VECT(TMU0_TUNI0, 0x400),
1159 INTC_VECT(TMU0_TUNI1, 0x420),
1160 INTC_VECT(TMU0_TUNI2, 0x440),
1162 INTC_VECT(IRDA, 0x480),
1164 INTC_VECT(SDHI1, 0x4E0),
1165 INTC_VECT(SDHI1, 0x500),
1166 INTC_VECT(SDHI1, 0x520),
1168 INTC_VECT(JPU, 0x560),
1169 INTC_VECT(_2DDMAC, 0x4A0),
1171 INTC_VECT(MMC_MMC2I, 0x5A0),
1172 INTC_VECT(MMC_MMC3I, 0x5C0),
1174 INTC_VECT(LCDC, 0xF40),
1176 INTC_VECT(TMU1_TUNI0, 0x920),
1177 INTC_VECT(TMU1_TUNI1, 0x940),
1178 INTC_VECT(TMU1_TUNI2, 0x960),
1181 static struct intc_group groups[] __initdata = {
1182 INTC_GROUP(DMAC1A, DMAC1A_DEI0, DMAC1A_DEI1, DMAC1A_DEI2, DMAC1A_DEI3),
1183 INTC_GROUP(_2DG, _2DG_TRI, _2DG_INI, _2DG_CEI),
1184 INTC_GROUP(DMAC0A, DMAC0A_DEI0, DMAC0A_DEI1, DMAC0A_DEI2, DMAC0A_DEI3),
1185 INTC_GROUP(VIO, VIO_CEU0, VIO_BEU0, VIO_VEU1, VIO_VOU),
1186 INTC_GROUP(USB, USB0, USB1),
1187 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
1188 INTC_GROUP(DMAC1B, DMAC1B_DEI4, DMAC1B_DEI5, DMAC1B_DADERR),
1189 INTC_GROUP(DMAC0B, DMAC0B_DEI4, DMAC0B_DEI5, DMAC0B_DADERR),
1190 INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
1191 INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
1192 INTC_GROUP(SPU, SPU_SPUI0, SPU_SPUI1),
1193 INTC_GROUP(MMCIF, MMC_MMC2I, MMC_MMC3I),
1196 static struct intc_mask_reg mask_registers[] __initdata = {
1197 { 0xa4080080, 0xa40800c0, 8, /* IMR0 / IMCR0 */
1198 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
1199 0, ENABLED, ENABLED, ENABLED } },
1200 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
1201 { VIO_VOU, VIO_VEU1, VIO_BEU0, VIO_CEU0,
1202 DMAC0A_DEI3, DMAC0A_DEI2, DMAC0A_DEI1, DMAC0A_DEI0 } },
1203 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
1204 { 0, 0, 0, VPU, ATAPI, ETHI, 0, SCIFA3 } },
1205 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
1206 { DMAC1A_DEI3, DMAC1A_DEI2, DMAC1A_DEI1, DMAC1A_DEI0,
1207 SPU_SPUI1, SPU_SPUI0, BEU1, IRDA } },
1208 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
1209 { 0, TMU0_TUNI2, TMU0_TUNI1, TMU0_TUNI0,
1210 JPU, 0, 0, LCDC } },
1211 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
1212 { KEYSC, DMAC0B_DADERR, DMAC0B_DEI5, DMAC0B_DEI4,
1213 VEU0, SCIF_SCIF2, SCIF_SCIF1, SCIF_SCIF0 } },
1214 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
1215 { 0, 0, ICB, SCIFA4,
1216 CEU1, 0, MSIOF_MSIOFI1, MSIOF_MSIOFI0 } },
1217 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
1218 { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
1219 I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI } },
1220 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
1221 { DISABLED, ENABLED, ENABLED, ENABLED,
1222 0, 0, SCIFA5, FSI } },
1223 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
1224 { 0, 0, 0, CMT, 0, USB1, USB0, 0 } },
1225 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
1226 { 0, DMAC1B_DADERR, DMAC1B_DEI5, DMAC1B_DEI4,
1227 0, RTC_CUI, RTC_PRI, RTC_ATI } },
1228 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
1229 { 0, _2DG_CEI, _2DG_INI, _2DG_TRI,
1230 0, TPU, 0, TSIF } },
1231 { 0xa40800b0, 0xa40800f0, 8, /* IMR12 / IMCR12 */
1232 { 0, 0, MMC_MMC3I, MMC_MMC2I, 0, 0, 0, _2DDMAC } },
1233 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
1234 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1237 static struct intc_prio_reg prio_registers[] __initdata = {
1238 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0_TUNI0, TMU0_TUNI1,
1239 TMU0_TUNI2, IRDA } },
1240 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, DMAC1A, BEU1 } },
1241 { 0xa4080008, 0, 16, 4, /* IPRC */ { TMU1_TUNI0, TMU1_TUNI1,
1242 TMU1_TUNI2, SPU } },
1243 { 0xa408000c, 0, 16, 4, /* IPRD */ { 0, MMCIF, 0, ATAPI } },
1244 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0A, VIO, SCIFA3, VPU } },
1245 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC0B, USB, CMT } },
1246 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF_SCIF0, SCIF_SCIF1,
1247 SCIF_SCIF2, VEU0 } },
1248 { 0xa408001c, 0, 16, 4, /* IPRH */ { MSIOF_MSIOFI0, MSIOF_MSIOFI1,
1250 { 0xa4080020, 0, 16, 4, /* IPRI */ { SCIFA4, ICB, TSIF, _2DG } },
1251 { 0xa4080024, 0, 16, 4, /* IPRJ */ { CEU1, ETHI, FSI, SDHI1 } },
1252 { 0xa4080028, 0, 16, 4, /* IPRK */ { RTC, DMAC1B, 0, SDHI0 } },
1253 { 0xa408002c, 0, 16, 4, /* IPRL */ { SCIFA5, 0, TPU, _2DDMAC } },
1254 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
1255 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1258 static struct intc_sense_reg sense_registers[] __initdata = {
1259 { 0xa414001c, 16, 2, /* ICR1 */
1260 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1263 static struct intc_mask_reg ack_registers[] __initdata = {
1264 { 0xa4140024, 0, 8, /* INTREQ00 */
1265 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
1268 static struct intc_desc intc_desc __initdata = {
1270 .force_enable = ENABLED,
1271 .force_disable = DISABLED,
1272 .hw = INTC_HW_DESC(vectors, groups, mask_registers,
1273 prio_registers, sense_registers, ack_registers),
1276 void __init plat_irq_setup(void)
1278 register_intc_controller(&intc_desc);
1283 unsigned long mmselr;
1284 unsigned long cs0bcr;
1285 unsigned long cs4bcr;
1286 unsigned long cs5abcr;
1287 unsigned long cs5bbcr;
1288 unsigned long cs6abcr;
1289 unsigned long cs6bbcr;
1290 unsigned long cs4wcr;
1291 unsigned long cs5awcr;
1292 unsigned long cs5bwcr;
1293 unsigned long cs6awcr;
1294 unsigned long cs6bwcr;
1296 unsigned short ipra;
1297 unsigned short iprb;
1298 unsigned short iprc;
1299 unsigned short iprd;
1300 unsigned short ipre;
1301 unsigned short iprf;
1302 unsigned short iprg;
1303 unsigned short iprh;
1304 unsigned short ipri;
1305 unsigned short iprj;
1306 unsigned short iprk;
1307 unsigned short iprl;
1318 unsigned char imr10;
1319 unsigned char imr11;
1320 unsigned char imr12;
1322 unsigned short rwtcnt;
1323 unsigned short rwtcsr;
1325 unsigned long irdaclk;
1326 unsigned long spuclk;
1327 } sh7724_rstandby_state;
1329 static int sh7724_pre_sleep_notifier_call(struct notifier_block *nb,
1330 unsigned long flags, void *unused)
1332 if (!(flags & SUSP_SH_RSTANDBY))
1336 sh7724_rstandby_state.mmselr = __raw_readl(0xff800020); /* MMSELR */
1337 sh7724_rstandby_state.mmselr |= 0xa5a50000;
1338 sh7724_rstandby_state.cs0bcr = __raw_readl(0xfec10004); /* CS0BCR */
1339 sh7724_rstandby_state.cs4bcr = __raw_readl(0xfec10010); /* CS4BCR */
1340 sh7724_rstandby_state.cs5abcr = __raw_readl(0xfec10014); /* CS5ABCR */
1341 sh7724_rstandby_state.cs5bbcr = __raw_readl(0xfec10018); /* CS5BBCR */
1342 sh7724_rstandby_state.cs6abcr = __raw_readl(0xfec1001c); /* CS6ABCR */
1343 sh7724_rstandby_state.cs6bbcr = __raw_readl(0xfec10020); /* CS6BBCR */
1344 sh7724_rstandby_state.cs4wcr = __raw_readl(0xfec10030); /* CS4WCR */
1345 sh7724_rstandby_state.cs5awcr = __raw_readl(0xfec10034); /* CS5AWCR */
1346 sh7724_rstandby_state.cs5bwcr = __raw_readl(0xfec10038); /* CS5BWCR */
1347 sh7724_rstandby_state.cs6awcr = __raw_readl(0xfec1003c); /* CS6AWCR */
1348 sh7724_rstandby_state.cs6bwcr = __raw_readl(0xfec10040); /* CS6BWCR */
1351 sh7724_rstandby_state.ipra = __raw_readw(0xa4080000); /* IPRA */
1352 sh7724_rstandby_state.iprb = __raw_readw(0xa4080004); /* IPRB */
1353 sh7724_rstandby_state.iprc = __raw_readw(0xa4080008); /* IPRC */
1354 sh7724_rstandby_state.iprd = __raw_readw(0xa408000c); /* IPRD */
1355 sh7724_rstandby_state.ipre = __raw_readw(0xa4080010); /* IPRE */
1356 sh7724_rstandby_state.iprf = __raw_readw(0xa4080014); /* IPRF */
1357 sh7724_rstandby_state.iprg = __raw_readw(0xa4080018); /* IPRG */
1358 sh7724_rstandby_state.iprh = __raw_readw(0xa408001c); /* IPRH */
1359 sh7724_rstandby_state.ipri = __raw_readw(0xa4080020); /* IPRI */
1360 sh7724_rstandby_state.iprj = __raw_readw(0xa4080024); /* IPRJ */
1361 sh7724_rstandby_state.iprk = __raw_readw(0xa4080028); /* IPRK */
1362 sh7724_rstandby_state.iprl = __raw_readw(0xa408002c); /* IPRL */
1363 sh7724_rstandby_state.imr0 = __raw_readb(0xa4080080); /* IMR0 */
1364 sh7724_rstandby_state.imr1 = __raw_readb(0xa4080084); /* IMR1 */
1365 sh7724_rstandby_state.imr2 = __raw_readb(0xa4080088); /* IMR2 */
1366 sh7724_rstandby_state.imr3 = __raw_readb(0xa408008c); /* IMR3 */
1367 sh7724_rstandby_state.imr4 = __raw_readb(0xa4080090); /* IMR4 */
1368 sh7724_rstandby_state.imr5 = __raw_readb(0xa4080094); /* IMR5 */
1369 sh7724_rstandby_state.imr6 = __raw_readb(0xa4080098); /* IMR6 */
1370 sh7724_rstandby_state.imr7 = __raw_readb(0xa408009c); /* IMR7 */
1371 sh7724_rstandby_state.imr8 = __raw_readb(0xa40800a0); /* IMR8 */
1372 sh7724_rstandby_state.imr9 = __raw_readb(0xa40800a4); /* IMR9 */
1373 sh7724_rstandby_state.imr10 = __raw_readb(0xa40800a8); /* IMR10 */
1374 sh7724_rstandby_state.imr11 = __raw_readb(0xa40800ac); /* IMR11 */
1375 sh7724_rstandby_state.imr12 = __raw_readb(0xa40800b0); /* IMR12 */
1378 sh7724_rstandby_state.rwtcnt = __raw_readb(0xa4520000); /* RWTCNT */
1379 sh7724_rstandby_state.rwtcnt |= 0x5a00;
1380 sh7724_rstandby_state.rwtcsr = __raw_readb(0xa4520004); /* RWTCSR */
1381 sh7724_rstandby_state.rwtcsr |= 0xa500;
1382 __raw_writew(sh7724_rstandby_state.rwtcsr & 0x07, 0xa4520004);
1385 sh7724_rstandby_state.irdaclk = __raw_readl(0xa4150018); /* IRDACLKCR */
1386 sh7724_rstandby_state.spuclk = __raw_readl(0xa415003c); /* SPUCLKCR */
1391 static int sh7724_post_sleep_notifier_call(struct notifier_block *nb,
1392 unsigned long flags, void *unused)
1394 if (!(flags & SUSP_SH_RSTANDBY))
1398 __raw_writel(sh7724_rstandby_state.mmselr, 0xff800020); /* MMSELR */
1399 __raw_writel(sh7724_rstandby_state.cs0bcr, 0xfec10004); /* CS0BCR */
1400 __raw_writel(sh7724_rstandby_state.cs4bcr, 0xfec10010); /* CS4BCR */
1401 __raw_writel(sh7724_rstandby_state.cs5abcr, 0xfec10014); /* CS5ABCR */
1402 __raw_writel(sh7724_rstandby_state.cs5bbcr, 0xfec10018); /* CS5BBCR */
1403 __raw_writel(sh7724_rstandby_state.cs6abcr, 0xfec1001c); /* CS6ABCR */
1404 __raw_writel(sh7724_rstandby_state.cs6bbcr, 0xfec10020); /* CS6BBCR */
1405 __raw_writel(sh7724_rstandby_state.cs4wcr, 0xfec10030); /* CS4WCR */
1406 __raw_writel(sh7724_rstandby_state.cs5awcr, 0xfec10034); /* CS5AWCR */
1407 __raw_writel(sh7724_rstandby_state.cs5bwcr, 0xfec10038); /* CS5BWCR */
1408 __raw_writel(sh7724_rstandby_state.cs6awcr, 0xfec1003c); /* CS6AWCR */
1409 __raw_writel(sh7724_rstandby_state.cs6bwcr, 0xfec10040); /* CS6BWCR */
1412 __raw_writew(sh7724_rstandby_state.ipra, 0xa4080000); /* IPRA */
1413 __raw_writew(sh7724_rstandby_state.iprb, 0xa4080004); /* IPRB */
1414 __raw_writew(sh7724_rstandby_state.iprc, 0xa4080008); /* IPRC */
1415 __raw_writew(sh7724_rstandby_state.iprd, 0xa408000c); /* IPRD */
1416 __raw_writew(sh7724_rstandby_state.ipre, 0xa4080010); /* IPRE */
1417 __raw_writew(sh7724_rstandby_state.iprf, 0xa4080014); /* IPRF */
1418 __raw_writew(sh7724_rstandby_state.iprg, 0xa4080018); /* IPRG */
1419 __raw_writew(sh7724_rstandby_state.iprh, 0xa408001c); /* IPRH */
1420 __raw_writew(sh7724_rstandby_state.ipri, 0xa4080020); /* IPRI */
1421 __raw_writew(sh7724_rstandby_state.iprj, 0xa4080024); /* IPRJ */
1422 __raw_writew(sh7724_rstandby_state.iprk, 0xa4080028); /* IPRK */
1423 __raw_writew(sh7724_rstandby_state.iprl, 0xa408002c); /* IPRL */
1424 __raw_writeb(sh7724_rstandby_state.imr0, 0xa4080080); /* IMR0 */
1425 __raw_writeb(sh7724_rstandby_state.imr1, 0xa4080084); /* IMR1 */
1426 __raw_writeb(sh7724_rstandby_state.imr2, 0xa4080088); /* IMR2 */
1427 __raw_writeb(sh7724_rstandby_state.imr3, 0xa408008c); /* IMR3 */
1428 __raw_writeb(sh7724_rstandby_state.imr4, 0xa4080090); /* IMR4 */
1429 __raw_writeb(sh7724_rstandby_state.imr5, 0xa4080094); /* IMR5 */
1430 __raw_writeb(sh7724_rstandby_state.imr6, 0xa4080098); /* IMR6 */
1431 __raw_writeb(sh7724_rstandby_state.imr7, 0xa408009c); /* IMR7 */
1432 __raw_writeb(sh7724_rstandby_state.imr8, 0xa40800a0); /* IMR8 */
1433 __raw_writeb(sh7724_rstandby_state.imr9, 0xa40800a4); /* IMR9 */
1434 __raw_writeb(sh7724_rstandby_state.imr10, 0xa40800a8); /* IMR10 */
1435 __raw_writeb(sh7724_rstandby_state.imr11, 0xa40800ac); /* IMR11 */
1436 __raw_writeb(sh7724_rstandby_state.imr12, 0xa40800b0); /* IMR12 */
1439 __raw_writew(sh7724_rstandby_state.rwtcnt, 0xa4520000); /* RWTCNT */
1440 __raw_writew(sh7724_rstandby_state.rwtcsr, 0xa4520004); /* RWTCSR */
1443 __raw_writel(sh7724_rstandby_state.irdaclk, 0xa4150018); /* IRDACLKCR */
1444 __raw_writel(sh7724_rstandby_state.spuclk, 0xa415003c); /* SPUCLKCR */
1449 static struct notifier_block sh7724_pre_sleep_notifier = {
1450 .notifier_call = sh7724_pre_sleep_notifier_call,
1451 .priority = SH_MOBILE_PRE(SH_MOBILE_SLEEP_CPU),
1454 static struct notifier_block sh7724_post_sleep_notifier = {
1455 .notifier_call = sh7724_post_sleep_notifier_call,
1456 .priority = SH_MOBILE_POST(SH_MOBILE_SLEEP_CPU),
1459 static int __init sh7724_sleep_setup(void)
1461 atomic_notifier_chain_register(&sh_mobile_pre_sleep_notifier_list,
1462 &sh7724_pre_sleep_notifier);
1464 atomic_notifier_chain_register(&sh_mobile_post_sleep_notifier_list,
1465 &sh7724_post_sleep_notifier);
1468 arch_initcall(sh7724_sleep_setup);