arch/sh/kernel/cpu/sh4a/clock-sh7722.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4a/clock-sh7722.c
   3  *
   4  * SH7722 clock framework support
   5  *
   6  * Copyright (C) 2009 Magnus Damm
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  20  */
  21 #include <linux/init.h>
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <asm/clkdev.h>
  25 #include <asm/clock.h>
  26 #include <asm/hwblk.h>
  27 #include <cpu/sh7722.h>
  28
  29 /* SH7722 registers */
  30 #define FRQCR           0xa4150000
  31 #define VCLKCR          0xa4150004
  32 #define SCLKACR         0xa4150008
  33 #define SCLKBCR         0xa415000c
  34 #define IRDACLKCR       0xa4150018
  35 #define PLLCR           0xa4150024
  36 #define DLLFRQ          0xa4150050
  37
  38 /* Fixed 32 KHz root clock for RTC and Power Management purposes */
  39 static struct clk r_clk = {
  40         .rate           = 32768,
  41 };
  42
  43 /*
  44  * Default rate for the root input clock, reset this with clk_set_rate()
  45  * from the platform code.
  46  */
  47 struct clk extal_clk = {
  48         .rate           = 33333333,
  49 };
  50
  51 /* The dll block multiplies the 32khz r_clk, may be used instead of extal */
  52 static unsigned long dll_recalc(struct clk *clk)
  53 {
  54         unsigned long mult;
  55
  56         if (__raw_readl(PLLCR) & 0x1000)
  57                 mult = __raw_readl(DLLFRQ);
  58         else
  59                 mult = 0;
  60
  61         return clk->parent->rate * mult;
  62 }
  63
  64 static struct clk_ops dll_clk_ops = {
  65         .recalc         = dll_recalc,
  66 };
  67
  68 static struct clk dll_clk = {
  69         .ops            = &dll_clk_ops,
  70         .parent         = &r_clk,
  71         .flags          = CLK_ENABLE_ON_INIT,
  72 };
  73
  74 static unsigned long pll_recalc(struct clk *clk)
  75 {
  76         unsigned long mult = 1;
  77         unsigned long div = 1;
  78
  79         if (__raw_readl(PLLCR) & 0x4000)
  80                 mult = (((__raw_readl(FRQCR) >> 24) & 0x1f) + 1);
  81         else
  82                 div = 2;
  83
  84         return (clk->parent->rate * mult) / div;
  85 }
  86
  87 static struct clk_ops pll_clk_ops = {
  88         .recalc         = pll_recalc,
  89 };
  90
  91 static struct clk pll_clk = {
  92         .ops            = &pll_clk_ops,
  93         .flags          = CLK_ENABLE_ON_INIT,
  94 };
  95
  96 struct clk *main_clks[] = {
  97         &r_clk,
  98         &extal_clk,
  99         &dll_clk,
 100         &pll_clk,
 101 };
 102
 103 static int multipliers[] = { 1, 2, 1, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1 };
 104 static int divisors[] = { 1, 3, 2, 5, 3, 4, 5, 6, 8, 10, 12, 16, 20 };
 105
 106 static struct clk_div_mult_table div4_div_mult_table = {
 107         .divisors = divisors,
 108         .nr_divisors = ARRAY_SIZE(divisors),
 109         .multipliers = multipliers,
 110         .nr_multipliers = ARRAY_SIZE(multipliers),
 111 };
 112
 113 static struct clk_div4_table div4_table = {
 114         .div_mult_table = &div4_div_mult_table,
 115 };
 116
 117 #define DIV4(_reg, _bit, _mask, _flags) \
 118   SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
 119
 120 enum { DIV4_I, DIV4_U, DIV4_SH, DIV4_B, DIV4_B3, DIV4_P, DIV4_NR };
 121
 122 struct clk div4_clks[DIV4_NR] = {
 123         [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
 124         [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
 125         [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
 126         [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
 127         [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
 128         [DIV4_P] = DIV4(FRQCR, 0, 0x1fff, 0),
 129 };
 130
 131 enum { DIV4_IRDA, DIV4_ENABLE_NR };
 132
 133 struct clk div4_enable_clks[DIV4_ENABLE_NR] = {
 134         [DIV4_IRDA] = DIV4(IRDACLKCR, 0, 0x1fff, 0),
 135 };
 136
 137 enum { DIV4_SIUA, DIV4_SIUB, DIV4_REPARENT_NR };
 138
 139 struct clk div4_reparent_clks[DIV4_REPARENT_NR] = {
 140         [DIV4_SIUA] = DIV4(SCLKACR, 0, 0x1fff, 0),
 141         [DIV4_SIUB] = DIV4(SCLKBCR, 0, 0x1fff, 0),
 142 };
 143
 144 enum { DIV6_V, DIV6_NR };
 145
 146 struct clk div6_clks[DIV6_NR] = {
 147         [DIV6_V] = SH_CLK_DIV6(&pll_clk, VCLKCR, 0),
 148 };
 149
 150 static struct clk mstp_clks[HWBLK_NR] = {
 151         SH_HWBLK_CLK(HWBLK_URAM, &div4_clks[DIV4_U], CLK_ENABLE_ON_INIT),
 152         SH_HWBLK_CLK(HWBLK_XYMEM, &div4_clks[DIV4_B], CLK_ENABLE_ON_INIT),
 153         SH_HWBLK_CLK(HWBLK_TMU, &div4_clks[DIV4_P], 0),
 154         SH_HWBLK_CLK(HWBLK_CMT, &r_clk, 0),
 155         SH_HWBLK_CLK(HWBLK_RWDT, &r_clk, 0),
 156         SH_HWBLK_CLK(HWBLK_FLCTL, &div4_clks[DIV4_P], 0),
 157         SH_HWBLK_CLK(HWBLK_SCIF0, &div4_clks[DIV4_P], 0),
 158         SH_HWBLK_CLK(HWBLK_SCIF1, &div4_clks[DIV4_P], 0),
 159         SH_HWBLK_CLK(HWBLK_SCIF2, &div4_clks[DIV4_P], 0),
 160
 161         SH_HWBLK_CLK(HWBLK_IIC, &div4_clks[DIV4_P], 0),
 162         SH_HWBLK_CLK(HWBLK_RTC, &r_clk, 0),
 163
 164         SH_HWBLK_CLK(HWBLK_SDHI, &div4_clks[DIV4_P], 0),
 165         SH_HWBLK_CLK(HWBLK_KEYSC, &r_clk, 0),
 166         SH_HWBLK_CLK(HWBLK_USBF, &div4_clks[DIV4_P], 0),
 167         SH_HWBLK_CLK(HWBLK_2DG, &div4_clks[DIV4_B], 0),
 168         SH_HWBLK_CLK(HWBLK_SIU, &div4_clks[DIV4_B], 0),
 169         SH_HWBLK_CLK(HWBLK_VOU, &div4_clks[DIV4_B], 0),
 170         SH_HWBLK_CLK(HWBLK_JPU, &div4_clks[DIV4_B], 0),
 171         SH_HWBLK_CLK(HWBLK_BEU, &div4_clks[DIV4_B], 0),
 172         SH_HWBLK_CLK(HWBLK_CEU, &div4_clks[DIV4_B], 0),
 173         SH_HWBLK_CLK(HWBLK_VEU, &div4_clks[DIV4_B], 0),
 174         SH_HWBLK_CLK(HWBLK_VPU, &div4_clks[DIV4_B], 0),
 175         SH_HWBLK_CLK(HWBLK_LCDC, &div4_clks[DIV4_P], 0),
 176 };
 177
 178 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 179
 180 static struct clk_lookup lookups[] = {
 181         /* main clocks */
 182         CLKDEV_CON_ID("rclk", &r_clk),
 183         CLKDEV_CON_ID("extal", &extal_clk),
 184         CLKDEV_CON_ID("dll_clk", &dll_clk),
 185         CLKDEV_CON_ID("pll_clk", &pll_clk),
 186
 187         /* DIV4 clocks */
 188         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 189         CLKDEV_CON_ID("umem_clk", &div4_clks[DIV4_U]),
 190         CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
 191         CLKDEV_CON_ID("bus_clk", &div4_clks[DIV4_B]),
 192         CLKDEV_CON_ID("b3_clk", &div4_clks[DIV4_B3]),
 193         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 194         CLKDEV_CON_ID("irda_clk", &div4_enable_clks[DIV4_IRDA]),
 195         CLKDEV_CON_ID("siua_clk", &div4_reparent_clks[DIV4_SIUA]),
 196         CLKDEV_CON_ID("siub_clk", &div4_reparent_clks[DIV4_SIUB]),
 197
 198         /* DIV6 clocks */
 199         CLKDEV_CON_ID("video_clk", &div6_clks[DIV6_V]),
 200
 201         /* MSTP clocks */
 202         CLKDEV_CON_ID("uram0", &mstp_clks[HWBLK_URAM]),
 203         CLKDEV_CON_ID("xymem0", &mstp_clks[HWBLK_XYMEM]),
 204         {
 205                 /* TMU0 */
 206                 .dev_id         = "sh_tmu.0",
 207                 .con_id         = "tmu_fck",
 208                 .clk            = &mstp_clks[HWBLK_TMU],
 209         }, {
 210                 /* TMU1 */
 211                 .dev_id         = "sh_tmu.1",
 212                 .con_id         = "tmu_fck",
 213                 .clk            = &mstp_clks[HWBLK_TMU],
 214         }, {
 215                 /* TMU2 */
 216                 .dev_id         = "sh_tmu.2",
 217                 .con_id         = "tmu_fck",
 218                 .clk            = &mstp_clks[HWBLK_TMU],
 219         },
 220         CLKDEV_CON_ID("cmt_fck", &mstp_clks[HWBLK_CMT]),
 221         CLKDEV_CON_ID("rwdt0", &mstp_clks[HWBLK_RWDT]),
 222         CLKDEV_CON_ID("flctl0", &mstp_clks[HWBLK_FLCTL]),
 223         {
 224                 /* SCIF0 */
 225                 .dev_id         = "sh-sci.0",
 226                 .con_id         = "sci_fck",
 227                 .clk            = &mstp_clks[HWBLK_SCIF0],
 228         }, {
 229                 /* SCIF1 */
 230                 .dev_id         = "sh-sci.1",
 231                 .con_id         = "sci_fck",
 232                 .clk            = &mstp_clks[HWBLK_SCIF1],
 233         }, {
 234                 /* SCIF2 */
 235                 .dev_id         = "sh-sci.2",
 236                 .con_id         = "sci_fck",
 237                 .clk            = &mstp_clks[HWBLK_SCIF2],
 238         },
 239         CLKDEV_CON_ID("i2c0", &mstp_clks[HWBLK_IIC]),
 240         CLKDEV_CON_ID("rtc0", &mstp_clks[HWBLK_RTC]),
 241         CLKDEV_CON_ID("sdhi0", &mstp_clks[HWBLK_SDHI]),
 242         CLKDEV_CON_ID("keysc0", &mstp_clks[HWBLK_KEYSC]),
 243         CLKDEV_CON_ID("usbf0", &mstp_clks[HWBLK_USBF]),
 244         CLKDEV_CON_ID("2dg0", &mstp_clks[HWBLK_2DG]),
 245         CLKDEV_CON_ID("siu0", &mstp_clks[HWBLK_SIU]),
 246         CLKDEV_CON_ID("vou0", &mstp_clks[HWBLK_VOU]),
 247         CLKDEV_CON_ID("jpu0", &mstp_clks[HWBLK_JPU]),
 248         CLKDEV_CON_ID("beu0", &mstp_clks[HWBLK_BEU]),
 249         CLKDEV_CON_ID("ceu0", &mstp_clks[HWBLK_CEU]),
 250         CLKDEV_CON_ID("veu0", &mstp_clks[HWBLK_VEU]),
 251         CLKDEV_CON_ID("vpu0", &mstp_clks[HWBLK_VPU]),
 252         CLKDEV_CON_ID("lcdc0", &mstp_clks[HWBLK_LCDC]),
 253 };
 254
 255 int __init arch_clk_init(void)
 256 {
 257         int k, ret = 0;
 258
 259         /* autodetect extal or dll configuration */
 260         if (__raw_readl(PLLCR) & 0x1000)
 261                 pll_clk.parent = &dll_clk;
 262         else
 263                 pll_clk.parent = &extal_clk;
 264
 265         for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
 266                 ret = clk_register(main_clks[k]);
 267
 268         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
 269
 270         if (!ret)
 271                 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
 272
 273         if (!ret)
 274                 ret = sh_clk_div4_enable_register(div4_enable_clks,
 275                                         DIV4_ENABLE_NR, &div4_table);
 276
 277         if (!ret)
 278                 ret = sh_clk_div4_reparent_register(div4_reparent_clks,
 279                                         DIV4_REPARENT_NR, &div4_table);
 280
 281         if (!ret)
 282                 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
 283
 284         if (!ret)
 285                 ret = sh_hwblk_clk_register(mstp_clks, HWBLK_NR);
 286
 287         return ret;
 288 }